Single-ended sensitive amplifier circuit, memory read circuit and memory

Abstract

The invention provides a single-ended sensitive amplifier circuit, a memory read circuit and a memory. The single-ended sensitive amplifier circuit comprises a clamping circuit with pre-charging control and a reference current comparison circuit, the clamping circuit with pre-charging control comprises a noise reduction unit, and the noise reduction unit is connected with the reference current comparison circuit; the clamping circuit with the pre-charging control is connected with the storage unit, and the clamping circuit with the pre-charging control is used for reading an operation signal; wherein the noise reduction unit is used for reducing the fluctuation quantity of the operation signal when the single-ended sensitive amplifier generates power supply noise fluctuation; and the reference current comparison circuit is used for comparing the operation signal processed by the noise reduction unit with a reference signal and outputting target data. The noise reduction unit is arranged in the single-end sensitive amplifier circuit, so that the fluctuation quantity of an operation signal in a power supply noise environment is remarkably reduced, and the anti-noise capability of the sensitive amplifier is improved.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to a single-ended sense amplifier circuit, a memory read circuit and a memory. Background Art

[0002] The sense amplifier is a key circuit for the read operation in Nor Flash (a type of non-volatile flash memory). It determines the current of the NorFlash cell (flash memory unit) and determines whether the data is 0 or 1. Generally speaking, the sense amplifier has two structures: differential and single-ended.

[0003] Traditional single-ended sense amplifiers have the advantages of simple circuit structure, simple control logic, low power consumption, and smaller area. However, compared with differential sense amplifiers, their ability to resist common-mode noise is weaker. Therefore, in an environment with large power supply noise (for example, Power Noise>0.7V), it is easy to cause misjudgment, resulting in Nor Flash read operation errors or failure to meet high-speed (for example, Quad I / O data transfer up to 532Mbits / s) reading requirements. Summary of the invention

[0004] The technical problem to be solved by the present disclosure is to overcome the defect that the single-ended sensitive amplifier used for Nor Flash in the prior art is prone to misjudgment in a power supply noise environment and cannot accurately read the data in the Nor Flash, and to provide a single-ended sensitive amplifier circuit, a memory read circuit and a memory.

[0005] The present invention solves the above technical problems through the following technical solutions:

[0006] According to a first aspect of the present disclosure, there is provided a single-ended sense amplifier circuit, the single-ended sense amplifier circuit comprising a clamp circuit with pre-charge control and a reference current comparison circuit;

[0007] The clamp circuit with pre-charge control includes a noise reduction unit, and the noise reduction unit is connected to the reference current comparison circuit;

[0008] The clamp circuit with pre-charge control is connected to the storage unit, and the clamp circuit with pre-charge control is used to read the operation signal;

[0009] Wherein, the noise reduction unit is used to reduce the fluctuation amount of the operation signal when the single-ended sensitive amplifier generates power supply noise fluctuation;

[0010] The reference current comparison circuit is used to compare the operation signal processed by the noise reduction unit with a reference signal and output target data.

[0011] Preferably, the noise reduction unit comprises a first transistor and a second transistor;

[0012] The first transistor is connected to the second transistor;

[0013] The first transistor and the second transistor are both triple well NMOS (N-Metal-Oxide-Semiconductor) transistors;

[0014] The second transistor is connected to the reference current comparison circuit.

[0015] Preferably, the clamping circuit with pre-charge control further includes a pre-charge switch and a capacitor unit;

[0016] The reference current comparison circuit includes a first current mirror, a second current mirror and a buffer;

[0017] The first transistor includes a first body electrode, a first substrate electrode, a first source electrode, a first gate electrode and a first drain electrode;

[0018] The second transistor includes a second body electrode, a second substrate electrode, a second source electrode, a second gate electrode and a second drain electrode;

[0019] The first source electrode, the first substrate electrode, the second source electrode, and the second substrate electrode are connected to the storage unit, and the first body electrode and the second body electrode are connected to the power supply terminal;

[0020] The first drain is connected to the power supply terminal via the pre-charging switch, and the first gate and the second gate are connected to the capacitor unit;

[0021] The second source and the second drain are respectively connected to the reference current comparison circuit;

[0022] The second source is used to read the memory cell current, and the memory cell current and the reference current form a clamping current flowing through the second drain;

[0023] The first current mirror is used to output the clamping current with a 1:1 current ratio;

[0024] The second current mirror is used to output the reference current with a current ratio of 1:2;

[0025] The buffer is used to convert a comparison current into a digital signal for output, wherein the comparison current is a difference between the clamp current output via the first current mirror and the reference current output via the second current mirror.

[0026] Preferably, the first current mirror includes a first PMOS (P-Channel-Oxide-Semiconductor) tube and a second PMOS tube, and the second current mirror includes a first NMOS tube and a second NMOS tube;

[0027] The first PMOS tube includes a fourth source, a fourth gate and a fourth drain;

[0028] The second PMOS tube includes a fifth source, a fifth gate and a fifth drain;

[0029] The first NMOS tube includes a sixth source, a sixth gate and a sixth drain;

[0030] The second NMOS tube includes a seventh source, a seventh gate and a seventh drain;

[0031] The fourth source electrode and the fifth source electrode are connected to the power supply terminal, and the fourth gate electrode, the fourth drain electrode, and the fifth gate electrode are connected to the second drain electrode;

[0032] The sixth drain is connected to the second source, the sixth gate and the seventh gate are connected to a reference voltage, and the sixth source and the seventh source are grounded;

[0033] The fifth drain and the seventh drain are connected to the buffer;

[0034] and / or,

[0035] The capacitor unit includes a third gate, a third source and a third drain, the capacitance value of the capacitor unit meets a preset condition, and the capacitor unit is used for voltage stabilization and noise reduction;

[0036] The third gate is connected to the first gate and the second gate, and the third drain is connected to the third source and then connected to an enable signal;

[0037] and / or,

[0038] The capacitance value of the capacitance unit is smaller than the MOS (metal oxide semiconductor field effect transistor) capacitance value of the second transistor.

[0039] Preferably, the noise reduction unit comprises a first transistor and a second transistor;

[0040] The first transistor is connected to the second transistor;

[0041] The first transistor and the second transistor are both NMOS transistors, and a width-to-length ratio of the first transistor and the second transistor is less than a preset threshold;

[0042] The second transistor is connected to the reference current comparison circuit.

[0043] Preferably, the clamping circuit with pre-charge control further includes a pre-charge switch and a capacitor unit;

[0044] The reference current comparison circuit includes a first current mirror, a second current mirror and a buffer;

[0045] The first transistor includes an eighth gate, an eighth source and an eighth drain;

[0046] The second transistor includes a ninth gate, a ninth source and a ninth drain;

[0047] The eighth source and the ninth source are connected to the storage unit;

[0048] The eighth drain is connected to the power supply terminal via the pre-charging switch, and the eighth gate and the ninth gate are connected to the capacitor unit;

[0049] The ninth source and the ninth drain are respectively connected to the reference current comparison circuit;

[0050] The ninth source is used to read the memory cell current, and the memory cell current and the reference current form a clamping current flowing through the ninth drain;

[0051] The first current mirror is used to output the clamping current with a 1:1 current ratio;

[0052] The second current mirror is used to output the reference current with a current ratio of 1:2;

[0053] The buffer is used to convert a comparison current into a digital signal for output, wherein the comparison current is a difference between the clamp current output via the first current mirror and the reference current output via the second current mirror.

[0054] Preferably, the first current mirror includes a first PMOS tube and a second PMOS tube, and the second current mirror includes a first NMOS tube and a second NMOS tube;

[0055] The first PMOS tube includes a fourth source, a fourth gate and a fourth drain;

[0056] The second PMOS tube includes a fifth source, a fifth gate and a fifth drain;

[0057] The first NMOS tube includes a sixth source, a sixth gate and a sixth drain;

[0058] The second NMOS tube includes a seventh source, a seventh gate and a seventh drain;

[0059] The fourth source electrode and the fifth source electrode are connected to the power supply terminal, and the fourth gate electrode, the fourth drain electrode, the fifth gate electrode and the ninth drain electrode are connected;

[0060] The sixth drain is connected to the ninth source, the sixth gate and the seventh gate are connected to a reference unit, and the sixth source and the seventh source are grounded;

[0061] The fifth drain and the seventh drain are connected to the buffer;

[0062] and / or,

[0063] The capacitor unit includes a third gate, a third source and a third drain, the capacitance value of the capacitor unit meets a preset condition, and the capacitor unit is used for voltage stabilization and noise reduction;

[0064] The third gate is connected to the eighth gate and the ninth gate, and the third drain is connected to the third source and then connected to an enable signal;

[0065] and / or,

[0066] The capacitance value of the capacitor unit is smaller than the MOS capacitance value of the second transistor.

[0067] Preferably, the noise reduction unit comprises a first transistor, a second transistor and a noise reduction capacitor;

[0068] The noise reduction capacitor comprises a capacitor gate, a capacitor source and a capacitor drain, the capacitance of the noise reduction capacitor meets a preset condition, and the noise reduction capacitor is used for voltage stabilization and noise reduction;

[0069] The capacitor gate is connected to the first transistor, the capacitor drain is connected to the capacitor source and then connected to an enable signal;

[0070] The first transistor is connected to the second transistor;

[0071] The second transistor is connected to the reference current comparison circuit.

[0072] According to a second aspect of the present disclosure, a memory read circuit is provided, wherein the memory read circuit comprises the single-ended sense amplifier circuit according to the first aspect of the present disclosure.

[0073] According to a third aspect of the present disclosure, a memory is provided, wherein the memory includes the memory read circuit described in the second aspect of the present disclosure.

[0074] On the basis of being in accordance with the common sense in the art, the above-mentioned preferred conditions can be arbitrarily combined to obtain the preferred embodiments of the present disclosure.

[0075] The positive progress effect of the present disclosure is that: in view of the fundamental reason why the traditional single-ended sense amplifier in Nor Flash is interfered in the power supply noise environment, a noise reduction unit is set in the single-ended sense amplifier circuit, and the fluctuation of the operating signal in the power supply noise environment is significantly reduced by controlling the capacitance size of its gate terminal, eliminating the substrate bias effect, and reducing the forward current and reverse recovery time, thereby improving the noise resistance of the sense amplifier, ensuring the accuracy of the Nor Flash read data, and meeting the needs of the Nor Flash high-speed read operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0076] Figure 1 It is a conventional single-ended sense amplifier circuit used in Nor Flash read circuit;

[0077] Figure 2 The single-ended sense amplifier circuit in Embodiment 1 of the present disclosure;

[0078] Figure 3 1 is a first circuit diagram of a single-ended sense amplifier circuit in Embodiment 2 of the present disclosure;

[0079] Figure 4 is a second circuit schematic diagram of a single-ended sense amplifier circuit in Embodiment 2 of the present disclosure;

[0080] Figure 5 is a third circuit schematic diagram of the single-ended sense amplifier circuit in Embodiment 2 of the present disclosure;

[0081] Figure 6 1 is a first circuit diagram of a single-ended sense amplifier circuit in Embodiment 3 of the present disclosure;

[0082] Figure 7 is a second circuit schematic diagram of the single-ended sense amplifier circuit in Embodiment 3 of the present disclosure;

[0083] Figure 8 is a third circuit schematic diagram of the single-ended sense amplifier circuit in Embodiment 3 of the present disclosure;

[0084] Fig. 9 The single-ended sense amplifier circuit in Embodiment 4 of the present disclosure;

[0085] Fig.10 The simulation diagram of the reading operation of the conventional single-ended sense amplifier used in the Nor Flash reading circuit in a noisy environment;

[0086] Fig.11 FIG. 4 is a schematic diagram of a simulation of a read operation of a single-ended sense amplifier in a noisy environment according to the present disclosure. DETAILED DESCRIPTION

[0087] The present disclosure is further described below by way of examples, but the present disclosure is not limited to the scope of the examples.

[0088] Prefixes such as "first" and "second" are used in the embodiments of the present disclosure only to distinguish different description objects, and have no limiting effect on the position, order, priority, quantity or content of the described objects. The use of prefixes such as ordinal numbers to distinguish description objects in the embodiments of the present disclosure does not constitute a limitation on the described objects. For the statement of the described objects, please refer to the description in the context of the claims or embodiments, and no unnecessary limitation should be constituted due to the use of such prefixes. In addition, in the description of the present embodiment, unless otherwise specified, the meaning of "plurality" is two or more.

[0089] In the embodiments of the present disclosure, the collection, storage, use, processing, transmission, provision and disclosure of user personal information involved are in compliance with the provisions of relevant laws and regulations and do not violate public order and good morals.

[0090] like Figure 1 As shown, the clamping circuit with pre-charge control in the conventional single-ended sense amplifier includes a pre-charge switch PM0, a first clamping MOS tube NM0 of the pre-charge path, a second clamping MOS tube NM1, and a voltage stabilizing capacitor NM4, and the reference current comparison circuit includes a group of NMOS current mirrors NM2 and NM3, a group of PMOS current mirrors PM1 and PM2, and a buffer BUF; wherein, the gates of NM0 and NM1 are both connected to a signal BLRD, which is used to control the voltage of a data line signal DL of a storage unit in a read operation, and the gates of NM2 and NM3 are both connected to a reference voltage signal VREF, the width-to-length ratio of NM3 is twice that of NM2, and VREF is generated by a reference current source or a current of a ref cell, so that the current flowing through NM3 is used as a reference to distinguish the size of the storage unit current icell.

[0091] In the actual operation of the traditional single-ended sense amplifier, when the precharge signal PRECHARGE is 0, the data line of the storage cell starts to be precharged, and the power supply terminal VDD forms a path with PM1 and the data line of the storage cell, and the storage cell current icell of the data line signal DL can be read from the storage cell. At this time, the drain and source voltages of NM0 and NM1 increase, and the parasitic capacitance of the two MOS tubes NM0 and NM1 will also make the BLRD signal high, and NM4, as a voltage-stabilizing capacitor device, suppresses this change, thereby ensuring the stability of BLRD. Among them, the typical time value of the PRECHARGE signal being 0 is 10ns; at the same time, under the action of VREF, a reference current iref will be generated on NM2, PM1 and PM2 are PMOS current mirrors with a current ratio of 1:1, and NM2 and NM3 are NMOS current mirrors with a current ratio of 1:2. Therefore, in DC (direct current state), the current flowing through PM2 is icell+iref, and the current flowing through NM3 is iref+iref. Buffer BUF converts the comparison result of PM2 current and NM3 current into a digital signal output, wherein, if icell>iref, the output signal SAOUT=1, and the read data is 1; if icell<iref current, SAOUT=0, and the read data is 0.

[0092] If the conventional single-ended sense amplifier works for a long enough time in the DC state, the above conditions will be met, and the accurate output signal SAOUT can be obtained by comparing the current of PM2 and the current of NM3. However, if it is in the AC state, some changes will occur. Since NM1 works in the saturation region, the current iNM1 flowing through NM1 can be calculated by the following formula:

[0093]

[0094] in, is the electron mobility, represents the gate oxide capacitance per unit area, and is a constant coefficient, represents the voltage of the signal BLRD, Represents the voltage of the data line signal DL, represents the threshold voltage of NM1, and W and L represent the width and length of NM1, respectively.

[0095] In the actual operation of the traditional single-ended sense amplifier under AC conditions, due to the ground voltage V GND Jitter will occur, not a true zero. When the IO (input and output port) of the Nor Flash read operation flips, it will generate a lot of noise. When the 4 IOs flip from all 1 to all 0, GND will rise significantly. For example, V GNDIt rises by 0.7V. Since NM4 is a relatively large capacitor, the coupling effect of the capacitor will make BLRD higher. For example, The data line of the storage unit also has a large parasitic capacitance, but it is not necessarily the capacitance to ground. The increase ratio is smaller than that of GND. For example, Increase by 0.3V, so the voltage V of NM1 GS will become high; and because the substrate of NM1 is grounded, when V GND When GND increases, the substrate voltage of NM1 also increases. The substrate and source of NM1 are not connected together, and the two are not at the same potential. The substrate bias effect of NM1 causes the threshold voltage of NM1 to decrease, for example, by 0.2V. Therefore, when GND increases, the driving voltage of NM1 will increase. It will become larger, causing the AC current flowing through NM1 to increase, and the data originally 0 in the storage unit will be misread as 1.

[0096] Assume iref=10uA, the original data in the storage unit is 0, icell=5uA read when not affected, the current flowing through PM2 is icell+iref=15uA, the current flowing through NM3 is iref+iref=20uA, then SAOUT=0, the output result is correct; but when power supply noise occurs, the current flowing through PM2 is icell+iref and becomes 25uA, then SAOUT=1, the output result is wrong.

[0097] Therefore, in order to address the defect that traditional single-ended sense amplifiers are prone to misjudgment and cannot accurately read data in a power supply noise environment, a single-ended sense amplifier circuit, a memory read circuit and a memory are provided, which significantly reduce the current change of the first transistor and the second transistor in the power supply noise environment, thereby improving the noise resistance of the sense amplifier, ensuring the accuracy of the Nor Flash read data, and meeting the needs of the Nor Flash high-speed read operation.

[0098] Example 1

[0099] In a specific embodiment of the present disclosure, a single-ended sense amplifier circuit is provided, such as Figure 2 As shown, the single-ended sense amplifier circuit includes a clamp circuit 1 with pre-charge control and a reference current comparison circuit 2;

[0100] The clamp circuit 1 with pre-charge control includes a noise reduction unit 11, and the noise reduction unit 11 is connected to a reference current comparison circuit 2;

[0101] The clamp circuit 1 with precharge control is connected to the storage unit, and the clamp circuit 1 with precharge control is used to read the operation signal;

[0102] The noise reduction unit 11 is used to reduce the fluctuation amount of the operating signal when the single-ended sensitive amplifier generates power supply noise fluctuation;

[0103] The reference current comparison circuit 2 is used to compare the operation signal processed by the noise reduction unit 11 with the reference signal and output target data.

[0104] Specifically, a noise reduction unit 11 capable of reducing the fluctuation amount of the operation signal under the power supply noise fluctuation state is provided in the clamp circuit 1 with precharge control, and the noise reduction unit 11 is connected to the reference current comparison circuit 2 and the storage unit respectively. When the precharge signal PRECHARGE is 0, the data line of the storage unit starts to precharge the read operation signal (for example, read the storage unit current icell), and the operation signal is transmitted to the reference current comparison circuit 2 after noise reduction processing by the noise reduction unit 11. The reference current comparison circuit 2 compares the operation signal with the reference signal (for example, the reference current iref), and outputs the target data of 0 or 1 corresponding to the storage unit according to the comparison result.

[0105] Among them, when there is power supply noise, the noise reduction unit can reduce the fluctuation of the operation signal, so that the operation signal transmitted to the reference current comparison current has higher accuracy, improves the anti-noise ability of the sensitive amplifier, ensures the accuracy of the read target data of 0 or 1, and meets the needs of high-speed reading operations.

[0106] This specific implementation scheme targets the fundamental reason why the traditional single-ended sense amplifier in Nor Flash is interfered with in a power supply noise environment. A noise reduction unit is set in the single-ended sense amplifier circuit to reduce the fluctuation of the operating signal in the power supply noise environment, thereby improving the noise resistance of the sense amplifier, ensuring the accuracy of the Nor Flash read data and meeting the requirements of the NorFlash high-speed read operation.

[0107] Example 2

[0108] As a further improvement of Example 1, Figure 2-3 As shown, the clamping circuit 1 with pre-charge control in the sense amplifier circuit further includes a pre-charge switch PM0 and a capacitor unit 12; the reference current comparison circuit 2 includes a first current mirror 21, a second current mirror 22 and a buffer 23; the noise reduction unit 11 includes a first transistor XNM0 and a second transistor XNM1; the first transistor XNM0 and the second transistor XNM1 are both double-well NMOS transistors;

[0109] The first transistor XNM0 includes a first body electrode, a first substrate electrode, a first source electrode, a first gate electrode and a first drain electrode; the second transistor XNM1 includes a second body electrode, a second substrate electrode, a second source electrode, a second gate electrode and a second drain electrode; the first source electrode, the first substrate electrode, the second source electrode and the second substrate electrode are connected to the storage unit, and the first body electrode and the second body electrode are connected to the power supply terminal; the first drain electrode is connected to the power supply terminal via the pre-charge switch PM0, and the first gate electrode and the second gate electrode are connected to the capacitor unit 12; the second source electrode and the second drain electrode are respectively connected to the reference current comparison circuit 2;

[0110] The second source is used to read the storage cell current, and the storage cell current and the reference current form a clamping current flowing through the second drain; the first current mirror 21 is used to output the clamping current with a current ratio of 1:1; the second current mirror 22 is used to output the reference current with a current ratio of 1:2; the buffer 23 is used to convert the comparison current into a digital signal output, and the comparison current is the difference between the clamping current output through the first current mirror 21 and the reference current output through the second current mirror 22.

[0111] Specifically, in order to improve the anti-noise capability of the sense amplifier, this embodiment targets the fundamental reason why the traditional single-ended sense amplifier is interfered in a power supply noise environment, and adopts double-well NMOS transistors XNM0 and XNM1 to replace NM0 and NM1 in the traditional single-ended sense amplifier, and connects the first source and the first substrate of XMN0 together, and the second source and the second substrate of XNM1 together, so that the source and the substrate of XNM0 and XNM1 are at the same voltage, and there is no voltage difference, thereby eliminating the substrate bias effect and reducing the forward current and reverse recovery time.

[0112] When the single-ended sense amplifier has large GND noise, such as GND is raised, the threshold voltage V th It will not change with GND noise, and the clamping current (icell+iref) flowing through the second drain of XNM1 is more accurate, thereby ensuring the accuracy of the comparison current, avoiding misreading, improving the noise resistance of the sensitive amplifier, ensuring the accuracy of the Nor Flash read data, and meeting the needs of Nor Flash high-speed read operations.

[0113] In a specific embodiment, Figure 4 As shown, the first current mirror 21 includes a first PMOS transistor and a second PMOS transistor, and the second current mirror 22 includes a first NMOS transistor and a second NMOS transistor;

[0114] The first PMOS tube includes a fourth source, a fourth gate and a fourth drain;

[0115] The second PMOS tube includes a fifth source, a fifth gate and a fifth drain;

[0116] The first NMOS tube includes a sixth source, a sixth gate and a sixth drain;

[0117] The second NMOS tube includes a seventh source, a seventh gate and a seventh drain;

[0118] The fourth source and the fifth source are connected to the power supply terminal, and the fourth gate, the fourth drain and the fifth gate are connected to the second drain;

[0119] The sixth drain is connected to the second source, the sixth gate and the seventh gate are connected to the reference voltage, and the sixth source and the seventh source are grounded;

[0120] The fifth drain and the seventh drain are connected to the buffer 23 .

[0121] Specifically, the first current mirror 21 is a PMOS current mirror, including a first PMOS tube PM1 and a second PMOS tube PM2. The fourth gate and the fourth drain of PM1 and the fifth gate of PM2 are all connected to the second drain of XNM1. The fifth drain of PM2 is connected to the buffer 23 as the output of the PMOS current mirror, and the current ratio of PM1 and PM2 is set to 1:1 to compare the clamp current replica output flowing through the second drain of XNM1 with the reference current.

[0122] The second current mirror 22 is an NMOS current mirror, including a first NMOS tube NM2 and a second NMOS tube NM3. The sixth gate of NM2 and the seventh gate of NM3 are both connected to the reference voltage, the sixth drain of NM2 is connected to the second source of XNM1, and the seventh drain of NM3 is connected to the buffer 23 as the output of the NMOS current mirror, and the current ratio of NM1 and NM2 is set to 1:2 to compare the reference current copy output with the clamping current.

[0123] As a preferred embodiment, Figure 5 As shown, the capacitor unit 12 includes a third gate, a third source and a third drain. The capacitance value of the capacitor unit 12 meets the preset conditions. The capacitor unit 12 is used for voltage stabilization and noise reduction. The third gate is connected to the first gate and the second gate, and the third drain is connected to the third source and then connected to the enable signal.

[0124] Specifically, in order to further reduce the power supply noise, the capacitance value of the capacitor unit 12 can be reduced to reduce the coupling effect of the capacitor, thereby suppressing the high ratio of BLRD, that is, reducing Therefore, a small-sized NMOS tube NM5 can be selected as the capacitor unit 12, wherein the capacitance value of NM5 is smaller than the capacitance value of NM4 in the traditional single-ended sense amplifier (for example, the capacitance value of NM5 is less than ten times the capacitance value of NM4), or the capacitance value of NM5 is smaller than the MOS capacitance value of XNM1 (for example, the capacitance value of NM5 is less than 1 / 5 of the MOS capacitance value of XNM1). Since the small capacitance value of NM5 will reduce the voltage stabilizing effect of the capacitor, in order to ensure the voltage stabilizing effect of NM5, the third drain and the third source of NM5 are connected and connected to the enable signal SAENB of the sense amplifier, so that the capacitor unit 12 provides an additional voltage coupling effect to stabilize the voltage when the read enable signal is flipped, so as to ensure the functions of voltage stabilization and noise reduction.

[0125] This embodiment aims at the fundamental reason why the traditional single-ended sense amplifier in Nor Flash is interfered in the power supply noise environment. A noise reduction unit is set in the single-ended sense amplifier circuit. By controlling the capacitance of its gate terminal, eliminating the substrate bias effect, and reducing the forward current and reverse recovery time, the fluctuation of the operating signal in the power supply noise environment is significantly reduced, so that the anti-noise ability of the sense amplifier is improved, and the accuracy of the Nor Flash read data is ensured, thereby meeting the demand for NorFlash high-speed read operation.

[0126] Example 3

[0127] As a further improvement of Example 1, Figure 6 As shown, the noise reduction unit 11 includes a first transistor and a second transistor;

[0128] The first transistor is connected to the second transistor;

[0129] The first transistor and the second transistor are both NMOS transistors, and a width-to-length ratio of the first transistor to the second transistor is less than a preset threshold;

[0130] The second transistor is connected to the reference current comparison circuit 2 .

[0131] Specifically, considering that the change in clamp current is also affected by the width-to-length ratio W / L of NM0 and NM1, the first transistor and the second transistor having a width-to-length ratio less than a preset threshold value can be used to replace NM0 and NM1 in the conventional single-ended sense amplifier. Since the width-to-length ratio of the first transistor and the second transistor affects the charging time of the capacitor on the data line of the storage unit, the width-to-length ratio of the first transistor and the second transistor can be set according to the requirements of the speed and accuracy of the actual read operation.

[0132] The first transistor and the second transistor may be common NMOS transistors or other special types of NMOS transistors, such as double-well NMOS, triple-well NMOS, etc., which are not limited in this specific implementation.

[0133] This specific implementation reduces the width-to-length ratio of the clamping MOS tube to reduce the change in the clamping current when power supply noise exists, thereby ensuring the accuracy of the comparison current, avoiding misreading, and improving the anti-noise capability of the sensitive amplifier.

[0134] As a preferred implementation, when a double-well NMOS transistor is used to replace NM0 and NM1 in a conventional sense amplifier and the width-to-length ratio of the double-well NMOS transistor is reduced, the fluctuation of the clamping current can be further reduced, and the accuracy of the sense amplifier can be further improved.

[0135] In a specific embodiment, Figure 6-7 As shown, the clamping circuit 1 with pre-charge control further includes a pre-charge switch and a capacitor unit 12;

[0136] The reference current comparison circuit 2 includes a first current mirror 21, a second current mirror 22 and a buffer 23;

[0137] The first transistor NM6 includes an eighth gate, an eighth source and an eighth drain;

[0138] The second transistor NM7 includes a ninth gate, a ninth source and a ninth drain;

[0139] The eighth source and the ninth source are connected to the storage unit;

[0140] The eighth drain is connected to the power supply terminal via the pre-charging switch, and the eighth gate and the ninth gate are connected to the capacitor unit 12;

[0141] The ninth source and the ninth drain are respectively connected to the reference current comparison circuit 2;

[0142] The ninth source is used to read the memory cell current, and the memory cell current and the reference current form a clamping current flowing through the ninth drain;

[0143] The first current mirror 21 is used to output the clamping current with a 1:1 current ratio;

[0144] The second current mirror 22 is used to output a reference current with a current ratio of 1:2;

[0145] The buffer 23 is used to convert the comparison current into a digital signal output, where the comparison current is the difference between the clamp current output via the first current mirror 21 and the reference current output via the second current mirror 22 .

[0146] Specifically, ordinary NMOS transistors NM6 and NM7 with a width-to-length ratio smaller than a preset threshold are used. When the single-ended sense amplifier has large GND noise, such as GND elevation, since NM6 and NM7 have a smaller width-to-length ratio, the clamping current flowing through the ninth drain of NM7 will not change greatly, thereby ensuring the accuracy of the comparison current, avoiding misreading, and improving the noise resistance of the sense amplifier.

[0147] In a specific implementation, the first current mirror 21 includes a first PMOS transistor and a second PMOS transistor, and the second current mirror 22 includes a first NMOS transistor and a second NMOS transistor;

[0148] The first PMOS tube includes a fourth source, a fourth gate and a fourth drain;

[0149] The second PMOS tube includes a fifth source, a fifth gate and a fifth drain;

[0150] The first NMOS tube includes a sixth source, a sixth gate and a sixth drain;

[0151] The second NMOS tube includes a seventh source, a seventh gate and a seventh drain;

[0152] The fourth source and the fifth source are connected to the power supply terminal, and the fourth gate, the fourth drain, the fifth gate and the ninth drain are connected;

[0153] The sixth drain is connected to the ninth source, the sixth gate and the seventh gate are connected to the reference unit, and the sixth source and the seventh source are grounded;

[0154] The fifth drain and the seventh drain are connected to the buffer 23 .

[0155] Specifically, the first current mirror 21 is a PMOS current mirror, including a first PMOS tube and a second PMOS tube. The gate and drain of the first PMOS tube and the second PMOS tube are connected to the drain of NM7. The drain of the second PMOS tube is connected to the buffer 23 as the output of the PMOS current mirror, and the current ratio of PM1 and PM2 is set to 1:1.

[0156] The second current mirror 22 is an NMOS current mirror, including a first NMOS tube and a second NMOS tube. The gates of the first NMOS tube and the second NMOS tube are connected to the reference voltage, the drain of the first NMOS tube is connected to the source of NM7, and the drain of the second NMOS tube is connected to the buffer 23 as the output of the NMOS current mirror, and the current ratio of NM1 and NM2 is set to 1:2.

[0157] In a specific embodiment, Figure 8As shown, the capacitor unit 12 includes a third gate, a third source and a third drain, the capacitance value of the capacitor unit 12 meets the preset conditions, and the capacitor unit 12 is used for voltage stabilization and noise reduction;

[0158] The third gate is connected to the eighth gate and the ninth gate, and the third drain is connected to the third source and then connected to the enable signal;

[0159] Specifically, in order to further reduce the power supply noise, the capacitance value of the capacitor unit 12 can be reduced to reduce the coupling effect of the capacitor, thereby suppressing the high ratio of BLRD, that is, reducing The fluctuation amount. Therefore, a small-sized NMOS tube NM5 can be selected as the capacitor unit 12, wherein the capacitance value of NM5 is smaller than the capacitance value of NM4 in the traditional single-ended sense amplifier (for example, the capacitance value of NM5 is less than ten times the capacitance value of NM4), or the capacitance value of NM5 is smaller than the MOS capacitance value of NM7 (for example, the capacitance value of NM5 is less than 1 / 5 of the MOS capacitance value of NM7). Since the small capacitance value of NM5 will reduce the voltage stabilizing effect of the capacitor, in order to ensure the voltage stabilizing effect of NM5, the third drain and the third source of NM5 are connected and connected to the enable signal SAENB of the sense amplifier, so that the capacitor unit 12 provides an additional voltage coupling effect to stabilize the voltage when the read enable signal is flipped, so as to ensure the functions of voltage stabilization and noise reduction.

[0160] It should be noted that if a double-well NMOS transistor with a width-to-length ratio less than a preset threshold is used to replace NM0 and NM1 in a traditional single-ended sense amplifier, the circuit connection method in Example 2 can be referred to to further improve the accuracy of the sense amplifier, which will not be described in detail in this embodiment.

[0161] This embodiment aims at the fundamental reason why the traditional single-ended sense amplifier in Nor Flash is interfered in the power supply noise environment. A noise reduction unit is set in the single-ended sense amplifier circuit. By controlling the capacitance of the gate terminal, eliminating the substrate bias effect, and reducing the forward current and reverse recovery time, the fluctuation of the operating signal in the power supply noise environment is significantly reduced, thereby improving the anti-noise ability of the sense amplifier, ensuring the accuracy of the Nor Flash read data, and meeting the requirements of high-speed read operations in Nor Flash.

[0162] Example 4

[0163] As a further improvement of any one of embodiments 1 to 3, Fig. 9As shown, the noise reduction unit 11 includes a first transistor, a second transistor and a noise reduction capacitor; the noise reduction capacitor includes a capacitor gate, a capacitor source and a capacitor drain, the capacitance of the noise reduction capacitor meets the preset conditions, and the noise reduction capacitor is used for voltage stabilization and noise reduction; the capacitor gate is connected to the first transistor, and the capacitor drain is connected to the capacitor source and then connected to the enable signal; the first transistor is connected to the second transistor; the second transistor is connected to the first current mirror 21 and the second current mirror 22 in the reference current comparison circuit 2 to transmit the comparison current to the buffer 23, and the buffer 23 converts the comparison current into a digital signal output.

[0164] Specifically, considering that the coupling effect of the voltage stabilizing capacitor will affect The fluctuation amount, therefore, a small-sized NMOS tube NM8 is used as a noise reduction capacitor, which together with the first transistor NM0 and the second transistor NM1 constitutes a noise reduction unit 11. Among them, the capacitance value of NM8 is smaller than the capacitance value of NM4 in the traditional single-ended sense amplifier (for example, the capacitance value of NM8 is less than more than ten times the capacitance value of NM4), or the capacitance value of NM8 is smaller than the MOS capacitance value of NM1 (for example, the capacitance value of NM8 is less than 1 / 5 of the MOS capacitance value of NM1). Since the small capacitance value of NM8 will reduce the voltage stabilizing effect of the capacitor, in order to ensure the voltage stabilizing effect of NM8, the third drain and the third source of NM8 are connected, and the enable signal SAENB of the sense amplifier is connected, so that the NM8 provides an additional voltage coupling effect to stabilize the voltage when the read enable signal is flipped, so as to ensure the functions of voltage stabilization and noise reduction.

[0165] The first transistor and the second transistor may be any type of NMOS transistor, for example, a common NMOS, a double-well NMOS, etc., which is not limited in this specific implementation.

[0166] The specific circuit structure of the first transistor and the second transistor of the ordinary NMOS is shown in Example 3, and the specific circuit structure of the first transistor and the second transistor of the double-well NMOS is shown in Example 2. The specific circuits and their implementation principles are not repeated here.

[0167] This embodiment aims at the fundamental reason why the traditional single-ended sense amplifier in Nor Flash is interfered in the power supply noise environment. A noise reduction unit is set in the single-ended sense amplifier circuit. By controlling the capacitance size of its gate terminal, the fluctuation of the operating signal in the power supply noise environment is reduced, so that the anti-noise ability of the sense amplifier is improved, the accuracy of the Nor Flash read data is ensured, and the demand for high-speed read operation of Nor Flash is met.

[0168] Example 5

[0169] In a specific embodiment of the present disclosure, a memory read circuit is provided. The memory read circuit includes the single-ended sense amplifier circuit described in any of the above embodiments.

[0170] In a specific example, if Fig.10 As shown, the horizontal axis represents time / ns (nanoseconds), and the vertical axis represents the voltage value of different signals. The two dotted lines in the figure correspond to the voltage values ​​corresponding to different voltage signals at two moments. For example, the voltage value of the voltage signal saout at the first dotted line moment is 3.12V, and the voltage value at the second dotted line moment is 235.0mV. It can be seen that the simulation results of the traditional single-ended sense amplifier with power supply noise at 3.7V voltage, the clock frequency is 133MHz, and under the noise condition where VDD is reduced to 2.9V and GND is raised to 0.7V, it can be seen that the output signal SAOUT of the traditional single-ended sense amplifier used in Nor Flash is changed to 1 due to noise interference when it is already 0.

[0171] And as Fig.11 As shown, the simulation results of the single-ended sense amplifier of the present invention with power supply noise at 3.7V voltage and a clock frequency of 133MHz, when VDD is reduced to 2.9V and GND is raised to 0.7V, the results of the single-ended sense amplifier of the present invention used in Nor Flash also remain correct.

[0172] This embodiment aims at the fundamental reason why the traditional single-ended sense amplifier is interfered in the power supply noise environment. A noise reduction unit is set in the single-ended sense amplifier circuit. By controlling the capacitance of the gate terminal, eliminating the substrate bias effect, and reducing the forward current and reverse recovery time, the fluctuation of the operating signal in the power supply noise environment is significantly reduced, ensuring the accuracy of the read data, thereby improving the anti-noise ability of the sense amplifier and meeting the needs of high-speed reading operations.

[0173] Example 6

[0174] In a specific embodiment of the present disclosure, a memory is provided, the memory comprising the memory reading circuit described in any of the above embodiments. In this embodiment, the memory is specifically Nor Flash.

[0175] This embodiment aims at the fundamental reason why the traditional single-ended sense amplifier is interfered in the power supply noise environment. A noise reduction unit is set in the single-ended sense amplifier circuit. By controlling the capacitance of the gate terminal, eliminating the substrate bias effect, and reducing the forward current and reverse recovery time, the fluctuation of the operating signal in the power supply noise environment is significantly reduced, ensuring the accuracy of the read data, thereby improving the anti-noise ability of the sense amplifier and meeting the needs of high-speed reading operations.

[0176] Although the specific embodiments of the present disclosure are described above, those skilled in the art should understand that this is only an example, and the protection scope of the present disclosure is defined by the appended claims. Those skilled in the art may make various changes or modifications to these embodiments without departing from the principles and essence of the present disclosure, but these changes and modifications all fall within the protection scope of the present disclosure.

Claims

1. A single-ended sense amplifier circuit, characterized in that: The single-ended sense amplifier circuit includes a clamp circuit with pre-charge control and a reference current comparison circuit; The clamp circuit with pre-charge control includes a noise reduction unit, and the noise reduction unit is connected to the reference current comparison circuit; The clamp circuit with pre-charge control is connected to the storage unit, and the clamp circuit with pre-charge control is used to read the operation signal; Wherein, the noise reduction unit is used to reduce the fluctuation amount of the operation signal when the single-ended sensitive amplifier generates power supply noise fluctuation; The reference current comparison circuit is used to compare the operation signal processed by the noise reduction unit with a reference signal and output target data.

2. The single-ended sense amplifier circuit according to claim 1, characterized in that: The noise reduction unit includes a first transistor and a second transistor; The first transistor is connected to the second transistor; The first transistor and the second transistor are both double-well NMOS transistors; The second transistor is connected to the reference current comparison circuit.

3. The single-ended sense amplifier circuit according to claim 2, characterized in that: The clamping circuit with pre-charge control further includes a pre-charge switch, and the noise reduction unit further includes a capacitor unit; The reference current comparison circuit includes a first current mirror, a second current mirror and a buffer; The first transistor includes a first body electrode, a first substrate electrode, a first source electrode, a first gate electrode and a first drain electrode; The second transistor includes a second body electrode, a second substrate electrode, a second source electrode, a second gate electrode and a second drain electrode; The first source electrode, the first substrate electrode, the second source electrode, and the second substrate electrode are connected to the storage unit, and the first body electrode and the second body electrode are connected to the power supply terminal; The first drain is connected to the power supply terminal via the pre-charging switch, and the first gate and the second gate are connected to the capacitor unit; The second source and the second drain are respectively connected to the reference current comparison circuit; The second source is used to read the memory cell current, and the memory cell current and the reference current form a clamping current flowing through the second drain; The first current mirror is used to output the clamping current with a 1:1 current ratio; The second current mirror is used to output the reference current with a current ratio of 1:2; The buffer is used to convert a comparison current into a digital signal for output, wherein the comparison current is a difference between the clamp current output via the first current mirror and the reference current output via the second current mirror.

4. The single-ended sense amplifier circuit according to claim 3, characterized in that: The first current mirror includes a first PMOS tube and a second PMOS tube, and the second current mirror includes a first NMOS tube and a second NMOS tube; The first PMOS tube includes a fourth source, a fourth gate and a fourth drain; The second PMOS tube includes a fifth source, a fifth gate and a fifth drain; The first NMOS tube includes a sixth source, a sixth gate and a sixth drain; The second NMOS tube includes a seventh source, a seventh gate and a seventh drain; The fourth source electrode and the fifth source electrode are connected to the power supply terminal, and the fourth gate electrode, the fourth drain electrode, and the fifth gate electrode are connected to the second drain electrode; The sixth drain is connected to the second source, the sixth gate and the seventh gate are connected to a reference voltage, and the sixth source and the seventh source are grounded; The fifth drain and the seventh drain are connected to the buffer; and / or, The capacitor unit includes a third gate, a third source and a third drain, the capacitance value of the capacitor unit meets a preset condition, and the capacitor unit is used for voltage stabilization and noise reduction; The third gate is connected to the first gate and the second gate, and the third drain is connected to the third source and then connected to an enable signal; and / or, The capacitance value of the capacitor unit is smaller than the MOS capacitance value of the second transistor.

5. The single-ended sense amplifier circuit according to claim 1, characterized in that: The noise reduction unit includes a first transistor and a second transistor; The first transistor is connected to the second transistor; The first transistor and the second transistor are both NMOS transistors, and a width-to-length ratio of the first transistor and the second transistor is less than a preset threshold; The second transistor is connected to the reference current comparison circuit.

6. The single-ended sense amplifier circuit according to claim 5, characterized in that: The clamping circuit with pre-charge control further includes a pre-charge switch, and the noise reduction unit further includes a capacitor unit; The reference current comparison circuit includes a first current mirror, a second current mirror and a buffer; The first transistor includes an eighth gate, an eighth source and an eighth drain; The second transistor includes a ninth gate, a ninth source and a ninth drain; The eighth source and the ninth source are connected to the storage unit; The eighth drain is connected to the power supply terminal via the pre-charging switch, and the eighth gate and the ninth gate are connected to the capacitor unit; The ninth source and the ninth drain are respectively connected to the reference current comparison circuit; The ninth source is used to read the memory cell current, and the memory cell current and the reference current form a clamping current flowing through the ninth drain; The first current mirror is used to output the clamping current with a 1:1 current ratio; The second current mirror is used to output the reference current with a current ratio of 1:2; The buffer is used to convert a comparison current into a digital signal for output, wherein the comparison current is a difference between the clamp current output via the first current mirror and the reference current output via the second current mirror.

7. The single-ended sense amplifier circuit according to claim 6, characterized in that: The first current mirror includes a first PMOS tube and a second PMOS tube, and the second current mirror includes a first NMOS tube and a second NMOS tube; The first PMOS tube includes a fourth source, a fourth gate and a fourth drain; The second PMOS tube includes a fifth source, a fifth gate and a fifth drain; The first NMOS tube includes a sixth source, a sixth gate and a sixth drain; The second NMOS tube includes a seventh source, a seventh gate and a seventh drain; The fourth source electrode and the fifth source electrode are connected to the power supply terminal, and the fourth gate electrode, the fourth drain electrode, the fifth gate electrode and the ninth drain electrode are connected; The sixth drain is connected to the ninth source, the sixth gate and the seventh gate are connected to a reference unit, and the sixth source and the seventh source are grounded; The fifth drain and the seventh drain are connected to the buffer; and / or, The capacitor unit includes a third gate, a third source and a third drain, the capacitance value of the capacitor unit meets a preset condition, and the capacitor unit is used for voltage stabilization and noise reduction; The third gate is connected to the eighth gate and the ninth gate, and the third drain is connected to the third source and then connected to an enable signal; and / or, The capacitance value of the capacitor unit is smaller than the MOS capacitance value of the second transistor.

8. The single-ended sense amplifier circuit according to claim 1, characterized in that: The noise reduction unit includes a first transistor, a second transistor and a noise reduction capacitor; The noise reduction capacitor comprises a capacitor gate, a capacitor source and a capacitor drain, the capacitance of the noise reduction capacitor meets a preset condition, and the noise reduction capacitor is used for voltage stabilization and noise reduction; The capacitor gate is connected to the first transistor, the capacitor drain is connected to the capacitor source and then connected to an enable signal; The first transistor is connected to the second transistor; The second transistor is connected to the reference current comparison circuit.

9. A memory read circuit, characterized in that: The memory read circuit comprises a single-ended sense amplifier circuit as claimed in any one of claims 1 to 8.

10. A memory, characterized in that: The memory comprises the memory read circuit as claimed in claim 9.

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