Chip packaging structure

Abstract

The invention relates to a chip packaging structure, and relates to the technical field of packaging, and the chip packaging structure comprises a substrate, and a transmission line and a chip which are located at one side of the substrate and are arranged at an interval; the connecting bridge structure comprises a first connecting part and a second connecting part which are connected with each other; the first connecting part is connected with the transmission line, and the second connecting part is connected with the chip. According to the chip packaging structure, the transmission line and the chip are connected by adopting the first connecting part and the second connecting part of the connecting bridge structure, and the width of the first connecting part in the first direction is greater than the preset width, so that the parasitic inductance between the chip and the transmission line is reduced. The parasitic inductance and the capacitance of the chip can generate a resonance effect, the parasitic inductance between the transmission line and the chip is reduced, the generated resonance effect can increase the modulation bandwidth of the chip packaging structure, and the use rate of the chip packaging structure is further increased.

Description

Technical Field

[0001] The present application relates to the field of packaging technology, and in particular to a chip packaging structure. Background Art

[0002] In short-distance applications, although directly modulated lasers (DMLs) have the advantages of low cost and low power consumption, their modulation bandwidth and transmission distance are limited by relaxation oscillation frequency and frequency chirp. Electro-absorption modulated laser (EML) integrated light sources have the characteristics of large modulation bandwidth and low frequency chirp. Compared with directly modulated lasers, electro-absorption modulated lasers have advantages in chirp effect, extinction ratio, eye diagram, jitter, transmission distance and other performances, and can achieve higher speed and longer distance transmission.

[0003] The frequency response of the existing electro-absorption modulated laser is strongly dependent on the load resistance and the length of the bonding wire. However, the modulation bandwidth increased by adjusting the length of the bonding wire is small and cannot significantly increase the use rate of the electro-absorption modulated laser.

[0004] Based on this, how to improve the modulation bandwidth of the lumped electro-absorption modulated laser without changing the chip structure has become a technical problem that technical personnel in this field need to solve urgently. Summary of the invention

[0005] Based on this, it is necessary to provide a chip packaging structure for the problem of how to improve the modulation bandwidth of the lumped electro-absorption modulated laser without changing the chip structure.

[0006] In order to achieve the above object, on the one hand, the present invention provides a chip packaging structure, the chip packaging structure comprising:

[0007] substrate;

[0008] A transmission line and a chip are located on one side of the substrate and are spaced apart from each other;

[0009] A connecting bridge structure, the connecting bridge structure comprising a first connecting portion and a second connecting portion connected to each other; the first connecting portion is connected to the transmission line, and the second connecting portion is connected to the chip;

[0010] Wherein, the width of the first connecting portion in the first direction is greater than a preset width; and the first direction is parallel to the plane where the substrate is located.

[0011] In one embodiment, the chip packaging structure further includes:

[0012] a plurality of first elements located on one side of the substrate;

[0013] The connecting bridge structure further includes a third connecting portion and a fourth connecting portion connected to each other, the third connecting portion is connected to at least one of the first elements, and the fourth connecting portion is connected to the chip.

[0014] In one embodiment, the first element includes a first pad; and a width of the third connecting portion in the first direction is smaller than a width of the first pad in the first direction.

[0015] In one embodiment, the second connection portion is connected to the fourth connection portion.

[0016] In one embodiment, in a direction perpendicular to the plane where the substrate is located, the thickness of the second connecting portion is greater than the thickness of the fourth connecting portion.

[0017] In one embodiment, a width of the first connecting portion in the first direction is greater than or equal to a width of the transmission line in the first direction.

[0018] In one embodiment, the widths of the connecting bridge structures in a second direction are the same, and the second direction is parallel to the plane where the substrate is located and perpendicular to the first direction.

[0019] In one embodiment, the width of the connecting bridge structure in the second direction is in the range of 50 μm-300 μm.

[0020] In one embodiment, the chip packaging structure further includes:

[0021] A conductive layer is located between the transmission line and the connection bridge structure and between the chip and the connection bridge structure.

[0022] In one embodiment, the material of the connecting bridge structure includes one or more combinations of copper-tungsten alloy material, copper-molybdenum alloy material, Kovar alloy material, copper material, aluminum metal, and iron metal.

[0023] Compared with the prior art, the above technical solution has the following advantages:

[0024] The present application provides a chip packaging structure, including a substrate, and a transmission line and a chip located on one side of the substrate and spaced apart; a connecting bridge structure, the connecting bridge structure including a first connecting portion and a second connecting portion connected to each other; the first connecting portion is connected to the transmission line, and the second connecting portion is connected to the chip. Since the first connecting portion and the second connecting portion of the connecting bridge structure are used to connect the transmission line and the chip in the chip packaging structure, and the width of the first connecting portion in the first direction is greater than the preset width, the parasitic inductance between the chip and the transmission line is reduced. The parasitic inductance and the capacitance of the chip will produce a resonance effect, and the parasitic inductance between the transmission line and the chip will decrease. The generated resonance effect will increase the modulation bandwidth of the chip packaging structure, further increasing the usage rate of the chip packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0026] Figure 1 A schematic cross-sectional structure diagram of a chip packaging structure is provided for an embodiment of the present application;

[0027] Figure 2 A schematic cross-sectional structure diagram of another chip packaging structure is provided for an embodiment of the present application;

[0028] Figure 3 A schematic diagram of a top view of a chip packaging structure is provided for an embodiment of the present application;

[0029] Figure 4 for Figure 3 Schematic diagram of the cross-sectional structure along AA';

[0030] Figure 5 A schematic cross-sectional structure diagram of another chip packaging structure is provided for an embodiment of the present application;

[0031] Figure 6 A schematic cross-sectional structure diagram of another chip packaging structure is provided for an embodiment of the present application;

[0032] Figure 7 A schematic cross-sectional structure diagram of another chip packaging structure is provided for an embodiment of the present application;

[0033] Figure 8 A schematic cross-sectional structure diagram of another chip packaging structure is provided for an embodiment of the present application;

[0034] Figure 9-12A schematic diagram of simulation results of a chip packaging structure provided in an embodiment of the present application.

[0035] Explanation of the figure markings: 01-substrate; 02-transmission line; 03-chip; 04-connection bridge structure; 041-first connection part; 042-second connection part; 043-third connection part; 044-fourth connection part; 05-pad layer; 06-first element; 061-first pad; 07-conductive layer; 21-power supply port. DETAILED DESCRIPTION

[0036] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0037] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" etc. specify the presence of stated features, wholes, steps, operations, components, parts or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts or combinations thereof.

[0039] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0040] Please refer to Figure 1 , Figure 1 A schematic cross-sectional structure diagram of a chip packaging structure is provided for an embodiment of the present application; the chip packaging structure comprises:

[0041] A substrate 01, and a transmission line 02 and a chip 03 located on one side of the substrate 01 and spaced apart from each other.

[0042] The connecting bridge structure 04 includes a first connecting portion 041 and a second connecting portion 042 connected to each other; the first connecting portion 041 is connected to the transmission line 02 , and the second connecting portion 042 is connected to the chip 03 .

[0043] The width of the first connection portion 041 in the first direction M is greater than the preset width; the first direction M is parallel to the plane where the substrate 01 is located.

[0044] Specifically, in this embodiment, the chip 03 is an electro-absorption modulated laser chip, and the device formed by the packaged structure thereof after packaging is an electro-absorption modulated laser.

[0045] The material of the substrate 01 may be aluminum nitride ceramic material, silicon material, or quartz material, etc., and is not specifically limited. The transmission line 02 formed on one side of the substrate 01 may be made according to a 50Ω characteristic impedance, and the transmission line 02 is used to transmit signals.

[0046] When the chip 03 is arranged on one side of the substrate 01, it is necessary to first form a pad layer 05 on the substrate 01. The pad layer 05 is a patterned pad layer, that is, the pad layer 05 is arranged between the substrate 01 and other components to be connected to increase firmness. Figure 1 The material of the pad layer 05 can be gold-tin material, tin-silver material, tin-silver-copper material, etc., and is not specifically limited.

[0047] The chip 03 is arranged on the pad layer 05 where the chip 03 is required to be arranged. The chip 03 includes a chip pad 031 for connecting to an external circuit. The first connection portion 041 is connected to the transmission line 02, the second connection portion 042 is connected to the chip 03, and the first connection portion 041 is connected to the second connection portion 042, that is, the chip 03 is connected to the transmission line 02 through the first connection portion 041 and the second connection portion 042.

[0048] The width of the first connection portion 041 in the first direction M is greater than a preset width, which may be the line width of a bonding wire in the packaging structure. In the existing structure, the chip 03 and the transmission line 02 are connected by bonding wires. In the present application, the width of the first connection portion 041 in the first direction M is greater than the line width of the bonding wire, which may greatly reduce the parasitic inductance between the chip 03 and the transmission line 02. The parasitic inductance and the capacitance of the chip produce a resonance effect, which increases the modulation bandwidth of the packaging structure of the chip 03 and ensures a sufficient extinction ratio, further increasing the utilization rate of the chip packaging structure.

[0049] Optional, reference Figure 2 , Figure 2 A schematic cross-sectional structure diagram of another chip packaging structure is provided for an embodiment of the present application; in another embodiment of the present application, a width l of the first connecting portion 041 in the first direction M is greater than or equal to a width L of the transmission line 02 in the first direction M.

[0050] Specifically, the width l of the first connection portion 041 in the first direction M needs to at least cover the width L of the transmission line 02 in the first direction M, so that the resistance of the first connection portion 041 can be increased, thereby reducing the parasitic inductance between the chip 03 and the transmission line 02.

[0051] It should be noted that the width l of the first connection portion 041 in the first direction M can range from 40μm to 200μm, including endpoint values. For example, the width l of the first connection portion 041 in the first direction M can be set to 260μm, 300μm, or 420μm, etc., without specific limitation.

[0052] Optional, reference Figure 3 , Figure 3 A schematic diagram of a top view of a chip packaging structure is provided for an embodiment of the present application; Figure 4 , Figure 4 for Figure 3 A schematic diagram of a cross-sectional structure along AA'; in another embodiment of the present application, the chip packaging structure further includes:

[0053] A plurality of first components 06 are located on one side of the substrate 01 .

[0054] The connecting bridge structure 04 further includes a third connecting portion 043 and a fourth connecting portion 044 which are connected to each other. The third connecting portion 043 is connected to at least one first element 06 , and the fourth connecting portion 044 is connected to the chip 03 .

[0055] Specifically, a plurality of first elements 06 are further disposed on one side of the substrate 01. The first elements 06 may be components such as capacitors and resistors, which are used to form an electro-absorption modulated laser.

[0056] Among them, at least one first element 06 is connected to the chip 03 through the third connection part 043 and the fourth connection part 044, and when connected to the chip 03, it can be connected to the chip pad 031. It should be noted that the third connection part 043 and the fourth connection part 044 can increase the parasitic inductance between the first element 06 and the chip 03. At this time, the parasitic inductance between the chip 03 and the transmission line 02 is reduced, while the parasitic inductance between the chip 03 and the first element 06 is increased, which can work together to increase the modulation width of the chip packaging structure, thereby increasing the use rate of the chip packaging structure.

[0057] In addition, the chip packaging structure also includes a power supply port 21 for providing power to the chip packaging structure.

[0058] Optional, reference Figure 3 And refer to Figure 4In another embodiment of the present application, the first element 06 includes a first pad 061 ; the width of the third connection portion 043 in the first direction M is smaller than the width of the first pad 061 in the first direction M.

[0059] Specifically, when the first component 06 is disposed on one side of the substrate 01, the first component 06 is provided with a first pad 061 for increasing the connection firmness, the first pad 061 has a width B in the first direction M, and the third connection portion 043 has a width b in the first direction M, and b is smaller than B. The third connection portion 043 needs to be set narrower to increase the parasitic inductance between the chip 03 and the first component 06.

[0060] It should be noted that the width b of the third connection portion 043 in the first direction M may be in the range of 200 μm-500 μm, including end values. For example, the width b of the third connection portion 043 in the first direction M is set to 260 μm, 300 μm, or 420 μm. By setting the width b of the third connection portion 043 in the first direction M to be smaller than the width B of the first pad 061 in the first direction M, the parasitic inductance between the chip 03 and the first component 06 can be increased.

[0061] Optional, reference Figure 5 , Figure 5 A schematic cross-sectional structure diagram of another chip packaging structure is provided for an embodiment of the present application; in another embodiment of the present application, the second connection portion 042 is connected to the fourth connection portion 044 .

[0062] Specifically, when the second connection part 042 is connected to the fourth connection part 044 , the connection bridge structure 04 can be formed in one piece, making the preparation easier.

[0063] Optional, reference Figure 6 , Figure 6 A schematic cross-sectional structure diagram of another chip packaging structure is provided for an embodiment of the present application; in another embodiment of the present application, in a direction perpendicular to the plane where the substrate 01 is located, a thickness H of the second connection portion 042 is greater than a thickness h of the fourth connection portion 044.

[0064] Specifically, in order to reduce the parasitic inductance between the chip 03 and the transmission line 02, a thicker thickness can be set to increase the resistance of the second connection part 042, thereby reducing the parasitic inductance. In order to increase the parasitic inductance between the chip 03 and the first element 06, the thickness of the fourth connection part 044 can be set relatively small to reduce the resistance of the fourth connection part, thereby increasing the parasitic inductance. Therefore, in the direction perpendicular to the plane where the substrate 01 is located, setting the thickness H of the second connection part 042 to be greater than the thickness h of the fourth connection part 044 can better achieve the effect of improving the modulation bandwidth, thereby better increasing the use rate of the chip packaging structure.

[0065] Optional, reference Figure 7 , Figure 7 A cross-sectional structural diagram of another chip packaging structure is provided for an embodiment of the present application; in another embodiment of the present application, the width X of the connecting bridge structure 04 in the second direction N is the same, the second direction N is parallel to the plane where the substrate 01 is located, and is perpendicular to the first direction M.

[0066] Specifically, the width X of the connecting bridge structure 04 in the second direction N is the same, which can make the preparation easier.

[0067] Optionally, in another embodiment of the present application, the width X of the connecting bridge structure 04 in the second direction N is in the range of 50 μm-300 μm.

[0068] Specifically, the connecting bridge structure 04 includes a first connecting part 041, a second connecting part 042, a third connecting part 043 and a fourth connecting part 044. During preparation, the widths of the first connecting part 041, the second connecting part 042, the third connecting part 043 and the fourth connecting part 044 in the second direction N can be set to be the same, and there is no specific limitation on this.

[0069] When the widths of the first connection portion 041, the second connection portion 042, the third connection portion 043 and the fourth connection portion 044 in the second direction N are the same, the width X of the connection bridge structure 04 in the second direction N can range from 50μm to 300μm, including endpoint values. For example, the width X of the connection bridge structure 04 in the second direction N can be 100μm or 150μm or 220μm, etc., without any specific limitation.

[0070] It should be noted that when the connecting bridge structure 04 is used for connection, the distance between the second connecting part 042 and the fourth connecting part 044 and the substrate 01 can be set according to the height of the specific chip 03. Preferably, it can be 100μm or 150μm. There is no specific limitation on this. It only needs to set the chip 03 thereunder.

[0071] Optional, reference Figure 8 , Figure 8 A schematic cross-sectional structure diagram of another chip packaging structure is provided for an embodiment of the present application; in another embodiment of the present application, the chip packaging structure further includes:

[0072] Conductive layer 07 , the conductive layer 07 is located between the transmission line 02 and the connecting bridge structure 04 and between the chip 03 and the connecting bridge structure 04 .

[0073] Specifically, the conductive layer 07 is disposed between the transmission line 02 and the connection bridge structure 04 and between the chip 03 and the connection bridge structure 04, which can increase the conductivity between the chip 03 and the transmission line 02, thereby further ensuring the performance of the device.

[0074] In addition, when the connecting bridge structure 04 includes the third connecting portion 043 and the fourth connecting portion 044 , a conductive layer 07 is also disposed between the first pad 061 of the first element 06 and the third connecting portion 043 , which can increase the conductivity between the chip 03 and the first element 06 .

[0075] It should be noted that the material of the conductive layer 07 can be silver glue or solder, such as gold-tin alloy material, tin-silver-copper alloy material, etc. The conductive method of the conductive layer 07 is used to connect the connecting bridge structure 04 across the area in the first direction M to ensure that it is completely and tightly connected with the three positions, which can increase the conductive performance of the chip packaging structure.

[0076] Optionally, in another embodiment of the present application, the material of the connecting bridge structure 04 includes one or more combinations of copper-tungsten alloy material, copper-molybdenum alloy material, Kovar alloy material, copper material, aluminum metal, iron metal, etc.

[0077] Specifically, in this embodiment, the metal connecting bridge can be processed by powder metallurgy. The material of the connecting bridge structure 04 includes but is not limited to one or more combinations of copper-tungsten alloy materials, copper-molybdenum alloy materials, Kovar alloy materials, copper materials, aluminum metal, and iron metal. Compared with the existing connection using bonding wires, the connecting bridge structure in the present application has a larger contact area and a more secure connection.

[0078] Based on the above chip packaging structure, the present application also provides simulation results of the chip packaging structure after adopting the connecting bridge structure 04 to further prove its effect. Figure 9-12 , Figure 9-12 A schematic diagram of simulation results of a chip packaging structure provided in an embodiment of the present application. Fig. 9 and Fig.11 is the transmission coefficient diagram S21, Fig.10 and Fig.12 is the reflection coefficient Figure S11.

[0079] When the total length Lm of the third connection portion 043 and the fourth connection portion 044 between the first element 06 and the chip 03 is 0 μm, and the total length Ls of the first connection portion 041 and the second connection portion 042 between the transmission line 02 and the chip 03 are 0 μm, 200 μm, 400 μm, 600 μm, 800 μm, and 1000 μm, respectively, Fig. 9 The transmission coefficients of Figure S21 and Fig.10The reflection coefficient of Figure S11, where the shorter Ls is, the smaller the parasitic inductance is. Fig. 9 It can be seen that the smaller the parasitic inductance, the higher the S21 curve and the wider the bandwidth. Fig.10 It can be seen that the smaller the parasitic inductance, the smaller S11 and the smaller the signal reflection.

[0080] For a wider modulation bandwidth, Ls is selected to be as small as possible, that is, the parasitic inductance is reduced. Increasing the width of the first connection portion 041 can reduce the parasitic inductance. At this time, the larger the width of the first connection portion 041 in the first direction M, the smaller the parasitic inductance between the chip 03 and the transmission line 02.

[0081] When the total length Ls of the first connection portion 041 and the second connection portion 042 between the transmission line 02 and the chip 03 is 0 μm, and the total length Lm of the third connection portion 043 and the fourth connection portion 044 between the first element 06 and the chip 03 is 0 μm, 200 μm, 400 μm, 600 μm, 800 μm, and 1000 μm, respectively, Fig.11 The transmission coefficients of Figure S21 and Fig.12 The reflection coefficient is shown in Figure S11, where the longer Lm is, the larger the parasitic inductance is. Fig.11 It can be seen that the longer Lm is, the larger the parasitic inductance is, the higher the S21 curve is, and the bandwidth becomes higher. However, when Lm is the longest, it can be seen that the peak value of the curve is also higher, which will cause overshoot in subsequent use. Therefore, Lm cannot be too short or too long, and needs to be within the preset range. Fig.12 It can be seen that the longer Lm is, the greater the parasitic inductance is, the lower the S11 curve is, and the smaller the signal reflection is, so Lm needs to be as long as possible, but too long will also cause a valley peak to appear in the S11 curve, so Lm needs to be kept within a preset range. Therefore, the width of the third connecting portion 043 in the first direction M is set to be smaller than the width of the first pad 061 in the first direction M as the preset width, and the range has been described above and will not be repeated here.

[0082] Obviously, reducing the parasitic inductance between the transmission line 02 and the chip 03 and increasing the parasitic inductance between the chip 03 and the first element 06 to a certain extent can increase the modulation bandwidth of the chip packaging structure and further increase the utilization rate of the chip packaging structure.

[0083] In the description of this specification, the description with reference to the terms "some embodiments", "another embodiment", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0084] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0085] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A chip packaging structure, characterized in that: The chip packaging structure comprises: substrate; A transmission line and a chip are located on one side of the substrate and are spaced apart from each other; A connecting bridge structure, the connecting bridge structure comprising a first connecting portion and a second connecting portion connected to each other; the first connecting portion is connected to the transmission line, and the second connecting portion is connected to the chip; Wherein, the width of the first connecting portion in the first direction is greater than a preset width; and the first direction is parallel to the plane where the substrate is located.

2. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes: a plurality of first elements located on one side of the substrate; The connecting bridge structure further includes a third connecting portion and a fourth connecting portion connected to each other, the third connecting portion is connected to at least one of the first elements, and the fourth connecting portion is connected to the chip.

3. The chip packaging structure according to claim 2, characterized in that: The first element includes a first pad; and a width of the third connection portion in the first direction is smaller than a width of the first pad in the first direction.

4. The chip packaging structure according to claim 2, characterized in that: The second connection portion is connected to the fourth connection portion.

5. The chip packaging structure according to claim 2, characterized in that: In a direction perpendicular to a plane where the substrate is located, a thickness of the second connecting portion is greater than a thickness of the fourth connecting portion.

6. The chip packaging structure according to claim 1, characterized in that: A width of the first connection portion in the first direction is greater than or equal to a width of the transmission line in the first direction.

7. The chip packaging structure according to claim 1, characterized in that: The widths of the connecting bridge structures in a second direction are the same. The second direction is parallel to the plane where the substrate is located and perpendicular to the first direction.

8. The chip packaging structure according to claim 7, characterized in that: The width of the connecting bridge structure in the second direction is in a range of 50 μm to 300 μm.

9. The chip packaging structure according to claim 1, characterized in that: The chip packaging structure further includes: A conductive layer is located between the transmission line and the connection bridge structure and between the chip and the connection bridge structure.

10. The chip packaging structure according to claim 1, characterized in that: The material of the connecting bridge structure includes one or more combinations of copper-tungsten alloy material, copper-molybdenum alloy material, Kovar alloy material, copper material, aluminum metal, and iron metal.

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