Self-adaptive DAC (Digital-to-Analog Converter) synchronization device and method suitable for high-speed data transmission modulation

Abstract

The invention relates to a self-adaptive DAC (Digital-to-Analog Converter) synchronization device and method suitable for high-speed data transmission modulation, and the method comprises the following steps: fixing the phase of an SYNC signal of one DAC chip, traversing and adjusting the phase of the SYNC signal of the other DAC chip, and simultaneously carrying out phase discrimination on the phase of an output clock of the DAC chip to find out the phase difference between the SYNC signals when the output clocks of the two DAC chips are synchronized; and SYNC signals of the two DAC chips are output according to the phase difference, so that sampling clock synchronization of the two DAC chips is realized.

Description

Technical Field

[0001] The invention relates to an adaptive DAC synchronization implementation method suitable for high-speed data transmission modulation, belongs to the field of satellite data processing and transmission, and can be used in the design of data transmission requiring high-speed high-order modulation such as satellite-borne high-speed data transmission modulator. Background Art

[0002] In order to meet the needs of downlinking massive payload data on the satellite, a higher-rate high-order modulation method is required for downlinking satellite data. The modulation data rate for high-speed data transmission is as high as 2.4GHz. High-speed DAC devices will complete the key digital / analog conversion function. In engineering implementation, two high-speed DACs are required to perform high-sampling-rate digital / analog conversion at the same time. How to ensure data synchronization between the two high-speed DAC chips at high sampling rates has become a key issue, and its synchronization performance directly affects the modulation performance.

[0003] Patent CN201710283876.5 discloses a DAC synchronization circuit for outputting an orthogonal modulator based on dual-loop frequency synthesis. The DAC synchronization circuit includes an I-channel frequency synthesizer, a Q-channel frequency synthesizer, an I-channel DAC, a Q-channel DAC, and a variable delay module. The I-channel frequency synthesizer generates the sampling clock required by the I-channel DAC. The I-channel DAC performs 1 / N frequency division processing on the I-channel DAC sampling clock, and sends one channel to the I-channel and Q-channel of the orthogonal modulator, so that the I-channel and Q-channel data of the orthogonal modulator are synchronously processed and output according to the I-channel frequency division clock. The other channel is output to the Q-channel frequency synthesizer after phase delay; the Q-channel frequency synthesizer uses the I-channel frequency division clock as a reference signal, performs phase detection, low-pass filtering, and N-multiplication of the Q-channel frequency division clock output by the Q-channel DAC, and generates the Q-channel DAC sampling clock. This solves the problem of asynchronous output data of the I / Q-channel high-speed DAC of the satellite-borne high-reliability modulator. This method uses an external frequency synthesizer and a variable delay module to realize synchronous detection of the DAC and phase shift the DAC clock. This method is not suitable for high-speed devices, consumes a lot of hardware resources, and has poor scalability. Summary of the invention

[0004] The technical problem solved by the present invention is to overcome the deficiencies of the prior art, provide an adaptive DAC synchronization device and method suitable for high-speed digital transmission modulation, and solve the synchronization problem of DAC in a high-speed transmission mode.

[0005] The solution to the technical problem of the present invention is: an adaptive DAC synchronization device suitable for high-speed data transmission modulation, used to achieve data synchronization between two DAC chips, the two DAC chips share a sampling clock, and divide the sampling clock to obtain an output clock; the synchronization device includes a phase detection module, a phase delay module, and a synchronization control module;

[0006] The phase detection module is used for phase detection of the output clocks CLKD of the two DAC chips and outputs a phase detection status word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase detection status word is a preset value;

[0007] A synchronous control module is used for data sampling of a DAC chip; a frequency division coefficient of output clocks of two DAC chips is set; a first synchronous control signal and a second synchronous control signal are generated, wherein the first synchronous control signal is connected to the SYNC signal terminal of the first DAC chip; and the second synchronous control signal is connected to the SYNC signal terminal of the second DAC chip; the phase of the first synchronous control signal is fixed, the phase delay of the second synchronous control signal is traversed, and when the phase of the second synchronous control signal changes relative to the phase of the first synchronous control signal, the state word output by the phase detection module is observed, and the phase delay of the second synchronous control signal that minimizes the phase difference between the two DAC chips is determined according to the phase delay of the second synchronous control signal corresponding to the preset value output by the phase detection module, the first synchronous control signal is kept unchanged, and the second synchronous control signal is output according to the phase delay, and the two DAC chips are synchronously sampled under the pulse drive of the first synchronous control signal and the second synchronous control signal respectively.

[0008] Preferably, the synchronization control module is implemented by a state machine method. The state machine includes 6 states, namely ST1 to ST6, which are initialized to ST1. The specific operations of the state machine are:

[0009] ST1: configure and reset the sampling clocks of the two DAC chips, and then enter state ST2; ST2: generate a synchronization control signal, and the synchronization control signal is delayed by 16 unit phases through the first global delay unit to obtain a first synchronization control signal; the synchronization control signal is delayed by 0 unit phases through the second global delay unit to obtain a second synchronization control signal; enter state ST3;

[0010] ST3: reset the phase detection module, then enter state ST4;

[0011] ST4: monitor and record the phase detection state word generated by the phase detector, add 1 to the phase delay of the second synchronous control signal, and determine whether the phase delay is greater than or equal to the preset threshold. If yes, enter state ST5; otherwise, return to state ST3;

[0012] ST5: extract and calculate the intermediate value of the phase delay corresponding to the second synchronous control signal when the phase-discrimination state word is a preset value, and enter state ST6;

[0013] ST6: fix the phase delay of the first synchronization control signal unchanged, select the phase delay of the second synchronization control signal as the intermediate value calculated in state ST5, and re-output the first synchronization control signal and the second synchronization control signal.

[0014] Preferably, the phase detection module includes eight D flip-flops, a PLL module, and a phase detection result output module;

[0015] Among them, four D flip-flops are used to latch the state of the output clock of the first DAC chip, and are respectively recorded as flip-flop A1, flip-flop A2, flip-flop A3, and flip-flop A4;

[0016] The other four D flip-flops are used to latch the state of the output clock of the second DAC chip, and are respectively denoted as flip-flop B1, flip-flop B2, flip-flop B3, and flip-flop B4;

[0017] The PLL module generates four phase-detection clocks with different phases and the same frequency according to the external input clock signal. The phases of the four phase-detection clocks are 22.5°, 67.5°, 112.5°, and 157.5°, respectively, which are recorded as the first phase-detection clock, the second phase-detection clock, the third phase-detection clock, and the fourth phase-detection clock. The first phase-detection clock is connected to the clock ends of the trigger A1 and the trigger B1; the second phase-detection clock is connected to the clock ends of the trigger A2 and the trigger B2; the third phase-detection clock is connected to the clock ends of the trigger A3 and the trigger B3; and the fourth phase-detection clock is connected to the clock ends of the trigger A4 and the trigger B4;

[0018] The phase-detection result output module corresponds the outputs of trigger A1, trigger A2, trigger A3, trigger A4, trigger B1, trigger B2, trigger B3, and trigger B4 from high to low as the data bits of the phase-detection status word.

[0019] Preferably, the preset threshold is less than or equal to The default value is 0xFF.

[0020] Preferably, the middle value of the phase delay corresponding to the second synchronous control signal is obtained by rounding down the average value of the phase delay corresponding to the second synchronous control signal.

[0021] Preferably, each unit phase delay is 78 ps.

[0022] Another technical solution of the present invention is: an adaptive DAC synchronization method suitable for high-speed digital transmission modulation, which fixes the phase of the SYNC signal of one DAC chip, traversally adjusts the phase of the SYNC signal of the other DAC chip, and simultaneously performs phase detection on the output clock phase of the DAC chip to find out the phase difference between the SYNC signals when the output clocks of the two DAC chips are synchronized, and outputs the SYNC signals of the two DAC chips according to the phase difference, thereby realizing the sampling clock synchronization of the two DAC chips.

[0023] The above-mentioned adaptive DAC synchronization method applicable to high-speed data transmission modulation includes the following steps:

[0024] S1, configure and reset the sampling clocks of the two DAC chips, and then proceed to step S2;

[0025] S2, generate a synchronization control signal, the synchronization control signal passes through the first global delay unit and is delayed by 16 unit phases to obtain a first synchronization control signal; the synchronization control signal passes through the second global delay unit and is delayed by 0 unit phases to obtain a second synchronization control signal; enter step S3; the first synchronization control signal is connected to the SYNC signal end of the first DAC chip; the second synchronization control signal is connected to the SYNC signal end of the second DAC chip;

[0026] S3, performing phase detection on the output clocks of the first DAC chip and the second DAC chip, and outputting a phase detection status word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase detection status word is a preset value;

[0027] S4, monitor and record the phase detection state word generated by the phase detector, add 1 to the phase delay of the second synchronous control signal, and determine whether the phase delay is greater than or equal to the preset threshold. If yes, proceed to step S5; otherwise, return to step S3;

[0028] S5, extracting and calculating the intermediate value of the phase delay corresponding to the second synchronous control signal when the phase-discrimination state word is a preset value, and entering state S6;

[0029] S6. Fix the phase delay of the first synchronous control signal unchanged, select the phase delay of the second synchronous control signal as the intermediate value calculated in state S5, and re-output the first synchronous control signal and the second synchronous control signal.

[0030] Preferably, the middle value of the phase delay corresponding to the second synchronous control signal is obtained by rounding down the average value of the phase delay corresponding to the second synchronous control signal.

[0031] Preferably, the preset threshold is less than or equal to The default value is 0xFF.

[0032] The beneficial effects of the present invention compared with the prior art are:

[0033] (1) The present invention utilizes the FPGA+DAC architecture. In the application scenario where high sampling rate DAC synchronization is required, it not only solves the selection problem caused by the device without using other hardware resources, but is also applicable to other mainstream FPGAs and DACs.

[0034] (2) The state machine module of the present invention utilizes a small amount of FPGA internal resources, does not require the use of other hardware resources, reduces human intervention, ensures the reliability of DAC synchronization, and utilizes the flexibility of programming within the FPGA, which is applicable to more different scenarios.

[0035] (3) The present invention can avoid the problem of multiple unsuccessful resets caused by the fixed phase of the reset signal, shorten the synchronization time, and achieve fast adaptive synchronization.

[0036] (4) The present invention is applicable to high sampling rate DAC devices, and the sampling rate can be as high as 2.4 GHz. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 This is a connection diagram between FPGA and DAC according to an embodiment of the present invention;

[0038] Figure 2 A block diagram of an adaptive DAC synchronization implementation method applicable to high-speed data transmission modulation according to an embodiment of the present invention;

[0039] Figure 3 The embodiment of the present invention is a flow chart of the FPGA processing state machine. DETAILED DESCRIPTION

[0040] The present invention will be further described below in conjunction with the embodiments.

[0041] The DAC chip realizes the digital-to-analog conversion of baseband data in high-speed digital transmission modulation, and converts the baseband data signal into an analog signal; the external interface of the DAC chip mainly includes the data interface (DATA), the clock output signal (CLKD), and the reset synchronization signal (SYNC); the data interface (DATA) is the parallel data output from the FPGA to the DAC; the clock output signal is the clock that the DAC outputs to the FPGA after dividing the sampling clock; the reset synchronization signal SYNC, when a pulse signal is input to the SYNC pin of the DAC, the clock output signal CLKD of the DAC will stop for a certain period of time and then restart.

[0042] In order to perform high-rate modulated data transmission, the present invention proposes an adaptive DAC synchronization device and implementation method suitable for high-speed data transmission modulation, by fixing the phase of the SYNC signal of one DAC chip, traversing and adjusting the phase of the SYNC signal of the other DAC chip, and performing phase detection on the output clock phase of the DAC chip, to find out the phase difference between the SYNC signals when the output clocks of the two DAC chips are synchronized, and outputting the SYNC signals of the two DAC chips according to the phase difference, thereby realizing the sampling clock synchronization of the two DAC chips.

[0043] like Figure 1As shown, the adaptive DAC synchronization device suitable for high-speed data transmission modulation provided by the present invention is used to realize data synchronization between two DAC chips. The adaptive DAC synchronization device is implemented by FPGA. The two DAC chips share a sampling clock, and the sampling clock is divided to obtain an output clock, and the output clock is fed back to the FPGA;

[0044] The adaptive DAC synchronization device includes a phase detection module, a phase delay module, and a synchronization control module;

[0045] The phase detection module is used for phase detection of the output clocks CLKD of the two DAC chips and outputs a phase detection status word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase detection status word is a preset value;

[0046] A synchronous control module is used for data sampling of a DAC chip; a frequency division coefficient of output clocks of two DAC chips is set; a first synchronous control signal and a second synchronous control signal are generated, wherein the first synchronous control signal is connected to the SYNC signal terminal of the first DAC chip; and the second synchronous control signal is connected to the SYNC signal terminal of the second DAC chip; the phase of the first synchronous control signal is fixed, the phase delay of the second synchronous control signal is traversed, and when the phase of the second synchronous control signal changes relative to the phase of the first synchronous control signal, the state word output by the phase detection module is observed, and the phase delay of the second synchronous control signal that minimizes the phase difference between the two DAC chips is determined according to the phase delay of the second synchronous control signal corresponding to the preset value output by the phase detection module, the first synchronous control signal is kept unchanged, and the second synchronous control signal is output according to the phase delay, and the two DAC chips are synchronously sampled under the pulse drive of the first synchronous control signal and the second synchronous control signal respectively.

[0047] Preferably, the synchronization control module is implemented by a state machine method. The state machine module mainly completes the entire DAC synchronization method and realizes the control of the process. The state machine includes 6 states, namely ST1 to ST6, which are initialized to ST1.

[0048] like Figure 3 As shown, the specific operations of the state machine are:

[0049] ST1: configure and reset the application mode and sampling clock of the two DAC chips, and then enter state ST2; the sampling clock configuration includes the configuration of the division ratio, etc.

[0050] ST2: Generate a synchronous control signal, the synchronous control signal passes through the first global delay unit and is delayed by 16 unit phases to obtain a first synchronous control signal; the synchronous control signal passes through the second global delay unit and is delayed by 0 unit phases to obtain a second synchronous control signal; enter state ST3;

[0051] ST3: reset the phase detection module, then enter state ST4;

[0052] ST4: monitor and record the phase detection status word generated by the phase detector, and then enter state ST5;

[0053] ST5: add 1 to the phase delay of the second synchronization control signal to determine whether the phase delay is greater than or equal to a preset threshold. If yes, enter state ST6; otherwise, return to state ST3;

[0054] ST6: extract and calculate the intermediate value of the phase delay corresponding to the second synchronous control signal when the phase-discrimination state word is the preset value, and enter state ST7;

[0055] ST7: fix the phase delay of the first synchronization control signal unchanged, select the phase delay of the second synchronization control signal as the intermediate value calculated in state ST6, and re-output the first synchronization control signal and the second synchronization control signal.

[0056] In a specific embodiment of the present invention, the phase detection module includes eight D flip-flops, a PLL module, and a phase detection result output module.

[0057] Among them, four D flip-flops are used to latch the state of the output clock of the first DAC chip, and are respectively recorded as flip-flop A1, flip-flop A2, flip-flop A3, and flip-flop A4;

[0058] The other four D flip-flops are used to latch the state of the output clock of the second DAC chip, and are respectively denoted as flip-flop B1, flip-flop B2, flip-flop B3, and flip-flop B4;

[0059] The PLL module generates four phase-detection clocks with different phases and the same frequency according to the external input clock signal. The phases of the four phase-detection clocks are 22.5°, 67.5°, 112.5°, and 157.5°, respectively, which are recorded as the first phase-detection clock, the second phase-detection clock, the third phase-detection clock, and the fourth phase-detection clock. The first phase-detection clock is connected to the clock ends of the trigger A1 and the trigger B1; the second phase-detection clock is connected to the clock ends of the trigger A2 and the trigger B2; the third phase-detection clock is connected to the clock ends of the trigger A3 and the trigger B3; and the fourth phase-detection clock is connected to the clock ends of the trigger A4 and the trigger B4;

[0060] The phase detection result output module outputs the outputs of trigger A1, trigger A2, trigger A3, trigger A4, trigger B1, trigger B2, trigger B3, and trigger B4 from high to low corresponding to the data bits of the phase detection status word. When the output clocks of the first DAC chip and the second chip are synchronized, the outputs of the four D flip-flops are the same. Therefore, when the phase detection status word is 0xFF, it can be indicated that the output clocks of the first DAC chip and the second chip are synchronized.

[0061] Preferably, the preset threshold is less than or equal to The default value is 0xFF.

[0062] The middle value of the phase delay corresponding to the second synchronous control signal is obtained by rounding down the average value of the phase delay corresponding to the second synchronous control signal.

[0063] The JFM7K325T-C series FPGA of Fudan Microelectronics Company is used, in which the built-in global delay unit has a phase delay of 78ps per unit.

[0064] The GDA12SL3GMCCRH series DAC from China Electronics 24 Institute is also suitable for other mainstream FPGAs and DACs.

[0065] Based on the above device, the present invention provides an adaptive DAC synchronization method suitable for high-speed data transmission modulation, which is suitable for the design of data transmission requiring high-speed high-order modulation such as satellite-borne high-speed data transmission modulator.

[0066] like Figure 2 As shown, the method comprises the following steps:

[0067] S1, configure and reset the sampling clocks of the two DAC chips, and then proceed to step S2;

[0068] S2, generate a synchronization control signal, the synchronization control signal passes through the first global delay unit and is delayed by 16 unit phases to obtain a first synchronization control signal; the synchronization control signal passes through the second global delay unit and is delayed by 0 unit phases to obtain a second synchronization control signal; enter step S3; the first synchronization control signal is connected to the SYNC signal end of the first DAC chip; the second synchronization control signal is connected to the SYNC signal end of the second DAC chip;

[0069] S3, performing phase detection on the output clocks of the first DAC chip and the second DAC chip, and outputting a phase detection status word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase detection status word is a preset value;

[0070] S4, monitor and record the phase detection state word generated by the phase detector, add 1 to the phase delay of the second synchronous control signal, and determine whether the phase delay is greater than or equal to a preset threshold. If yes, proceed to step S5; otherwise, return to step S3;

[0071] S5, extracting and calculating the intermediate value of the phase delay corresponding to the second synchronous control signal when the phase-discrimination state word is a preset value, and entering state S6;

[0072] S6. Fix the phase delay of the first synchronous control signal unchanged, select the phase delay of the second synchronous control signal as the intermediate value calculated in state S5, and re-output the first synchronous control signal and the second synchronous control signal.

[0073] Although the present invention has been disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications to the technical solution of the present invention by using the methods and technical contents disclosed above without departing from the spirit and scope of the present invention. Therefore, any simple modifications, equivalent changes and modifications made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention shall fall within the protection scope of the technical solution of the present invention.

Claims

1. An adaptive DAC synchronization device suitable for high-speed data transmission modulation, used to achieve data synchronization between two DAC chips, the two DAC chips share a sampling clock, and the sampling clock is divided to obtain an output clock; characterized in that It includes a phase detection module, a phase delay module and a synchronization control module; The phase detection module is used for phase detection of the output clocks CLKD of the two DAC chips and outputs a phase detection status word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase detection status word is a preset value; Synchronous control module, used for data sampling of DAC chip; The frequency division coefficient of the output clocks of the two DAC chips is set; a first synchronous control signal and a second synchronous control signal are generated, wherein the first synchronous control signal is connected to the SYNC signal terminal of the first DAC chip; and the second synchronous control signal is connected to the SYNC signal terminal of the second DAC chip; the phase of the first synchronous control signal is fixed, the phase delay of the second synchronous control signal is traversed, and when the phase of the second synchronous control signal changes relative to the phase of the first synchronous control signal, the state word output by the phase detection module is observed, and the phase delay of the second synchronous control signal that minimizes the phase difference between the two DAC chips is determined according to the phase delay of the second synchronous control signal corresponding to the preset value output by the phase detection module, the first synchronous control signal is kept unchanged, and the second synchronous control signal is output according to the phase delay, and the two DAC chips are synchronously sampled under the pulse drive of the first synchronous control signal and the second synchronous control signal respectively.

2. The adaptive DAC synchronization device suitable for high-speed data transmission modulation according to claim 1, characterized in that: The synchronization control module is implemented by a state machine method. The state machine includes 6 states, namely ST1 to ST6, which are initialized to ST1. The specific operations of the state machine are: ST1: configure and reset the sampling clocks of the two DAC chips, and then enter state ST2; ST2: generate a synchronization control signal, and the synchronization control signal is delayed by 16 unit phases through the first global delay unit to obtain a first synchronization control signal; the synchronization control signal is delayed by 0 unit phases through the second global delay unit to obtain a second synchronization control signal; enter state ST3; ST3: reset the phase detection module, then enter state ST4; ST4: monitor and record the phase detection state word generated by the phase detector, add 1 to the phase delay of the second synchronous control signal, and determine whether the phase delay is greater than or equal to the preset threshold. If yes, enter state ST5; otherwise, return to state ST3; ST5: extract and calculate the intermediate value of the phase delay corresponding to the second synchronous control signal when the phase-discrimination state word is a preset value, and enter state ST6; ST6: fix the phase delay of the first synchronization control signal unchanged, select the phase delay of the second synchronization control signal as the intermediate value calculated in state ST5, and re-output the first synchronization control signal and the second synchronization control signal.

3. The adaptive DAC synchronization device suitable for high-speed data transmission modulation according to claim 1, characterized in that: The phase detection module includes eight D flip-flops, a PLL module, and a phase detection result output module; Among them, four D flip-flops are used to latch the state of the output clock of the first DAC chip, and are respectively recorded as flip-flop A1, flip-flop A2, flip-flop A3, and flip-flop A4; The other four D flip-flops are used to latch the state of the output clock of the second DAC chip, and are respectively denoted as flip-flop B1, flip-flop B2, flip-flop B3, and flip-flop B4; The PLL module generates four phase-detection clocks with different phases and the same frequency according to the external input clock signal. The phases of the four phase-detection clocks are 22.5°, 67.5°, 112.5°, and 157.5°, respectively, which are recorded as the first phase-detection clock, the second phase-detection clock, the third phase-detection clock, and the fourth phase-detection clock. The first phase-detection clock is connected to the clock ends of the trigger A1 and the trigger B1; the second phase-detection clock is connected to the clock ends of the trigger A2 and the trigger B2; the third phase-detection clock is connected to the clock ends of the trigger A3 and the trigger B3; and the fourth phase-detection clock is connected to the clock ends of the trigger A4 and the trigger B4; The phase-detection result output module corresponds the outputs of trigger A1, trigger A2, trigger A3, trigger A4, trigger B1, trigger B2, trigger B3, and trigger B4 from high to low as the data bits of the phase-detection status word.

4. The adaptive DAC synchronization device suitable for high-speed data transmission modulation according to claim 3, characterized in that: The preset threshold is less than or equal to The default value is 0xFF.

5. The adaptive DAC synchronization device suitable for high-speed data transmission modulation according to claim 2, characterized in that: The middle value of the phase delay corresponding to the second synchronous control signal is obtained by rounding down the average value of the phase delay corresponding to the second synchronous control signal.

6. The adaptive DAC synchronization device suitable for high-speed data transmission modulation according to claim 2, characterized in that: Each unit phase delay is 78ps.

7. An adaptive DAC synchronization method suitable for high-speed data transmission modulation, characterized in that By fixing the phase of the SYNC signal of one of the DAC chips, traversing and adjusting the phase of the SYNC signal of the other DAC chip, and at the same time performing phase detection on the output clock phase of the DAC chip, the phase difference between the SYNC signals when the output clocks of the two DAC chips are synchronized is found, and the SYNC signals of the two DAC chips are output according to the phase difference, thereby achieving sampling clock synchronization of the two DAC chips.

8. An adaptive DAC synchronization method suitable for high-speed data transmission modulation according to claim 7, characterized in that The steps include: S1, configure and reset the sampling clocks of the two DAC chips, and then proceed to step S2; S2, generate a synchronization control signal, the synchronization control signal passes through the first global delay unit and is delayed by 16 unit phases to obtain a first synchronization control signal; the synchronization control signal passes through the second global delay unit and is delayed by 0 unit phases to obtain a second synchronization control signal; enter step S3; the first synchronization control signal is connected to the SYNC signal end of the first DAC chip; the second synchronization control signal is connected to the SYNC signal end of the second DAC chip; S3, performing phase detection on the output clocks of the first DAC chip and the second DAC chip, and outputting a phase detection status word; when the phase difference between the output clocks of the two DAC chips is less than a preset threshold, the phase detection status word is a preset value; S4, monitoring and recording the phase detection state word generated by the phase detector, adding 1 to the phase delay of the second synchronization control signal, and determining whether the phase delay is greater than or equal to a preset threshold. If yes, proceeding to step S5; Otherwise, return to step S3; S5, extracting and calculating the intermediate value of the phase delay corresponding to the second synchronous control signal when the phase-discrimination state word is a preset value, and entering state S6; S6. Fix the phase delay of the first synchronous control signal unchanged, select the phase delay of the second synchronous control signal as the intermediate value calculated in state S5, and re-output the first synchronous control signal and the second synchronous control signal.

9. The adaptive DAC synchronization method suitable for high-speed data transmission modulation according to claim 1, characterized in that: The middle value of the phase delay corresponding to the second synchronous control signal is obtained by rounding down the average value of the phase delay corresponding to the second synchronous control signal.

10. The adaptive DAC synchronization method suitable for high-speed data transmission modulation according to claim 1, characterized in that: The preset threshold is less than or equal to The default value is 0xFF.

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