Junction terminal expansion structure and preparation method thereof

Abstract

The invention relates to the technical field of MOS semiconductors, and discloses a junction terminal expansion structure, which comprises a metal drain electrode, source region source electrode metal, grid electrode metal, terminal source electrode metal and a semiconductor epitaxial layer, polycrystalline silicon is arranged between the source region source electrode metal and the semiconductor epitaxial layer and between the gate electrode metal and the semiconductor epitaxial layer, the polycrystalline silicon is in ohmic contact with the gate electrode metal, the surface of the polycrystalline silicon is covered with a gate oxide layer, the semiconductor epitaxial layer comprises a substrate layer and a diffusion layer, and the diffusion layer comprises an active region, a main junction and a multi-region junction terminal expansion structure. The active region comprises an active region heavily doped N layer and a source region P layer; the main junction comprises two main junction P layers, a main junction heavily doped P layer and a main junction isolation ring. According to the invention, whether the epitaxial layer of the sampled semiconductor meets the requirements of a production process is tested through the source and drain current, the power consumption and the delay time of the sampled semiconductor, so that the time required by sampling detection is greatly shortened, and the accuracy of sampling detection is effectively ensured.

Description

Technical Field

[0001] The present invention relates to the field of MOS semiconductor technology, and in particular to a junction terminal extension structure and a preparation method thereof. Background Art

[0002] Silicon Carbide high-voltage power devices have better electrothermal properties than traditional silicon devices and can work normally in more demanding environments, so they have broad application prospects in photovoltaic power generation, electric vehicles, aerospace and other fields. In order to meet the development needs of high energy efficiency, high power density and small and lightweight power electronic systems, SiC power devices are developing in the direction of high voltage, high power, high frequency and low loss.

[0003] The existing patent discloses a terminal structure of a silicon carbide power device and a manufacturing method thereof (publication number CN105977310A), wherein the device includes a device cell and a device terminal; the device terminal includes a P-type junction terminal expansion area, wherein there is an N+ injection ring and an etching groove in the P-type junction terminal expansion area, wherein the etching groove is connected to the N+ injection ring, wherein the etching groove is located outside the N+ injection ring, wherein the etching groove is filled with an oxide layer, wherein adjacent N+ injection rings are separated by the etching groove and the P-type junction terminal expansion area, wherein adjacent etching grooves are separated by the P-type junction terminal expansion area and the N+ injection ring, wherein the upper surface of the P-type junction terminal expansion area and the N+ injection ring is covered with an oxide layer. In the technology disclosed in the patent, due to the limited number of partitions and the sudden change in concentration between different areas, new electric field spikes are easily introduced, resulting in the efficiency of the surface electric field being much lower than that of the ideal terminal; and the terminal length is very long and the area occupied by the terminal is increased, wherein the junction terminal structure is difficult to design, requires high process precision, and has high manufacturing costs. Summary of the invention

[0004] The main technical problem solved by the present invention is to provide a junction terminal extension structure and a preparation method thereof, which solves the problems in the above-mentioned background technology.

[0005] To solve the above technical problems, according to one aspect of the present invention, more specifically, a junction terminal extension structure includes a metal drain, a source region source metal, a gate metal, a terminal source metal and a semiconductor epitaxial layer; polysilicon is provided between the source region source metal and the gate metal and the semiconductor epitaxial layer, wherein the polysilicon is in ohmic contact with the gate metal, the surface of the polysilicon is covered with a gate oxide layer, the semiconductor epitaxial layer includes a substrate layer and a diffusion layer, and the diffusion layer includes an active region, a main junction and a multi-region junction terminal extension structure; The active region includes an active region heavily doped N layer and a source region P layer; the main junction includes two main junction P layers, a main junction heavily doped P layer and a main junction isolation ring, wherein the main junction heavily doped P layer is located inside the main junction P layer, and a plurality of main junction isolation rings are provided, and the main junction isolation ring is located between the two main junction P layers; The multi-region junction terminal extension structure includes two JTE body regions and a terminal heavily doped N body region, and a plurality of guard rings are formed inside the two JTE body regions by ion implantation; The surface of the multi-region junction terminal extension structure is covered with a terminal oxide layer, and the terminal oxide layer includes two side protrusion layers, and the two side protrusion layers protrude downward to the inside of the JTE body region and contact with the guard ring.

[0006] Furthermore, a terminal isolation ring is formed in the multi-region junction terminal extension structure and on one side of the JTE body region by ion implantation.

[0007] Furthermore, the terminal oxide layer also includes two middle protruding layers, the two middle protruding layers are respectively located on one side of the two side protruding layers, and two protective rings are formed under the two middle protruding layers by ion implantation.

[0008] Furthermore, a high-resistance field plate is provided in the inner lower layer of the terminal oxide layer.

[0009] A method for preparing a junction terminal extension structure comprises the following steps: S1. Forming different patterns on the surface of the semiconductor epitaxial layer by photolithography; S2, forming an active region, a main junction and a multi-region junction terminal extension structure inside the diffusion layer by ion implantation; S3, performing metal bonding on randomly sampled epitaxial layers, and performing static working characteristic test on the sampled epitaxial layers according to the bonding; S4, depositing a terminal oxide layer and a gate oxide layer on the surface of the semiconductor epitaxial layer; S5. Cover the source metal and the drain metal to connect the source and drain regions to the external circuit.

[0010] Furthermore, in step S3, the source-drain current, power consumption and delay time are used to test whether the sampled semiconductor epitaxial layer meets the production process requirements, including: In the formula, It indicates that the sampled semiconductor epitaxial layer meets the comprehensive coefficient of production process requirements. It represents the actual current value measured by the sampled semiconductor under the applied voltage of 1.2V. It indicates the nominal current measured by the semiconductor under 1.2V applied voltage. It represents the actual power consumption of the sampled semiconductor during a half-hour test. Indicates the delay time of the sampled semiconductor after the gate voltage is connected.

[0011] Furthermore, when When , it indicates that the comprehensive performance of the source leakage current, reverse leakage current and delay time of the sampled semiconductor epitaxial layer meets the preparation requirements; when When , it means that the comprehensive performance of the source leakage current, reverse leakage current and delay time of the sampled semiconductor epitaxial layer does not meet the preparation requirements.

[0012] Furthermore, in step S3, when testing the sampled semiconductor epitaxial layer, the temperature of the semiconductor epitaxial layer needs to be controlled at 60° C. for testing. Beneficial effects: 1. The present invention tests whether the sampled semiconductor epitaxial layer meets the production process requirements by measuring the source / drain current, power consumption and delay time of the sampled semiconductor. This not only greatly shortens the time required for sampling detection, but also effectively ensures the accuracy of sampling detection.

[0013] 2. The present invention increases the process window of the terminal structure and the stability of the terminal structure under long-term complex working conditions by additionally introducing a trench-assisted protection ring structure inside each JTE area.

[0014] 3. The present invention provides an additional discharge channel for the large current caused by the high-speed charge and discharge effect by additionally introducing a high-resistance field plate above the terminal structure, thereby further improving the switching reliability of the power device. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 It is a structural schematic diagram of Embodiment 1 of the present invention; Figure 2 It is a structural schematic diagram of Embodiment 2 of the present invention; Figure 3 This is a schematic diagram of the structure of Embodiment 3 of the present invention; Figure 4 It is a structural schematic diagram of embodiment 4 of the present invention.

[0016] In the figure: 1. Metal drain; 2. Substrate layer; 3. Diffusion layer; 4. Source metal in source region; 5. Gate oxide layer; 6. Polysilicon; 7. Gate metal; 8. Terminal heavily doped N body region; 9. Terminal source metal; 10. Source region heavily doped N layer; 11. Source region P layer; 12. Main junction P layer; 13. Main junction heavily doped P layer; 14. Main junction isolation ring; 15. JTE body region; 16. High resistance field plate; 17. Terminal oxide layer; 18. Terminal isolation ring; 19. Guard ring one; 20. Guard ring two; 1701. Side protrusion layer; 1702. Middle protrusion layer. DETAILED DESCRIPTION

[0017] In order to make the technical solution of the present invention clearer, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0018] like Figure 1 - 4, according to one aspect of the present invention, a method for preparing a junction terminal extension structure is provided, comprising the following steps: Step 1: forming different patterns on the surface of the semiconductor epitaxial layer by photolithography; Step 2: forming an active region, a main junction and a multi-region junction terminal extension structure inside the diffusion layer 3 by ion implantation; Step 3: Perform metal bonding on the randomly sampled epitaxial layers, and perform static working characteristic tests on the sampled epitaxial layers based on the bonding; when testing the sampled semiconductor epitaxial layers, the temperature of the semiconductor epitaxial layers needs to be controlled at 60°C for testing.

[0019] Step 4: depositing a terminal oxide layer 17 and a gate oxide layer 5 on the surface of the semiconductor epitaxial layer; Step 5: Cover the source metal and drain metal to connect the source and drain areas to the external circuit.

[0020] In step 3, the source-drain current, power consumption and delay time are used to test whether the sampled semiconductor epitaxial layer meets the production process requirements, including: In the formula, It indicates that the sampled semiconductor epitaxial layer meets the comprehensive coefficient of production process requirements. It represents the actual current value measured by the sampled semiconductor under the applied voltage of 1.2V. It indicates the nominal current measured by the semiconductor under 1.2V applied voltage. It represents the actual power consumption of the sampled semiconductor during a half-hour test. Indicates the delay time of the sampled semiconductor after the gate voltage is connected.

[0021] when When , it indicates that the comprehensive performance of the source leakage current, reverse leakage current and delay time of the sampled semiconductor epitaxial layer meets the preparation requirements; when When , it means that the comprehensive performance of the source leakage current, reverse leakage current and delay time of the sampled semiconductor epitaxial layer does not meet the preparation requirements.

[0022] 1. When the sampled semiconductor X is tested, the actual current value of the sampled semiconductor X measured under the applied voltage of 1.2V is (Ampere), the nominal current of a semiconductor measured at 1.2V applied voltage is taken as (Ampere), the actual power consumption of the sampled semiconductor during the half-hour test (W), the delay time of the sampled semiconductor after the gate voltage is connected is (ns), then we have: From the above calculations, it can be known that the comprehensive performance of the source leakage current, reverse leakage current and delay time of the sampled semiconductor X meets the preparation requirements.

[0023] 2. When the sampled semiconductor Y is tested, the actual current value measured by the sampled semiconductor Y under the applied voltage of 1.2V is (Ampere), the nominal current of a semiconductor measured at 1.2V applied voltage is taken as (Ampere), the actual power consumption of the sampled semiconductor during the half-hour test (W), the delay time of the sampled semiconductor after the gate voltage is connected is (ns), then we have: From the above calculations, it can be seen that the comprehensive performance of the source leakage current, reverse leakage current and delay time of the sampled semiconductor Y does not meet the preparation requirements.

[0024] Example 1 like Figure 1 As shown, a junction terminal extension structure includes a metal drain 1, a source region source metal 4, a gate metal 7, a terminal source metal 9 and a semiconductor epitaxial layer; polysilicon 6 is provided between the source region source metal 4 and the gate metal 7 and the semiconductor epitaxial layer, wherein the polysilicon 6 is in ohmic contact with the gate metal 7, and the surface of the polysilicon 6 is covered with a gate oxide layer 5, the semiconductor epitaxial layer includes a substrate layer 2 and a diffusion layer 3, and the diffusion layer 3 includes an active region, a main junction and a multi-region junction terminal extension structure; The active region includes an active region heavily doped N layer 10 and a source region P layer 11; the main junction includes two main junction P layers 12, a main junction heavily doped P layer 13 and a main junction isolation ring 14, wherein the main junction heavily doped P layer 13 is located inside the main junction P layer 12, a plurality of main junction isolation rings 14 are provided, and the main junction isolation ring 14 is located between the two main junction P layers 12; the main junction is segmented and an isolation ring structure (main junction isolation ring 14) is introduced to physically block the current path formed by the charging and discharging effect during the switching process of the power device, prevent the formation of a strong electric field and leakage current at the sensitive position of the main junction, and protect the main junction and cells adjacent to the active region from premature damage during high-speed switching.

[0025] The multi-region junction terminal extension structure includes two JTE body regions 15 and a terminal heavily doped N body region 8, and a plurality of guard rings 19 are formed inside the two JTE body regions 15 by ion implantation; the surface of the multi-region junction terminal extension structure is covered with a terminal oxide layer 17, and the terminal oxide layer 17 includes two side protrusion layers 1701, and the two side protrusion layers 1701 protrude downward to the inside of the JTE body region 15 and contact the guard ring 19. A terminal isolation ring 18 is formed inside the multi-region junction terminal extension structure and on one side of the JTE body region 15 by ion implantation.

[0026] In order to further suppress the influence of the charge and discharge effect of the JTE terminal structure on the device, the JTE terminal structure is segmented and an isolation ring structure (terminal isolation ring 18) is introduced to further reduce the current generated by the large-area JTE terminal charge and discharge effect and its derivative effects introduced locally in the device, such as local strong electric field breakdown and local overheating and burning.

[0027] Example 2 like Figure 2 As shown, the terminal oxide layer 17 also includes two middle protruding layers 1702, the two middle protruding layers 1702 are respectively located on one side of the two side protruding layers 1701, and two guard rings 20 are formed under the two middle protruding layers 1702 by ion implantation.

[0028] An additional trench-assisted P+ guard ring structure (guard ring 20) is introduced inside and outside each JTE area to increase the process window of the terminal structure, suppress the electric field peak at the end of the JTE, and improve the stability of the terminal structure under long-term complex working conditions.

[0029] Example 3 like Figure 3 As shown, two guard rings 20 are formed under the two middle protruding layers 1702 by ion implantation, and a high-resistance field plate 16 is provided in the lower inner layer of the terminal oxide layer 17 .

[0030] At the same time, the trench-assisted P+ guard ring structure (guard ring 20) and the high-resistance field plate (high-resistance field plate 16) provide additional discharge channels for the large current caused by the high-speed charge and discharge effect, further improving the switching reliability of the power device.

[0031] Example 4 like Figure 4 As shown, a terminal isolation ring 18 is formed by ion implantation in the multi-region junction terminal extension structure and on one side of the JTE body region 15, a high-resistance field plate 16 is provided in the lower inner layer of the terminal oxide layer 17, and an additional high-resistance field plate (high-resistance field plate 16) is introduced above the terminal structure to provide an additional discharge channel for the large current caused by the high-speed charge and discharge effect.

[0032] The above-mentioned embodiments only express several implementation methods of the present invention, and the description thereof is relatively specific and detailed, but it cannot be understood as limiting the scope of the patent of the present invention. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the concept of the present invention, which all belong to the protection scope of the present invention. Therefore, the protection scope of the patent of the present invention shall be subject to the attached claims.

Claims

1. A junction terminal extension structure, comprising a metal drain (1), a source region source metal (4), a gate metal (7), a terminal source metal (9) and a semiconductor epitaxial layer; polysilicon (6) is provided between the source region source metal (4) and the gate metal (7) and the semiconductor epitaxial layer, wherein the polysilicon (6) and the gate metal (7) are in ohmic contact, and the surface of the polysilicon (6) is covered with a gate oxide layer (5), characterized in that: The semiconductor epitaxial layer comprises a substrate layer (2) and a diffusion layer (3), and the diffusion layer (3) comprises an active region, a main junction and a multi-region junction terminal extension structure; The active region comprises an active region heavily doped N layer (10) and a source region P layer (11); the main junction comprises two main junction P layers (12), a main junction heavily doped P layer (13) and a main junction isolation ring (14), wherein the main junction heavily doped P layer (13) is located inside the main junction P layer (12), a plurality of main junction isolation rings (14) are provided, and the main junction isolation ring (14) is located between the two main junction P layers (12); The multi-region junction terminal extension structure comprises two JTE body regions (15) and a terminal heavily doped N body region (8), and a plurality of guard rings (19) are formed inside the two JTE body regions (15) by ion implantation; The surface of the multi-region junction terminal extension structure is covered with a terminal oxide layer (17), and the terminal oxide layer (17) includes two side protrusion layers (1701), and the two side protrusion layers (1701) protrude downward to the inside of the JTE body region (15) and contact the first guard ring (19).

2. The terminal extension structure according to claim 1, characterized in that: A terminal isolation ring (18) is formed by ion implantation in the multi-region junction terminal extension structure and on one side of the JTE body region (15).

3. The junction terminal expansion structure according to claim 1, characterized in that: The terminal oxide layer (17) further comprises two intermediate protruding layers (1702), the two intermediate protruding layers (1702) being respectively located on one side of the two side protruding layers (1701), and two protective rings (20) are formed under the two intermediate protruding layers (1702) by ion implantation.

4. The terminal extension structure according to any one of claims 1 to 3, characterized in that: A high-resistance field plate (16) is provided in the inner lower layer of the terminal oxide layer (17).

5. A method for preparing a junction terminal extension structure according to any one of claims 1 to 4, characterized in that: The following steps are involved: S1. Forming different patterns on the surface of the semiconductor epitaxial layer by photolithography; S2, forming an active region, a main junction and a multi-region junction terminal extension structure inside the diffusion layer (3) by ion implantation; S3, performing metal bonding on randomly sampled epitaxial layers, and performing static working characteristic test on the sampled epitaxial layers according to the bonding; S4, depositing a terminal oxide layer (17) and a gate oxide layer (5) on the surface of the semiconductor epitaxial layer; S5. Cover the source metal and the drain metal to connect the source and drain regions to the external circuit.

6. The method for preparing a junction terminal extension structure according to claim 5, characterized in that: In step S3, the source-drain current, power consumption and delay time are used to test whether the sampled semiconductor epitaxial layer meets the production process requirements, including: In the formula, It indicates that the sampled semiconductor epitaxial layer meets the comprehensive coefficient of production process requirements. It represents the actual current value measured by the sampled semiconductor under the applied voltage of 1.2V. It indicates the nominal current measured by the semiconductor under 1.2V applied voltage. It represents the actual power consumption of the sampled semiconductor during a half-hour test. Indicates the delay time of the sampled semiconductor after the gate voltage is connected.

7. The method for preparing a junction terminal extension structure according to claim 6, characterized in that: when When , it indicates that the comprehensive performance of the source leakage current, reverse leakage current and delay time of the sampled semiconductor epitaxial layer meets the preparation requirements; when When , it means that the comprehensive performance of the source leakage current, reverse leakage current and delay time of the sampled semiconductor epitaxial layer does not meet the preparation requirements.

8. The method for preparing a junction terminal extension structure according to claim 5, characterized in that: In the step S3, when testing the sampled semiconductor epitaxial layer, the temperature of the semiconductor epitaxial layer needs to be controlled at 60°C for testing.

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