Low-power-consumption organic field effect transistor memory array and preparation method and application thereof

Abstract

The invention relates to a low-power-consumption organic field effect transistor (OFET) memory array and a preparation method and application thereof, and belongs to the technical field of semiconductor memory arrays. According to the memory array, the OFET memory is used as a basic device unit, and the dielectric layer of the memory array is made of a zinc salt doped polyelectrolyte dielectric material processed by a solution, so that low-voltage operation and effective electrical property regulation and control of the device can be realized. The OFET memory array provided by the invention has a good storage characteristic, and distinguishing and effective writing and reading of different pixel points in a figure image can be realized by programming grid pulse voltage. Compared with the prior art, the OFET memory array can simplify the manufacturing process and reduce the cost, not only has the advantages of simple structure, excellent performance, low energy consumption and the like, but also can be easily integrated into a high-density flexible memory array to realize effective electric pulse imaging and picture smooth processing and calculation; and a new thought is provided for development of a storage technology and application of imaging, image processing and neuromorphic calculation.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor memory arrays, and relates to a low-power organic field effect transistor memory array and a preparation method and application thereof. Background Art

[0002] As the degree of informatization of social development deepens, a large amount of data is continuously generated, which puts forward higher requirements for advanced storage technology. In information storage, it is currently hoped that the memory can be integrated into a storage array to realize the storage of large-scale information and make the stored information accessible at any time; it is also hoped that the storage array can perform efficient computational processing on the stored information to achieve parallel storage and computation. In order to solve the high energy consumption and high cost problems brought about by large-scale information storage and computation, it is particularly important to develop advanced low-power memory and its array.

[0003] Organic field-effect transistors (OFETs) can realize the effective writing and reading of information, data storage, and in-memory computing due to their flexibility, lightness, and easy-to-control properties of organic semiconductors and dielectric materials. They have become an effective carrier of emerging storage technologies and have great potential in the field of new generation storage devices. Integrating organic field-effect transistors into storage arrays can not only ensure their tunable storage characteristics, but also achieve large-scale information storage at the array level. Therefore, this integrated structure makes it possible for storage arrays to break through the von Neumann structure used in current computer systems, greatly reducing the large amount of time required for data information to be transferred between the processor and the memory, thereby significantly improving the data processing speed. At the same time, organic field-effect transistors are also an excellent sensor carrier with rich sensing mechanisms and unique signal amplification characteristics. Various types of sensors based on organic field-effect transistors have been widely used in smart wearables, electronic skin, biomedical testing, environmental protection and other fields. In addition, organic field-effect transistor memory can further enhance its application value in practical applications by virtue of its own sensing and storage capabilities. It can directly store detection information in the array, achieve long-term storage and use it for subsequent information calculation and processing, thereby improving the survival efficiency and operating speed of the organic field-effect transistor memory array.

[0004] By utilizing the response of the organic field effect transistor memory array to the photoelectric signal, the input signal can be converted into an electrical signal to realize electrical pulse imaging, and the image can be directly processed and calculated, thereby enhancing the data processing speed and function, and providing an effective way to improve the computer operation speed. Therefore, the design and development of integrated low-power organic field effect transistor memory arrays has a wide range of needs and important practical significance, and will show great potential and application value in the fields of pulse imaging, image processing, smart sensor chips and neuromorphic computing. Summary of the invention

[0005] In view of this, one of the objects of the present invention is to provide a low-power organic field effect transistor memory array; a second object of the present invention is to provide a method for preparing a low-power organic field effect transistor memory array; a third object of the present invention is to provide an application of a low-power organic field effect transistor memory array in pulse imaging, image processing, artificial synapse or neuromorphic computing technology.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] 1. According to one aspect of the present invention, there is provided a low-power consumption organic field effect transistor memory array, wherein the memory array is formed by integrating organic field effect transistor memories that realize storage functions based on ion migration effects;

[0008] The memory array is a top-gate bottom-contact structure, which includes, from bottom to top, a substrate 1, a source / drain electrode pair, an organic semiconductor layer 4, a dielectric passivation layer 5, a doped polyelectrolyte dielectric layer 6 and a gate 7;

[0009] The source / drain electrode pair is located between the surface of the substrate 1 and the organic semiconductor layer 4, and the source / drain electrode pair is composed of a source electrode 2 and a drain electrode 3 arranged side by side, and a channel with a micro-nano scale spacing is formed between the source electrode 2 and the drain electrode 3;

[0010] The number of the source / drain electrode pairs and the gate 7 are both 4 or more, and the gate 7 region covers the channel region of the corresponding source / drain electrode pair.

[0011] Preferably, the material of the substrate 1 is any one or more of polyethylene terephthalate, polyethylene naphthalate, polyimide, polydimethylsiloxane, polycarbonate, polyvinyl alcohol, glass, silicon wafer (ie, silicon dioxide / silicon) or sapphire.

[0012] More preferably, the material of the substrate 1 is any one of polyethylene naphthalate, polyethylene terephthalate, polyimide or polydimethylsiloxane.

[0013] Preferably, the material of the source electrode 2, the drain electrode 3 or the gate electrode 7 is any one or more of gold, silver, aluminum, copper, chromium, platinum, titanium, nickel, indium tin oxide, fluorine-doped tin oxide, zinc aluminum oxide, carbon nanotubes, graphene or conductive polymers;

[0014] The conductive polymer has a conjugated main electron system on its main chain and is a polymer material that achieves a conductive state through doping. The conductive polymer includes any one of polypyrrole, polyaniline, polythiophene, poly(3,4-ethylenedioxythiophene) or polyacetylene.

[0015] Further preferably, the material of the source electrode 2 , the drain electrode 3 or the gate electrode 7 is any one of gold, silver, aluminum or copper.

[0016] Preferably, the material of the organic semiconductor layer 4 is an organic small molecule semiconductor material or a conjugated polymer semiconductor material;

[0017] The organic small molecule semiconductor material includes any one or more of pentacene or its derivatives, 7,7,8,8-tetracyanoquinodimethane or its derivatives, and copper phthalocyanine;

[0018] The conjugated polymer semiconductor material includes any one or more of poly 3-hexylthiophene or its derivatives, indomethacin-1,1-dithiophene-benzothiadiazole copolymer, 7,7,8,8-tetracyanoquinodimethane-doped indomethacin-1,1-dithiophene-benzothiadiazole copolymer, poly{4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b']disulfide-2,6-diyl}{3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3,4-b]thiophenediyl} or its derivatives, and copolymers of terthiophene and perylene imide units.

[0019] Further preferably, the material of the organic semiconductor layer 4 is a conjugated polymer semiconductor material, selected from any one or more of poly (3-hexylthiophene) and its derivatives, indomethacin-1-thiophene-benzothiadiazole copolymer, and 7,7,8,8-tetracyanoquinodimethane-doped indomethacin-1-thiophene-benzothiadiazole copolymer.

[0020] Preferably, the material of the dielectric passivation layer 5 includes any one or more of polymethyl methacrylate or its derivatives, polystyrene or its derivatives, amorphous fluororesin or its derivatives, aluminum oxide, hafnium dioxide or zirconium dioxide.

[0021] Further preferably, the material of the dielectric passivation layer 5 includes any one or more of polymethyl methacrylate or its derivatives, polystyrene or its derivatives, and amorphous fluororesin or its derivatives.

[0022] Preferably, the doped polyelectrolyte dielectric layer 6 is a dielectric film material of a soluble zinc salt doped polyelectrolyte;

[0023] The material of the polyelectrolyte in the dielectric film material of the soluble zinc salt doped polyelectrolyte is at least one of polyacrylic acid or its derivatives, polyacrylamide or its derivatives, a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polymethyl methacrylate, a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polyethylene glycol, and a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polyvinyl alcohol;

[0024] The soluble zinc salt is any one or more of zinc chloride, zinc bromide, zinc iodide, zinc acetate, zinc sulfate, zinc nitrate, zinc fluorosilicate, zinc fluoroborate or zinc gluconate.

[0025] Further preferably, the polyelectrolyte material in the dielectric film material doped with a soluble zinc salt is at least one of polyacrylic acid and its derivatives, polyacrylamide and its derivatives, and a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polyethylene glycol;

[0026] The soluble zinc salt is any one or more of zinc chloride, zinc bromide and zinc iodide.

[0027] More preferably, the soluble zinc salt-doped polyelectrolyte dielectric film material is prepared according to the following method:

[0028] First, a polyelectrolyte material is dissolved in a solvent to obtain a polyelectrolyte precursor solution; then, a soluble zinc salt is added and fully dissolved to obtain a soluble zinc salt-doped polyelectrolyte dielectric material solution; finally, the solution is processed into a film by a solution processing method and annealed to prepare a soluble zinc salt-doped polyelectrolyte dielectric film material;

[0029] The doping content of the soluble zinc salt accounts for 0.5-10 wt.% of the total mass of the entire polyelectrolyte material and the zinc salt material.

[0030] 2. According to another aspect of the present invention, a method for preparing the above-mentioned low-power organic field effect transistor memory array is provided, and the preparation method comprises the following steps:

[0031] (1) forming four or more pairs of source / drain electrode pairs consisting of source and drain electrodes arranged side by side on the surface of the substrate by any one of vacuum thermal evaporation, magnetron sputtering, atomic layer deposition, inkjet printing or drop coating, wherein a channel with a micro-nanoscale spacing is formed between the source and drain electrodes;

[0032] (2) forming an organic semiconductor layer on the surface of the source electrode, the drain electrode and the substrate by any one of spin coating, blade coating or inkjet printing;

[0033] (3) forming a dielectric passivation layer on the surface of the organic semiconductor layer by any one of atomic layer deposition, vacuum thermal evaporation, magnetron sputtering, spin coating, doctor blade coating or inkjet printing;

[0034] (4) on the surface of the dielectric passivation layer, a solution of a dielectric material doped with a soluble zinc salt and a polyelectrolyte is processed into a film by a solution processing method, and then annealed to form a doped polyelectrolyte dielectric layer;

[0035] (5) On the surface of the doped polyelectrolyte dielectric layer, a mask is combined and a gate is formed by any one of magnetron sputtering, vacuum thermal evaporation, atomic layer deposition, inkjet printing or drop coating, wherein the number of the gates is the same as the number of source / drain electrode pairs, thereby obtaining a low-power organic field-effect transistor memory array.

[0036] Preferably, in step (4), the solution processing method is any one of spin coating, blade coating or inkjet printing;

[0037] In step (4), the concentration of the polyelectrolyte material in the solution used in the spin coating method is 5 to 50 mg / mL, the spin coating speed is 200 to 4000 rpm, and the spin coating time is 30 to 120 s;

[0038] In step (4), the annealing temperature is 50-200° C., and the annealing time is not less than 60 minutes.

[0039] Further preferably, in step (4), the concentration of the polyelectrolyte material in the solution used in the spin coating method is 10 to 40 mg / mL, and the temperature of the annealing treatment is 60 to 180°C.

[0040] More preferably, in step (4), the concentration of the polyelectrolyte material in the solution used in the spin coating method is 15-35 mg / mL, and the temperature of the annealing treatment is 70-150°C.

[0041] 3. According to another aspect of the present invention, there is provided an application of the low-power organic field-effect transistor memory array in pulse imaging, image processing, artificial synapse or neuromorphic computing technology.

[0042] The beneficial effect of the present invention is that the low-power organic field effect transistor memory array disclosed by the present invention has the following advantages:

[0043] (1) The organic field effect transistor memory array of the present invention realizes storage function based on the ion migration enhancement effect of the novel dielectric material system of zinc salt doped polyelectrolyte dielectric layer, and can regulate the memory storage characteristics of ion migration by voltage, thereby successfully developing a flexible organic field effect transistor memory array with low voltage and multi-level storage characteristics. This new type of organic field effect transistor memory array breaks through the traditional strategy of realizing storage characteristics based on floating gate device structure, and provides a new choice and beneficial idea for high-performance and low-power transistor memory arrays.

[0044] (2) The organic field effect transistor memory array of the present invention can make full use of the three-terminal structure advantage of a single memory cell in the device array. By applying different voltages to the gate, it can realize the writing of electric pulses of different amplitudes, and can realize reverse programming gate pulse voltage erasure. It can also realize the rapid writing of electric pulses to meet the application requirements of information learning and memory functional memories, and has great potential in machine vision, deep learning and other aspects.

[0045] (3) The organic field effect transistor memory array of the present invention also has the advantages of simple structure, excellent performance, low energy consumption, etc., and can be effectively integrated into a high-density multi-pixel storage array for applications such as electric pulse imaging and image processing. The storage and computing applications of this type of organic field effect transistor memory array can output the smoothing processing results of the image while completing the imaging, and can efficiently and accurately complete storage, imaging and calculation. Compared with traditional technologies, the low-power organic field effect transistor memory array of the present invention not only has a simple manufacturing process, but also has the characteristics of simple process, low preparation cost, and effective promotion. It can also integrate intrinsically flexible organic semiconductors and dielectric materials and flexible substrates to construct large-area flexible storage arrays and integrated devices, providing new inspiration for the application and development of new storage technologies and neuromorphic computing technologies in the future.

[0046] (4) The organic field effect transistor memory array of the present invention can also be used as an important carrier to be integrated with various flexible sensing materials, devices and chips, greatly improving the data processing speed and combining the three functions of sensing, storage and computing, thereby providing an important foundation for the development and application of new integrated electronic devices and smart terminals with integrated sensing-storage-computing functions.

[0047] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0049] Figure 1 A schematic diagram of the structure of the organic field effect transistor memory array prepared in Example 1;

[0050] Figure 2 Typical transfer (a) and output (b) characteristic curves of a single primitive organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 1;

[0051] Figure 3 The (a) positive bias and (b) negative bias electrical pulse response characteristics of a single unit organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 1;

[0052] Figure 4 Typical transfer (a) and output (b) characteristic curves of a single primitive organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 2;

[0053] Figure 5 The transfer (a) and output (b) characteristic curves of a single primitive organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 3;

[0054] Figure 6 The equivalent circuit diagram of the organic field effect transistor memory array prepared in Example 1 (a) and the additional equivalent circuit diagram based on image processing (b);

[0055] Figure 7 The original image of a person (a) and the electric pulse imaging image (b) of the organic field effect transistor memory array prepared in Example 1;

[0056] Figure 8 This is an imaging smoothing process diagram of the organic field effect transistor memory array prepared in Example 1;

[0057] Fig. 9 A schematic diagram of an imaging concept model of the organic field effect transistor memory array prepared in Example 1;

[0058] Among them, in the structural diagram of the organic field effect transistor memory array, 1 is the substrate, 2 is the source, 3 is the drain, 4 is the organic semiconductor layer, 5 is the dielectric passivation layer, 6 is the doped polyelectrolyte dielectric layer, and 7 is the gate. DETAILED DESCRIPTION

[0059] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0060] In the following examples, the polyelectrolyte in the dielectric material doped with a soluble zinc salt is a cross-linked compound of polyacrylic acid and polyethylene glycol (mass ratio 7:3), and the doped soluble zinc salt is zinc chloride.

[0061] In the following examples, if no specific conditions are specified, all the reactions were carried out under conventional conditions or conditions recommended by the manufacturer. Unless otherwise specified, the raw materials and solvents in the examples of the present invention were purchased from commercial sources, including:

[0062] Organic polymer semiconductor material indomethacrylic acid-benzothiadiazole copolymer was purchased from Shenzhen Ruixun Optoelectronic Material Technology Co., Ltd.;

[0063] Chlorobenzene solvent and methanol solvent were purchased from Sigma-Aldrich (Shanghai) Trading Co., Ltd.;

[0064] Polyacrylic acid and polyethylene glycol were purchased from Sigma-Aldrich (Shanghai) Trading Co., Ltd.;

[0065] Zinc chloride was purchased from Shanghai MacLean Biochemical Technology Co., Ltd.;

[0066] Polystyrene was purchased from Sigma-Aldrich (Shanghai) Trading Co., Ltd.;

[0067] Butyl acetate solvent was purchased from Sinopharm Chemical Reagent Co., Ltd.

[0068] Example 1

[0069] A low power consumption organic field effect transistor memory array, the specific structure is as follows Figure 1 As shown, it includes, from bottom to top: a substrate 1, an organic semiconductor layer 4, a dielectric passivation layer 5, a doped polyelectrolyte dielectric layer 6 and a gate 7, and 100 source / drain electrode pairs are respectively arranged between the surface of the substrate 1 and the organic semiconductor layer 4 (the source / drain electrode pairs are formed by the source 2 and the drain 3 arranged side by side). The preparation method of the low-power organic field effect transistor memory array is as follows:

[0070] (1) Using 125 μm thick polyethylene naphthalate as the substrate;

[0071] (2) On the surface of the above substrate, a vacuum thermal evaporation process (vacuum degree is about 2×10 -4 Pa, evaporation rate is about ) prepare 50 nm thick gold as the source and drain of 10×10 arrays (wherein the width and length of the channel between the source and drain are 3.75 mm and 0.15 mm, respectively), to obtain a substrate prepared with the source and drain of 10×10 arrays;

[0072] (3) In a nitrogen atmosphere, a chlorobenzene solution of an indodecene-dithiophene-benzothiadiazole copolymer with a concentration of 5 mg / mL was prepared and spin-coated onto the substrate with a 10×10 array of source and drain electrodes prepared in step (2) (the spin coating speed was 2000 rpm and the spin coating time was 30 s). After the spin coating, the organic semiconductor layer was prepared by annealing on a heating table at 90° C. for 20 min.

[0073] (4) In a nitrogen atmosphere, a 5 mg / mL polystyrene butyl acetate solution was spin-coated onto the organic semiconductor layer obtained in step (3) (the spin-coating speed was 2000 rpm and the spin-coating time was 30 s), and then allowed to stand for 10 min to form a dielectric passivation layer;

[0074] (5) In a nitrogen atmosphere, polyacrylic acid and polyethylene glycol in a mass ratio of 7:3 are dissolved in methanol to obtain a polyelectrolyte solution of polyacrylic acid and polyethylene glycol (wherein the concentration of polyacrylic acid in the solution is 30 mg / mL), zinc chloride is added for doping (wherein the mass of zinc chloride accounts for 2.62 wt.% of the total mass of the polyacrylic acid, polyethylene glycol and zinc chloride solute) to obtain a soluble zinc salt-doped polyelectrolyte dielectric material solution, which is spin-coated onto the dielectric passivation layer obtained in step (4) (the spin-coating process has a rotation speed of 500 rpm, a spin-coating time of 30 s, and a spin-coating number of times of two times), and then annealed on a heating table at 90° C. for 120 min to prepare a doped polyelectrolyte dielectric layer;

[0075] (6) On the doped polyelectrolyte dielectric layer, a vacuum thermal evaporation process (vacuum degree of about 2×10 -4 Pa, evaporation rate is about ) Prepare 50nm thick gold as the gate, where 100 gates cover the channel parts formed between the source and the drain in 100 source / drain electrode pairs respectively, and a low-power organic field-effect transistor memory array can be prepared.

[0076] Embodiments 2 to 12

[0077] The differences between the preparation process of the low power organic field effect transistor memory array in Examples 2 to 12 and Example 1 are shown in Table 1, and the parts not described are the same as those in Example 1.

[0078] Table 1 Various materials used in preparing low power organic field effect transistor memory arrays in different embodiments

[0079]

[0080]

[0081] Performance Testing

[0082] 1. Performance test of the low-power organic field-effect transistor memory array prepared in the embodiment

[0083] Using Agilent 4155c semiconductor parameter analyzer, electrical performance tests were performed on each unit organic field effect transistor memory of the organic field effect transistor memory array prepared in the above embodiment 1, and the performance fluctuation between the memory device units was small. Figure 2 The typical transfer (a) and output (b) characteristic curves of a single-element organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 1. Figure 2 It can be seen that the single primitive organic field effect transistor memory in the organic field effect transistor memory array of the present invention can operate at a low voltage of -1.5V and has good low power consumption transistor characteristics. The electric pulse response characteristics of the single primitive organic field effect transistor memory in the organic field effect transistor memory array of the above embodiment 1 are tested by further using the 4155c semiconductor parameter analyzer. By adjusting the programming gate pulse voltage, the electric pulse response characteristics of the single primitive organic field effect transistor memory in the organic field effect transistor memory array prepared in embodiment 1 are as follows: Figure 3 As shown, a is the positive bias voltage electric pulse response characteristic of the organic field effect transistor memory, and b is the negative bias voltage electric pulse response characteristic of the organic field effect transistor memory. Figure 3 It can be seen that the pulse current changes with the applied programming gate pulse voltage. The higher the programming gate pulse voltage, the larger the pulse current and the longer the current duration, indicating that the organic field effect transistor memory based on the soluble zinc salt doped polyelectrolyte dielectric layer of the present invention has excellent dynamic storage characteristics. At the same time, applying a reverse programming gate pulse voltage realizes the erasing operation of the organic field effect transistor memory in the array, and can realize fast erasing or reverse writing by ultraviolet light irradiation.

[0084] The performance of a single primitive organic field effect transistor memory in the organic field effect transistor memory array prepared in the above-mentioned embodiment 2 and embodiment 3 was tested using an Agilent 4155c semiconductor parameter analyzer. Figure 4 The typical transfer (a) and output (b) characteristic curves of a single primitive organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 2 are shown in FIG. Figure 5The transfer (a) and output (b) characteristic curves of a single unit organic field effect transistor memory in the organic field effect transistor memory array prepared in Example 3. By comparing the typical transfer and output characteristic curves of a single unit organic field effect transistor memory in the organic field effect transistor memory array in different embodiments, it can be seen that the performance of the organic field effect transistor memory of the present invention is dependent on the polyelectrolyte dielectric layer with different zinc chloride doping contents, and has the potential for easy adjustment of storage characteristics.

[0085] Similarly, the performance of a single primitive organic field effect transistor memory in the organic field effect transistor memory array prepared in other embodiments was tested according to the above test method, and the result was similar to the performance of a single primitive organic field effect transistor memory in the organic field effect transistor memory array prepared in the above embodiment 1, indicating that a single organic field effect transistor memory unit in the organic field effect transistor memory array prepared according to the present invention can also utilize the ion migration characteristics to realize low-power memory devices and arrays thereof, and has good prospects in the future research and development of polyelectrolyte system dielectric layer materials and storage applications.

[0086] 2. Application of electrical pulse imaging to organic field effect transistor memory arrays

[0087] First, based on the low-power organic field effect transistor memory array prepared in Example 1, 36 such 10×10 organic field effect transistor memory arrays are further expanded and integrated into a 60×60 array. Then, the 60×60 memory array is used to realize the electric pulse imaging of the original image of the person. The equivalent circuit diagram of the array and the additional equivalent circuit diagram based on image processing and the additional equivalent circuit diagram based on image processing are shown as follows: Figure 6 a and 6b. Figure 6 a It can be seen that the prepared 60×60 memory array has 3600 independent gates, 60 drain lead wires, and each drain wire has 60 drains connected in parallel, totaling 3600 drains, and similarly 3600 sources, ultimately forming 3600 source / drain electrode pairs. Figure 6 b is a mean current calculation circuit, which introduces four adjacent output currents in the 60×60 storage array into the mean current calculation circuit, and the circuit outputs the average value of the four output currents.

[0088] The original image of the character of the organic field effect transistor memory array prepared in Example 1 is as follows Figure 7 As shown in a, programming gate pulse voltages of +1.5, -1.5, -2.5, -3.5 and -4.5 V are applied to the storage array in sequence to distinguish the pixels in the character pixel map and form an image, and the result is as follows Figure 7b) and stores the image information in an organic field effect transistor memory array. Figure 7 It can be seen that the character electrical pulse imaging image realized by the memory array can clearly present the image details in the character pixel image, but the clarity at the edge still needs to be improved ( Figure 7 b) In particular, the clarity of the eyes and collar of clothes in the electric pulse imaging of people is poor and needs to be further improved.

[0089] 3. Smoothing calculation of organic field effect transistor memory array imaging

[0090] Thanks to the characteristics of fast storage and convenient memory of the prepared low-power organic field effect transistor memory, especially the organic field effect transistor memory with a zinc chloride doping content of 2.62wt.%, which has a wide memory window, multi-level storage characteristics and effective erasing function, this type of organic field effect transistor memory can be further integrated into a flexible storage array for image processing and analog calculation. Therefore, firstly, the four adjacent pixels in the organic field effect transistor memory array are used as the calculation area, and the five levels of programming gate pulse voltage corresponding to the pixel points of each level in the original image of the character in the organic field effect transistor memory array are applied to the calculation area. The organic field effect transistor memory array converts the received five levels of programming gate pulse voltage into a current signal and outputs it. At the same time, the output current enters the additional mean current circuit to calculate the mean of the electric pulse current in the calculation area and output it, and then transfers to the next calculation area after completion. The mean current of the calculation area is output in turn, and it is used as the center point of the calculation area to replace the entire calculation area, that is, the smoothing of the current output by the four transistors in the calculation area is completed. Finally, the obtained mean current is arranged in turn to draw an image, so as to obtain a smoothed image, as shown in Figure 8 As shown. Figure 8 It can be seen that compared with the character electric pulse imaging image of the storage array, it is found that the character image after smoothing is better in the eyes and clothing collar, and the image after image smoothing has a better character image and three-dimensional sense as a whole, indicating that the use of mean filtering to process the pixels in the storage array can better preserve the key point information data in the character imaging process. The comprehensive comparison shows the superiority of using mean filtering in the storage array, which successfully retains the key information in the character pixel image while reducing the original Figure 4 It can save one-third of the storage space and make the image smoother and more three-dimensional.

[0091] Therefore, we propose a conceptual imaging model for low-power organic field-effect transistor memory arrays. Fig. 9As shown, the electric pulse signal is used to write information point-to-point to the organic field effect transistor memory array, and the written information can be erased by ultraviolet light irradiation. At the same time, the additional mean current calculation circuit calculates the mean of the output current of the programming gate pulse voltage point-to-point written information, and the memory array can simultaneously complete the smoothing of the entire image. It can be seen that the low-power organic field effect transistor memory array of the present invention not only realizes the electric pulse imaging of the character image, and guarantees the corresponding basic image information, but also can realize the smoothing and calculation of the image using a simple additional circuit. The organic field effect transistor memory array exhibits the characteristics of fast storage and convenient memory. Using a simple storage array circuit filtering process, the display effect of the image can be directly and effectively processed, showing the application value of the organic field effect transistor memory array in the direction of pulse imaging and array simulation calculation.

[0092] In summary, the present invention discloses a low-power organic field-effect transistor memory array, which is mainly constructed by using zinc chloride doped polyacrylic acid and polyethylene glycol composite cross-linking materials to construct a doped polyelectrolyte dielectric film, and using voltage to regulate the ion migration ability in this type of new polyelectrolyte dielectric film, thereby successfully developing a low-power, high-performance flexible organic field-effect transistor memory array. The low-power organic field-effect transistor memory of the present invention can make full use of the advantages of the three-terminal structure of the organic field-effect transistor, and realize the dynamic storage regulation of the basic storage unit in the memory array by electric pulses by applying different programming gate pulse voltages to the gate, so as to meet the needs of fast storage and erasure of information learning and memory functional storage devices. In addition, the storage calculation application of the organic field-effect transistor memory array can simultaneously output the smoothing processing results of the imaging image while completing the imaging, further improving the running speed of the storage calculation. Compared with traditional technologies, the organic field-effect transistor memory array of the present invention simplifies the manufacturing process and reduces costs. It has the advantages of simple structure, excellent performance, and low energy consumption. It can be integrated into a high-density multi-pixel storage array and a large-area flexible storage array to effectively write or erase electric pulses, providing useful ideas for the research of new storage materials and devices in the future, as well as the promotion and application of technologies such as electric pulse imaging, image processing, sensor chips, and neuromorphic computing.

[0093] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A low power consumption organic field effect transistor memory array, characterized in that: The memory array is a memory array formed by integrating organic field effect transistor memories that realize storage functions based on ion migration effects; The memory array is a top-gate bottom-contact structure, and comprises, from bottom to top, a substrate (1), a source / drain electrode pair, an organic semiconductor layer (4), a dielectric passivation layer (5), a doped polyelectrolyte dielectric layer (6), and a gate (7); The source / drain electrode pair is located between the surface of the substrate (1) and the organic semiconductor layer (4), the source / drain electrode pair is composed of a source electrode (2) and a drain electrode (3) arranged side by side, and a channel with a micro-nanoscale spacing is formed between the source electrode (2) and the drain electrode (3); The number of the source / drain electrode pairs and the gate (7) is 4 or more, and the gate (7) region covers the channel region of the corresponding source / drain electrode pair.

2. The low power consumption organic field effect transistor memory array according to claim 1, characterized in that: The material of the substrate (1) is any one or more of polyethylene terephthalate, polyethylene naphthalate, polyimide, polydimethylsiloxane, polycarbonate, polyvinyl alcohol, glass, silicon wafer or sapphire.

3. The low power consumption organic field effect transistor memory array according to claim 1, characterized in that: The material of the source electrode (2), the drain electrode (3) or the gate electrode (7) is any one or more of gold, silver, aluminum, copper, chromium, platinum, titanium, nickel, indium tin oxide, fluorine-doped tin oxide, zinc aluminum oxide, carbon nanotubes, graphene or conductive polymers; The conductive polymer has a conjugated main electron system on its main chain and is a polymer material that achieves a conductive state through doping. The conductive polymer includes any one of polypyrrole, polyaniline, polythiophene, poly(3,4-ethylenedioxythiophene) or polyacetylene.

4. The low power consumption organic field effect transistor memory array according to claim 1, characterized in that: The material of the organic semiconductor layer (4) is an organic small molecule semiconductor material or a conjugated polymer semiconductor material; The organic small molecule semiconductor material includes any one or more of pentacene or its derivatives, 7,7,8,8-tetracyanoquinodimethane or its derivatives, and copper phthalocyanine; The conjugated polymer semiconductor material includes any one or more of poly 3-hexylthiophene or its derivatives, indomethacin-1,1-dithiophene-benzothiadiazole copolymer, 7,7,8,8-tetracyanoquinodimethane-doped indomethacin-1,1-dithiophene-benzothiadiazole copolymer, poly{4,8-bis[(2-ethylhexyl)oxy]benzo[1,2-b:4,5-b']disulfide-2,6-diyl}{3-fluoro-2-[(2-ethylhexyl)carbonyl]thieno[3,4-b]thiophenediyl} or its derivatives, and copolymers of terthiophene and perylene imide units.

5. The low power consumption organic field effect transistor memory array according to claim 1, characterized in that: The material of the dielectric passivation layer (5) includes any one or more of polymethyl methacrylate or its derivatives, polystyrene or its derivatives, amorphous fluororesin or its derivatives, aluminum oxide, hafnium dioxide or zirconium dioxide.

6. The low power consumption organic field effect transistor memory array according to claim 1, characterized in that: The doped polyelectrolyte dielectric layer (6) is a dielectric film material of a soluble zinc salt doped polyelectrolyte; The material of the polyelectrolyte in the dielectric film material of the soluble zinc salt doped polyelectrolyte is at least one of polyacrylic acid or its derivatives, polyacrylamide or its derivatives, a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polymethyl methacrylate, a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polyethylene glycol, and a polyelectrolyte composite dielectric material formed by a composite of polyacrylic acid and polyvinyl alcohol; The soluble zinc salt is any one or more of zinc chloride, zinc bromide, zinc iodide, zinc acetate, zinc sulfate, zinc nitrate, zinc fluorosilicate, zinc fluoroborate or zinc gluconate.

7. The low power consumption organic field effect transistor memory array according to claim 6, characterized in that: The dielectric film material of the soluble zinc salt doped polyelectrolyte is prepared according to the following method: First, a polyelectrolyte material is dissolved in a solvent to obtain a polyelectrolyte precursor solution; then, a soluble zinc salt is added and fully dissolved to obtain a soluble zinc salt-doped polyelectrolyte dielectric material solution; finally, the solution is processed into a film by a solution processing method and annealed to prepare a soluble zinc salt-doped polyelectrolyte dielectric film material; The doping content of the soluble zinc salt accounts for 0.5-10 wt.% of the total mass of the entire polyelectrolyte material and the zinc salt material.

8. The method for preparing a low power consumption organic field effect transistor memory array according to any one of claims 1 to 7, characterized in that: The preparation method comprises the following steps: (1) forming four or more pairs of source / drain electrode pairs consisting of source and drain electrodes arranged side by side on the surface of the substrate by any one of vacuum thermal evaporation, magnetron sputtering, atomic layer deposition, inkjet printing or drop coating, wherein a channel with a micro-nanoscale spacing is formed between the source and drain electrodes; (2) forming an organic semiconductor layer on the surface of the source electrode, the drain electrode and the substrate by any one of spin coating, blade coating or inkjet printing; (3) forming a dielectric passivation layer on the surface of the organic semiconductor layer by any one of atomic layer deposition, vacuum thermal evaporation, magnetron sputtering, spin coating, doctor blade coating or inkjet printing; (4) on the surface of the dielectric passivation layer, a solution of a dielectric material doped with a soluble zinc salt and a polyelectrolyte is processed into a film by a solution processing method, and then annealed to form a doped polyelectrolyte dielectric layer; (5) On the surface of the doped polyelectrolyte dielectric layer, a mask is combined and a gate is formed by any one of magnetron sputtering, vacuum thermal evaporation, atomic layer deposition, inkjet printing or drop coating, wherein the number of the gates is the same as the number of source / drain electrode pairs, thereby obtaining a low-power organic field-effect transistor memory array.

9. The preparation method according to claim 8, characterized in that: In step (4), the solution processing method is any one of spin coating, blade coating or inkjet printing; In step (4), the concentration of the polyelectrolyte material in the solution used in the spin coating method is 5 to 50 mg / mL, the spin coating speed is 200 to 4000 rpm, and the spin coating time is 30 to 120 s; In step (4), the annealing temperature is 50-200° C., and the annealing time is not less than 60 minutes.

10. Application of the low-power organic field-effect transistor memory array according to any one of claims 1 to 7 in pulse imaging, image processing, artificial synapse or neuromorphic computing technology.

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