Power gating system, power gating method and system on chip

Abstract

The invention discloses a power gating system, a power gating method and a system on chip. Relates to the technical field of power management, and comprises a central processing unit used for writing software power-down configuration information into a register module; the register module is used for triggering a software power-down request according to the software power-down configuration information and sending the software power-down request to the power gating controller; the system power consumption controller is used for determining a system power consumption mode according to the state of the central processing unit, triggering a hardware power-down request and sending the hardware power-down request to the power gating controller under the condition that the system power consumption mode is a low-power-consumption mode; and the power gate controller is used for detecting the state of a bus of the power domain based on the software power-down request or the hardware power-down request, and executing power-down time sequence control on the power domain under the condition that the state of the bus is detected to be an idle state. The technical problems that the power gating speed is low and the software overhead is large when the bus state is inquired through software with high complexity in the prior art are solved.

Description

Technical Field

[0001] The present application relates to the technical field of power management, and in particular to a power gating system, a power gating method and a system on chip. Background Art

[0002] With the development of semiconductor process technology and the increasing complexity of system design, the importance of power consumption in integrated circuit design has become increasingly prominent. High power consumption brings many serious challenges, such as increasing the operating temperature of the chip, reducing the reliability of the chip, shortening the battery life of the device, and increasing the power supply cost of the device.

[0003] Power gating is an important technology to reduce chip power consumption. It is achieved by turning off the power of a certain power domain on the chip to completely save the power consumption of that part of the circuit. Before turning off the power of a power domain, it is necessary to ensure that the bus in the power domain is in an idle state and there is no unfinished data transmission. If there is an active bus in the power domain, turning off the power of the power domain will cause data transmission interruption and lead to chip function failure. Therefore, bus status detection before power gating is of great significance for the safe shutdown of the power domain.

[0004] At present, in the related technology, before executing the power-off timing control on the power domain, the system ensures that the bus enters the idle state through software. For example, before turning off the power of a power domain, the software first queries in the power domain to see if all devices on the bus have completed data transmission, and then turns off the power of the power domain. However, for complex systems, the devices on the bus may be located in multiple power domains, and the software needs to query all devices related to this bus, which is inefficient, has a large delay, has a large software overhead, and has a low power gating speed.

[0005] To address the above-mentioned problems, no effective solution has been proposed yet. Summary of the invention

[0006] The embodiments of the present application provide a power gating system, a power gating method and a system on chip, so as to at least solve the technical problems in the related art of querying the bus status through highly complex software before executing power-off timing control on the power domain, resulting in low power gating speed and large software overhead.

[0007] According to one aspect of an embodiment of the present application, a power gating system is provided, including: a central processing unit, used to write software power-off configuration information to a register module, wherein the software power-off configuration information is configuration information of a power gating controller; a register module, used to trigger a software power-off request based on the software power-off configuration information and send it to the power gating controller; a system power consumption controller, used to determine a system power consumption mode based on a state of the central processing unit, and when the system power consumption mode is a low power consumption mode, trigger a hardware power-off request and send it to the power gating controller; a power gating controller, used to detect the state of a bus of a power domain based on a software power-off request or a hardware power-off request, and when it is detected that the state of the bus is an idle state, perform power-off timing control on the power domain.

[0008] Furthermore, the power gating system also includes: an isolation unit, which is used to receive an isolation enable signal issued by a power gating controller during the process of executing power-off timing control on a power domain, and isolate the output signal of the power domain based on the isolation enable signal; a reset generation module, which is used to receive a reset control signal issued by a power gating controller during the process of executing power-off timing control on a power domain, and reset the power domain based on the reset control signal; and a clock generation module, which is used to receive a clock gating signal issued by a power gating controller during the process of executing power-off timing control on a power domain, and control the clock of the power domain based on the clock gating signal.

[0009] Furthermore, the power gating controller is also used to control the memory of the power domain to enter a shutdown mode after controlling the clock of the power domain based on the clock gating signal; the power gating controller is also used to control the power switch of the power domain to be turned off after controlling the memory of the power domain to enter a shutdown mode.

[0010] Furthermore, the power gating system further includes: a system interrupt controller, which is used to receive a power failure interrupt signal sent by the power gating controller after the power switch of the controlled power domain is turned off, and feed back the power failure interrupt signal to the central processing unit.

[0011] Furthermore, the system interrupt controller is also used to receive a power-off interrupt signal sent by the power gating controller when detecting that the state of the bus is an active state, and feed back the power-off interrupt signal to the central processing unit.

[0012] Furthermore, the power gating controller includes: a power gating control state machine, which is used to receive a software power-off request from a register module or a hardware power-off request from a system power consumption controller, and generate a bus state detection start signal to send to a bus state detection circuit; a bus state detection circuit, which is used to interact with the bus low power consumption interface of the power domain after receiving the bus state detection start signal, and when the interaction is successful, determine that the state of the bus is an idle state, and generate a bus idle state signal to return to the power gating control state machine.

[0013] Furthermore, the power gating control state machine is also used to generate an isolation enable signal to the isolation unit, a reset control signal to the reset generation module, a clock gating signal to the clock generation module, a shutdown control signal to the memory of the power domain, and a shutdown control signal to the power switch of the power domain based on the bus idle state signal after receiving the bus idle state signal.

[0014] Furthermore, the power gating controller also includes: an interrupt generating circuit for receiving a power-off completion status signal generated by the power gating control state machine after receiving a feedback signal from the power switch of the power domain, and generating a power-off interrupt to the system interrupt controller based on the power-off completion status signal.

[0015] Furthermore, the bus state detection circuit is also used to determine that the state of the bus is an active state when the interaction fails, and to generate a bus active state signal to return to the power gating control state machine.

[0016] Furthermore, the interrupt generation circuit is also used to receive a bus low power rejection signal generated by the power gating control state machine based on the bus activity state signal, and generate a bus low power rejection interrupt to the system interrupt controller based on the bus low power rejection signal.

[0017] Furthermore, the register module is also used to transmit the interval time between the steps in the process of controlling the power off of the power domain to the power gating controller, so that the power gating controller executes the process of controlling the power off of the power domain based on the interval time between the steps, wherein the process of controlling the power off of the power domain at least includes detecting the state of the bus of the power domain and performing power off timing control on the power domain.

[0018] Furthermore, the register module is also used to transmit an interrupt clear signal to the power gating controller so that the power gating controller clears the interrupt based on the interrupt clear signal; the register module is also used to transmit an interrupt mask signal to the power gating controller so that the power gating controller masks the interrupt based on the interrupt mask signal.

[0019] According to one aspect of an embodiment of the present application, a power gating method is provided, comprising: writing software power-off configuration information to a register module through a central processing unit, wherein the software power-off configuration information is configuration information of a power gating controller; triggering a software power-off request through the register module according to the software power-off configuration information and sending the request to the power gating controller; determining a system power consumption mode through a system power consumption controller according to a state of the central processing unit, and triggering a hardware power-off request and sending the request to the power gating controller when the system power consumption mode is a low power consumption mode; detecting the state of a bus of a power domain based on a software power-off request or a hardware power-off request through the power gating controller, and executing power-off timing control on the power domain when the state of the bus is detected to be an idle state.

[0020] According to another aspect of an embodiment of the present invention, a system on chip is provided, including: a memory storing an executable program; and a processor for running the program, wherein the power gating method described above is executed when the program is running.

[0021] According to another aspect of an embodiment of the present invention, a computing device is provided. The computing device uses the above-mentioned system on chip when performing calculations.

[0022] According to another aspect of an embodiment of the present invention, a computer program product is provided, including a computer program or instructions, and the computer program or instructions implement the above power gating method when executed by a processor.

[0023] In an embodiment of the present application, a power gating system supporting bus state detection is provided, wherein software power-off configuration information is written to a register module by a central processing unit, wherein the software power-off configuration information is configuration information of a power gating controller; a software power-off request is triggered by the register module according to the software power-off configuration information and sent to the power gating controller; a system power consumption mode is determined by a system power consumption controller according to the state of the central processing unit, and when the system power consumption mode is a low power consumption mode, a hardware power-off request is triggered and sent to the power gating controller; a power gating controller detects the state of a bus of a power domain based on a software power-off request or a hardware power-off request, and when the state of the bus is detected to be an idle state, a power-off timing control is performed on the power domain, thereby realizing that before the power-off timing control is performed on the power domain, the bus state of the power domain is detected by hardware, thereby ensuring the safety of power-off of the power domain, achieving the purpose of reducing the complexity of software design and improving the efficiency of bus state detection, thereby achieving the technical effect of improving the power gating speed, and thus solving the technical problem that before the power-off timing control is performed on the power domain, the bus state is queried by a software method with high complexity, and the power gating speed is low and the software overhead is large. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0025] Figure 1 A schematic diagram of a power gating system provided according to Embodiment 1 of the present application Figure 1 ;

[0026] Figure 2 A schematic diagram of a power gating system provided according to Embodiment 1 of the present application Figure 2 ;

[0027] Figure 3 is a schematic diagram of a power gating controller provided according to Embodiment 1 of the present application;

[0028] Figure 4 It is a schematic diagram of a flow chart of a power gating controller controlling power-off of a power domain according to the first embodiment of the present application;

[0029] Figure 5 It is a schematic diagram of a process of controlling power-on of a power domain by a power gating controller provided in Embodiment 1 of the present application;

[0030] Figure 6 is a flow chart of a power gating method provided according to Embodiment 2 of the present application;

[0031] Figure 7 It is a structural block diagram of a computing device provided according to Embodiment 4 of the present application. DETAILED DESCRIPTION

[0032] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0033] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchangeable where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0034] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards in the relevant regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0035] First, some nouns or terms that appear in the description of the embodiments of the present application are subject to the following explanations:

[0036] Power Gating: A power management technology that is mainly used to reduce the power consumption of an integrated circuit (IC) or system-on-chip (SoC) in standby mode by cutting off the power supply of unnecessary modules or circuits to reduce static power consumption and thus improve energy efficiency.

[0037] Bus: In digital circuits, a bus is a set of signal channels used to transfer data and control signals between different components or modules.

[0038] System-on-a-chip (SoC) refers to the technology of integrating a complete system on a single chip and packaging all or part of the necessary electronic circuits.

[0039] Example 1

[0040] With the development of semiconductor process technology and the increasing complexity of system design, the importance of power consumption in integrated circuit design has become increasingly prominent. High power consumption brings many serious challenges, such as increasing the operating temperature of the chip, reducing the reliability of the chip, shortening the battery life of the device, and increasing the power supply cost of the device.

[0041] Power gating is an important technology to reduce chip power consumption. It is achieved by turning off the power of a certain power domain on the chip to completely save the power consumption of that part of the circuit. Before turning off the power of a power domain, it is necessary to ensure that the bus in the power domain is in an idle state and there is no unfinished data transmission. If there is an active bus in the power domain, turning off the power of the power domain will cause data transmission interruption and lead to chip function failure. Therefore, bus status detection before power gating is of great significance for the safe shutdown of the power domain.

[0042] At present, in the related technology, before executing the power-off timing control on the power domain, the system ensures that the bus enters the idle state through software. For example, before turning off the power of a power domain, the software first queries in the power domain to see if all devices on the bus have completed data transmission, and then turns off the power of the power domain. However, for complex systems, the devices on the bus may be located in multiple power domains, and the software needs to query all devices related to this bus, which is inefficient, has a large delay, has a large software overhead, and has a low power gating speed.

[0043] In the above technical background, the present application provides Figure 1 The power gating system shown. Figure 1 A schematic diagram of a power gating system provided according to Embodiment 1 of the present application Figure 1 The system includes:

[0044] A central processing unit, used for writing software power-off configuration information into the register module, wherein the software power-off configuration information is configuration information of a power gating controller;

[0045] A register module, used for triggering a software power-down request according to the software power-down configuration information and sending the request to the power gating controller;

[0046] The system power consumption controller is used to determine the system power consumption mode according to the state of the central processing unit, and trigger a hardware power-off request and send it to the power gating controller when the system power consumption mode is a low power consumption mode;

[0047] The power gating controller is used to detect the state of the bus of the power domain based on a software power-off request or a hardware power-off request, and perform power-off timing control on the power domain when it is detected that the state of the bus is an idle state.

[0048] Optionally, the central processing unit may write software power-off configuration information to the register module. For example, the central processing unit may write registers in the register module to generate a configuration signal to a power gating controller (such as the power gating controller 1).

[0049] Optionally, the register module may trigger a software power-down request according to the software power-down configuration information and send the request to the power gating controller.

[0050] Optionally, the system power consumption controller is responsible for switching and managing the system power consumption mode, and can issue a hardware power-off request to the power gating controller, and can also issue a hardware power-on request to the power gating controller. For example, the system power consumption controller can determine the system power consumption mode based on the state of the central processing unit, and when the system power consumption mode is a low power consumption mode, trigger a hardware power-off request and send it to the power gating controller.

[0051] Optionally, the power gating controller is responsible for controlling the power gating of the power domain, such as Figure 1 As shown, each power domain corresponds to its own power gating controller. The power domain includes at least one group of buses. The power gating controller can detect the state of the bus of the power domain based on a software power-off request or a hardware power-off request, and perform power-off timing control on the power domain when it is detected that the state of the bus is in an idle state.

[0052] In an optional embodiment, the present application provides Figure 2 The power gating system shown. Figure 2 A schematic diagram of a power gating system provided according to Embodiment 1 of the present application Figure 2 Optionally, the power gating system further includes: an isolation unit, which is used to receive an isolation enable signal issued by a power gating controller during the process of performing power-off timing control on a power domain, and isolate the output signal of the power domain based on the isolation enable signal; a reset generation module, which is used to receive a reset control signal issued by a power gating controller during the process of performing power-off timing control on a power domain, and reset the power domain based on the reset control signal; and a clock generation module, which is used to receive a clock gating signal issued by a power gating controller during the process of performing power-off timing control on a power domain, and control the clock of the power domain based on the clock gating signal.

[0053] Optionally, when the power gating controller detects that the bus state is in an idle state, it starts a power-off process for the power domain, for example, Figure 2 As shown, the power gating controller 1 sends an isolation enable signal to the isolation unit corresponding to the power domain 1 to enable the isolation unit corresponding to the power domain 1; the power gating controller 1 sends a reset control signal to the reset generation module corresponding to the power domain 1 to reset the power domain 1; the power gating controller 1 sends a clock gating signal to the clock generation module corresponding to the power domain 1 to gate the clock of the power domain 1.

[0054] The isolation unit can receive the isolation enable signal issued by the power gating controller, and isolate the output signal of the power domain based on the isolation enable signal; the reset generation module can receive the reset control signal issued by the power gating controller, and reset the power domain based on the reset control signal; the clock generation module can receive the clock gating signal issued by the power gating controller, and control the clock of the power domain based on the clock gating signal.

[0055] In an optional embodiment, the power gating controller is also used to control the memory of the power domain to enter a shutdown mode after controlling the clock of the power domain based on a clock gating signal; the power gating controller is also used to control the power switch of the power domain to be turned off after controlling the memory of the power domain to enter a shutdown mode.

[0056] Alternatively, if Figure 2 As shown, the power gating controller 1 can also send a memory control signal to the memory (Memory) of the power domain 1 to control the memory of the power domain 1 to enter the shutdown mode (ShutDown mode). The power gating controller 1 can also send a power switch control signal to the power switch of the power domain 1 to control the power switch of the power domain 1 to turn off, and receive the feedback signal of the power switch of the power domain 1 to generate a power-off interrupt to the system interrupt controller, and the power-off process ends.

[0057] In an optional embodiment, the power gating system further includes: a system interrupt controller, configured to receive a power-off interrupt signal sent by the power gating controller after the power switch of the controlled power domain is turned off, and feed the power-off interrupt signal back to the central processing unit.

[0058] Alternatively, if Figure 2 As shown, the power gating system also includes a system interrupt controller, which can receive a power-off interrupt signal sent by the power gating controller and feed the power-off interrupt signal back to the central processing unit, that is, the system interrupt controller can receive an interrupt source from the power gating controller and generate an interrupt signal to the central processing unit.

[0059] In an optional embodiment, the system interrupt controller is further configured to receive a power-off interrupt signal sent by the power gating controller when detecting that the bus state is an active state, and feed the power-off interrupt signal back to the central processing unit.

[0060] Optionally, after the power gating controller detects the state of the bus in the power domain based on a software power-off request or a hardware power-off request, if it is detected that the state of the bus is active, an interrupt is generated to the system interrupt controller and the power-off process is ended. At this time, the system interrupt controller can receive the power-off interrupt signal issued by the power gating controller and feed the power-off interrupt signal back to the central processing unit.

[0061] In an optional embodiment, the power gating controller includes: a power gating control state machine, which is used to receive a software power-off request from a register module or a hardware power-off request from a system power consumption controller, and generate a bus state detection start signal to send to a bus state detection circuit; a bus state detection circuit, which is used to interact with the bus low power consumption interface of the power domain after receiving the bus state detection start signal, and when the interaction is successful, determine that the state of the bus is an idle state, and generate a bus idle state signal to return to the power gating control state machine.

[0062] Optionally, the power gating controller includes a power gating control state machine and a bus state detection circuit. The power gating control state machine can receive a software power-off request from a register module or a hardware power-off request from a system power consumption controller, generate a bus state detection start signal and send it to the bus state detection circuit. After receiving the bus state detection start signal, the bus state detection circuit can interact with the bus low power consumption interface of the power domain, and if the interaction is successful, determine that the state of the bus is an idle state, generate a bus idle state signal and return it to the power gating control state machine.

[0063] In an optional embodiment, the power gating control state machine is also used to generate an isolation enable signal to the isolation unit, a reset control signal to the reset generation module, a clock gating signal to the clock generation module, a shutdown control signal to the memory of the power domain, and a shutdown control signal to the power switch of the power domain based on the bus idle state signal after receiving the bus idle state signal.

[0064] Optionally, after receiving the bus idle state signal, the power gating control state machine can also generate an isolation enable signal to the isolation unit based on the bus idle state signal, send the isolation enable signal to the isolation unit corresponding to the power domain, and enable the isolation unit corresponding to the power domain; generate a reset control signal to the reset generation module based on the bus idle state signal, and send the reset control signal to the reset generation module corresponding to the power domain to reset the power domain; generate a clock gating signal to the clock generation module based on the bus idle state signal, and send the clock gating signal to the clock generation module corresponding to the power domain to gate the clock of the power domain; generate a shutdown control signal (i.e., the aforementioned memory control signal) to the memory of the power domain based on the bus idle state signal, send the shutdown control signal to the memory of the power domain, and control the memory of the power domain to enter the shutdown mode; generate a shutdown control signal (i.e., the aforementioned power switch control signal) to the power switch of the power domain based on the bus idle state signal, and send the shutdown control signal to the power switch of the power domain to control the power switch of the power domain to shut down.

[0065] In an optional embodiment, the power gating controller also includes: an interrupt generating circuit, which is used to receive a power-off completion status signal generated by the power gating control state machine after receiving a feedback signal from the power switch of the power domain, and generate a power-off interrupt to the system interrupt controller based on the power-off completion status signal.

[0066] Optionally, the power gating controller also includes an interrupt generating circuit, which can receive a power-off completion status signal generated by the power gating control state machine after receiving a feedback signal from the power switch of the power domain, and generate a power-off interrupt to the system interrupt controller based on the power-off completion status signal.

[0067] In an optional embodiment, the bus state detection circuit is further used to determine that the state of the bus is an active state when the interaction fails, and generate a bus active state signal to return to the power gating control state machine.

[0068] Optionally, after receiving the bus state detection start signal, the bus state detection circuit can interact with the bus low power interface of the power domain. If the interaction fails, it determines that the bus state is active and generates a bus activity state signal to return to the power gating control state machine.

[0069] In an optional embodiment, the interrupt generation circuit is also used to receive a bus low power rejection signal generated by the power gating control state machine based on the bus activity state signal, and generate a bus low power rejection interrupt to the system interrupt controller based on the bus low power rejection signal.

[0070] Optionally, the power gating control state machine generates a bus low power rejection signal based on the bus activity status signal and sends it to the interrupt generation circuit. The interrupt generation circuit can receive the bus low power rejection signal generated by the power gating control state machine based on the bus activity status signal, and generate a bus low power rejection interrupt to the system interrupt controller based on the bus low power rejection signal.

[0071] Figure 3 is a schematic diagram of a power gating controller provided according to the first embodiment of the present application, such as Figure 3 As shown, the power gating controller includes a power gating control state machine, a bus state detection circuit and an interrupt generation circuit.

[0072] The power gating control state machine is responsible for implementing the power-off (or power-on) control process of the power domain. It receives a software power-off request reg_pd_req (or a power-on request reg_pu_req) from a register, or receives a hardware power-off request hw_pd_req (or a power-on request hw_pu_req) from a system power consumption controller, generates an isolation enable signal hw_iso_en for the isolation unit, a clock gating signal hw_clk_en for the clock generation module, a reset control signal hw_rst_n for the reset generation module, a memory control signal hw_mem_sd for the memory of the power domain, a power switch control signal hw_sw_en for the power switch of the power domain, and receives a feedback signal hw_sw_ack from the power switch.

[0073] After the bus state detection circuit detects the bus state detection start signal bus_test, it interacts with the bus in the power domain based on the low-power interface of the bus, confirms the idle state of the bus, and returns the bus idle state signal bus_idle or the bus active state signal bus_busy to the power gating control state machine.

[0074] The power gating control state machine generates a power-down completion state signal pd_done (or a power-on completion state signal pu_done), or a bus low power consumption rejection signal bus_deny to the interrupt generation circuit. The interrupt generation circuit generates a power-down interrupt pd_int (or a power-on interrupt pu_int), or a bus low power consumption rejection interrupt bus_int to the system interrupt controller.

[0075] In an optional embodiment, the register module is also used to transmit the interval time between the steps in the process of controlling power off of the power domain to the power gating controller, so that the power gating controller executes the process of controlling power off of the power domain based on the interval time between the steps, wherein the process of controlling power off of the power domain at least includes detecting the state of the bus of the power domain and performing power off timing control on the power domain.

[0076] Optionally, the register module may also transmit the interval time between the steps in the process of controlling the power domain power off to the power gating controller, so that the power gating controller executes the process of controlling the power domain power off based on the interval time between the steps. Figure 3 As shown, the registers in the register module can transmit the interval time between the steps in the process of controlling the power off (or power on) of the power domain to the power gating control state machine, that is, the counter waiting count value corresponding to each step in the power off (or power on) control process comes from the register reg_wait_cnt.

[0077] In an optional embodiment, the register module is also used to transmit an interrupt clear signal to the power gating controller so that the power gating controller clears the interrupt based on the interrupt clear signal; the register module is also used to transmit an interrupt mask signal to the power gating controller so that the power gating controller masks the interrupt based on the interrupt mask signal.

[0078] Optionally, the register module may also transmit an interrupt clear signal to the power gating controller, so that the power gating controller clears the interrupt based on the interrupt clear signal; the register module may also transmit an interrupt mask signal to the power gating controller, so that the power gating controller masks the interrupt based on the interrupt mask signal. Figure 3 As shown, for the power gating control state machine, the reg_int_clr from the register can be used to clear the interrupt, and the reg_int_mask can be used to mask the interrupt.

[0079] In the embodiment of the present application, a power gating system supporting bus status detection is provided. Before the power-off timing control is performed on the power domain, the bus status in the power domain is detected by hardware. The power domain will be further powered off only when the bus is in an idle state, otherwise an interruption will be generated, thereby ensuring the safety of power-off of the power domain, reducing the complexity of software design, and improving the speed of power gating. The system can receive power-on and power-off requests from software, as well as power-on and power-off requests from hardware during power consumption mode switching. It can be applied to a variety of scenarios with power-on and power-off requirements, has good versatility, covers a variety of controls such as power gating, clock, reset, isolation, and memory shutdown in the power-on and power-off process of the power domain, and can be widely used in the power-on and power-off control of the power domain.

[0080] In an optional embodiment, Figure 4 FIG. 1 is a flow chart of a power gating controller controlling power-off of a power domain according to the first embodiment of the present application. Figure 4 As shown in the figure, the process of the power gating controller controlling the power domain power down is as follows:

[0081] The central processing unit generates a software power-off request to the power gating controller by configuring the registers in the register module, or the system power consumption controller generates a hardware power-off request to the power gating controller according to the low power consumption mode of the system;

[0082] The power gating controller detects the bus status of the power domain. If there is an active bus, an interrupt is generated to the system interrupt controller and the power-off process ends.

[0083] If all buses in the power domain are in an idle state, the power gating controller starts to power down, including enabling the isolation unit of the power domain, resetting the power domain, gating the clock of the power domain, controlling the memory in the power domain to enter the shutdown mode, and turning off the power switch of the power domain;

[0084] The power gating controller generates a power-off interrupt to the system interrupt controller, and the power-off process ends.

[0085] In an optional embodiment, Figure 5 FIG. 1 is a flow chart of a power gating controller controlling power on of a power domain according to the first embodiment of the present application. Figure 5 As shown in the figure, the process of the power gating controller controlling the power domain to power on is as follows:

[0086] The central processing unit generates a software power-on request to the power gating controller by configuring the registers in the register module, or the system power mode controller generates a hardware power-on request to the power gating controller according to the system wake-up request;

[0087] The power gating controller completes the power-on process, including turning on the power switch of the power domain, controlling the memory to enter the normal working mode, releasing the isolation unit of the power domain, turning on the clock of the power domain, and releasing the reset of the power domain;

[0088] The power gating controller generates a power-on interrupt to the system interrupt controller, and the power-on process ends.

[0089] In an embodiment of the present application, a power gating system supporting bus state detection is provided, wherein software power-off configuration information is written to a register module by a central processing unit, wherein the software power-off configuration information is configuration information of a power gating controller; a software power-off request is triggered by the register module according to the software power-off configuration information and sent to the power gating controller; a system power consumption mode is determined by a system power consumption controller according to the state of the central processing unit, and when the system power consumption mode is a low power consumption mode, a hardware power-off request is triggered and sent to the power gating controller; a power gating controller detects the state of a bus of a power domain based on a software power-off request or a hardware power-off request, and when the state of the bus is detected to be an idle state, a power-off timing control is performed on the power domain, thereby realizing that before the power-off timing control is performed on the power domain, the bus state of the power domain is detected by hardware, thereby ensuring the safety of power-off of the power domain, achieving the purpose of reducing the complexity of software design and improving the efficiency of bus state detection, thereby achieving the technical effect of improving the power gating speed, and thus solving the technical problem that before the power-off timing control is performed on the power domain, the bus state is queried by a software method with high complexity, and the power gating speed is low and the software overhead is large.

[0090] Example 2

[0091] With the development of semiconductor process technology and the increasing complexity of system design, the importance of power consumption in integrated circuit design has become increasingly prominent. High power consumption brings many serious challenges, such as increasing the operating temperature of the chip, reducing the reliability of the chip, shortening the battery life of the device, and increasing the power supply cost of the device.

[0092] Power gating is an important technology to reduce chip power consumption. It is achieved by turning off the power of a certain power domain on the chip to completely save the power consumption of that part of the circuit. Before turning off the power of a power domain, it is necessary to ensure that the bus in the power domain is in an idle state and there is no unfinished data transmission. If there is an active bus in the power domain, turning off the power of the power domain will cause data transmission interruption and lead to chip function failure. Therefore, bus status detection before power gating is of great significance for the safe shutdown of the power domain.

[0093] At present, in the related technology, before executing the power-off timing control on the power domain, the system ensures that the bus enters the idle state through software. For example, before turning off the power of a power domain, the software first queries in the power domain to see if all devices on the bus have completed data transmission, and then turns off the power of the power domain. However, for complex systems, the devices on the bus may be located in multiple power domains, and the software needs to query all devices related to this bus, which is inefficient, has a large delay, has a large software overhead, and has a low power gating speed.

[0094] In the above technical background, the present application provides Figure 6 The power gating method shown. Figure 6 1 is a flow chart of a power gating method provided according to Embodiment 2 of the present application. The method comprises:

[0095] Step S601, writing software power-off configuration information into a register module through a central processing unit, wherein the software power-off configuration information is configuration information of a power gating controller;

[0096] Step S602, triggering a software power-off request according to the software power-off configuration information through a register module and sending the request to a power gating controller;

[0097] Step S603, determining the system power consumption mode according to the state of the central processing unit through the system power consumption controller, and triggering a hardware power-off request and sending it to the power gating controller when the system power consumption mode is a low power consumption mode;

[0098] Step S604: The power gating controller detects the state of the bus of the power domain based on the software power-off request or the hardware power-off request, and performs power-off timing control on the power domain when it is detected that the state of the bus is an idle state.

[0099] In this solution, software power-off configuration information is written to the register module by the central processing unit, wherein the software power-off configuration information is the configuration information of the power gating controller; a software power-off request is triggered by the register module according to the software power-off configuration information and sent to the power gating controller; a system power consumption mode is determined by the system power consumption controller according to the state of the central processing unit, and when the system power consumption mode is a low power consumption mode, a hardware power-off request is triggered and sent to the power gating controller; the power gating controller detects the state of the bus of the power domain based on the software power-off request or the hardware power-off request, and when the state of the bus is detected to be an idle state, a power-off timing control is performed on the power domain, thereby realizing that before the power-off timing control is performed on the power domain, the bus state of the power domain is detected by hardware, and the safety of the power domain power-off is ensured, and the purpose of reducing the complexity of software design and improving the efficiency of bus state detection is achieved, thereby achieving the technical effect of improving the power gating speed, and then solving the technical problems of low power gating speed and large software overhead in the related technology that the bus state is queried by a highly complex software method before the power-off timing control is performed on the power domain.

[0100] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

[0101] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods of each embodiment of the present application.

[0102] Example 3

[0103] An embodiment of the present application can provide a system on chip, which can execute the program code of the following steps in the power gating method: writing software power-off configuration information to a register module through a central processing unit, wherein the software power-off configuration information is the configuration information of a power gating controller; triggering a software power-off request through the register module based on the software power-off configuration information and sending it to the power gating controller; determining a system power consumption mode through a system power consumption controller based on the state of the central processing unit, and triggering a hardware power-off request and sending it to the power gating controller when the system power consumption mode is a low power consumption mode; detecting the state of the bus of the power domain based on the software power-off request or the hardware power-off request through the power gating controller, and executing power-off timing control on the power domain when it is detected that the state of the bus is an idle state.

[0104] Example 4

[0105] An embodiment of the present application also provides a computing device, which uses the above-mentioned system on chip when performing calculations.

[0106] Optionally, Figure 7 is a structural block diagram of a computing device according to an embodiment of the present application. Figure 7 As shown, the computing device 70 may include: one or more ( Figure 7 Only one is shown in the figure) processor 702, memory 704. The computing device 70 may also include a storage controller, through which the memory 704 is controlled and managed; the computing device 70 may also include a bus, through which the access device is connected.

[0107] Among them, the memory can be used to store software programs and modules, such as program instructions / modules corresponding to the power gating method in the embodiment of the present application. The processor executes various functional applications and data processing by running the software programs and modules stored in the memory, that is, the above-mentioned power gating method is realized. The memory may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory may further include a memory remotely arranged relative to the processor, and these remote memories can be connected to the terminal 10 via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0108] The processor can call the information and application programs stored in the memory through the transmission device to execute the following steps: write software power-off configuration information to the register module through the central processing unit, wherein the software power-off configuration information is the configuration information of the power gating controller; trigger a software power-off request according to the software power-off configuration information through the register module and send it to the power gating controller; determine the system power consumption mode according to the state of the central processing unit through the system power consumption controller, and when the system power consumption mode is a low power consumption mode, trigger a hardware power-off request and send it to the power gating controller; detect the state of the bus of the power domain based on the software power-off request or the hardware power-off request through the power gating controller, and when it is detected that the state of the bus is an idle state, perform power-off timing control on the power domain.

[0109] It can be understood by those skilled in the art that Figure 7 The structure shown is for illustration only. Figure 7 The structure of the electronic device is not limited. For example, the computing device 70 may also include Figure 7 More or fewer components (such as network interfaces, display devices, etc.) shown in, or having Figure 7 Different configurations are shown.

[0110] A person of ordinary skill in the art can understand that all or part of the steps in the various methods of the above embodiments can be completed by instructing the hardware related to the terminal device through a program, and the program can be stored in a computer-readable storage medium, and the storage medium may include: a flash drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk, etc.

[0111] Example 5

[0112] The embodiment of the present application further provides a computer program product. Optionally, in this embodiment, the computer program product may include a computer program, and when the computer program is executed by a processor, the power gating method provided in the second embodiment is implemented.

[0113] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0114] In the above embodiments of the present application, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, please refer to the relevant description of other embodiments.

[0115] In the several embodiments provided in this application, it should be understood that the disclosed technical content can be implemented in other ways. Among them, the device embodiments described above are only schematic, for example, the division of units is only a logical function division, and there may be other division methods in actual implementation, for example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of units or modules, which can be electrical or other forms.

[0116] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0117] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit. The above-mentioned integrated unit may be implemented in the form of hardware or in the form of software functional units.

[0118] If the integrated unit is implemented in the form of a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art or all or part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, server or network device, etc.) to perform all or part of the steps of each embodiment method of the present application. The aforementioned storage medium includes: U disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), mobile hard disk, disk or optical disk, etc. Various media that can store program codes.

[0119] The above are only preferred implementations of the present application. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present application. These improvements and modifications should also be regarded as the scope of protection of the present application.

Claims

1. A power gating system, characterized in that: include: A central processing unit, used for writing software power-off configuration information into the register module, wherein the software power-off configuration information is configuration information of a power gating controller; The register module is used to trigger a software power-off request according to the software power-off configuration information and send the request to the power gating controller; A system power consumption controller, configured to determine a system power consumption mode according to a state of the central processing unit, and trigger a hardware power-off request and send the request to the power gating controller when the system power consumption mode is a low power consumption mode; The power gating controller is used to detect the state of the bus of the power domain based on the software power-off request or the hardware power-off request, and perform power-off timing control on the power domain when it is detected that the state of the bus is an idle state.

2. The system according to claim 1, characterized in that The power gating system further includes: an isolation unit, configured to receive an isolation enable signal sent by the power gating controller during the process of performing power-off timing control on the power domain, and isolate an output signal of the power domain based on the isolation enable signal; A reset generation module, configured to receive a reset control signal sent by the power gating controller during a process of performing power-off timing control on the power domain, and reset the power domain based on the reset control signal; The clock generating module is used to receive the clock gating signal sent by the power gating controller during the process of executing power-off timing control on the power domain, and control the clock of the power domain based on the clock gating signal.

3. The system according to claim 2, characterized in that The power gating controller is further used to control the memory of the power domain to enter a shutdown mode after controlling the clock of the power domain based on the clock gating signal; The power gating controller is further configured to control the power switch of the power domain to be turned off after controlling the memory of the power domain to enter a shutdown mode.

4. The system according to claim 3, characterized in that The power gating system further includes: The system interrupt controller is used to receive a power-off interrupt signal sent by the power gating controller after controlling the power switch of the power domain to be turned off, and feed back the power-off interrupt signal to the central processing unit.

5. The system according to claim 4, characterized in that The system interrupt controller is further configured to receive a power-off interrupt signal sent by the power gating controller when detecting that the state of the bus is an active state, and feed back the power-off interrupt signal to the central processing unit.

6. The system according to claim 1, characterized in that The power gating controller comprises: A power gating control state machine, used for receiving the software power-off request of the register module or the hardware power-off request of the system power consumption controller, generating a bus state detection start signal and sending it to a bus state detection circuit; The bus state detection circuit is used to interact with the bus low power consumption interface of the power domain after receiving the bus state detection start signal, and if the interaction is successful, determine that the state of the bus is an idle state, generate a bus idle state signal and return it to the power gating control state machine.

7. The system according to claim 6, characterized in that The power gating control state machine is also used to generate an isolation enable signal to the isolation unit, a reset control signal to the reset generation module, a clock gating signal to the clock generation module, a shutdown control signal to the memory of the power domain, and a shutdown control signal to the power switch of the power domain based on the bus idle state signal after receiving the bus idle state signal.

8. The system according to claim 7, characterized in that The power gating controller further includes: The interrupt generating circuit is used to receive the power-off completion status signal generated by the power gating control state machine after receiving the feedback signal of the power switch of the power domain, and generate a power-off interrupt to the system interrupt controller based on the power-off completion status signal.

9. The system according to claim 8, characterized in that The bus state detection circuit is also used to determine that the state of the bus is an active state when the interaction fails, and generate a bus active state signal to return to the power gating control state machine.

10. The system according to claim 9, characterized in that The interrupt generation circuit is also used to receive a bus low power consumption rejection signal generated by the power gating control state machine based on the bus activity state signal, and generate a bus low power consumption rejection interrupt to the system interrupt controller based on the bus low power consumption rejection signal.

11. The system according to claim 1, characterized in that The register module is also used to transmit the interval time between the steps in the process of controlling the power off of the power domain to the power gating controller, so that the power gating controller executes the process of controlling the power off of the power domain based on the interval time between the steps, wherein the process of controlling the power off of the power domain at least includes detecting the state of the bus of the power domain and performing power off timing control on the power domain.

12. The system according to claim 1, characterized in that The register module is further used to transmit an interrupt clear signal to the power gating controller, so that the power gating controller clears the interrupt based on the interrupt clear signal; The register module is further configured to transmit an interrupt masking signal to the power gating controller, so that the power gating controller masks interrupts based on the interrupt masking signal.

13. A power gating method, characterized in that: The power gating system according to any one of claims 1 to 12 comprises: Writing software power-off configuration information into the register module through the central processing unit, wherein the software power-off configuration information is configuration information of the power gating controller; Triggering a software power-off request according to the software power-off configuration information through the register module and sending the request to the power gating controller; Determine the system power consumption mode according to the state of the central processing unit by the system power consumption controller, and trigger a hardware power-off request and send it to the power gating controller when the system power consumption mode is a low power consumption mode; The power gating controller detects the state of the bus of the power domain based on the software power-off request or the hardware power-off request, and performs power-off timing control on the power domain when it is detected that the state of the bus is an idle state.

14. A system on chip, characterized in that: include: A memory storing an executable program; A processor is used to run the program, wherein the power gating method of claim 13 is executed when the program is run.

15. A computing device, characterized in that: The computing device uses the system on chip of claim 14 when performing computing.

16. A computer program product, characterized in that The method comprises a computer program or an instruction, which implements the power gating method according to claim 13 when the computer program or the instruction is executed by a processor.

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