SIC chip and manufacturing method thereof

Abstract

The invention provides an SIC chip and a manufacturing method thereof, and belongs to the field of semiconductors. The manufacturing method of the SIC chip comprises the steps that the SIC chip is provided, passivation layers are deposited on the inner wall and the bottom of a through hole, and the passivation layers extend to a metal covering layer around the through hole; forming a first PI layer on the surface of the passivation layer, and filling the through hole; a second PI layer is formed on the surface of the first PI layer, and the first PI layer and the second PI layer are opposite in adhesive property; and forming a plastic package layer on the surface of the second PI layer, wherein the plastic package layer covers the second PI layer and the metal covering layer. According to the invention, two PI layers with opposite colloidality are formed. By using the two PI layers, the surface stress gradient structure of the SIC chip can be formed, and the shear stress between the molding compound and the SIC chip in the thermal cycle process can be effectively reduced, so that the shear stress at the edge and the corner of the SIC chip can be reduced, the layering of the SIC chip and the molding compound and the cracking of the SIC chip can be avoided, and the service life of the SIC chip is prolonged. And physical property abnormity and electrical property failure of the device can be further avoided.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a SIC chip and a manufacturing method thereof. Background Art

[0002] SIC chip, or silicon carbide chip, is a semiconductor chip that uses silicon carbide (SiC) as the main material. Silicon carbide is a compound composed of carbon and silicon, which has the characteristics of high temperature resistance, high frequency resistance, and high voltage resistance, which makes it widely used in the field of power electronic devices. In SIC chips, the existing top metal layer (TM) and passivation layer (PA) structure is based on the sequential action of the top metal layer and the passivation layer. First, a through hole is formed in the top metal layer, and a TM / PA structure is formed on the sidewall and top of the through hole. Then, a PI layer is operated to prevent the metal at the corresponding position from directly contacting the external environment, thereby protecting the wafer from contamination and oxidation. Improve the reliability and stability of the wafer.

[0003] Ginseng Figure 1 As shown, Figure 1 1 is a schematic diagram of the structure of a SIC chip including TM / PA in one embodiment. Among them, 10-PA layer; 20-PI material layer; 30-molding material layer; 40-TM layer. The material used for the PI material layer 20 is polyimide (abbreviated as "PI"). During the thermal cycle test, the stress difference between the TM layer 40 and the PA layer 10 on the surface of the SIC chip and the molding material layer 30 is large. When cooling, the molding material layer 30 shrinks more than the SIC chip, but the bonding force between the two prevents relative sliding, so a large shear stress appears on the interface. The generated shear stress is concentrated on the edges and corners of the SIC chip. During the continuous thermal cycle process, the SIC chip and the molding material layer 30 are delaminated, and even the SIC chip is cracked, which leads to abnormal physical properties of the device and electrical failure.

[0004] It should be noted that the information disclosed in the background technology section of the invention is only intended to deepen the understanding of the general background technology of the invention, and should not be regarded as an admission or suggestion in any form that the information constitutes prior art already known to those skilled in the art. Summary of the invention

[0005] The object of the present invention is to provide a SIC chip and a manufacturing method thereof, so as to solve the problem that shear stress is generated at the edges and corners of the SIC chip during a thermal cycle test, causing delamination of the SIC chip and the plastic packaging material, or even cracking of the SIC chip, thereby causing abnormal physical properties of the device and electrical failure.

[0006] In order to solve the above technical problems, the present invention provides a SIC chip, comprising: The active region has a device functional structure; A terminal region, disposed around the periphery of the active region; A semiconductor structure layer, located between the active area and the terminal area and disposed close to the edge of the active area, the semiconductor structure layer comprising an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer and a metal covering layer sequentially deposited on the surface of the epitaxial layer; The metal covering layer is provided with a through hole, a passivation layer is deposited on the inner wall and the bottom of the through hole, the passivation layer extends to the metal covering layer around the through hole, a first PI layer and a second PI layer are sequentially provided on the surface of the passivation layer, the first PI layer covers the passivation layer and fills the through hole, the second PI layer covers the first PI layer, a plastic sealing layer is plastic-sealed on the surface of the second PI layer, and the plastic sealing layer covers the second PI layer and the metal covering layer; The first PI layer and the second PI layer have opposite adhesive properties.

[0007] Preferably, the first PI layer is a positive photoresist PI, and the second PI layer is a negative photoresist PI.

[0008] Preferably, the first PI layer is a negative-resist PI, and the second PI layer is a positive-resist PI.

[0009] Preferably, the thickness of the positive photoresist PI is 4 μm-7 μm, the thickness of the negative photoresist PI is 7 μm-12 μm, and the total thickness of the positive photoresist PI and the negative photoresist PI is less than or equal to 20 μm.

[0010] Based on the same inventive concept, the present invention also provides a SIC chip manufacturing method, comprising: A SIC chip is provided, the SIC chip comprising an active area, a device functional structure is formed, a terminal area, which is arranged around the periphery of the active area, and a semiconductor structure layer, which is located between the active area and the terminal area and is arranged close to the edge of the active area, the semiconductor structure layer comprises an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer and a metal covering layer which are sequentially deposited on the surface of the epitaxial layer, and a through hole is formed on the surface of the metal covering layer; Depositing a passivation layer on the inner wall and bottom of the through hole, and the passivation layer extends to the metal covering layer around the through hole; forming a first PI layer on the surface of the passivation layer and filling the through hole; Forming a second PI layer on the surface of the first PI layer, wherein the first PI layer and the second PI layer have opposite adhesive properties; A plastic sealing layer is formed on the surface of the second PI layer, and the plastic sealing layer covers the second PI layer and the metal covering layer.

[0011] Preferably, the first PI layer is a positive photoresist PI, and the second PI layer is a negative photoresist PI.

[0012] Preferably, forming a first PI layer on the surface of the passivation layer and filling the through hole comprises: Spin-coat positive resist PI on the wafer surface; The spin-coated positive photoresist PI is exposed and developed to form a first PI layer; The first PI layer is cured at a temperature of 200° C. to 400° C. and for a duration of 30 min to 120 min.

[0013] Preferably, forming a second PI layer on the surface of the first PI layer comprises: Spin-coat negative photoresist PI on the wafer surface; The spin-coated negative photoresist PI is exposed and developed to form a second PI layer; The second PI layer is cured at a temperature of 300° C. to 500° C. and for a duration of 30 min to 120 min.

[0014] Preferably, the first PI layer is a negative-resist PI, and the second PI layer is a positive-resist PI.

[0015] Preferably, the thickness of the positive photoresist PI is 4 μm-7 μm, the thickness of the negative photoresist PI is 7 μm-12 μm, and the total thickness of the positive photoresist PI and the negative photoresist PI is less than or equal to 20 μm.

[0016] Compared with the prior art, the SIC chip of the present invention has the following advantages: The present invention forms a first PI layer on the surface of the passivation layer and fills the through hole. A second PI layer is formed on the surface of the first PI layer, wherein the first PI layer and the second PI layer have opposite adhesive properties. The surface of the second PI layer is plastic-sealed with a plastic sealing layer, and the plastic sealing layer covers the second PI layer and the metal covering layer. Using two PI layers, a stress gradient structure on the surface of the SIC chip can be formed, which effectively reduces the shear stress between the plastic sealing material and the SIC chip during the thermal cycle, thereby protecting the electrical parameters of the device from being stable. Using two PI layers, after the first PI layer is formed, the position with a groove or hole structure on the surface of the passivation layer is completely filled with PI material, and when the second PI layer is formed, the interface of the two PI layers is smoother, which can release more shear stress and reduce the stress on the bottom passivation layer and the metal covering layer, thereby reducing the shear stress at the edges and corners of the SIC chip, thereby avoiding the delamination of the SIC chip and the plastic sealing material, and the cracking of the SIC chip, and further avoiding the abnormal physical properties of the device and electrical failure.

[0017] The SIC chip provided by the present invention and the SIC chip manufacturing method provided by the present invention belong to the same inventive concept, therefore, the SIC chip provided by the present invention has at least all the advantages of the SIC chip manufacturing method provided by the present invention, by forming a first PI layer on the surface of the passivation layer and filling the through hole. A second PI layer is formed on the surface of the first PI layer, wherein the first PI layer and the second PI layer have opposite adhesive properties. The surface of the second PI layer is plastic-sealed with a plastic sealing layer, and the plastic sealing layer covers the second PI layer and the metal covering layer. By using two PI layers, a stress gradient structure on the surface of the SIC chip can be formed, which effectively reduces the shear stress between the plastic sealing material and the SIC chip during the thermal cycle, thereby reducing the shear stress at the edges and corners of the SIC chip, thereby avoiding the delamination of the SIC chip and the plastic sealing material, and the cracking of the SIC chip, and further avoiding the abnormal physical properties of the device and electrical failure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1 Schematic diagram of the structure of a SIC chip including TM / PA in one embodiment.

[0019] Figure 2 FIG. 1 is a flow chart of a method for manufacturing a SIC chip according to an embodiment of the present invention.

[0020] Figure 3 It is a schematic diagram of a part of the structure after a passivation layer is deposited on the metal covering layer in one embodiment of the present invention.

[0021] Figure 4 It is a schematic diagram of a partial structure in which the passivation layer covers the first PI layer in one embodiment of the present invention.

[0022] Figure 5 It is a partial structural schematic diagram of covering the surface of the first PI layer with a second PI layer in one embodiment of the present invention.

[0023] Figure 6 It is a structural schematic diagram of forming a plastic sealing layer on the surface of the second PI layer and the metal covering layer in one embodiment of the present invention.

[0024] In the figure, 10-PA layer; 20-PI material layer; 30-plastic encapsulation material layer; 40-TM layer; 100-epitaxial layer; 101-field oxide layer; 102-polysilicon layer; 103-dielectric layer; 104-metal covering layer; 105-passivation layer; 106-first PI layer; 107-second PI layer; 108-plastic encapsulation layer; 200-through hole. DETAILED DESCRIPTION

[0025] In order to make the purpose, advantages and features of the present invention clearer, the SIC chip and its manufacturing method proposed by the present invention are further described in detail in combination with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not in precise proportions, which are only used to conveniently and clearly assist in explaining the purpose of the embodiments of the present invention. It should be understood that the drawings in the specification do not necessarily show the specific structure of the present invention in proportion, and the illustrative features used to illustrate certain principles of the present invention in the drawings in the specification will also adopt a slightly simplified drawing method. The specific design features of the present invention disclosed herein include, for example, specific dimensions, directions, positions and shapes, which will be determined in part by the specific environment to be applied and used. And, in the embodiments described below, sometimes the same figure mark is used in common between different drawings to represent the same part or the part with the same function, and its repeated description is omitted. In this specification, similar numbers and letters are used to represent similar items, so once an item is defined in one drawing, it does not need to be further discussed in subsequent drawings.

[0026] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0027] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0028] The core idea of ​​the present invention is to provide a SIC chip manufacturing method that can reduce the interface stress of the SIC chip, so as to solve the problem that the SIC chip and the plastic packaging material are delaminated, or even the SIC chip is cracked, which leads to abnormal physical properties and electrical failure of the device due to shear stress generated at the edges and corners of the SIC chip.

[0029] In order to realize the above idea, the present invention provides a method for manufacturing a SIC chip. Figures 2 to 6A specific implementation of a SIC chip manufacturing method disclosed herein includes the following steps S1 to S5.

[0030] Step S1: providing a SIC chip, wherein the SIC chip comprises an active area (not shown in the figure), formed with a device functional structure, a terminal area, arranged around the periphery of the active area, and a semiconductor structure layer, located between the active area and the terminal area, and arranged close to the edge of the active area, wherein the semiconductor structure layer comprises an epitaxial layer 100, a field oxide layer 101, a polysilicon layer 102, a dielectric layer 103 and a metal covering layer 104 sequentially deposited on the surface of the epitaxial layer 100, and a through hole 200 is formed on the surface of the metal covering layer 104.

[0031] Specifically, refer to Figure 2 and Figure 3 As shown, a SIC chip is provided. The chip has an active area and a terminal area. The active area is formed with a device functional structure, such as a source, a drain, a gate structure and other functional structures. The terminal area is arranged around the periphery of the active area. The semiconductor structure layer includes an epitaxial layer 100. A field oxide layer 101 is deposited on the surface of the epitaxial layer 100. A polysilicon layer 102 is deposited on the surface of the field oxide layer 101. A dielectric layer 103 is deposited on the surface of the polysilicon layer 102. A metal covering layer 104 is deposited on the surface of the dielectric layer 103. The metal covering layer 104 is a top metal layer. The top metal layer can be used as metal interconnection, heat dissipation, etc. at different levels in the chip. A through hole 200 can be formed on the surface of the metal covering layer 104 by a photolithography process.

[0032] Step S2 : depositing a passivation layer 105 on the inner wall and the bottom of the through hole 200 , and the passivation layer 105 extends to the metal covering layer 104 around the through hole 200 .

[0033] Specifically, refer to Figure 2 and Figure 3 As shown, a passivation layer 105 is deposited on the inner wall and bottom of the through hole 200. And the passivation layer 105 extends to the metal cover layer 104 around the through hole 200. The passivation layer 105 can be formed on the inner wall, bottom and surrounding of the through hole 200 by chemical vapor deposition, atomic layer deposition, etc. using silicon nitride (SiN) material. The passivation layer 105 has the functions of protecting the chip, preventing the external environment from corroding the chip, and preventing leakage current. The formed passivation layer 105 extends to the terminal area.

[0034] Step S3 : forming a first PI layer 106 on the surface of the passivation layer 105 and filling the through hole 200 .

[0035] Specifically, refer to Figure 2 and Figure 4As shown, the first PI layer 106 can be a positive PI or a negative PI. The first PI layer 106 is a positive PI as an example for explanation. Forming the first PI layer 106 on the surface of the passivation layer 105 and filling the through hole 200 includes: First, a positive resist PI is spin-coated on the surface of the wafer. That is, the surfaces of the active area, the terminal area and the semiconductor structure layer are all coated with the positive resist PI. When the positive resist PI is spin-coated, the through hole 200 is filled with the positive resist PI.

[0036] Next, the spin-coated positive photoresist PI is exposed and developed to form the first PI layer 106. The positive photoresist PI at the position covering the passivation layer 105 is shielded by a mask. At the same time, the remaining positive photoresist PI is exposed. After the exposure process, the positive photoresist PI of the exposed part is developed so that the positive photoresist PI of the exposed part is dissolved. The positive photoresist PI at the position covering the passivation layer 105 is retained to form the first PI layer 106. The first PI layer 106 is a positive photoresist PI with a thickness d1 of 4μm~7μm. That is, the thickness of the first PI layer 106 can be 4μm, 4.5μm, 4μm, 5.5μm, 6μm, 6.5μm, 7μm, or any value within the range of 4μm~7μm. In this embodiment, preferably, the first PI layer 106 is a positive photoresist PI with a thickness of 5μm~6μm.

[0037] Finally, the first PI layer 106 is cured at a temperature of 200°C to 400°C and for a duration of 30 min to 120 min. That is, the first PI layer 106 can be cured at a temperature of 200°C, 250°C, 300°C, 350°C, 400°C, or any temperature in the range of 200°C to 400°C. The duration of the curing process can be 30 min, 50 min, 80 min, 100 min, 120 min, or any time in the range of 30 min to 120 min.

[0038] Step S4: forming a second PI layer 107 on the surface of the first PI layer 106 , wherein the first PI layer 106 and the second PI layer 107 have opposite adhesive properties.

[0039] Specifically, refer to Figure 2 and Figure 5As shown, the second PI layer 107 can also be a positive PI or a negative PI. If the first PI layer 106 is a positive PI, then the second PI layer 107 is a negative PI. If the first PI layer 106 is a negative PI, then the second PI layer 107 is a positive PI. That is, the first PI layer 106 and the second PI layer 107 have opposite adhesive properties. In step S3, the first PI layer 106 is an example of a positive PI, so in this embodiment, the second PI layer 107 is a negative PI for explanation.

[0040] Forming the second PI layer 107 on the surface of the first PI layer 106 includes: First, negative resist PI is spin-coated on the surface of the wafer, that is, negative resist PI is coated on the surfaces of the active area, the terminal area and the semiconductor structure layer.

[0041] Next, the spin-coated negative photoresist PI is exposed, and after development, a second PI layer 107 is formed. The negative photoresist PI covering the first PI layer 106 is exposed. The remaining negative photoresist PI is shielded using a mask. Then the negative photoresist PI is developed. Since the negative photoresist PI of the non-exposed part is dissolved in the developer, the negative photoresist PI covering the first PI layer 106 is retained to form a second PI layer 107. The thickness d2 of the second PI layer 107 as the negative photoresist PI is 7μm~12μm. That is, the thickness of the second PI layer 107 can be 7μm, 8μm, 9μm, 10μm, 11μm, 12μm, or any value in the range of 7μm~12μm. In this embodiment, preferably, the thickness of the second PI layer 107 as the negative photoresist PI is 8μm~10μm. At this time, the sum of the thickness of the positive photoresist PI and the thickness of the negative photoresist PI does not exceed 20μm.

[0042] Finally, the second PI layer 107 is cured at a temperature of 300°C to 500°C, and the curing time is 30min to 120min. That is, the curing temperature of the second PI layer 107 can be 300°C, 350°C, 400°C, 450°C, 500°C, or any temperature in the range of 300°C to 500°C. The curing time can be 30min, 50min, 80min, 100min, 120min, or any time in the range of 30min to 120min. Both the first PI layer 106 and the second PI layer 107 extend to the terminal area.

[0043] Step S5: forming a plastic encapsulation layer 108 on the surface of the second PI layer 107 , wherein the plastic encapsulation layer 108 covers the second PI layer 107 and the metal covering layer 104 .

[0044] Specifically, refer to Figure 2 and Figure 6As shown, a plastic encapsulation layer 108 is formed on the surface of the second PI layer 107. The plastic encapsulation layer 108 not only covers the second PI layer 107, but also covers the metal covering layer 104 to protect the chip.

[0045] It should be noted that Figures 3 to 6 This is a schematic diagram of a structure formed during the process of forming the first PI layer 106, the second PI layer 107 and the plastic encapsulation layer 108 on the surface of the wafer. The schematic diagram of the structure only shows a part and does not show all of it. For those skilled in the art, the specific structure of the chip is already familiar.

[0046] A first PI layer 106 is formed on the surface of the passivation layer 105, and the through hole 200 is filled. A second PI layer 107 is formed on the surface of the first PI layer 106, wherein the first PI layer 106 and the second PI layer 107 have opposite adhesive properties. A plastic layer 108 is plastic-sealed on the surface of the second PI layer 107, and the plastic layer 108 covers the second PI layer 107 and the metal covering layer 104. The thermal expansion coefficient of the positive glue is 36ppm / ℃, and the thermal expansion coefficient of the negative glue is 55ppm / ℃. The plastic material used in the currently commonly used plastic layer is 10ppm / ℃ at the glass transition temperature (generally 180~190℃). After exceeding the glass transition temperature, the thermal expansion coefficient will increase to 45ppm / ℃. In the reliability test related to thermal cycling, a large stress will be generated between the plastic material and the SIC chip; using two layers of PI layers, a stress gradient structure on the surface of the SIC chip can be formed, which effectively reduces the shear stress between the plastic material and the SIC chip during the thermal cycle, thereby protecting the stability of the electrical parameters of the device.

[0047] By using two PI layers, after the first PI layer 106 is formed, the positions with grooves or hole structures on the surface of the passivation layer 105 are completely filled with PI materials, and when the second PI layer 107 is formed, the interface between the two PI layers is smoother, which can release more shear stress and reduce the stress on the bottom passivation layer 105 and the metal covering layer 104, thereby reducing the shear stress on the edges and corners of the SIC chip, thereby avoiding delamination of the SIC chip and the plastic packaging material, and cracking of the SIC chip, and further avoiding abnormal physical properties of the device and electrical failure.

[0048] To realize the above idea, the embodiment also discloses a SIC chip, comprising: an active area, in which a device functional structure is formed; a terminal area, which is arranged around the periphery of the active area; a semiconductor structure layer, which is located between the active area and the terminal area and is arranged close to the edge of the active area, wherein the semiconductor structure layer comprises an epitaxial layer 100, a field oxide layer 101, a polysilicon layer 102, a dielectric layer 103 and a metal covering layer 104 which are sequentially deposited on the surface of the epitaxial layer 100; the metal covering layer 104 is provided with a through hole 200, and a passivation layer 105 is deposited on the inner wall and bottom of the through hole 200, The passivation layer 105 extends to the metal covering layer 104 around the through hole 200, and the surface of the passivation layer 105 is sequentially provided with a first PI layer 106 and a second PI layer 107, wherein the first PI layer 106 covers the passivation layer 105 and fills the through hole 200, and the second PI layer 107 covers the first PI layer 106, and the surface of the second PI layer 107 is plastic-sealed with a plastic sealing layer 108, and the plastic sealing layer 108 covers the second PI layer 107 and the metal covering layer 104, wherein the first PI layer 106 and the second PI layer 107 have opposite adhesive properties. The first PI layer 106 is a positive PI, and the second PI layer 107 is a negative PI. Or, the first PI layer 106 is a negative PI, and the second PI layer 107 is a positive PI. The thickness of the positive PI is 4μm~7μm, the thickness of the negative PI is 7μm~12μm, and the total thickness of the positive PI and the negative PI is less than or equal to 20μm.

[0049] The SIC chip provided in this embodiment and the SIC chip manufacturing method provided in this embodiment belong to the same inventive concept, therefore, the SIC chip provided in this embodiment has at least all the advantages of the SIC chip manufacturing method provided in this embodiment, by forming a first PI layer 106 on the surface of the passivation layer 105 and filling the through hole 200. A second PI layer 107 is formed on the surface of the first PI layer 106, wherein the first PI layer 106 and the second PI layer 107 have opposite adhesive properties. A plastic sealing layer 108 is plastic-sealed on the surface of the second PI layer 107, and the plastic sealing layer 108 covers the second PI layer 107 and the metal covering layer 104. By using two PI layers, a stress gradient structure on the surface of the SIC chip can be formed, which effectively reduces the shear stress between the plastic sealing material and the SIC chip during the thermal cycle, thereby reducing the shear stress at the edges and corners of the SIC chip, thereby avoiding the delamination of the SIC chip and the plastic sealing material, and the cracking of the SIC chip, and further avoiding the abnormal physical properties of the device and electrical failure.

[0050] In summary, the above embodiments describe in detail different configurations of the SIC chip and the manufacturing method thereof. Of course, the above description is only a description of the preferred embodiments of the present invention, and is not intended to limit the scope of the present invention. The present invention includes but is not limited to the configurations listed in the above embodiments. Those skilled in the art can draw inferences based on the contents of the above embodiments. Any changes and modifications made by those of ordinary skill in the field of the present invention based on the above disclosure shall fall within the scope of protection of the claims.

Claims

1. A SIC chip, characterized in that: include: The active region has a device functional structure; A terminal region, disposed around the periphery of the active region; A semiconductor structure layer, located between the active area and the terminal area and arranged close to the edge of the active area, the semiconductor structure layer comprising an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer and a metal covering layer sequentially deposited on the surface of the epitaxial layer; The metal covering layer is provided with a through hole, and a passivation layer is deposited on the inner wall and the bottom of the through hole, and the passivation layer extends to the metal covering layer around the through hole. The surface of the passivation layer is sequentially provided with a first PI layer and a second PI layer, and the first PI layer covers the passivation layer and fills the through hole, and the second PI layer covers the first PI layer. A plastic sealing layer is plastic-sealed on the surface of the second PI layer, and the plastic sealing layer covers the second PI layer and the metal covering layer, wherein the first PI layer and the second PI layer have opposite adhesive properties.

2. The SIC chip according to claim 1, characterized in that: The first PI layer is a positive photoresist PI, and the second PI layer is a negative photoresist PI.

3. The SIC chip according to claim 1, characterized in that: The first PI layer is a negative-resist PI, and the second PI layer is a positive-resist PI.

4. The SIC chip according to claim 2 or 3, characterized in that: The thickness of the positive photoresist PI is 4 μm to 7 μm, the thickness of the negative photoresist PI is 7 μm to 12 μm, and the total thickness of the positive photoresist PI and the negative photoresist PI is less than or equal to 20 μm.

5. A method for manufacturing a SIC chip as claimed in any one of claims 1 to 4, characterized in that: include: A SIC chip is provided, the SIC chip comprising an active area, a device functional structure is formed, a terminal area, which is arranged around the periphery of the active area, and a semiconductor structure layer, which is located between the active area and the terminal area and is arranged close to the edge of the active area, the semiconductor structure layer comprises an epitaxial layer, a field oxide layer, a polysilicon layer, a dielectric layer and a metal covering layer which are sequentially deposited on the surface of the epitaxial layer, and a through hole is formed on the surface of the metal covering layer; Depositing a passivation layer on the inner wall and bottom of the through hole, and the passivation layer extends to the metal covering layer around the through hole; forming a first PI layer on the surface of the passivation layer and filling the through hole; Forming a second PI layer on the surface of the first PI layer, wherein the first PI layer and the second PI layer have opposite adhesive properties; A plastic sealing layer is formed on the surface of the second PI layer, and the plastic sealing layer covers the second PI layer and the metal covering layer.

6. The SIC chip according to claim 5, characterized in that: The first PI layer is a positive photoresist PI, and the second PI layer is a negative photoresist PI.

7. The SIC chip according to claim 6, characterized in that: The forming a first PI layer on the surface of the passivation layer and filling the through hole comprises: Spin-coat positive resist PI on the wafer surface; The spin-coated positive photoresist PI is exposed and developed to form a first PI layer; The first PI layer is cured at a temperature of 200° C. to 400° C. and for a duration of 30 min to 120 min.

8. The SIC chip according to claim 6, characterized in that: The forming of the second PI layer on the surface of the first PI layer comprises: Spin-coat negative photoresist PI on the wafer surface; The spin-coated negative photoresist PI is exposed and developed to form a second PI layer; The second PI layer is cured at a temperature of 300° C. to 500° C. and for a duration of 30 min to 120 min.

9. The SIC chip according to claim 5, characterized in that: The first PI layer is a negative-resist PI, and the second PI layer is a positive-resist PI.

10. The SIC chip according to claim 6, characterized in that: The thickness of the positive photoresist PI is 4 μm to 7 μm, the thickness of the negative photoresist PI is 7 μm to 12 μm, and the total thickness of the positive photoresist PI and the negative photoresist PI is less than or equal to 20 μm.

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