Storage circuit and random access memory

Abstract

The invention discloses a storage circuit and a random access memory. The storage circuit comprises a control chip and a storage chip, wherein the storage chip is connected with the control chip; wherein one of the control chip and the storage chip comprises a redundancy repairing module, and the control chip is configured to obtain information of a damaged storage unit in the storage chip according to a preset triggering requirement; the redundancy repair module is configured to store the information of the damaged storage unit and send a redundancy replacement address to the storage chip based on the information of the damaged storage unit in response to the storage operation instruction so as to execute the corresponding storage operation. By means of the mode, the storage circuit can repair the damaged storage unit in the storage chip in real time through the redundancy repair module in the use process of the random access memory, so that the stability of the random access memory is improved, and the possibility that the random access memory reads and writes data mistakenly is reduced.

Description

Technical Field

[0001] The present application relates to the field of memory repair technology, and in particular to a storage circuit and a random access memory. Background Art

[0002] In the manufacturing process of random access memory, especially dynamic random access memory (DRAM), there may be a short circuit or open circuit of the word line (WL) in the row direction, a short circuit or open circuit of the bit line (BL) in the column direction, or a damaged memory cell (MC). Therefore, in order to improve the yield of random access memory, it is necessary to add some spare circuits and spare memory cells to replace the damaged word lines, bit lines and memory cells. These spare circuits and spare memory cells are collectively referred to as replacement (RDN, redundancy) resources.

[0003] However, in the prior art, the RDN repair information of the random access memory is mostly stored in the electrically programmed fuse array inside the memory chip. Once the RDN repair information is burned into the electrically programmed fuse array, it cannot be modified. If a new bad point appears during the actual use of the random access memory, it cannot be repaired, causing read and write data errors. Summary of the invention

[0004] In order to solve the above problems, the present application provides a storage circuit and a random access memory for repairing damaged storage cells in a storage chip in real time.

[0005] In order to solve the above technical problems, a technical solution adopted in the present application is: providing a storage circuit, which includes a control chip and a storage chip, and the storage chip is connected to the control chip; wherein, one of the control chip and the storage chip includes a redundant repair module, and the control chip is configured to obtain information of damaged storage cells in the storage chip according to preset trigger requirements; the redundant repair module is configured to store information of damaged storage cells, and in response to a memory operation instruction, sends a redundant replacement address to the storage chip based on the information of the damaged storage cell to perform a corresponding memory operation.

[0006] In some embodiments, the redundant repair module is an independent control logic grain, which is packaged into a storage chip through three-dimensional bonding with at least one storage grain included in the storage chip, or the redundant repair module is integrated in the control chip and configured as a functional module of the control chip.

[0007] In some embodiments, the preset trigger requirements include: when the control chip determines that the storage circuit is powered on again, or when the control chip determines that a preset time has passed since the last acquisition operation; wherein the control chip is configured to perform multiple sequences of reading and writing on the storage chip, and obtain information about damaged storage units in the storage chip through data verification results of the read and write.

[0008] In some embodiments, the storage circuit also includes a bad point address loading module, the bad point address loading module is connected to the control chip, the bad point address in the information of the damaged storage unit sent by the storage control chip, and a redundant control timing signal is generated according to the information of the damaged storage unit; wherein the redundant repair module is connected to the bad point address loading module, wherein the redundant repair module is configured to load the bad point address from the bad point address loading module according to the redundant control timing signal, compare the addressing address and the bad point address corresponding to the memory operation instruction, and generate a corresponding redundant replacement address in response to the addressing address matching the bad point address, so that the storage chip performs a corresponding redundant replacement operation based on the redundant replacement address.

[0009] In some embodiments, a memory chip includes at least one memory grain; a redundant repair module includes at least one redundant repair submodule, each redundant repair submodule corresponds to one memory grain and is respectively connected to a bad point address loading module, wherein each redundant repair submodule is configured to load the bad point address of the corresponding memory grain according to a redundant control timing signal; in response to an addressing operation on the corresponding memory grain, compare the addressing address and the bad point address; and in response to the addressing address matching the bad point address, generate a redundant replacement address of the corresponding memory grain, so that the memory grain performs a corresponding redundant replacement operation based on the redundant replacement address.

[0010] In some embodiments, each redundant repair submodule includes a redundant latch circuit and a redundant matching circuit, respectively. The redundant latch circuit is configured to load the bad pixel address of the corresponding storage grain according to the redundant control timing signal; the redundant matching circuit is connected to the redundant latch circuit and is configured to respond to the addressing operation of the corresponding storage grain, compare the addressing address and the bad pixel address; and generate a redundant replacement address of the corresponding storage grain in response to matching the addressing address with the bad pixel address.

[0011] In some embodiments, the bad pixel address includes a row bad pixel address and a column bad pixel address, the redundant latch circuit includes a row address latch circuit and a column address latch circuit, the row address latch circuit is configured to load the row bad pixel address of the corresponding storage grain according to the redundant control timing signal; the column address latch circuit is configured to load the column bad pixel address of the corresponding storage grain according to the redundant control timing signal.

[0012] In some embodiments, the redundant control timing signal includes a loading enable signal, a row bad pixel address loading enable signal, a column bad pixel address loading enable signal and a redundant repair submodule identification signal; in response to the loading enable signal being high and the row bad pixel address loading enable signal being high, the row bad pixel address is stored in the redundant repair submodule corresponding to the redundant repair submodule identification signal based on the redundant repair submodule identification signal; in response to the loading enable signal being high and the column bad pixel address loading enable signal being high, the column bad pixel address is stored in the redundant repair submodule corresponding to the redundant repair submodule identification signal based on the redundant repair submodule identification signal.

[0013] In some embodiments, the bad pixel address loading module is connected to the redundant repair module through a multiplexed address bus; in response to the row bad pixel address loading enable signal being at a high level, the bad pixel address transmitted by the multiplexed address bus is the row bad pixel address; in response to the column bad pixel address loading enable signal being at a high level, the bad pixel address transmitted by the multiplexed address bus is the column bad pixel address.

[0014] In some embodiments, the redundant replacement address includes a redundant replacement identifier, and the memory chip selects to address the redundant storage area or the normal storage area according to whether the redundant replacement identifier is valid.

[0015] In order to solve the above technical problem, another technical solution adopted by the present application is: to provide a random access memory, which includes any one of the storage circuits mentioned above.

[0016] Different from the prior art, the storage circuit of the present application includes a control chip and a storage chip, and a redundant repair module is set in one of the storage chip and the control chip, wherein the control chip is configured to obtain information about damaged storage cells in the storage chip according to a preset trigger requirement, and the redundant repair module is configured to store information about damaged storage cells, and in response to a memory operation instruction, send a redundant replacement address to the storage chip based on the information about the damaged storage cells to perform a corresponding memory operation. In the above manner, the storage circuit of the present application can obtain information about damaged storage cells in the storage chip in real time according to a preset trigger requirement (for example, each time power is turned on or every certain period of time), and then use the redundant repair module to send a redundant replacement address to the storage chip based on the information about the damaged storage cells obtained in real time to repair the storage chip. Therefore, compared with the prior art, the storage circuit of the present application can obtain information about damaged storage cells in the storage chip in real time during the use of the random access memory through the redundant repair module, and repair the damaged storage cells in the storage chip according to the aforementioned information about the damaged storage cells obtained in real time, thereby solving the problem that newly generated bad points in the actual use of traditional storage chips after leaving the factory cannot be repaired, thereby increasing the service life of the random access memory and reducing the possibility of errors in reading and writing data in the random access memory. In addition, compared with the prior art of burning repair information into an electrically programmable fuse array, the storage circuit of the embodiment of the present application does not require an electrically programmable fuse array, which can greatly save the chip area of ​​the storage circuit. In a further embodiment, the redundant repair module of the embodiment of the present application is implemented with a logic circuit independent of the storage grain of the storage chip, so there is no need to set up a storage space for temporarily storing the bad point address and a peripheral circuit for comparing with the addressing address in the storage grain. In a further embodiment, the bad point address loading module of the embodiment of the present application communicates with the redundant repair module through a customized redundant control timing to load the corresponding bad point address, which has a higher design flexibility. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. Among them:

[0018] Figure 1 is a structural schematic diagram of a first embodiment of a storage circuit provided by the present application;

[0019] Figure 2 is a structural schematic diagram of a second embodiment of a storage circuit provided by the present application;

[0020] Figure 3is a structural schematic diagram of a third embodiment of a storage circuit provided by the present application;

[0021] Figure 4 is a schematic structural diagram of a fourth embodiment of a storage circuit provided by the present application;

[0022] Figure 5 It is a structural diagram of the redundant repair submodule provided by this application;

[0023] Figure 6 This is a timing diagram of an embodiment of the present application in which a bad pixel address is loaded into a redundant repair module;

[0024] Figure 7 It is a schematic diagram of the structure of a random access memory according to an embodiment of the present application. DETAILED DESCRIPTION

[0025] The technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. It will be understood that the specific embodiments described herein are only used to explain the present application, rather than to limit the present application. It should also be noted that, for ease of description, only some but not all structures related to the present application are shown in the drawings. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without making creative work are within the scope of protection of the present application.

[0026] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0027] In the manufacturing process of random access memory, especially dynamic random access memory (DRAM), there may be a short circuit or open circuit of the word line (WL) in the row direction, or a short circuit or open circuit of the bit line (BL) in the column direction, or a damage to the memory cell (MC). Therefore, in order to improve the yield of random access memory, it is necessary to add some spare circuits and spare memory cells to replace the damaged word lines, bit lines and memory cells. These spare circuits and spare memory cells are collectively referred to as replacement (RDN, redundancy) resources. When the word line of the random access memory is damaged, it is necessary to replace it in the row direction, which we call ROW RDN; when the BL of the bit line of the random access memory is damaged, it is necessary to replace it in the column direction, which is called COL RDN.

[0028] In the prior art, the RDN repair information of the random access memory is mostly stored in the electrical programming fuse array inside the memory chip. The RDN repair information is usually burned into the electrical programming fuse array after the random access memory is tested and determined before leaving the factory. Once burned into the electrical programming fuse array, it cannot be modified. If new bad points appear during the actual use of the random access memory, they cannot be repaired, causing read and write data errors.

[0029] In order to solve the above problems, the present application first proposes a storage circuit. Figure 1 , Figure 1 Schematic diagram of the structure of the first embodiment of the storage circuit provided by the present application. Figure 1 As shown, the storage circuit 100 of this embodiment includes a control chip 10 and a storage chip 20 .

[0030] Among them, the control chip 10 is configured to obtain information about damaged storage cells in the storage chip 20 according to preset trigger requirements; the redundant repair module 30 is configured to store information about damaged storage cells, and in response to memory operation instructions, send redundant replacement addresses to the storage chip 20 based on the information about the damaged storage cells to perform corresponding memory operations.

[0031] In this embodiment, the control chip 10 may be a microcontroller unit (MCU), and the control chip 10 is configured to obtain information about damaged storage cells in the storage chip 20 according to a preset trigger requirement.

[0032] Among them, the preset trigger requirements include: when the control chip 10 determines that the storage circuit 100 is powered on again, or when the control chip 10 determines that a preset time has passed since the last acquisition operation; wherein the control chip 10 is configured to perform multiple sequences of reading and writing on the storage chip 20, and obtain information about damaged storage units in the storage chip 20 through data verification results of the read and write.

[0033] For example, the control chip 10 can be configured to perform multiple sequences of reading and writing on the memory chip 20 each time the memory circuit 100 is powered on, obtain the damaged memory cells in the memory chip 20 by verifying the read and write data, and then calculate the information of the damaged memory cells based on the corresponding algorithm. In this embodiment, the algorithm can be a DRAM algorithm, which is not limited here.

[0034] In other embodiments, the control chip 10 can also be configured to perform multiple sequences of reading and writing on the storage chip 20 at preset time intervals, obtain the damaged storage unit in the storage chip 20 by verifying the read and write data, and then calculate the information of the damaged storage unit based on the corresponding algorithm.

[0035] In this embodiment, the memory chip 20 includes a plurality of word lines (WL), a plurality of pairs of complementary bit lines (target bit line BL and complementary bit line BL#) and a plurality of memory cells, wherein each memory cell is respectively connected to a word line WL and a pair of complementary bit lines (target bit line BL and complementary bit line BL#).

[0036] Each storage unit includes an access switch and a storage capacitor. The storage capacitor represents the logical "1" and "0" by the amount of charge stored in it, or the high and low voltage difference across the storage capacitor. The on and off of the access switch determines whether the information stored in the storage capacitor can be read or rewritten.

[0037] When a word line, a complementary bit line or a storage unit is short-circuited or open-circuited, it will cause read and write data errors. At this time, the control chip 10 reads and writes the storage chip 20 in multiple ways according to the preset trigger requirements, and the information of the currently damaged storage unit in the storage chip 20 can be obtained.

[0038] In addition, if Figure 1As shown, in this embodiment, the redundant repair module 30 is an independent control logic grain. When the redundant repair module 30 is used as an independent control logic grain, the redundant repair module 30 can be set to be packaged as a memory chip 20 through three-dimensional bonding with at least one memory grain 21 included in the memory chip 20. That is, when the redundant repair module 30 is used as an independent control logic grain, it can be stacked with the memory grain 21 of the memory chip 20. In this embodiment, if the redundant repair module 30 and the memory chip 20 are three-dimensionally bonded and packaged, the two can be 3D bonded by a technology such as hybrid bonding. The hybrid bonding technology can make the control logic grain of the redundant repair module 30 and the memory grain 21 of the memory chip 20 completely bonded at room temperature, and other non-conductive parts are also completely attached. Therefore, the use of hybrid bonding technology to 3D bond the two can reduce the volume of the two after bonding, which is conducive to the miniaturization of the memory chip 20.

[0039] In the prior art, the common storage circuits all place the redundant repair registers on the peripheral control circuit of the storage chip 20. The redundant repair module 30 of this embodiment is implemented as a logic circuit independent of the storage crystal grain of the storage chip, and is configured to be packaged as the storage chip 20 through three-dimensional bonding with at least one storage crystal grain 21 included in the storage chip 20. Compared with the prior art, the peripheral control circuit of the storage circuit 100 of the present application does not need to set up a storage space (such as a latch) for temporarily storing the bad point address and a peripheral circuit for comparing with the addressing address. Compared with the prior art, the storage circuit 100 of this embodiment is more concise and smaller in size.

[0040] In this embodiment, the redundant repair module 30 stores the control chip 10 to obtain the information of the damaged storage unit, and in response to the memory operation instruction, sends a redundant replacement address to the memory chip 20 based on the information of the damaged storage unit to perform the corresponding memory operation. That is, when the user sends a new read, write, refresh, etc. instruction, the redundant repair module 30 will match the memory operation instruction with the information of the damaged storage unit one by one. If they match, the corresponding redundant replacement address will be sent to the memory chip 20, otherwise the memory operation instruction will be normally output to the memory chip 20.

[0041] Different from the prior art, the storage circuit 100 of the present application includes a control chip 10 and a storage chip 20, and a redundant repair module 30 is set in one of the storage chip 20 and the control chip 10, wherein the control chip 10 is configured to obtain information about damaged storage cells in the storage chip 20 according to a preset trigger requirement, and the redundant repair module 30 is configured to store information about damaged storage cells, and in response to a memory operation instruction, send a redundant replacement address to the storage chip 20 based on the information about the damaged storage cell to perform a corresponding memory operation. In the above manner, the storage circuit 100 of the present application can obtain information about damaged storage cells in the storage chip 20 in real time according to a preset trigger requirement (for example, each time power is turned on or at intervals). The redundant repair module 30 obtains the information of the damaged storage unit in real time, and then uses the redundant repair module 30 to generate a redundant replacement address to the storage chip 20 based on the information of the damaged storage unit obtained in real time, thereby repairing the storage chip 20. Therefore, compared with the prior art, the storage circuit 100 of the present application can obtain the information of the damaged storage unit in the storage chip 20 in real time during the use of the random access memory through the redundant repair module 30, and repair the damaged storage unit in the storage chip 20 according to the aforementioned real-time information of the damaged storage unit, which solves the problem that the newly generated bad points in the actual use of the traditional storage chip after leaving the factory cannot be repaired, improves the service life of the random access memory, and reduces the possibility of random access memory reading and writing data errors. In addition, compared with the prior art of burning the repair information into the electrically programmed fuse array, the storage circuit 100 of the embodiment of the present application does not need an electrically programmed fuse array, which can greatly save the chip area of ​​the storage circuit 100.

[0042] Optionally, see Figure 2 , Figure 2 is a schematic diagram of the structure of the second embodiment of the storage circuit provided by the present application. Figure 2 As shown, in this embodiment, the control chip 10 includes a redundancy repair module 30, that is, the redundancy repair module 30 is integrated in the control chip 10 and configured as a functional module of the control chip 10. When the redundancy repair module 30 is integrated with the control chip 10, the stacking volume of the storage circuit 100 can be reduced.

[0043] Optionally, see Figure 3 , Figure 3 is a schematic diagram of the structure of the third embodiment of the storage circuit provided by the present application. Figure 3 The storage circuit of this embodiment further includes a bad pixel address loading module 40, which is connected to the control chip 10, stores the bad pixel address in the information of the damaged storage unit sent by the control chip 10, and generates a redundant control timing signal according to the information of the damaged storage unit.

[0044] Among them, the redundant repair module 30 is configured to load the bad point address from the bad point address loading module 40 according to the redundant control timing signal, compare the addressing address and the bad point address corresponding to the memory operation instruction, and generate a corresponding redundant replacement address in response to the addressing address matching the bad point address, so that the memory chip 20 performs a corresponding redundant replacement operation based on the redundant replacement address.

[0045] In this embodiment, if the redundant repair module 30 is an independent control logic chip, the bad pixel address loading module 40 can be set on the control logic chip corresponding to the redundant repair module 30. If the redundant repair module 30 is a functional module of the control chip 10, the bad pixel address loading module 40 can also be integrated on the control chip 10.

[0046] When the control chip 10 obtains the information of the damaged storage unit of the storage chip 20, the bad point address loading module 40 stores the information of the current damaged storage unit and loads the bad point address into the redundancy repair module 30 based on the redundancy control timing signal. The method of loading the bad point address based on the redundancy control timing signal is described below.

[0047] After the redundant repair module 30 stores the bad pixel address corresponding to the current damaged storage unit information, during the normal use of the random access memory, when the user sends a new memory operation instruction, the redundant repair module 30 can compare the addressing address corresponding to the memory operation instruction and the stored bad pixel address, and generate a corresponding redundant replacement address in response to the addressing address matching the bad pixel address, so that the storage chip 20 performs the corresponding redundant replacement operation based on the redundant replacement address, thereby ensuring that the random access memory reads and writes data normally.

[0048] In addition, compared with the prior art, in this embodiment, the bad pixel address loading module 40 and the redundant repair module 30 communicate with each other through a customized redundant control sequence to load the corresponding bad pixel address, and the design flexibility is higher.

[0049] Optionally, see Figure 4 , Figure 4 is a schematic diagram of the structure of the fourth embodiment of the storage circuit provided by the present application. Figure 4As shown, the memory chip 20 includes at least one memory grain 21; the redundant repair module 30 includes at least one redundant repair submodule 31, each redundant repair submodule 31 corresponds to one memory grain 21, and is respectively connected to the bad point address loading module 40, wherein each redundant repair submodule 31 is configured to load the bad point address of the corresponding memory grain 21 according to the redundant control timing signal; in response to the addressing operation of the corresponding memory grain 21, compare the addressing address and the bad point address; and in response to the addressing address matching the bad point address, generate a redundant replacement address of the corresponding memory grain 21, so that the memory grain 21 performs the corresponding redundant replacement operation based on the redundant replacement address.

[0050] like Figure 4 As shown, in this embodiment, the redundant repair module 30 may include a plurality of redundant repair submodules 31, and correspondingly, the memory chip 20 also includes a plurality of memory grains 21. Each redundant repair submodule 31 corresponds to a memory grain 21, that is, the damaged storage unit in the corresponding memory grain 21 is replaced and repaired by the corresponding redundant repair submodule 31. That is, each redundant repair submodule 31 may be based on the bad point address in the memory grain 21 corresponding to the redundant control timing signal. When the redundant repair submodule 31 obtains the addressing operation of the corresponding memory grain 21, that is, as described above, it may compare the addressing address of its addressing operation with the bad point address stored in the redundant repair submodule 31 to see whether they match. In response to the addressing address matching the bad point address, the redundant repair submodule 31 generates a redundant replacement address of the corresponding memory grain 21, so that the memory grain 21 performs the corresponding redundant replacement operation based on the redundant replacement address.

[0051] In this embodiment, the stability of the redundant repair module 30 can be ensured by setting a plurality of redundant repair submodules 31 , and when an error occurs in a redundant repair submodule 31 , other redundant repair submodules 31 will not be affected.

[0052] In this embodiment, the multiple redundant repair submodules 31 of the redundant repair module 30 are connected together with the common interfaces of the multiple storage grains 21 in the storage chip 20 by means of mixed binding. This architecture can realize that the control chip 10 controls the multiple storage grains 21 and realizes the simultaneous operation of the multiple storage grains 21, thereby improving the data bandwidth of the storage circuit 100 and improving the data processing speed of the storage circuit 100.

[0053] Optionally, based on the above embodiment, please refer to Figure 5 ,like Figure 5 As shown, Figure 5 Schematic diagram of the structure of the redundant repair submodule provided by this application. Figure 4 and Figure 5As shown, in the present embodiment, each redundant repair submodule 31 includes a redundant latch circuit 311 and a redundant matching circuit 312, wherein the redundant latch circuit 311 is configured to load the bad pixel address of the corresponding storage grain 21 according to the redundant control timing signal; the redundant matching circuit 312 is connected to the redundant latch circuit 311, and is configured to respond to the addressing operation of the corresponding storage grain 21, compare the addressing address and the bad pixel address; and generate a redundant replacement address of the corresponding storage grain 21 in response to matching the addressing address with the bad pixel address.

[0054] That is, before each redundant repair submodule 31 works, it must first load the bad pixel address of the storage grain 21 corresponding to itself from the bad pixel address loading module 40 according to the redundant control timing signal, and store it in the redundant latch circuit 311. After the bad pixel address of the storage grain 21 corresponding to itself is stored, if the subsequent control chip 10 sends the addressing operation of the storage grain 21 corresponding to the redundant repair submodule 31, the redundant matching circuit 312 in the redundant repair submodule will match the addressing address corresponding to the addressing operation with the bad pixel address stored in the redundant latch circuit 311 while decoding. If the addressing address matches the bad pixel address and it is determined that the current operation is an operation on the bad pixel, a redundant replacement address of the corresponding storage grain 21 is generated and sent to the corresponding storage grain 21. If it does not match, the addressing address corresponding to the addressing operation is sent to the storage grain 21.

[0055] Optionally, based on the above embodiment, the bad pixel address includes a row bad pixel address and a column bad pixel address, such as Figure 5 As shown, the redundant latch circuit 311 includes a row address latch circuit A and a column address latch circuit B. The row address latch circuit A is configured to load the row bad pixel address of the corresponding storage grain 21 according to the redundant control timing signal; the column address latch circuit B is configured to load the column bad pixel address of the corresponding storage grain 21 according to the redundant control timing signal.

[0056] The row address latch circuit A is used to store the row bad pixel address, and the column address latch circuit B is used to store the column bad pixel address. In this embodiment, the row address latch circuit A for storing the row bad pixel address requires 12 latches, wherein the row latch row rdn latch

[11] stores the flag of whether the current information is valid, and the row rdn latch[10:0] stores the row bad pixel address; the row address latch circuit B for storing the column bad pixel address only requires 6 latches, wherein the column latch col rdn latch[5] stores the flag of whether the current information is valid, and the col rdn latch[4:0] stores the column bad pixel address.

[0057] In other embodiments, the number of latches of the row address latch circuit A and the column address latch circuit B in the redundant latch circuit 311 may be determined according to the capacity of the actual memory chip 20 and a repair scheme, and is not limited here.

[0058] Optionally, based on the above embodiment, the redundant control timing signal includes a loading enable signal, a row bad pixel address loading enable signal, a column bad pixel address loading enable signal and a redundant repair sub-module identification signal; in response to the loading enable signal being high and the row bad pixel address loading enable signal being high, the row bad pixel address is stored in the redundant repair sub-module 31 corresponding to the redundant repair sub-module identification signal based on the redundant repair sub-module identification signal; in response to the loading enable signal being high and the column bad pixel address loading enable signal being high, the column bad pixel address is stored in the redundant repair sub-module 31 corresponding to the redundant repair sub-module identification signal based on the redundant repair sub-module identification signal.

[0059] See also Figure 6 , Figure 6 1 is a timing diagram of an embodiment of the present application in which the bad pixel address is loaded into the redundant repair module. Figure 6 As shown, when the loading enable signal RDN_LDEN and the row bad pixel address loading enable signal RDN_ROWEN are both high, the bad pixel address loading module 40 stores the corresponding row bad pixel address in the redundant repair submodule 31 corresponding to the redundant repair submodule identification signal based on the redundant repair submodule identification signal. When the loading enable signal RDN_LDEN and the column bad pixel address loading enable signal RDN_COLEN are both high, the bad pixel address loading module 40 stores the corresponding column bad pixel address in the redundant repair submodule 31 corresponding to the redundant repair submodule identification signal based on the redundant repair submodule identification signal.

[0060] In this embodiment, the bit width of the transmitted row bad pixel address and column bad pixel address is set to 12 bits, but in fact the bit width of the column bad pixel address is not 12 bits, but only 6 bits, that is, when obtaining the column bad pixel address, only the lower 6 bits can be obtained.

[0061] Optionally, based on the above embodiment, the bad pixel address loading module 40 is connected to the redundant repair module 30 through a multiplexed address bus; in response to the row bad pixel address loading enable signal being at a high level, the bad pixel address transmitted by the multiplexed address bus is the row bad pixel address; in response to the column bad pixel address loading enable signal being at a high level, the bad pixel address transmitted by the multiplexed address bus is the column bad pixel address.

[0062] That is, in this embodiment, Figure 6The bad pixel address in is transmitted through a multiplexed address bus. When the row bad pixel address load enable signal RDN_ROWEN is 1, it means that the row bad pixel address is transmitted. When the column bad pixel address load enable signal RDN_COLEN is 1, it means that the column bad pixel address is transmitted.

[0063] Optionally, based on the above-mentioned embodiments, in this embodiment, the redundant repair module 30 stores the control chip 10 to obtain the information of the damaged storage unit, and in response to the memory operation instruction, sends a redundant replacement address to the memory chip 20 based on the information of the damaged storage unit to perform the corresponding memory operation. When the redundant repair module 30 sends the corresponding redundant replacement address to the memory chip 20, the sent redundant replacement address includes a redundant replacement identifier, and the memory chip 20 will select to address the redundant storage area or the normal storage area according to whether the redundant replacement identifier is valid.

[0064] That is, when the user sends new read, write, refresh and other instructions, the redundant repair module 30 will match the memory operation instructions and the information of the damaged storage unit one by one. If they can match, the redundant replacement address sent at this time is valid, and the redundant repair module 30 will send it to the redundant storage area in the storage chip 20. Otherwise, the redundant repair module 30 will send the normally input addressing address to the normal storage area in the storage chip 20.

[0065] Different from the prior art, the storage circuit 100 of the present application includes a control chip 10 and a storage chip 20, and a redundant repair module 30 is set in one of the storage chip 20 and the control chip 10, wherein the control chip 10 is configured to obtain information about damaged storage cells in the storage chip 20 according to a preset trigger requirement, and the redundant repair module 30 is configured to store information about damaged storage cells, and in response to a memory operation instruction, send a redundant replacement address to the storage chip 20 based on the information about the damaged storage cell to perform a corresponding memory operation. In the above manner, the storage circuit 100 of the present application can obtain information about damaged storage cells in the storage chip 20 in real time according to a preset trigger requirement (for example, each time power is turned on or at intervals). The redundant repair module 30 uses the information of the damaged storage unit obtained in real time to generate a redundant replacement address to the storage chip 20, thereby repairing the storage chip 20. Therefore, compared with the prior art, the storage circuit 100 of the present application can obtain the information of the damaged storage unit in the storage chip 20 in real time during the use of the random access memory through the redundant repair module 30, and repair the damaged storage unit in the storage chip 20 according to the aforementioned information of the damaged storage unit obtained in real time, which solves the problem that the newly generated bad points in the actual use of the traditional storage chip after leaving the factory cannot be repaired, improves the service life of the random access memory, and reduces the possibility of errors in reading and writing data in the random access memory. In addition, compared with the prior art of burning the repair information into the electrically programmed fuse array, the storage circuit 100 of the embodiment of the present application does not need an electrically programmed fuse array, which can greatly save the chip area of ​​the storage circuit 100. In a further embodiment, the redundant repair module 30 of the embodiment of the present application is implemented by a logic circuit independent of the storage grain of the storage chip 20, so there is no need to set up a storage space for temporarily storing the bad point address and a peripheral circuit for comparing with the addressing address in the storage grain 21. In a further embodiment, the bad pixel address loading module 40 of the embodiment of the present application communicates with the redundant repair module 30 through a customized redundant control sequence to load the corresponding bad pixel address, which has a higher design flexibility.

[0066] Optionally, the present application further proposes a random access memory, see Figure 7 , Figure 7 1 is a schematic diagram of the structure of a random access memory of the present application. Figure 7 As shown, the random access memory 200 of this embodiment includes the storage circuit 100 of any of the above embodiments. The random access memory 200 can be a random access memory DRAM, a static random access memory SRAM or a pseudo static random access memory (Pseudo SRAM, PSRAM).

[0067] When the embodiments of the present application are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present application is essentially or the part that contributes to the prior art or all or part of the technical solution can be embodied in the form of a software product, and the computer software product is stored in a storage medium, including several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) or a processor to perform all or part of the steps of the method described in each embodiment of the present application. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a disk or an optical disk.

[0068] The above description is only an implementation method of the present application, and does not limit the patent scope of the present application. Any equivalent structure or equivalent process transformation made according to the description and drawings of the present application, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present application.

Claims

1. A storage circuit, characterized in that: include: Control chip; A storage chip connected to the control chip; Wherein, one of the control chip and the storage chip includes a redundancy repair module, and the control chip is configured to obtain information of damaged storage units in the storage chip according to a preset trigger requirement; The redundancy repair module is configured to store the information of the damaged storage unit, and in response to a memory operation instruction, issue a redundant replacement address to the memory chip based on the information of the damaged storage unit to perform a corresponding memory operation.

2. The storage circuit according to claim 1, wherein: The redundant repair module is an independent control logic grain, which is packaged into the storage chip through three-dimensional bonding with at least one storage grain included in the storage chip, or the redundant repair module is integrated in the control chip and configured as a functional module of the control chip.

3. The storage circuit according to claim 1, wherein: The preset trigger requirement includes: when the control chip determines that the storage circuit is powered on again, or when the control chip determines that a preset time has passed since the last acquisition operation; The control chip is configured to perform multiple sequences of reading and writing on the storage chip, and obtain information about damaged storage units in the storage chip through data verification results of the reading and writing.

4. The storage circuit according to claim 1, wherein: The storage circuit further comprises a bad pixel address loading module, the bad pixel address loading module is connected to the control chip, stores the bad pixel address in the information of the damaged storage unit sent by the control chip, and generates a redundant control timing signal according to the information of the damaged storage unit; Wherein, the redundant repair module is connected to the bad point address loading module, wherein the redundant repair module is configured to load the bad point address from the bad point address loading module according to the redundant control timing signal, compare the addressing address corresponding to the memory operation instruction with the bad point address, and generate the corresponding redundant replacement address in response to the addressing address matching the bad point address, so that the memory chip performs the corresponding redundant replacement operation based on the redundant replacement address.

5. The storage circuit according to claim 4, characterized in that: The memory chip includes at least one memory grain; The redundant repair module includes at least one redundant repair submodule, each of which corresponds to one of the storage grains and is respectively connected to the bad point address loading modules, wherein each of the redundant repair submodules is configured to load the bad point address of the corresponding storage grain according to a redundant control timing signal; in response to an addressing operation on the corresponding storage grain, compare the addressing address and the bad point address; and in response to the addressing address matching the bad point address, generate a redundant replacement address corresponding to the storage grain, so that the storage grain performs a corresponding redundant replacement operation based on the redundant replacement address.

6. The storage circuit according to claim 5, characterized in that: Each of the redundant repair submodules comprises: A redundant latch circuit is configured to load the bad pixel address of the corresponding storage grain according to a redundant control timing signal; A redundant matching circuit is connected to the redundant latch circuit and is configured to compare an addressing address with the bad pixel address in response to an addressing operation on the corresponding storage grain; and to generate the redundant replacement address corresponding to the storage grain in response to the addressing address matching the bad pixel address.

7. The storage circuit according to claim 6, characterized in that: The bad pixel address includes a row bad pixel address and a column bad pixel address, and the redundant latch circuit includes: A row address latch circuit, configured to load the row bad pixel address of the corresponding storage die according to the redundancy control timing signal; The column address latch circuit is configured to load the column bad pixel address of the corresponding storage chip according to the redundancy control timing signal.

8. The storage circuit according to claim 7, characterized in that: The redundant control timing signal includes a loading enable signal, a row bad pixel address loading enable signal, a column bad pixel address loading enable signal and a redundant repair submodule identification signal; In response to the load enable signal being at a high level and the row bad pixel address load enable signal being at a high level, the row bad pixel address is stored in the redundant repair submodule corresponding to the redundant repair submodule identification signal based on the redundant repair submodule identification signal; In response to the load enable signal being at a high level and the column bad pixel address load enable signal being at a high level, the column bad pixel address is stored in the redundant repair submodule corresponding to the redundant repair submodule identification signal based on the redundant repair submodule identification signal.

9. The storage circuit according to claim 8, characterized in that: The bad point address loading module is connected to the redundant repair module via a multiplexed address bus; In response to the row bad pixel address loading enable signal being at a high level, the bad pixel address transmitted by the multiplexed address bus is the row bad pixel address; in response to the column bad pixel address loading enable signal being at a high level, the bad pixel address transmitted by the multiplexed address bus is the column bad pixel address.

10. The storage circuit according to claim 4, characterized in that: The redundant replacement address includes a redundant replacement identifier, and the storage chip selects to address a redundant storage area or a normal storage area according to whether the redundant replacement identifier is valid.

11. A random access memory, characterized in that: The storage circuit comprises the storage circuit according to any one of claims 1 to 10.

Images