Low-noise transconductance amplifier, chip, receiver and electronic equipment

Abstract

The invention relates to a low-noise transconductance amplifier, a chip, a receiver and electronic equipment, the low-noise transconductance amplifier comprises a first-stage amplification circuit and a second-stage amplification circuit, the first-stage amplification circuit comprises a first-stage input end, a cascode amplification module, a common-source module, a feedback resistor and a first-stage output end, and the second-stage amplification circuit comprises a second-stage input end and a second-stage output end; the cascode amplification module is used for carrying out input matching and amplification processing on an input signal and outputting an obtained first-stage output signal through a first-stage output end; the common source module is used for carrying out noise elimination on an input signal; the second-stage amplification circuit comprises a second-stage input end, a transconductance amplification module and a second-stage output end which are connected in sequence, and the transconductance amplification module is used for conducting transconductance amplification and linearity adjustment on the first-stage output signal and outputting the obtained second-stage output signal through the second-stage output end. According to the low-noise transconductance amplifier, the performance of high gain, high linearity and large bandwidth of the low-noise transconductance amplifier is achieved.

Description

Technical Field

[0001] The present application relates to the field of microelectronics technology, and in particular to a low-noise transconductance amplifier, a chip, a receiver and an electronic device. Background Art

[0002] The low noise transconductance amplifier (LNTA) is an important component of the current mode architecture receiver. The signal received by the antenna is first converted into a current signal through it, and then down-converted to the baseband for processing. Similar to the traditional low noise amplifier, the low noise transconductance amplifier needs to ensure a sufficiently low noise figure and a sufficiently high gain to ensure that the link has good gain and noise performance; in addition, its linearity, bandwidth, power consumption and other indicators also need to be comprehensively considered during the design. However, it is difficult to balance the design of low noise figure, large bandwidth and input matching in the traditional low noise transconductance amplifier, and the performance is poor. Summary of the invention

[0003] Based on this, it is necessary to provide a low-noise transconductance amplifier, chip, receiver and electronic device that can improve performance.

[0004] In a first aspect, the present application provides a low-noise transconductance amplifier, comprising a first-stage amplifier circuit and a second-stage amplifier circuit, wherein:

[0005] The first-stage amplifier circuit includes a first-stage input terminal, a common-source and common-gate amplifier module, a common-source module, a feedback resistor and a first-stage output terminal; the feedback resistor is connected between the first-stage input terminal and the first-stage output terminal; the first-stage input terminal is used to receive an input signal, the common-source and common-gate amplifier module is used to perform input matching and amplification processing on the input signal, and output the obtained first-stage output signal through the first-stage output terminal; the common-source module is used to eliminate noise on the input signal;

[0006] The second-stage amplifier circuit includes a second-stage input terminal, a transconductance amplifier module, and a second-stage output terminal connected in sequence. The second-stage input terminal is used to receive the first-stage output signal. The transconductance amplifier module is used to perform transconductance amplification and linearity adjustment on the first-stage output signal, and the obtained second-stage output signal is output through the second-stage output terminal.

[0007] In one of the embodiments, the cascode amplification module includes a complementary cascode amplification unit;

[0008] The complementary cascode amplifier unit comprises a first cascode transistor pair and a first cascode transistor pair;

[0009] The gate electrodes of the two common-source tubes in the first common-source tube pair are connected to the first-stage input terminal, the source electrode of one common-source tube in the first common-source tube pair is used for grounding, the source electrode of the other common-source tube in the first common-source tube pair is used for accessing a power supply, and the drain electrodes of the two common-source tubes in the first common-source tube pair are respectively connected to the sources of the two common-gate tubes in the first common-gate tube pair; the gate electrode of one common-gate tube in the first common-gate tube pair is used for accessing a power supply, the gate electrode of the other common-gate tube in the first common-gate tube pair is used for grounding, and the drain electrodes of the two common-gate tubes in the first common-gate tube pair are connected to the first-stage output terminal.

[0010] In one embodiment, the two common-gate transistors in the first common-gate transistor pair are MOS devices, and the two common-source transistors in the first common-source transistor pair are MOS devices.

[0011] In one embodiment, one common-gate transistor in the first common-gate transistor pair is an NMOS transistor of a high threshold voltage HVT type, and the other common-gate transistor in the first common-gate transistor pair is a PMOS transistor of a high threshold voltage HVT type;

[0012] One common source transistor in the first common source transistor pair is an NMOS transistor of a common threshold voltage RVT type, and the other common source transistor in the first common source transistor pair is a PMOS transistor of a common threshold voltage RVT type.

[0013] In one of the embodiments, the width-to-length ratio of the two common-gate transistors in the first common-gate transistor pair is configured based on the overdrive voltage.

[0014] In one embodiment, the first-stage amplifier circuit further includes a transconductance enhancement module for improving the equivalent transconductance of the complementary cascode amplifier unit.

[0015] In one embodiment, the transconductance enhancement module includes a first transistor, a second transistor, a first resistor, and a second resistor;

[0016] The gate of the first transistor is connected to the source of one of the first common-gate tubes in the common-gate tube pair, the drain of the first transistor is connected to the gate of one of the common-gate tubes in the first common-gate tube pair, and the source of the first transistor is used for grounding; one end of the first resistor is connected between the drain of the first transistor and the gate of one of the common-gate tubes in the first common-gate tube pair, and the other end of the first resistor is used for connecting to a power supply;

[0017] The gate of the second transistor is connected to the source of the other common-gate tube in the first common-gate tube pair, the drain of the second transistor is connected to the gate of the other common-gate tube in the first common-gate tube pair, and the source of the second transistor is used to access the power supply; one end of the second resistor is connected between the drain of the second transistor and the gate of the other common-gate tube in the first common-gate tube pair, and the other end of the second resistor is used for grounding.

[0018] In one embodiment, the first transistor is an ultra-low threshold voltage ULVT type NMOS transistor, and the second transistor is an ultra-low threshold voltage ULVT type PMOS transistor.

[0019] In one embodiment, the common source module includes a complementary common source unit for adjusting the impedance of the complementary common source and common gate amplifier unit.

[0020] In one of the embodiments, the complementary common source unit includes a second common source tube pair;

[0021] The gate electrodes of the two common source tubes in the second common source tube pair are connected to the input terminal of the first stage, the drain electrodes of the two common source tubes in the second common source tube pair are connected to the output terminal of the first stage, the source electrode of one common source tube in the second common source tube pair is used for grounding, and the source electrode of the other common source tube in the second common source tube pair is used for connecting to the power supply.

[0022] In one embodiment, one common source transistor in the second common source transistor pair is an ultra-low threshold voltage ULVT type NMOS transistor, and the other common source transistor in the second common source transistor pair is an ultra-low threshold voltage ULVT type PMOS transistor.

[0023] In one embodiment, the first-stage output signal includes a voltage signal, and the second-stage output signal includes a current signal;

[0024] The transconductance amplification module includes a complementary common-source amplification unit, which is used to apply a transconductance gain to a voltage signal to generate a current signal; wherein the complementary common-source amplification unit is used to complete linearity adjustment by derivative superposition.

[0025] In one embodiment, the complementary common-source amplifier unit includes a third transistor, a fourth transistor, a fifth transistor and a sixth transistor;

[0026] The gate of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor are connected to the second-stage input terminal, and the drain of the third transistor, the drain of the fourth transistor, the drain of the fifth transistor and the drain of the sixth transistor are connected to the second-stage output terminal; the source of the third transistor and the source of the fifth transistor are used for grounding, and the source of the fourth transistor and the source of the sixth transistor are used for connecting to a power supply.

[0027] In one embodiment, the third transistor is an NMOS tube of a universal threshold voltage RVT type, the fourth transistor is a PMOS tube of a universal threshold voltage RVT type, the fifth transistor is an NMOS tube of a high threshold voltage HVT type, and the sixth transistor is a PMOS tube of a high threshold voltage HVT type.

[0028] In one embodiment, the width-to-length ratio of the fourth transistor and the width-to-length ratio of the third transistor are set according to a first preset ratio; the width-to-length ratio of the sixth transistor and the width-to-length ratio of the fifth transistor are set according to a second preset ratio.

[0029] In one of the embodiments, the complementary common-source amplifier unit further includes an error amplifier, a third resistor and a fourth resistor;

[0030] The positive end of the error amplifier is connected to the second stage output end through the third resistor, the negative end of the error amplifier is used to access the standard reference voltage, and the output end of the error amplifier is connected to the second stage input end through the fourth resistor.

[0031] In one embodiment, the resistance value of the third resistor is greater than 10k ohms, and the resistance value of the fourth resistor is greater than 10k ohms.

[0032] In a second aspect, the present application provides a chip, the chip comprising the low-noise transconductance amplifier as described above.

[0033] In a third aspect, the present application provides a receiver, including an antenna, and a low-noise transconductance amplifier as described above.

[0034] In a fourth aspect, the present application provides an electronic device, comprising the low-noise transconductance amplifier as described above, or the chip as described above, or the receiver as described above.

[0035] The above-mentioned low-noise transconductance amplifier, chip, receiver and electronic device, the low-noise transconductance amplifier includes a first-stage amplifier circuit and a second-stage amplifier circuit, the first-stage amplifier circuit may include a common-source and common-gate amplifier module and a common-source module, the common-source and common-gate amplifier module is used to perform input matching and amplification processing on the input signal, and output the obtained first-stage output signal through the first-stage output terminal, the common-source module is used to eliminate noise on the input signal, and then improve the bandwidth through the common-source and common-gate structure combined with the auxiliary common-source stage, wherein the common-source module as an auxiliary common-source stage also provides a noise elimination effect to improve noise performance; further, the second-stage amplifier circuit may include a transconductance amplifier module, the transconductance amplifier module is used to perform transconductance amplification and linearity adjustment on the first-stage output signal to obtain a second-stage output signal, which can improve linearity; the present application realizes the high gain, high linearity and large bandwidth performance of the low-noise transconductance amplifier. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 is an application environment diagram of a low noise transconductance amplifier in one embodiment;

[0038] Figure 2 A low noise transconductance amplifier of one embodiment;

[0039] Figure 3 A module structure of a common-source and common-gate amplifier module in an embodiment;

[0040] Figure 4 Another module structure of a common-source and common-gate amplifier module in an embodiment;

[0041] Figure 5 A module structure of a common source module in an embodiment;

[0042] Figure 6 is a schematic structural diagram of a first-stage amplifier circuit in one embodiment;

[0043] Figure 7 A module structure of a transconductance amplification module in an embodiment;

[0044] Figure 8 Another module structure of a transconductance amplification module in one embodiment;

[0045] Fig. 9 is a simplified structural diagram of a low noise transconductance amplifier in one embodiment;

[0046] Fig.10 A schematic diagram of the specific structure of a low noise transconductance amplifier in one embodiment;

[0047] Fig.11 A schematic diagram of improving circuit bandwidth by combining a common-source and common-gate stage with an auxiliary common-source stage in one embodiment;

[0048] Fig.12 A schematic diagram of a circuit simulation result in an embodiment;

[0049] Fig.13 It is a schematic diagram of the simulation result of the circuit in another embodiment. DETAILED DESCRIPTION

[0050] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0051] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0052] It is understood that the terms "first", "second", etc. used in this application can be used to describe various elements in this article, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. It is understood that the "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the connected circuits, modules, units, etc. have transmission of electrical signals or data with each other.

[0053] It can be understood that “at least one” means one or more, “plurality” means two or more, and “at least a portion of an element” means a part or all of an element.

[0054] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0055] With the development of chip manufacturing technology, the power supply voltage of the circuit continues to decline, which brings certain advantages in terms of chip power consumption and digital circuit speed, but low power supply voltage will bring challenges to analog / RF circuit design. The reason is that low power supply voltage will affect the working state of active devices in the circuit and deteriorate circuit linearity, gain, dynamic range, frequency range and other indicators. Current mode architecture receivers are considered to be suitable for this low voltage scenario because the signal in its link is transmitted in the form of current, without the need for high-resistance nodes, so that the signal has a large enough swing space.

[0056] Low-noise transconductance amplifiers are an important component of current-mode receivers. However, it is difficult to design traditional low-noise transconductance amplifiers in terms of low noise figure, large bandwidth, and input matching. Noise cancellation is often used to coordinate the design of input matching and noise performance, but the effect is limited. In addition, existing low-noise transconductance amplifiers often have limited bandwidth and are difficult to apply to today's increasingly expanding communication frequency bands.

[0057] Based on the traditional resistive feedback amplifier, the embodiment of the present application adopts a transconductance enhanced common source and common gate structure to improve the noise and transconductance performance, and combines an auxiliary common source stage to improve the bandwidth. At the same time, the derivative superposition method is used to optimize the nonlinear performance, and finally a high-gain, high-linearity, large-bandwidth low-noise transconductance amplifier can be designed.

[0058] Exemplarily, the low noise transconductance amplifier in the embodiment of the present application can be applied to a chip, such as a digital chip, an analog chip, etc.; optionally, the chip can be a radio frequency transceiver chip. Further, the low noise transconductance amplifier in the embodiment of the present application can be applied to a receiver. Optionally, taking the application of the low noise transconductance amplifier to a current mode broadband receiver system as an example, Figure 1 A schematic diagram of an application scenario of a low noise transconductance amplifier provided in an embodiment of the present application. Figure 1 In the current mode receiver system architecture shown in FIG. 1 , a low noise transconductance amplifier is placed after the antenna (ANT), where TIA stands for trans-impedance amplifier (TIA), and Mixer stands for mixer. The performance of the mixer is controlled by the local oscillator frequency LO (Local Oscillator).

[0059] The embodiment of the present application is based on a common source and common gate structure combined with an auxiliary common source stage to improve the bandwidth of a transconductance amplifier, thereby realizing a low-noise transconductance amplifier with high gain, high linearity and large bandwidth; the low-noise transconductance amplifier adopts a two-stage common source amplifier structure, the first stage improves the bandwidth and gain performance by transconductance enhancement of the common source and common gate structure combined with an auxiliary common source stage, the second stage improves the input third-order intercept point of the amplifier by derivative elimination, and at the same time reduces the required power consumption by current multiplexing, thereby realizing the coexistence of low power consumption, low noise, large bandwidth, high gain and high third-order intercept point.

[0060] It should be noted that the beneficial effects brought about by the embodiments of the present application or the technical problems solved are not limited to this one, but may also include other implicit or related problems. For details, please refer to the description of the following embodiments.

[0061] The technical solution of the present application and how the technical solution of the present application solves the above-mentioned technical problems are described in detail below with specific embodiments. The following specific embodiments can be combined with each other, and the same or similar concepts or processes may not be repeated in some embodiments. The embodiments of the present application will be described below in conjunction with the accompanying drawings.

[0062] like Figure 2 As shown, a low noise transconductance amplifier of an embodiment includes a first stage amplifier circuit 10 and a second stage amplifier circuit 20, wherein:

[0063] The first-stage amplifier circuit 10 includes a first-stage input terminal, a common-source common-gate amplifier module 102, a common-source module 104, a feedback resistor R1 and a first-stage output terminal; the feedback resistor R1 is connected between the first-stage input terminal and the first-stage output terminal; the first-stage input terminal is used to receive an input signal, the common-source common-gate amplifier module 102 is used to perform input matching and amplification processing on the input signal, and output the obtained first-stage output signal through the first-stage output terminal; the common-source module 204 is used to eliminate noise on the input signal;

[0064] The second-stage amplifier circuit 20 includes a second-stage input terminal, a transconductance amplifier module 202 and a second-stage output terminal connected in sequence. The second-stage input terminal is used to receive the first-stage output signal. The transconductance amplifier module 202 is used to perform transconductance amplification and linearity adjustment on the first-stage output signal, and output the obtained second-stage output signal through the second-stage output terminal.

[0065] Specifically, the low noise transconductance amplifier includes a two-stage structure, namely a first-stage amplifier circuit 10 and a second-stage amplifier circuit 20; illustratively, the low noise transconductance amplifier can adopt a two-stage common source amplifier structure to optimize performance, for example, by adopting a common source and common gate structure and two-stage amplification, thereby having a higher transconductance gain. It can be understood that in the embodiment of the present application, the first-stage amplifier circuit can be referred to as the first-stage amplifier, and the second-stage amplifier circuit can be referred to as the second-stage amplifier.

[0066] The first-stage amplifier circuit 10 includes a first-stage input terminal, a common-source common-gate amplifier module 102, a common-source module 104, a feedback resistor R1, and a first-stage output terminal; it can be understood that the common-source common-gate amplifier module 102, the common-source module 104, and the feedback resistor R1 can constitute a structure for resistor feedback common-source stage noise elimination. Exemplarily, the first-stage input terminal can receive an input signal as a signal input terminal of a low-noise transconductance amplifier; optionally, the input signal can be an input voltage.

[0067] In the embodiment of the present application, the cascode amplifier module 102 may refer to an amplifier module of a cascode structure, so that the low-noise transconductance amplifier can have a higher bandwidth, wherein the cascode amplifier module 102 can be used to perform input matching and amplification processing on the input signal to obtain a first-stage output signal; it can be understood that the first-stage output signal can be a voltage signal. Exemplarily, taking the input signal as an input voltage as an example, based on the cascode amplifier module 102, the first-stage amplifier circuit can achieve input matching and perform preliminary amplification on the input voltage.

[0068] Optionally, the embodiment of the present application can design the transconductance of the common-source and common-gate amplifier module and the size of the feedback resistor R1 according to the input matching to achieve a higher bandwidth, for example, the feedback resistor R1 can be slightly greater than 50Ω. Traditional broadband low-noise transconductance amplifiers use a common-gate stage or a resistor feedback common-source stage to achieve broadband input matching, but they all face contradictions between various indicators such as input matching, gain and noise. In this regard, the present application proposes to avoid the impact on the circuit bandwidth through a common-source and common-gate structure; illustratively, the common-source and common-gate structure can weaken the impact of the Miller effect on the circuit bandwidth, wherein the load of the common-source tube can be used as the input impedance of the common-gate stage, thereby reducing the gain of the common-source tube.

[0069] The embodiment of the present application adopts a common source and common gate structure to suppress the Miller effect of the gate-drain capacitance of the common source amplifier. It can be understood that the above-mentioned common source and common gate amplifier module can also adopt other forms (for example, by combining the common source and common gate structure with the auxiliary common source stage to expand the working bandwidth), and is not limited to the forms mentioned in the above embodiments, as long as it can achieve the functions of completing the input matching and amplification processing.

[0070] Furthermore, the common source module 204 can be used to eliminate noise from the input signal; wherein the common source module 204 provides a noise elimination effect as an auxiliary common source stage to improve noise performance. Exemplarily, the common source module 204 cooperates with the common source and common gate amplifier module 102 as a common source and common gate combined with an auxiliary common source stage structure to improve bandwidth and gain performance.

[0071] Optionally, a lower noise coefficient can be achieved by using a corresponding noise elimination method through the common source module 204. Exemplarily, the common source module can be implemented by an auxiliary common source stage circuit, or by a corresponding transistor. It can be understood that the common source module can also be implemented in other forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the function of completing the noise elimination process.

[0072] Regarding the second stage amplifier circuit 20, as shown in FIG. Figure 2 As shown, the second-stage amplifier circuit 20 may include a second-stage input terminal, a transconductance amplification module 202, and a second-stage output terminal connected in sequence, wherein the second-stage input terminal may be connected to the first-stage output terminal for receiving the first-stage output signal, and the transconductance amplification module 202 is used to perform transconductance amplification and linearity adjustment on the first-stage output signal, and then output the second-stage output signal through the second-stage output terminal. It can be understood that the second-stage output terminal can be used as a signal output terminal of a low-noise transconductance amplifier, and optionally, the input signal can be an input voltage. Exemplarily, taking the input signal as an input voltage (Vin) as an example, the first-stage output signal may be a voltage signal, and the second-stage output signal may be a current signal (Iout).

[0073] Based on the transconductance amplification module 202, the second-stage amplifier circuit 20 can achieve the functions of transconductance amplification and linearity adjustment. Exemplarily, the transconductance amplification module can adopt a transconductance unit of a common source stage structure to optimize nonlinear performance. Optionally, the transconductance amplification module can be implemented using corresponding transistors. It can be understood that the above-mentioned transconductance amplification module can also adopt other forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the functions of completing transconductance amplification and linearity adjustment.

[0074] The above-mentioned low-noise transconductance amplifier has a high transconductance gain through a common-source common-gate structure and two-stage amplification; wherein, a common-source common-gate stage combined with an auxiliary common-source stage is used to expand the working bandwidth, and further, the auxiliary common-source stage also provides a noise elimination effect to improve the noise performance. The use of a transconductance amplification module can achieve an improvement in linearity, thereby significantly improving the performance of the low-noise transconductance amplifier.

[0075] In an exemplary embodiment, the common-source and common-gate amplification module includes a complementary common-source and common-gate amplification unit; the complementary common-source and common-gate amplification unit includes a first common-gate tube pair and a first common-source tube pair; the gates of the two common-source tubes in the first common-source tube pair are connected to the first-stage input terminal, the source of one common-source tube in the first common-source tube pair is used for grounding, the source of the other common-source tube in the first common-source tube pair is used for access to a power supply, and the drains of the two common-source tubes in the first common-source tube pair are respectively connected to the sources of the two common-gate tubes in the first common-gate tube pair; the gate of one common-gate tube in the first common-gate tube pair is used for access to a power supply, the gate of the other common-gate tube in the first common-gate tube pair is used for grounding, and the drains of the two common-gate tubes in the first common-gate tube pair are connected to the first-stage output terminal.

[0076] Specifically, the cascode amplification module may include a complementary cascode amplification unit. The complementary cascode amplification unit, as a cascode structure, may be used to perform input matching and amplification processing on the input signal. Exemplarily, the complementary cascode amplification unit may be implemented using a complementary cascode amplifier or a corresponding transistor, and the present application does not limit this.

[0077] Exemplarily, the complementary common-source common-gate amplification unit may include a first common-gate tube pair and a first common-source tube pair; wherein, the gates of the two common-source tubes in the first common-source tube pair are connected to the first-stage input terminal, the source of one common-source tube in the first common-source tube pair is used for grounding, the source of the other common-source tube in the first common-source tube pair is used for connecting to a power supply, and the drains of the two common-source tubes in the first common-source tube pair are respectively connected to the sources of the two common-gate tubes in the first common-gate tube pair; the gate of one common-gate tube in the first common-gate tube pair is used for connecting to a power supply, the gate of the other common-gate tube in the first common-gate tube pair is used for grounding, and the drains of the two common-gate tubes in the first common-gate tube pair are connected to the first-stage output terminal.

[0078] In the traditional common-source amplifier structure, the equivalent capacitance seen from the input end is the input tube gate-source capacitance and the multiplied gate-drain capacitance (Miller effect), which generates a pole with the input resistance, thereby limiting the bandwidth of the circuit. Based on the above-mentioned complementary common-source and common-gate amplifier unit, the embodiment of the present application can weaken the influence of the Miller effect on the circuit bandwidth, and the load of the common-source tube (the first common-source tube pair) becomes the input impedance of the common-gate stage (the first common-gate tube pair), reducing the gain of the common-source tube, thereby suppressing the Miller effect of the gate-drain capacitance of the common-source amplifier.

[0079] In one embodiment, the two common-gate transistors in the first common-gate transistor pair are MOS devices, and the two common-source transistors in the first common-source transistor pair are MOS devices.

[0080] Specifically, the embodiments of the present application can implement related functions of the first common-gate transistor pair and the first common-source transistor pair through MOS devices.

[0081] like Figure 3 As shown, taking the MOS device using PMOS and NMOS as an example, the gates of the two common source tubes (M1, M4) in the first common source tube pair are connected to the first stage input terminal (Vin), the source of one common source tube (M1) in the first common source tube pair is used for grounding, the source of the other common source tube (M4) in the first common source tube pair is used for connecting to the power supply, and the drains of the two common source tubes (M1, M4) in the first common source tube pair are respectively connected to the sources of the two common gate tubes (M2, M5) in the first common gate tube pair; the gate of one common gate tube (M2) in the first common gate tube pair is used for connecting to the power supply, the gate of the other common gate tube (M5) in the first common gate tube pair is used for grounding, and the drains of the two common gate tubes (M2, M5) in the first common gate tube pair are connected to the first stage output terminal. Among them, the NMOS tubes M1, NMOS tubes M2 and the PMOS tubes M4, PMOS tubes M5 form a complementary common source and common gate structure, thereby realizing the relevant functions of the complementary common source and common gate amplification unit.

[0082] Understandably, Figure 3 Where Av may represent gain, Gm may represent transconductance, C1 may represent a capacitor connected between the first-stage output terminal and the second-stage input terminal, and R1 may represent a feedback resistor connected between the first-stage input terminal and the first-stage output terminal.

[0083] In the traditional common-source amplifier structure, the equivalent capacitance from the input end perspective is the input tube gate-source capacitance and the multiplied gate-drain capacitance (Miller effect), which generates a pole with the input resistance, thereby limiting the bandwidth of the circuit. In response to this, the present application proposes to adopt a common-source common-gate structure to weaken the influence of the Miller effect on the circuit bandwidth, wherein the load of the common-source tube (M1, M4) becomes the input impedance of the common-gate stage (M2, M5), reducing the gain of the common-source tube (M1, M4).

[0084] In practical applications, the power supply voltage is generally only about 1V, which brings design difficulties to the complementary common-source common-gate structure; in this regard, in one embodiment, one common-gate transistor (M2) in the first common-gate transistor pair is a high threshold voltage HVT type NMOS transistor, and the other common-gate transistor (M5) in the first common-gate transistor pair is a high threshold voltage HVT type PMOS transistor;

[0085] One common source transistor (M1) in the first common source transistor pair is an NMOS transistor of a universal threshold voltage RVT type, and the other common source transistor (M4) in the first common source transistor pair is a PMOS transistor of a universal threshold voltage RVT type.

[0086] Specifically, in the present application, a low-threshold type MOS tube is selected for the input common-source tube (such as M1 and M4), and a high-threshold voltage MOS tube is selected for the common-gate tube (such as M2 and M5). By adjusting the bias voltage, it is ensured that all MOS tubes operate in the saturation region.

[0087] In the circuit structure proposed in the present application, transistors with different threshold voltages are selected. On the one hand, the elimination of high-order conduction of transconductance is considered; on the other hand, the static power consumption and static operating point of the circuit are considered. In the complementary common-source and common-gate amplifier unit, the common-source transistors M1 and M4 use RVT to ensure that their gate-source voltage is around VDD / 2, and the drain-source can be stable in the saturation region when it is around VDD / 4; M2 and M5 choose HVT, which can reduce power consumption as much as possible while eliminating high-order conduction of transconductance. It can be understood that in the embodiment of the present application, transistors of different threshold voltage types are selective. For example, the common-gate transistors M2 and M5 can be replaced with ultra-low threshold voltage ULVT types, and the bias voltage can be adjusted to keep them in the saturation region.

[0088] In one of the embodiments, the width-to-length ratio of the two common-gate transistors in the first common-gate transistor pair is configured based on the overdrive voltage.

[0089] Specifically, taking the two common-gate transistors in the first common-gate transistor pair as common-gate transistors M2 and M5, the width-to-length ratio of the common-gate transistors M2 and M5 needs to take into account the over-driving voltage, and needs to be properly allocated to ensure that each MOS transistor operates in the saturation region.

[0090] It is understandable that the common-gate tube is generally believed to provide no transconductance, but the transconductance value of the common-gate tube itself will affect the size of the Miller effect of the common-source tube (M1, M4), and thus affect the circuit bandwidth; at the same time, the overdrive voltage of the common-gate tube will affect the high-order nonlinear transconductance g of the first-stage amplifier. m Therefore, it is necessary to select a suitable bias voltage. The bias voltage can be provided from outside the chip to facilitate off-chip performance adjustment, or it can be generated from within the chip.

[0091] Further, taking the MOS device using a PMOS tube and an NMOS tube as an example, by adjusting the sizes of the NMOS and the PMOS in a complementary structure, the transconductance can have different change trends, wherein adjusting the size can refer to adjusting the ratio of the width-to-length ratio of the PMOS to the width-to-length ratio of the NMOS. Exemplarily, adjusting the size ratio of the NMOS and the PMOS in the complementary structure can have different change trends for the high-order terms of the transconductance.

[0092] In one embodiment, the first-stage amplifier circuit further includes a transconductance enhancement module for improving the equivalent transconductance of the complementary cascode amplifier unit.

[0093] Specifically, the first-stage amplifier circuit may further include a transconductance enhancement module, which may be used to improve the equivalent transconductance of the complementary common-source and common-gate amplifier unit. The embodiment of the present application improves the noise and transconductance performance by adopting a transconductance enhanced common-source and common-gate structure, and may be combined with an auxiliary common-source stage to improve the bandwidth.

[0094] Exemplarily, the transconductance enhancement module may use a transconductance enhancement structure to implement corresponding functions; optionally, the transconductance enhancement module may also be implemented using corresponding transistors, which is not limited in the present application.

[0095] In the low-noise transconductance amplifier of the embodiment of the present application, a common-source and common-gate stage combined with an auxiliary common-source stage structure is used to expand the operating bandwidth, and transconductance enhancement (gm-boosting) is combined to improve the gain. The auxiliary common-source stage also provides a noise elimination effect to improve noise performance.

[0096] like Figure 4 As shown, a transconductance enhancement module of an embodiment may include a first transistor (M3), a second transistor (M6), a first resistor (R2) and a second resistor (R3);

[0097] The gate of the first transistor (M3) is connected to the source of a common-gate tube (M2) in the first common-gate tube pair, the drain of the first transistor (M3) is connected to the gate of a common-gate tube (M2) in the first common-gate tube pair, and the source of the first transistor (M3) is used for grounding; one end of the first resistor (R2) is connected between the drain of the first transistor (M3) and the gate of a common-gate tube (M2) in the first common-gate tube pair, and the other end of the first resistor (R2) is used for connecting to a power supply;

[0098] The gate of the second transistor (M6) is connected to the source of the other common-gate tube (M5) in the first common-gate tube pair, the drain of the second transistor (M6) is connected to the gate of the other common-gate tube (M5) in the first common-gate tube pair, and the source of the second transistor (M6) is used to access the power supply; one end of the second resistor (R3) is connected between the drain of the second transistor (M6) and the gate of the other common-gate tube (M5) in the first common-gate tube pair, and the other end of the second resistor (R3) is used to be grounded.

[0099] Specifically, the first transistor (M3), the second transistor (M6), the first resistor (R2) and the second resistor (R3) form a transconductance enhancement structure for the common-gate transistor (M2, M5). It can be understood that since the transconductance enhancement is to improve the equivalent transconductance of the common-gate transistor, the module (transconductance enhancement module) can be independently added or deleted in the embodiment of the present application.

[0100] In one embodiment, the first transistor (M3) is an ultra-low threshold voltage ULVT type NMOS transistor, and the second transistor (M6) is an ultra-low threshold voltage ULVT type PMOS transistor.

[0101] Specifically, for M3 and M6 of the transconductance enhancement stage, since their gate voltages are relatively low, transistors with relatively low threshold voltages need to be selected to ensure that they operate in a saturation region or a subthreshold region.

[0102] It should be noted that transistors of different threshold voltage types are selective. For example, the auxiliary common source stages M3 and M6 can be replaced with universal threshold voltages RVT or high threshold voltages HVT. These replacements will cause the power consumption, bandwidth, and noise coefficient performance of the circuit to change, so that it can be applied to different scenarios. The example given in this application is one of the options, which increases power consumption in order to meet the corresponding communication frequency bands, such as the 5G (5th Generation Mobile Communication Technology) communication frequency band. Since the selection of different types of transistors only changes the trade-offs between their different performances, the circuit principles involved are the same, so they are still within the scope of this application.

[0103] It can be understood that the above-mentioned transconductance enhancement module can also adopt other forms, and is not limited to the forms mentioned in the above embodiments, as long as it can achieve the function of completing transconductance enhancement.

[0104] In one embodiment, the common source module may include a complementary common source unit for adjusting the impedance of the complementary common source and common gate amplifier unit.

[0105] Specifically, in the embodiment of the present application, the common source module can realize corresponding functions through complementary common source units, for example, providing noise elimination effect to improve noise performance, and adjusting the impedance of complementary common source and common gate amplifier units to increase the operating frequency of the circuit.

[0106] Exemplarily, the complementary common source unit may refer to a complementary common source amplifier; optionally, the complementary common source unit may also be implemented by using corresponding transistors. It is understood that the complementary common source unit may also be implemented in other forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the functions of noise elimination and impedance adjustment.

[0107] like Figure 5 As shown, the complementary common source unit of an embodiment may include a second common source tube pair; the gates of the two common source tubes (M7, M8) in the second common source tube pair are connected to the first stage input terminal, the drains of the two common source tubes (M7, M8) in the second common source tube pair are connected to the first stage output terminal, the source of one common source tube (M7) in the second common source tube pair is used for grounding, and the source of the other common source tube (M8) in the second common source tube pair is used for connecting to a power supply.

[0108] Specifically, the complementary common source unit can be a complementary common source amplifier composed of two common source transistors (M7, M8). Based on the complementary common source common gate amplifier unit and the complementary common source unit, the embodiment of the present application can use current summing instead of the traditional voltage summing method using an adder to save power consumption and voltage domain, wherein the drains of transistors M7 and M8 are connected to the drains of transistors M2 and M5.

[0109] Exemplarily, the main architecture of the present application adopts a complementary common source stage, and current is summed at the drain end of the transistor, and then by controlling the threshold voltage, the gate bias voltage can adjust the high-order terms of the transconductance in the total output current. In addition, at the output node of the first stage (the first stage output end), the high output resistance of the common source and common gate tube will limit the voltage swing of the node, and the common source and common gate amplifier module and the common source module adopt the current summing method to not only achieve noise elimination, but also reduce the output resistance of the node. The embodiment of the present application reduces the required power consumption by current multiplexing.

[0110] Understandably, Figure 5 The structure shown does not use a transconductance enhancement module. In some examples, such as Figure 6 As shown, based on the complementary common-source common-gate amplifier unit and the complementary common-source unit, a transconductance enhancement module can also be added, and the transconductance enhancement module includes a first transistor (M3), a second transistor (M6), a first resistor (R2) and a second resistor (R3).

[0111] In one embodiment, one common source transistor (M7) in the second common source transistor pair is an ultra-low threshold voltage ULVT type NMOS transistor, and the other common source transistor (M8) in the second common source transistor pair is an ultra-low threshold voltage ULVT type PMOS transistor.

[0112] Specifically, in the complementary common source unit, transistors M7 and M8 are ULVT type, which can increase the static current, reduce the output impedance, and thus improve the bandwidth performance. It should be noted that transistors of different threshold voltage types are selective, and this application does not limit this.

[0113] Furthermore, the embodiment of the present application can also adjust the size of the transistor in the complementary common source unit, thereby reducing the load impedance of the common source common gate tube (i.e., the common source common gate amplifier module), and then the auxiliary common source stage and the noise elimination stage can be simultaneously implemented with the complementary common source unit. For example, taking the complementary common source unit as an auxiliary common source stage circuit as an example, the load impedance of the common source common gate tube is reduced by a small-sized auxiliary common source stage circuit (small size can refer to the small W and L of the transistor), ensuring that its size is in the order of 1 / gm, thereby reducing the equivalent capacitance at the input node (first stage input end) and increasing the operating frequency of the circuit. At the same time, the auxiliary common source stage circuit can have a smaller gate length and gate width to avoid introducing additional parasitic capacitance.

[0114] It can be understood that since the present application adopts a common source and common gate structure, the Miller effect of the gate-drain capacitance of the common source amplifier is suppressed, and smaller transistors are used to avoid excessive parasitic capacitance, thereby having a higher 3dB bandwidth.

[0115] Regarding the transconductance amplification module in the second-stage amplification circuit in the embodiment of the present application, a transconductance unit of a complementary common source stage structure can be used, and transistors with different threshold voltages can be connected in parallel to achieve the effect of eliminating high-order nonlinearity. In one embodiment, the transconductance amplification module may include a complementary common source amplification unit for applying a transconductance gain to a voltage signal to generate a current signal; wherein the complementary common source amplification unit is used to complete linearity adjustment by derivative superposition.

[0116] Specifically, in an embodiment of the present application, the first-stage output signal may include a voltage signal, and the second-stage output signal may include a current signal, wherein the complementary common-source amplifier unit may be used to apply a transconductance gain to the voltage signal to generate a current signal, that is, the second-stage amplifier circuit in the embodiment of the present application can achieve a certain transconductance gain; optionally, the second-stage amplifier circuit in the embodiment of the present application may also be referred to as a second-stage transconductance amplifier.

[0117] In some examples, the complementary common-source amplifier unit can use complementary derivative superposition and other methods to achieve improved linearity, such as using derivative superposition to optimize nonlinear performance, or improving the input third-order intercept point of the amplifier by derivative elimination.

[0118] Exemplarily, the complementary common source amplifier unit may refer to a transconductance unit using a complementary common source stage structure; optionally, the complementary common source amplifier unit may be implemented using corresponding transistors. It is understood that the complementary common source amplifier unit may also be implemented in other forms, not limited to the forms mentioned in the above embodiments, as long as it can achieve the function of achieving a certain transconductance gain.

[0119] In the above-mentioned low-noise transconductance amplifier, a common-source and common-gate stage combined with an auxiliary common-source stage structure is used to expand the operating bandwidth, and transconductance enhancement technology is combined to improve the gain. The auxiliary common-source stage also provides a noise elimination effect to improve noise performance, and uses complementary derivative superposition and other methods to achieve improved linearity.

[0120] like Figure 7 As shown, a complementary common-source amplifier unit of an embodiment may include a third transistor (M9), a fourth transistor (M10), a fifth transistor (M11) and a sixth transistor (M12); wherein the gate of the third transistor (M9), the gate of the fourth transistor (M10), the gate of the fifth transistor (M11) and the gate of the sixth transistor (M12) are connected to the second-stage input terminal, and the drain of the third transistor (M9), the drain of the fourth transistor (M10), the drain of the fifth transistor (M11) and the drain of the sixth transistor (M12) are connected to the second-stage output terminal; the source of the third transistor (M9) and the source of the fifth transistor (M11) are used for grounding, and the source of the fourth transistor (M10) and the source of the sixth transistor (M12) are used for connecting to a power supply.

[0121] Specifically, the gate of the third transistor (M9), the gate of the fourth transistor (M10), the gate of the fifth transistor (M11), and the gate of the sixth transistor (M12) can be used as the second-stage input terminal, and the drain of the third transistor (M9), the drain of the fourth transistor (M10), the drain of the fifth transistor (M11), and the drain of the sixth transistor (M12) can be used as the second-stage output terminal. Among them, the source of the third transistor (M9) and the source of the fifth transistor (M11) are used for grounding, and the source of the fourth transistor (M10) and the source of the sixth transistor (M12) are used for access to the power supply, so no additional bias control voltage is required.

[0122] Based on the complementary common-source amplifier unit, the embodiment of the present application can use complementary derivative superposition and other methods to improve linearity, and adopt multiple methods to suppress high-order nonlinear terms.

[0123] In an exemplary embodiment, the third transistor (M9) is an NMOS tube of a universal threshold voltage RVT type, the fourth transistor (M10) is a PMOS tube of a universal threshold voltage RVT type, the fifth transistor (M11) is an NMOS tube of a high threshold voltage HVT type, and the sixth transistor (M12) is a PMOS tube of a high threshold voltage HVT type.

[0124] Specifically, in the second-stage amplifier circuit, in order to achieve the effect of derivative superposition, reduce power consumption and increase output impedance, RVT type transistors are selected for M9 and M10, and HVT type transistors are selected for M11 and M12. It should be noted that transistors of different threshold voltage types are selective, and these replacements will change the power consumption, bandwidth, and noise coefficient performance of the circuit, making it applicable to different scenarios.

[0125] In one embodiment, the width-to-length ratio of the fourth transistor (M10) and the width-to-length ratio of the third transistor (M9) are set according to a first preset ratio; the width-to-length ratio of the sixth transistor (M12) and the width-to-length ratio of the fifth transistor (M11) are set according to a second preset ratio.

[0126] Specifically, the first preset ratio and the second preset ratio can be set according to the requirements, and the present application has no limitation on this. In the embodiment of the present application, the size of the second stage amplifier circuit can be designed to be smaller to save power consumption, reduce parasitic capacitance, and achieve the functions of transconductance amplification and linearity adjustment.

[0127] For example, the ratio of the sizes of the transistors in the second-stage amplifier circuit can be fine-tuned to ensure that the high-order nonlinear transconductance g m " is fully suppressed. Regarding the size adjustment, taking the third transistor (M9) and the fifth transistor (M11) as NMOS transistors, and the fourth transistor (M10) and the sixth transistor (M12) as PMOS transistors as an example, the ratio of the width-to-length ratio of the PMOS transistor M10 to the NMOS transistor M9, and the ratio of the width-to-length ratio of the PMOS transistor M12 to the NMOS transistor M11 can be adjusted.

[0128] For the second stage amplifier circuit of the embodiment of the present application, since the resistor self-biasing structure is not adopted, a common mode feedback loop can be added to stabilize the output common mode point at a preset value (eg, VDD / 2). Figure 8 As shown, the complementary common-source amplifier unit of an embodiment may also include an error amplifier (U1), a third resistor (R5) and a fourth resistor (R4); wherein the positive end of the error amplifier (U1) is connected to the second-stage output end through the third resistor (R5), the negative end of the error amplifier (U1) is used to access the standard reference voltage (Vref), and the output end of the error amplifier (U1) is connected to the second-stage input end through the fourth resistor (R4).

[0129] Specifically, the output voltage of the second-stage output terminal can be connected to the positive terminal of the error amplifier (U1) through the third resistor (R5), the negative terminal of the error amplifier (U1) can be connected to the standard reference voltage (Vref), and the output terminal of the error amplifier (U1) can be connected to the second-stage input terminal through the fourth resistor (R4), thereby forming a common-mode feedback loop (also referred to as a common-mode feedback circuit).

[0130] For example, the error amplifier in the common-mode feedback circuit may be in the form of a five-transistor OTA (Operational Transconductance Amplifier), thereby saving power consumption.

[0131] In practical applications, the error amplifier can be DC coupled through a large resistor. In one embodiment, the resistance of the third resistor (R5) is greater than 10k ohms, and the resistance of the fourth resistor (R4) is greater than 10k ohms.

[0132] Specifically, the large resistor in the embodiment of the present application may refer to a resistor with a resistance value of 10k ohms or more. The third resistor (R5) and the fourth resistor (R4) may be large resistors, and the resistance value of the third resistor (R5) is greater than 10k ohms, and the resistance value of the fourth resistor (R4) is greater than 10k ohms, thereby forming a common-mode feedback loop.

[0133] The above-mentioned low-noise transconductance amplifier has the performance of high gain, high linearity and large bandwidth; wherein, with respect to high gain, since the embodiment of the present application adopts a common source and common gate structure and two-stage amplification, it has a higher transconductance gain. With respect to large bandwidth, since the embodiment of the present application adopts a common source and common gate structure, the Miller effect of the gate-drain capacitance of the common source stage amplifier is suppressed, and a smaller-sized transistor is used to avoid excessive parasitic capacitance, thereby having a higher 3dB bandwidth. With respect to low noise, since the embodiment of the present application adopts a noise elimination method, it has a lower noise coefficient. With respect to high linearity, since the embodiment of the present application adopts complementary NMOS / PMOS derivative elimination, different threshold voltage transistor derivative elimination and other methods, the high-order nonlinearity of the transconductance is suppressed, thereby having a higher third-order intercept point.

[0134] To further explain the present application, the present application is described in detail below through specific examples. Fig. 9 It is a simplified block diagram of a two-stage low-noise transconductance amplifier proposed in an embodiment of the present application, wherein Av may represent gain, Gm represents transconductance, and further, Gm1 represents a complementary common-source common-gate amplifier, and Gm2 represents a complementary common-source amplifier.

[0135] The following Fig.10Take the low noise transconductance amplifier as an example to explain it in detail. Fig.10 It is a specific circuit of a low-noise transconductance amplifier. The circuit has a two-stage structure, in which NMOS tubes M1, M2, M3, M7, PMOS tubes M4, M5, M6, M8, and resistors R1, R2, and R3 constitute the first stage of the circuit (first stage amplifier circuit); NMOS tubes M9, M11, PMOS tubes M10, M12, resistors R4, R5, and error amplifier constitute the second stage of the circuit (second stage amplifier circuit). In addition, Fig.10 The RVT in FIG. 1 represents a universal threshold voltage transistor, the ULVT represents an ultra-low threshold voltage transistor, and the HVT represents a high threshold voltage transistor.

[0136] Regarding the first-stage amplifier circuit, Gm1, Gm2 and feedback resistor R1 constitute a resistor feedback common source stage noise elimination structure, wherein Gm1 is a complementary common source common gate amplifier composed of NMOS tubes M1, M2 and PMOS tubes M4, M5, and NMOS tubes M3, PMOS tubes M6 and resistors R3, R2 form a transconductance enhancement structure for the common gate tubes (M2, M5); Gm2 is a complementary common source amplifier composed of NMOS tubes M7 and PMOS tubes M8. The embodiment of the present application abandons the traditional method of using an adder to sum voltages and uses current summing to save power consumption and voltage domains, that is, the drains of MOS tubes M7 and M8 are connected to the drains of MOS tubes M2 and M5.

[0137] Since the transconductance enhancement structure is to improve the equivalent transconductance of the common-gate transistor, the above transconductance enhancement structure can be added or deleted independently. It is temporarily not considered in the analysis to simplify the calculation. Among them, the input impedance (R in ) and gain (A V1 ) are:

[0138]

[0139] Among them, R out1 =g m2 r o2 r o1 / / g m5 r o5 r o4 / / r o7 / / r o8 ≈r o7 / / r o8 is the output impedance of the first stage amplifier, g mi express Fig.10 The transconductance of the transistor labeled i, r oi express Fig.10 The small signal output impedance of the transistor labeled i. m1,total =G m1 +Gm2 =g m1 +g m7 +g m4 +g m8 Represents the equivalent transconductance of the first-stage amplifier circuit.

[0140] In the traditional common-source amplifier structure, the equivalent capacitance at the input end is the input tube gate-source capacitance and the multiplied gate-drain capacitance (Miller effect). This capacitance and the input resistance form a pole, thereby limiting the bandwidth of the circuit. In response to this, the present application proposes to use a common-source common-gate structure to weaken the influence of the Miller effect on the circuit bandwidth. The load of the common-source tube becomes the input impedance of the common-gate stage, reducing the gain of the common-source tube, such as Fig.11 Shown on the left.

[0141] However, if Fig.11 As shown in the middle, when the load of the common source and common gate stage increases, the load impedance of the common source tube cannot be approximated as low resistance, and may even become high resistance, further increasing the Miller equivalent capacitance at the input end, deteriorating the bandwidth. The embodiment of the present application proposes to add a small-sized auxiliary common source stage circuit to reduce the load impedance of the common source and common gate tube, ensuring that its size is in the order of 1 / gm, thereby reducing the equivalent capacitance at the input node and increasing the operating frequency of the circuit, such as Fig.11 As shown on the right, the auxiliary common source stage and the noise elimination stage can be realized simultaneously with Gm2. For the transconductance enhancement structure, the load of the common source tube (taking the common source tube M1 as an example) becomes The Miller effect is further suppressed and the equivalent transconductance of the circuit is improved. At the same time, the noise elimination stage Gm2 also reduces the output impedance of the first stage amplifier circuit, avoiding the working bandwidth being limited by the output node of the first stage.

[0142] In actual process, the power supply voltage is generally only about 1V, which brings design difficulties to the complementary common source and common gate structure. In the embodiment of the present application, a low-threshold MOS tube is selected for the input common source tube, and a high-threshold voltage MOS tube is selected for the common gate tube. By adjusting the bias voltage, it is ensured that all MOS tubes work in the saturation region.

[0143] Furthermore, the second-stage amplifier circuit can use a transconductance unit with a complementary common-source structure, and use MOS tubes with different threshold voltages in parallel to achieve the effect of eliminating high-order nonlinearity. m2,total =g m9 +g m10 +g m11 +g m12 , and the equivalent transconductance of the overall circuit is:

[0144]

[0145] In a current-mode receiver, a low-noise transconductance amplifier is followed by a mixer and a baseband transimpedance amplifier, so its load impedance is often low. When the noise factor of the circuit is considered, its voltage gain can be obtained:

[0146]

[0147] Among them, R L is the load impedance. represents the output noise voltage of Rs, R1, Gm1, Gm2, Gm3, Gm4, Rs represents the source impedance, then when When , the noise of Gm1 module can be considered to be eliminated. At this time, the noise coefficient of the circuit is:

[0148]

[0149] When the noise cancellation condition is met and R in =R s In the case of , after simplification, we can get:

[0150]

[0151] In order to reduce the noise factor, Gm3 and Gm4 can be increased, or R1 can be increased, but it is necessary to adjust Gm1 and Gm2 at the same time to meet the matching and noise elimination conditions. Among them, increasing Gm3 and Gm4 can refer to increasing the equivalent transconductance of the transconductance unit Gm3 level (M9 and M10). It should be noted that Gm3 can refer to the transconductance unit composed of these two transistors, or it can refer to the performance indicator of the circuit-equivalent transconductance; what is increased here is the equivalent transconductance of the circuit. That is, "transconductance unit" refers to the two transistors themselves, and "equivalent transconductance" refers to the performance of these two transistors. In addition, increasing R1 can refer to increasing the resistance value of R1. Adjusting Gm1 and Gm2 at the same time can refer to adjusting the equivalent transconductance of these two transconductance units.

[0152] For the common source amplifier circuit, the small signal current is modeled by the second-order Taylor series, and the following results are obtained:

[0153]

[0154] Among them, g″ m It is the main component that limits the third-order intercept point, and its size is usually determined by the overdrive voltage and the width-to-length ratio. The main architecture of this application adopts a complementary common source stage to sum the current at the drain end of the transistor, and then the high-order terms of the transconductance in the total output current can be adjusted by controlling the threshold voltage and the gate bias voltage; and the transconductance change trends of NMOS and PMOS themselves are different, so the complementary structure is more conducive to the realization of derivative superposition.

[0155] The embodiment of the present application adopts the following two methods to suppress the high-order nonlinear term: ① Adjust the size of NMOS and PMOS in the complementary structure so that they have different change trends for transconductance; wherein, adjusting the size can refer to adjusting the ratio of the width-to-length ratio of PMOS to the width-to-length ratio of NMOS, that is, by adjusting the size ratio of NMOS and PMOS in the complementary structure, the high-order terms of transconductance have different change trends. ② Use transistors with different threshold voltages to sum small signal currents. The common-gate tube and Gm4 in Gm1 are both MOS tubes with high threshold voltages. By adjusting the width-to-length ratio, they can have different small signal transconductances under the same voltage bias. At the output node of the first stage, the high output resistance of the common-source common-gate tube will limit the voltage swing of the node, and the current summing method of Gm2 and Gm1 can not only achieve noise elimination, but also reduce the output resistance of the node. Through the combination of the above methods, the third-order intercept point of the circuit can be improved by more than 10dBm.

[0156] In the circuit structure of the embodiment of the present application, transistors with different threshold voltages are selected. On the one hand, the elimination of high-order conduction of transconductance is considered; on the other hand, the static power consumption and static operating point of the circuit are considered. In Gm1, the common source tubes M1 and M4 use RVT to ensure that their gate-source voltage is around VDD / 2, and the drain-source can be stable in the saturation region when it is around VDD / 4; M2 and M5 choose HVT to reduce power consumption as much as possible while eliminating high-order conduction of transconductance; M3 and M6 of the transconductance enhancement stage need to select transistors with lower threshold voltages due to their lower gate voltages to ensure that they work in the saturation region or subthreshold region. In Gm2, transistors M7 and M8 choose ULVT type to increase static current, reduce output impedance, and thus improve bandwidth performance. Furthermore, in the second-stage amplifier circuit, in order to achieve the effect of derivative superposition, reduce power consumption and increase output impedance, RVT type transistors are selected for M9 and M10, and HVT type transistors are selected for M11 and M12.

[0157] It should be noted that the transistors of different threshold voltage types in the embodiments of the present application are selective. For example, the common-gate transistors M2 and M5 can be replaced with ULVT types, and the bias voltage is adjusted so that they are still in the saturation region; the transconductance enhancement stages M3 and M6 can be replaced with RVT or HVT. These replacements will change the power consumption, bandwidth, and noise coefficient performance of the circuit, allowing it to be applied to different scenarios. This application provides one of the options, which increases power consumption in order to meet the 5G communication frequency band. Since the selection of different types of transistors only changes the trade-offs between their different performances, the circuit principles involved are the same, so it still falls within the scope of this application.

[0158] For the second-stage amplifier circuit in the embodiment of the present application, since the resistor self-biasing structure is not used, a common-mode feedback loop can be added to stabilize the output common-mode point at about VDD / 2. The error amplifier in the common-mode feedback circuit adopts a five-tube OTA form to save power consumption; and DC coupling is performed through a large resistor.

[0159] Combine the following Fig.10 The specific structure of the two-stage amplifier circuit in the present application is described, wherein the first-stage amplifier circuit realizes input matching and performs preliminary amplification on the input voltage, and the second-stage amplifier circuit realizes a certain transconductance gain.

[0160] Among them, regarding the first-stage amplifier circuit, the input end (first-stage input end) Vin of the first-stage amplifier circuit is the gate of the NMOS tubes M1, M7 and the PMOS tubes M4, M8, the source of the NMOS input tubes M1, M7 is connected to the ground, and the source of the PMOS input tubes M4, M8 is connected to the power supply. The drains of the NMOS tube M1 and the PMOS tube M4 are respectively connected to the source of the NMOS tube M2 and the PMOS tube M5, forming a common source and common gate amplifier structure. The NMOS tube M3 and the resistor R2 constitute the transconductance enhancement structure of the NMOS tube M2, wherein the gate of the NMOS tube M3 is connected to the source of the NMOS tube M2, and the drain of M3 is connected to the gate of M2; similarly, the PMOS tube M6 and the resistor R3 constitute the transconductance enhancement structure of the PMOS tube M5, wherein the gate of the PMOS tube M6 is connected to the source of the PMOS tube M4, and the drain of M6 is connected to the gate of M5. The output end of the first stage amplifier circuit (first stage output end) is the drain of the NMOS tubes M2, M7 and the PMOS tubes M5, M8. The feedback resistor R1 is connected between the first stage input end and the first stage output end.

[0161] Regarding the second-stage amplifier circuit, the second-stage amplifier circuit includes NMOS tubes M9, M11 and PMOS tubes M10, M12. The input end (second-stage input end) of the second-stage amplifier circuit is the gate of the NMOS tubes M9, M11, and the PMOS tubes M10, M12, and the output end is the drain of the NMOS tubes M9, M11 and the PMOS tubes M10, M12. The source of the NMOS tubes M9 and M11 is connected to the ground, and the source of the PMOS tubes M10 and M12 is connected to the power supply, and no additional bias control voltage is required. The output voltage of the second-stage amplifier circuit is connected to the positive and negative ends of the error amplifier through a large resistor R5 and a standard reference voltage, respectively. The output of the error amplifier is connected to the input of the second stage through a large resistor R4 to form a common-mode feedback loop; wherein, the large resistor can refer to more than 10k ohms.

[0162] In the embodiment of the present application, the transconductance of transistors M1 and M4 and the size of feedback resistor R1 in the first-stage amplifier circuit can be designed according to input matching. At the beginning, it can be slightly larger than 50Ω, and then M7 and M8 are connected to optimize the transconductance and noise. The width-to-length ratio of the common-gate tubes M2 and M5 needs to take into account the over-drive voltage, and a suitable distribution is required to ensure that each MOS tube operates in the saturation region. It is generally believed that the common-gate tube does not provide transconductance, but its transconductance value itself will affect the size of the Miller effect of the common-source tubes M1 and M4, and thus affect the circuit bandwidth; at the same time, its over-drive voltage will affect the high-order nonlinear transconductance g of the first-stage amplifier. m ”, so it is necessary to select a suitable bias voltage. The bias voltage can be provided outside the chip to facilitate off-chip performance adjustment, or it can be generated inside the chip. The transconductance enhancement module is to adjust the equivalent transconductance of the NMOS tube M2 and the PMOS tube M5, but at the same time, its parasitic capacitance needs to be considered. The second-stage amplifier circuit mainly plays the role of transconductance amplification and linearity adjustment. The size can be designed to be smaller to save power consumption and reduce parasitic capacitance. At the same time, it is necessary to fine-tune the ratio of its size (for fine-tuning, please refer to the relevant description of transistors M9, M10, M11 and M12 in the previous text, which will not be repeated here) to ensure that the high-order nonlinear transconductance g m "Fully suppressed.

[0163] Based on the embodiment of the present application, since no inductor and too many DC blocking capacitors are used, the layout area is small. Parasitic parameters are extracted from the layout, and post-simulation is performed at tt process angle and 55°C. The S parameter post-simulation results of the low-noise transconductance amplifier in the embodiment of the present application are as follows: Fig.12 As shown in the figure (circuit post-simulation results: S21 and S11), the load impedance is 40 ohms, which is used to simulate the impedance of the rear stage in the actual current mode receiver. It can be seen that the 3dB bandwidth of the circuit is as high as 8.1GHz, and the input matching within the working frequency band is good, and S11 is less than -10dB. The noise coefficient of the low noise transconductance amplifier is simulated as follows Fig.13 As shown (circuit post-simulation results: NF), it is 2-2.6dB in the operating frequency range.

[0164] Compared with the traditional solution, the present application can achieve higher bandwidth and lower noise figure without using inductors. For example, the performance values ​​of the embodiments of the present application may include: process (nm) is 22, frequency range (GHz) is 0.61-8.14, voltage gain (dB) is 20.9, minimum noise figure (dB) is 2, IIP3 (dBm) is 10.8@4GHz, supply voltage (V) is 0.9, power consumption (mW) is 4.6, number of inductors (pieces) is 0, active area (mm 2) is 0.0079w, the figure of merit 1 (FOM1) is 31.88, the figure of merit 2 (FOM2) is 11.28, and the figure of merit 3 (FOM3) is 53, where the definitions of the figures of merit involved are as follows:

[0165]

[0166] FOM refers to Figure of merit; log refers to logarithmic operation; BW [GHz] refers to bandwidth (GHz refers to the unit); Gain [abs] refers to voltage gain, and abs means the format should be linear rather than logarithmic; P DC Refers to direct power (power consumption), the unit is mW (milliwatt); F min It refers to the lowest noise figure; IIP3[mW] refers to the input third-level intercept point (in mW); A refers to the chip area (in square millimeters).

[0167] The low-noise transconductance amplifier of the embodiment of the present application has high gain performance, because the present application adopts a common source and common gate structure and two-stage amplification, and thus can have a higher transconductance gain. It has a large bandwidth performance, because the present application adopts a common source and common gate structure, suppresses the Miller effect of the gate-drain capacitance of the common source amplifier, and adopts a smaller size transistor to avoid excessive parasitic capacitance, and thus can have a higher 3dB bandwidth. It has low noise performance, because the noise elimination method is adopted, and thus has a lower noise coefficient. It has high linearity performance, because the present application adopts complementary NMOS / PMOS derivative elimination, different threshold voltage transistor derivative elimination and other methods, so that the high-order nonlinearity of the transconductance is suppressed, and thus has a higher third-order intercept point.

[0168] The low-noise transconductance amplifier can be applied to electronic devices such as chips, receivers, or similar devices.

[0169] In one embodiment, the present application provides a chip, the chip comprising the low-noise transconductance amplifier as described above.

[0170] In one embodiment, the present application provides a receiver, including an antenna and the low-noise transconductance amplifier as described above.

[0171] In one embodiment, the present application provides an electronic device which may include the above-mentioned receiver.

[0172] Optionally, the electronic device may be a radio frequency device such as a mobile phone, a router, etc. Of course, the electronic device may also be other devices, which is not limited in the embodiments of the present application.

[0173] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0174] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features in the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0175] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A low noise transconductance amplifier, characterized in that: It includes a first-stage amplifier circuit and a second-stage amplifier circuit, wherein: The first-stage amplifier circuit includes a first-stage input terminal, a common-source and common-gate amplifier module, a common-source module, a feedback resistor and a first-stage output terminal; the feedback resistor is connected between the first-stage input terminal and the first-stage output terminal; the first-stage input terminal is used to receive an input signal, the common-source and common-gate amplifier module is used to perform input matching and amplification processing on the input signal, and output the obtained first-stage output signal through the first-stage output terminal; the common-source module is used to eliminate noise on the input signal; The second-stage amplifier circuit includes a second-stage input terminal, a transconductance amplifier module, and a second-stage output terminal connected in sequence, the second-stage input terminal is used to receive the first-stage output signal, the transconductance amplifier module is used to perform transconductance amplification and linearity adjustment on the first-stage output signal, and the obtained second-stage output signal is output through the second-stage output terminal.

2. The low noise transconductance amplifier according to claim 1, characterized in that: The cascode amplification module comprises a complementary cascode amplification unit; The complementary cascode amplification unit comprises a first cascode transistor pair and a first cascode transistor pair; The gate electrodes of the two common source transistors in the first common source transistor pair are connected to the first stage input terminal, the source electrode of one common source transistor in the first common source transistor pair is used for grounding, the source electrode of the other common source transistor in the first common source transistor pair is used for connecting to a power supply, and the drain electrodes of the two common source transistors in the first common source transistor pair are respectively connected to the sources of the two common gate transistors in the first common gate transistor pair; The gate of one common-gate tube in the first common-gate tube pair is used to access a power supply, the gate of the other common-gate tube in the first common-gate tube pair is used to be grounded, and the drains of the two common-gate tubes in the first common-gate tube pair are connected to the first-stage output end.

3. The low noise transconductance amplifier according to claim 2, characterized in that: The two common-gate transistors in the first common-gate transistor pair are MOS devices, and the two common-source transistors in the first common-source transistor pair are MOS devices.

4. The low noise transconductance amplifier according to claim 3, characterized in that: One of the common-gate transistors in the first common-gate transistor pair is an NMOS transistor of a high threshold voltage HVT type, and the other common-gate transistor in the first common-gate transistor pair is a PMOS transistor of a high threshold voltage HVT type; One common source transistor in the first common source transistor pair is an NMOS transistor of a universal threshold voltage RVT type, and the other common source transistor in the first common source transistor pair is a PMOS transistor of a universal threshold voltage RVT type.

5. The low noise transconductance amplifier according to claim 2, characterized in that: The width-to-length ratio of the two common-gate tubes in the first common-gate tube pair is configured based on the over-driving voltage.

6. The low noise transconductance amplifier according to claim 2, characterized in that: The first-stage amplifier circuit also includes a transconductance enhancement module, which is used to improve the equivalent transconductance of the complementary cascode amplifier unit.

7. The low noise transconductance amplifier according to claim 6, characterized in that: The transconductance enhancement module includes a first transistor, a second transistor, a first resistor and a second resistor; The gate of the first transistor is connected to the source of one of the first common-gate transistors, the drain of the first transistor is connected to the gate of one of the first common-gate transistors, and the source of the first transistor is grounded; one end of the first resistor is connected between the drain of the first transistor and the gate of one of the first common-gate transistors, and the other end of the first resistor is connected to a power supply; The gate of the second transistor is connected to the source of the other common-gate tube in the first common-gate tube pair, the drain of the second transistor is connected to the gate of the other common-gate tube in the first common-gate tube pair, and the source of the second transistor is used to access a power supply; one end of the second resistor is connected between the drain of the second transistor and the gate of the other common-gate tube in the first common-gate tube pair, and the other end of the second resistor is used for grounding.

8. The low noise transconductance amplifier according to claim 7, characterized in that: The first transistor is an ultra-low threshold voltage ULVT type NMOS transistor, and the second transistor is an ultra-low threshold voltage ULVT type PMOS transistor.

9. The low noise transconductance amplifier according to claim 2, characterized in that: The common source module includes a complementary common source unit, which is used to adjust the impedance of the complementary common source and common gate amplifier unit.

10. The low noise transconductance amplifier according to claim 9, characterized in that: The complementary common source unit comprises a second common source tube pair; The gates of the two common source tubes in the second common source tube pair are connected to the first stage input terminal, the drains of the two common source tubes in the second common source tube pair are connected to the first stage output terminal, the source of one common source tube in the second common source tube pair is used for grounding, and the source of the other common source tube in the second common source tube pair is used for connecting to a power supply.

11. The low noise transconductance amplifier according to claim 9, characterized in that: One common source transistor in the second common source transistor pair is an ultra-low threshold voltage ULVT type NMOS transistor, and the other common source transistor in the second common source transistor pair is an ultra-low threshold voltage ULVT type PMOS transistor.

12. The low noise transconductance amplifier according to claim 1, characterized in that: The first-stage output signal includes a voltage signal, and the second-stage output signal includes a current signal; The transconductance amplification module includes a complementary common-source amplification unit, which is used to apply a transconductance gain to the voltage signal to generate the current signal; wherein the complementary common-source amplification unit is used to complete the linearity adjustment by derivative superposition.

13. The low noise transconductance amplifier according to claim 12, characterized in that: The complementary common-source amplifying unit includes a third transistor, a fourth transistor, a fifth transistor and a sixth transistor; The gate of the third transistor, the gate of the fourth transistor, the gate of the fifth transistor and the gate of the sixth transistor are connected to the second-stage input terminal, and the drain of the third transistor, the drain of the fourth transistor, the drain of the fifth transistor and the drain of the sixth transistor are connected to the second-stage output terminal; the source of the third transistor and the source of the fifth transistor are used for grounding, and the source of the fourth transistor and the source of the sixth transistor are used for connecting to a power supply.

14. The low noise transconductance amplifier according to claim 13, characterized in that: The third transistor is an NMOS tube of a general threshold voltage RVT type, the fourth transistor is a PMOS tube of a general threshold voltage RVT type, the fifth transistor is an NMOS tube of a high threshold voltage HVT type, and the sixth transistor is a PMOS tube of a high threshold voltage HVT type.

15. The low noise transconductance amplifier according to claim 13, characterized in that: The width-to-length ratio of the fourth transistor and the width-to-length ratio of the third transistor are set according to a first preset ratio; the width-to-length ratio of the sixth transistor and the width-to-length ratio of the fifth transistor are set according to a second preset ratio.

16. The low noise transconductance amplifier according to claim 13, characterized in that: The complementary common-source amplification unit further includes an error amplifier, a third resistor and a fourth resistor; The positive end of the error amplifier is connected to the second-stage output end through the third resistor, the negative end of the error amplifier is used to access the standard reference voltage, and the output end of the error amplifier is connected to the second-stage input end through the fourth resistor.

17. The low noise transconductance amplifier according to claim 16, characterized in that: The resistance value of the third resistor is greater than 10k ohms, and the resistance value of the fourth resistor is greater than 10k ohms.

18. A chip, characterized in that: The chip comprises the low-noise transconductance amplifier according to any one of claims 1 to 17.

19. A receiver, characterized in that: It comprises an antenna and a low-noise transconductance amplifier as claimed in any one of claims 1 to 17.

20. An electronic device, characterized in that: It comprises the low-noise transconductance amplifier according to any one of claims 1 to 17, or the chip according to claim 18, or the receiver according to claim 19.

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