Superconducting quantum chip packaging structure and flip-chip packaging method of superconducting quantum chip

Abstract

The present invention provides a superconducting quantum chip packaging structure and a flip-chip packaging method for a superconducting quantum chip. By using SU-8 photoresist with characteristics such as high resolution and high aspect ratio, the photoresist is used as a supporting structure to achieve flip-chip packaging of the superconducting quantum chip. Compared with the prior art, the flip-chip packaging method can realize personalized design of the supporting structure according to different circuit wiring layer structures, which is more conducive to the large-scale integration of superconducting quantum chips, and does not require manual operation during operation. It has a high degree of mechanization, can significantly improve the flip-chip packaging efficiency of the superconducting quantum chip, thereby reducing the manufacturing cost of the superconducting quantum chip, and does not require space for flip-chip operation around the device when flip-chip packaging is performed, so that a process for flip-chip packaging on a superconducting quantum chip of 4*4mm or smaller can be achieved, which is more conducive to the large-scale integration of superconducting quantum chips.

Description

Technical Field

[0001] The present invention relates to the technical field of microelectronic component manufacturing, and in particular to a superconducting quantum chip packaging structure and a flip-chip packaging method for the superconducting quantum chip. Background Art

[0002] In the field of microelectronics manufacturing, SU-8 photoresist has become an important micro-nano processing material because of its outstanding characteristics. SU-8 photoresist is a negative photoresist with high contrast based on epoxy resin materials. It can overcome the problem of insufficient aspect ratio of conventional photoresists adopting ultraviolet lithography, and its unique molecular structure makes its light absorption very low within the scope of near-ultraviolet light (365nm-400nm), making the exposure amount obtained by the entire photoresist layer uniform. SU-8 photoresist can undergo a cross-linking reaction after being subjected to ultraviolet radiation, thereby obtaining required micron-scale patterns. The above-mentioned excellent performance of SU-8 photoresist has made it gradually being applied to fields such as micro-electromechanical systems (MEMS), chip packaging and micro-machining. At present, directly adopting SU-8 photoresist to prepare microstructures and micro-components with high aspect ratio has become a new technology in the field of micro-machining.

[0003] However, while SU-8 photoresist has a wide range of applications in the MEMS field, its use in flip-chip packaging technology for superconducting quantum chips is relatively rare. Currently, only the solution proposed by the University of Chicago team can achieve non-electrical flip-chip packaging based on SU-8 photoresist. However, its process is mostly manual, simply using SU-8 photoresist to create a "fence" structure on the chip, and requires manual dispensing, which has poor stability and cannot achieve a high level of integration. In addition, this solution also requires a gap of at least 4mm around the device to facilitate the flip-chip operation. Therefore, it is not suitable for the manufacture of small-sized, high-precision superconducting quantum chips.

[0004] It should be noted that the above technical background is merely provided to provide a clear and complete description of the technical solutions of this application and to facilitate understanding by those skilled in the art. Simply because these solutions are described in the background technology section of this application, it should not be assumed that the above technical solutions are well known to those skilled in the art. Summary of the Invention

[0005] In view of the above-mentioned shortcomings of the prior art, the object of the present invention is to provide a superconducting quantum chip packaging structure and a flip-chip packaging method for a superconducting quantum chip, which are used to solve the problems faced in the prior art of using SU-8 photoresist for flip-chip packaging of superconducting quantum chips, such as low mechanization, poor repeatability, and inability to achieve a high degree of integration. At the same time, the prior art of using SU-8 photoresist to implement flip-chip packaging of superconducting quantum chips is not suitable for the manufacture of small-sized, high-precision superconducting quantum chips.

[0006] To achieve the above and other related objectives, a method for flip-chip packaging of a superconducting quantum chip comprises the following steps:

[0007] A semiconductor wafer is provided, comprising a first surface and a second surface disposed opposite to each other, wherein a circuit wiring layer is formed on the first surface of the semiconductor wafer;

[0008] coating a negative photoresist on the first surface of the semiconductor wafer to form a first photoresist layer;

[0009] exposing and developing the first photoresist layer to form a support structure;

[0010] Re-coating a negative photoresist on the support structure and other areas without a circuit wiring layer to form a second photoresist layer and slicing the semiconductor wafer to obtain a superconducting quantum chip;

[0011] The second chip is placed on the superconducting quantum chip to achieve flip-chip packaging of the superconducting quantum chip.

[0012] Optionally, before exposing and developing the first photoresist layer, a step of making a pattern mask is further included, and the shape of the pattern mask should be adapted to different types of superconducting quantum chips.

[0013] Optionally, the steps of exposing and developing the first photoresist layer to form a support structure include: performing a pre-bake treatment on the first photoresist layer, and then performing an exposure treatment to divide the first photoresist layer into an exposure area and a non-exposure area, baking the first photoresist layer after the exposure treatment to cause a cross-linking reaction in the photoresist material in the exposure area, and performing a development operation on the semiconductor wafer to obtain a support structure corresponding to the exposure area.

[0014] Optionally, the development operation includes at least the following steps: first, the semiconductor wafer is immersed in a developer for the first time, then the developer is replaced and the semiconductor wafer is immersed for a second time, then the semiconductor wafer is rinsed with deionized water and immersed in isopropyl alcohol for a set time, and finally the semiconductor wafer is placed in a nitrogen environment for surface drying.

[0015] Optionally, the thickness of the first photoresist layer is at least 10 microns.

[0016] Optionally, the second photoresist layer is thicker than the first photoresist layer.

[0017] Optionally, the first photoresist layer, the second photoresist layer and the support structure are made of the same material and are all SU-8 photoresist.

[0018] Optionally, bonding the second chip to the superconducting quantum chip includes: using a robotic arm to absorb the superconducting quantum chip and the second chip and aligning and leveling them, then heating the robotic arm to a first temperature so that the support structure softens appropriately, then continuing to heat the robotic arm to a second temperature, applying pressure to the superconducting quantum chip and the second chip and maintaining it for a fixed time to bond the superconducting quantum chip and the second chip, and after bonding the second chip to the superconducting quantum chip, removing the bonding pressure and continuing to heat the robotic arm to a third temperature and maintaining it for a fixed time.

[0019] Optionally, the second chip is a control chip.

[0020] The present invention also provides a superconducting quantum chip packaging structure, which is obtained according to any of the above-mentioned flip-chip packaging methods for superconducting quantum chips.

[0021] As described above, the superconducting quantum chip packaging structure and the flip-chip packaging method of the superconducting quantum chip of the present invention have the following advantages compared to the prior art: the flip-chip packaging method utilizes the high resolution and high aspect ratio characteristics of SU-8 photoresist to achieve customization of the required flip-chip structure on a chip size of 4*4mm or smaller, and the method does not require manual operation, and can achieve high-precision superconducting quantum chip manufacturing. The technical solution has a simple operating process and a high degree of mechanization, which can significantly improve the packaging efficiency of the superconducting quantum chip flip chip and reduce the manufacturing cost of the superconducting quantum chip. It can also realize personalized design of the support structure according to different circuit wiring layer structures, which is more conducive to the large-scale integration of superconducting quantum chips. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 A process flow chart showing a flip-chip packaging method for a superconducting quantum chip provided by an embodiment of the present invention is shown.

[0023] Figure 2 Shown is a schematic diagram of the cross-sectional structure of a semiconductor wafer provided in the flip-chip packaging method of the present invention.

[0024] Figure 3 It is a schematic diagram showing the cross-sectional structure of the first photoresist layer formed in the flip-chip packaging method of the present invention.

[0025] Figure 4 It shows a schematic diagram of the structure after placing the pattern mask in the flip chip packaging method of the present invention.

[0026] Figure 5 It shows a schematic cross-sectional structure diagram after exposure and development in the flip-chip packaging method of the present invention.

[0027] Figure 6 It shows a schematic cross-sectional structure diagram of the chip after bonding in the flip-chip packaging method of the present invention.

[0028] Figure 7 Shown is the pressure and temperature control curve during flip-chip bonding of the present invention.

[0029] Component number description

[0030] 101. Semiconductor wafer; 102. Circuit wiring layer; 103. First photoresist layer; 104. Pattern mask; 105. Support structure; 106. Superconducting quantum chip; 107. Second chip; S1 to S5. Steps. DETAILED DESCRIPTION

[0031] The following describes the implementation of the present invention through specific embodiments. People skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification.

[0032] It should be noted that the illustrations provided in this embodiment are only used to schematically illustrate the basic concept of the present invention. Therefore, the illustrations only show components related to the present invention and are not drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component can be changed at will, and the component layout type may also be more complicated.

[0033] See also Figures 1 to 7 . It should be noted that the structures, proportions, sizes, etc. illustrated in the drawings of this specification are only used to match the contents disclosed in the specification for people familiar with this technology to understand and read, and are not used to limit the limiting conditions for the implementation of the present invention. Therefore, they have no substantive technical significance. Any modification of the structure, change in the proportional relationship or adjustment of the size should still fall within the scope of the technical content disclosed by the present invention without affecting the efficacy and purpose that can be achieved by the present invention. At the same time, the terms such as "upper", "lower", "left", "right", "middle", "first", "second", etc. quoted in this specification are only for the convenience of description, and are not used to limit the scope of the implementation of the present invention. Changes or adjustments in their relative relationships should also be regarded as the scope of the implementation of the present invention without substantially changing the technical content.

[0034] The embodiment of the present invention provides a flip-chip packaging method for a superconducting quantum chip, such as Figure 1 As shown, it is a process flow chart of the flip chip packaging method, which includes the following steps:

[0035] S1: providing a semiconductor wafer, comprising a first surface and a second surface opposite to each other, wherein a circuit wiring layer is formed on the first surface of the semiconductor wafer;

[0036] S2: coating a negative photoresist on the first surface of the semiconductor wafer to form a first photoresist layer;

[0037] S3: exposing and developing the first photoresist layer to form a support structure;

[0038] S4: coating the support structure and other areas without circuit wiring layers with a negative photoresist to form a second photoresist layer and slicing the semiconductor wafer to obtain a superconducting quantum chip;

[0039] S5: Bonding the second chip to the superconducting quantum chip, thereby achieving flip-chip packaging of the superconducting quantum chip.

[0040] The following is a further introduction to the flip-chip packaging method of the superconducting quantum chip with reference to the accompanying drawings, as follows:

[0041] In step S1, see Figure 1 and Figure 2 , a semiconductor wafer 101 is provided, comprising a first surface 1011 and a second surface 1012 arranged opposite to each other, wherein a circuit wiring layer 102 is formed on the first surface 1011 of the semiconductor wafer.

[0042] Specifically, such as Figure 1 and Figure 2 FIG. 1 is a schematic cross-sectional view of a semiconductor wafer 101. The semiconductor wafer 101 includes several chip regions and a circuit wiring layer 102 located within the chip regions. Prior to performing circuit wiring on the provided semiconductor wafer 101, it undergoes inspection, including visual inspection, electrical performance inspection, flatness inspection, and size inspection, to ensure that the quality of the semiconductor wafer 101 meets the requirements of subsequent processing. The provided semiconductor wafer 101 can be made of silicon or other semiconductor materials using existing technologies.

[0043] In step S2, see Figure 1 and Figure 3 A negative photoresist is coated on the first surface of the semiconductor wafer 101 to form a first photoresist layer 103 .

[0044] The photoresist provided in the embodiment of the present invention can be SU-8 photoresist. Specifically, when forming the first photoresist layer 103 on the semiconductor wafer 101, the semiconductor wafer 101 after inspection and processing can be placed on a spin coater carrier and its surface can be blown clean using a nitrogen gun. Then, the vacuum system is turned on to allow the semiconductor wafer 101 to be adsorbed and fixed to the spin coater carrier. A rubber-tipped dropper is used to drop an appropriate amount of photoresist material onto the first side of the semiconductor wafer on which the circuit wiring layer is prepared. Here, taking a two-inch wafer as an example, the spin coater is started and the spin coater is operated at a speed of 3000 rpm to form the first photoresist layer 103 on the first side of the semiconductor wafer 101. The thickness of the first photoresist layer 103 finally formed is not less than 10 microns. Of course, when the size of the semiconductor wafer 101 changes, the speed of the spin coater and the amount of photoresist can be appropriately adjusted to adjust the thickness of the first photoresist layer 103.

[0045] In step S3, see Figure 1 、 Figure 4 and Figure 5 , exposing and developing the first photoresist layer 103 to form a support structure 105.

[0046] As an example, before exposing and developing the first photoresist layer 103, a step of making a pattern mask 104 is also included, and the shape of the pattern mask 104 must be adapted to different types of superconducting quantum chips. In this embodiment, before exposing and developing the first photoresist layer 103, since the circuit wiring layer 102 structures on different types of superconducting quantum chips are different, it is also necessary to make pattern masks 104 with different patterns according to the circuit wiring layers 102 with different structures formed on the semiconductor wafer 101. Figure 4 As shown, the pattern mask 104 can cover the circuit wiring layer 102 on the semiconductor wafer 101, thereby exposing the blank area on the first side of the semiconductor wafer 101 without the circuit wiring layer 102. And the pattern mask 104 can be reused, thereby reducing the manufacturing cost of the superconducting quantum chip. The steps of exposing and developing the first photoresist layer 103 to form the support structure 105 provided in the embodiment of the present invention include: performing a pre-baking treatment on the first photoresist layer 103, and then performing an exposure treatment to divide the first photoresist layer 103 into an exposure area and a non-exposure area, baking the first photoresist layer 103 after the exposure treatment to cause the photoresist material in the exposure area to undergo a cross-linking reaction, and performing a development operation on the semiconductor wafer 101 to obtain the support structure 105 corresponding to the exposure area.

[0047] In this embodiment, after the photoresist is evenly coated on the semiconductor wafer 101, the semiconductor wafer 101 needs to be placed in a drying device with a base temperature of 75°C for pre-baking treatment. The first drying time is set to 3 minutes. After the first drying is completed, the drying equipment is ramped up to 110°C, and the drying time is set to 7 minutes, so as to remove moisture and part of the solvent in the first photoresist layer 103.

[0048] After placing the pattern mask 104, the first photoresist layer 103 is exposed using an ultraviolet lithography machine. The pattern mask can divide the first photoresist layer 103 into an exposure area and a non-exposure area. The semiconductor wafer 101 is developed so that the first photoresist layer 103 corresponding to the exposure area can be retained to form the support structure 104. Specifically, in this embodiment, the ultraviolet lithography machine used is a SUSS MA6 ultraviolet lithography machine, and the exposure dose of the exposure process is at least 220mJ / cm 2 ; And the first photoresist layer 103 after the exposure treatment is baked, and the baking time is at least 6 seconds, so that the photoresist material in the exposed area fully produces a cross-linking reaction. Figure 5 As shown, a developing solution is then used to develop the semiconductor wafer 101 , so that the first photoresist layer 103 corresponding to the exposed area can be retained to form a support structure 104 .

[0049] In another embodiment, the development operation includes at least the following steps: first, the semiconductor wafer 101 is immersed in a developer for a first time, then the developer is replaced and the semiconductor wafer 101 is immersed for a second time, then it is rinsed with deionized water and immersed in isopropyl alcohol for a set time, and finally the semiconductor wafer 101 is placed in a nitrogen environment for surface drying.

[0050] Specifically, after removing the pattern mask, the semiconductor wafer 101 after the exposure process is placed in a developer for immersion, the type of developer is JFX-PMA SU8 photoresist developer, and the immersion time is not less than 2 minutes. Then, a new developer is replaced for a second immersion development, and the second immersion time is not less than 30 seconds. Then, the semiconductor wafer 101 is rinsed with deionized water and immersed again with an isopropyl alcohol solution for a immersion time of not less than 20 seconds. Finally, the semiconductor wafer 101 is placed in a nitrogen environment for surface drying treatment, so that the first photoresist layer 103 corresponding to the exposure area can be retained to form a support structure 104.

[0051] In step S4, see Figure 1, negative photoresist is again coated on the support structure 104 and other areas without circuit wiring layers to form a second photoresist layer (not shown) and the semiconductor wafer 101 is sliced ​​to obtain superconducting quantum chips 106 .

[0052] In the production process of chip, it is also necessary to put semiconductor wafer 101 into dicing and cutting, thereby form small-sized chip.But in the process that semiconductor wafer 101 is cut, may produce debris thereby chip is damaged, thereby reduce production yield.Therefore, in order to prevent above-mentioned damage generation, the first side of semiconductor wafer 101 is coated with negative photoresist again to form the second photoresist layer, the second photoresist layer is used as protective adhesive layer, and the step of coating the second photoresist layer is identical with the step of forming the first photoresist layer 103, and does not repeat them here.Because the first photoresist layer 103 uses SU-8 photoresist, in order to guarantee that in the process of subsequent removal of photoresist, support structure is not damaged, the photoresist type that the second photoresist layer here uses is identical with the first photoresist layer 103, and the thickness of the second photoresist layer is greater than the thickness of the first photoresist layer 103, thereby realizes the protection to semiconductor wafer 101 and circuit wiring layer 102. After applying the second photoresist layer, the second photoresist layer is baked to solidify the photoresist, thereby facilitating subsequent scribing and cutting operations. The developer used to remove the second photoresist layer is the same as that used to develop the first photoresist layer 103. Since the thickness of the second photoresist layer is greater than that of the first photoresist layer 103, the soaking time is extended to ensure that the protective rubber layer can be completely removed.

[0053] In step S5, see Figure 1 and Figure 6 , bonding the second chip 107 to the superconducting quantum chip 106 , thereby realizing flip-chip packaging of the superconducting quantum chip.

[0054] After the semiconductor wafer is sliced ​​and cut to form a small-sized superconducting quantum chip 106, the superconducting quantum chip 106 needs to be flip-chip bonded to the second chip 107. The steps of flip-chip bonding are as follows: use a robotic arm to adsorb the superconducting quantum chip 106 and the second chip 107. Use a microscope, laser leveler and other tools to level it, then heat the robotic arm to a first temperature so that the support structure 105 softens appropriately. After the temperature reaches the desired temperature, apply a certain pressure and continue to heat it to the second temperature and maintain it for a fixed time to achieve the bonding of the superconducting quantum chip 106 and the second chip 107. After the bonding is completed, remove the bonding pressure and continue to heat it to the third temperature and maintain it for a fixed time. Figure 7 As shown, it shows the pressure and temperature control curve during flip-chip bonding. Figure 7The green curve in the figure represents the change in the pressure applied by the FC-150 device's robotic arm to the superconducting quantum chip 106 and the second chip 107 over time during the bonding process. Figure 7 The yellow and red curves in Figure 7 ) represent the temperature variation curves of the superconducting quantum chip 106 and the second chip 107 over time during the bonding and process respectively; Figure 7 It can be seen that by applying bonding pressure to the superconducting quantum chip 106 and the second chip 107 while heating them, and then removing the bonding pressure and heating them again for a period of time after the initial bonding is completed, the mechanical strength of the flip-chip bonding structure can be increased.

[0055] Specifically, in this embodiment, the flip-chip bonding equipment used is an FC150 PLATINUM multifunctional flip-chip bonder. Since the temperature resistance of SU-8 photoresist is approximately 200°C, the parameters during the heat treatment process for flip-chip packaging of superconducting quantum chip 106 and second chip 107 can be set to: a first temperature of not less than 100°C, a second temperature of not less than 130°C, and a holding time of not less than 3 minutes; a third temperature of not less than 140°C, and a holding time of not less than 2 minutes. Of course, in the actual bonding process, different heat treatment processes can also be selected based on the different heat resistances of different types of superconducting quantum chips, and this is not a limitation here.

[0056] In another embodiment, the second chip 107 is a control chip. The flip-chip packaging technology described above is used to achieve high-precision bonding between the superconducting quantum chip 106 and the control chip. A heat treatment process incorporated into the bonding process enhances the chip's thermal stability and mechanical strength, achieving electrical coupling and mechanical fixation between the superconducting quantum chip and the control chip.

[0057] Based on the same inventive concept, an embodiment of the present invention further provides a superconducting quantum chip packaging structure, including a structure prepared by the flip-chip packaging method of the superconducting quantum chip provided by any of the above embodiments.

[0058] In summary, the superconducting quantum chip packaging structure of the present invention and the flip-chip packaging method of superconducting quantum chip, compared to the prior art, the flip-chip packaging method can realize the personalized design of the supporting structure according to different circuit wiring layer structures, which is more conducive to the large-scale integration of superconducting quantum chips, and the operating process is simple, and the degree of mechanization is higher, which can significantly improve the superconducting quantum chip flip-chip packaging efficiency, and reduce the manufacturing cost of superconducting quantum chips. And due to the high resolution, high aspect ratio and other characteristics that SU-8 photoresist has, it is not necessary to reserve the space for flip-chip operation around the device when flip-chip packaging is carried out, and it is possible to realize the process of flip-chip packaging on a superconducting quantum chip of 4*4mm or smaller size, which is more conducive to the large-scale integration of superconducting quantum chips, and the method does not need to be manually operated, and can realize high-precision superconducting quantum chip manufacturing. Therefore, the present invention effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.

[0059] The above embodiments are merely illustrative of the principles and effects of the present invention and are not intended to limit the present invention. Anyone skilled in the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by one of ordinary skill in the art without departing from the spirit and technical principles disclosed herein are intended to be covered by the claims of the present invention.

Claims

1. A flip-chip packaging method for a superconducting quantum chip, characterized in that: The following steps are involved: A semiconductor wafer is provided, comprising a first surface and a second surface disposed opposite to each other, wherein a circuit wiring layer is formed on the first surface of the semiconductor wafer; coating a negative photoresist on the first surface of the semiconductor wafer to form a first photoresist layer; Performing a pre-baking process on the first photoresist layer and then performing an exposure process to divide the first photoresist layer into an exposure area and a non-exposure area, baking the first photoresist layer after the exposure process to cause a cross-linking reaction of the photoresist material in the exposure area, and performing a development operation on the semiconductor wafer to obtain a support structure corresponding to the exposure area; A negative photoresist is again applied to the support structure and other areas without a circuit wiring layer to form a second photoresist layer, and the semiconductor wafer is sliced ​​to obtain a superconducting quantum chip, wherein the first photoresist layer, the second photoresist layer, and the support structure are made of the same material, namely, SU-8 photoresist; The second chip is bonded to the superconducting quantum chip, thereby realizing flip-chip packaging of the superconducting quantum chip.

2. The flip chip packaging method according to claim 1, wherein: Before exposing and developing the first photoresist layer, a step of making a pattern mask is also included, and the shape of the pattern mask must be adapted to different types of superconducting quantum chips.

3. The flip chip packaging method according to claim 1, wherein: The development operation includes at least the following steps: first, the semiconductor wafer is immersed in a developer for a first time, then the developer is replaced and the semiconductor wafer is immersed for a second time, then it is rinsed with deionized water and immersed in isopropyl alcohol for a set time, and finally the semiconductor wafer is placed in a nitrogen environment for surface drying.

4. The flip chip packaging method according to claim 1, wherein: The thickness of the first photoresist layer is at least 10 microns.

5. The flip chip packaging method according to claim 1, wherein: The second photoresist layer is thicker than the first photoresist layer.

6. The flip chip packaging method according to claim 1, wherein: Bonding the second chip to the superconducting quantum chip includes: using a robotic arm to absorb the superconducting quantum chip and the second chip and aligning and leveling them, then heating the robotic arm to a first temperature so that the support structure softens appropriately, then continuing to heat the robotic arm to a second temperature, applying pressure to the superconducting quantum chip and the second chip and maintaining it for a fixed time to bond the superconducting quantum chip and the second chip, and after the second chip is bonded to the superconducting quantum chip, removing the bonding pressure and continuing to heat the robotic arm to a third temperature and maintaining it for a fixed time.

7. The flip chip packaging method according to claim 1, wherein: The second chip is a control chip.

8. A superconducting quantum chip packaging structure obtained by the flip-chip packaging method of a superconducting quantum chip according to any one of claims 1 to 7.

Images