Data interaction method and device based on shared memory, virtual electronic equipment and storage medium

Abstract

The invention provides a data interaction method and device based on a shared memory, virtual electronic equipment and a storage medium, and the method comprises the steps: responding to a detected packet sending request of a first application for a first protocol stack of first virtual network equipment, and calling a first packet sending function; encapsulating the to-be-sent data into a first data packet based on the first packet sending function; obtaining a storage address of the first data packet, and mapping the storage address in a mode of directly accessing a mapping interface by a memory to obtain a mapped physical address; and filling the physical address into a corresponding position of the descriptor of the first virtual network equipment, and updating the position of a tail pointer of the descriptor. The RC and the EP are registered as the virtual network card through the network driving technology, so that the communication function can be realized through the PCIE slot and by means of the PCIE connecting line, data message transmission can be realized without the aid of peripheral equipment such as the network card, the stability of data transmission is improved, and the configuration cost of hardware is saved.

Description

Technical Field

[0001] The present disclosure relates to data processing technology, and in particular to a data interaction method and device based on shared memory, a virtual electronic device, and a storage medium. Background Art

[0002] The high-speed serial computer expansion bus standard (Peripheral Component Interconnect Express, PCIE) is an upgraded version of the peripheral component interconnect standard (Peripheral Component Interconnect, PCI), which is mainly an optimization of the implementation method generated by the physical link upgrade. For example, the access mechanism of the configuration space is not only compatible with the configuration space access mechanism of PCI, but also provides an enhanced configuration space access mechanism. The topology of PCIE includes at least RC and EP. Although the existing technical solution can complete the data transfer between the root complex (Root Complex, RC) and the endpoint device (Endpoint device, EP) through direct memory access (Direct Memory Access, DMA), it cannot provide an interface that can be directly called by the upper-level application for data communication, which makes it quite inconvenient to use. In addition, although the data communication between RC and EP can be completed with the help of DMA, there is a lack of other mechanism guarantees, and the data transmission performance is low. Summary of the invention

[0003] The present disclosure provides a data interaction method and device based on shared memory, a virtual electronic device, and a storage medium to at least solve the above technical problems existing in the prior art.

[0004] According to a first aspect of the present disclosure, a shared memory-based data interaction method is provided, which is applied to a first virtual network device, and the method includes:

[0005] In response to detecting a packet sending request from a first application to a first protocol stack of the first virtual network device, calling a first packet sending function;

[0006] Based on the first packet sending function, encapsulate the data to be sent into a first data packet; the first data packet at least includes the destination MAC address and cyclic redundancy check data information;

[0007] Acquire the storage address of the first data packet, and map the storage address by means of a direct memory access mapping interface to obtain a mapped physical address;

[0008] The physical address is filled into the corresponding position of the descriptor of the first virtual network device, and the position of the tail pointer of the descriptor is updated.

[0009] In some executable embodiments, before responding to detecting a packet sending request of the first application to the first protocol stack of the first virtual network device, the method further includes:

[0010] Before responding to detecting a packet sending request of the first application to the first protocol stack of the first virtual network device, the method further includes:

[0011] In response to detecting a change in the electrical signal of the PCIE slot, calling a first driver application of the first virtual network device, configuring a first physical device for the first virtual network device based on an identification table of a PCI device; configuring a general network device so that the general network device is associated with the first physical device; wherein the change in the electrical signal is caused by the first virtual network device being inserted into the PCIE slot;

[0012] An address storage space is configured for the first physical device, and the address storage space is mapped to a data transceiver space.

[0013] In some executable embodiments, after configuring the universal network device, the method further includes:

[0014] A MAC address is configured for the universal network device, and a maximum transmission unit of data is configured for the universal network device.

[0015] In some executable embodiments, the method further includes:

[0016] In response to a registration request of the universal network device, registering the first virtual network device as a universal network device;

[0017] A release function of the address space is configured for the first virtual network device to release the address space of the sent message after the data is received or sent.

[0018] In some executable embodiments, after registering the first virtual network device as a general network device, the method further includes:

[0019] Configuring a first memory space for the first virtual network device to store a message sending address, and configuring a first transmission physical address linked list to store a physical address of the message sending;

[0020] Configure a second memory space for the first virtual network device to store the address of the received message, and configure a third memory space to store the received message; map the third memory space with the received message to obtain the physical address of the received message, and configure a second transmission physical address linked list to store the physical address of the received message.

[0021] In some executable embodiments, the method further includes:

[0022] A first interrupt signal is detected and the first interrupt signal is turned off; a new application programming interface message sending mode of the first virtual network device is enabled, the universal network device is turned on, and the message sending and receiving network port is started.

[0023] In some executable embodiments, the method further includes:

[0024] Fill the cyclic redundancy check data into the shared descriptor of the first virtual network device and the second virtual network device; wherein the second virtual network device accesses the shared descriptor through the message transceiver network port.

[0025] In some executable embodiments, the method further includes:

[0026] Detecting a second interrupt signal, turning off the second interrupt signal; enabling a new application programming interface message receiving mode of the first virtual network device;

[0027] In response to detecting the header value and tail value of the descriptor at the second virtual network device end, if they are inconsistent, the physical address of the message is searched in the descriptor corresponding to the header value, and the message is read from the physical address to the corresponding memory space in a direct memory access manner.

[0028] According to a second aspect of the present disclosure, a shared memory-based data interaction method is provided, which is applied to a second virtual network device, and the method includes:

[0029] In response to the occurrence of a detection event, the tail value of the shared descriptor is detected in a polling manner. If the tail value changes, the physical address of the message is searched in the descriptor corresponding to the changed tail value, and the message is read from the physical address to the corresponding memory space in a direct memory access manner; wherein the physical address is obtained by the first virtual network device mapping the storage address of the message through a direct memory access mapping interface, and is filled in the corresponding position of the descriptor of the first virtual network device; the shared descriptor is shared by the second virtual network device and the first virtual network device.

[0030] According to a third aspect of the present disclosure, a data interaction device based on a shared memory is provided, which is applied to a first virtual network device, and the device includes:

[0031] A first calling unit, configured to call a first packet sending function in response to detecting a packet sending request of a first application for a first protocol stack of the first virtual network device;

[0032] An encapsulation unit, configured to encapsulate the data to be sent into a first data packet based on the first packet sending function; the first data packet at least includes information of a destination MAC address and cyclic redundancy check data;

[0033] A mapping unit, used for acquiring a storage address of the first data packet, mapping the storage address by means of a direct memory access mapping interface, and obtaining a mapped physical address;

[0034] The processing unit is used to fill the physical address into the corresponding position of the descriptor of the first virtual network device, and update the position of the tail pointer of the descriptor.

[0035] In some executable embodiments, the device further includes:

[0036] a second calling unit, configured to call a first driver application of the first virtual network device in response to detecting a change in an electrical signal of the PCIE slot, configure a first physical device for the first virtual network device based on an identification table of a PCI device, and configure a general network device to associate the general network device with the first physical device; wherein the change in the electrical signal is caused by the first virtual network device being inserted into the PCIE slot;

[0037] The first configuration unit is used to configure an address storage space for the first physical device and map the address storage space into a data receiving and sending space.

[0038] In some executable embodiments, the device further includes:

[0039] The second configuration unit is used to configure a MAC address for the universal network device and configure a maximum transmission unit of data for the universal network device.

[0040] In some executable embodiments, the device further includes:

[0041] a registering unit, configured to register the first virtual network device as a universal network device in response to a registration request of the universal network device;

[0042] The third configuration unit is used to configure a release function of the address space for the first virtual network device, so as to release the address space of the sent message after the data is received or sent.

[0043] In some executable embodiments, the device further includes:

[0044] A fourth configuration unit, configured to configure a first memory space for the first virtual network device to store a message sending address, and to configure a first transmission physical address linked list to store a physical address of the message sending;

[0045] The fifth configuration unit is used to configure a second memory space for the first virtual network device to store the address of the received message, and configure a third memory space to store the received message; map the third memory space with the received message to obtain the physical address of the received message, and configure a second transmission physical address linked list to store the physical address of the received message.

[0046] In some executable embodiments, the device further includes:

[0047] A first shut-down unit, configured to detect a first interrupt signal and shut down the first interrupt signal;

[0048] The first enabling unit is used to enable a new application programming interface message sending mode of the first virtual network device, turn on the universal network device, and start a message sending and receiving network port.

[0049] In some executable embodiments, the encapsulation unit is further used for:

[0050] Fill the cyclic redundancy check data into the shared descriptor of the first virtual network device and the second virtual network device; wherein the second virtual network device accesses the shared descriptor through the message transceiver network port.

[0051] In some executable embodiments, the device further includes:

[0052] A second shut-down unit, configured to detect a second interrupt signal and shut down the second interrupt signal;

[0053] A second enabling unit, configured to enable a new application programming interface message receiving mode of the first virtual network device;

[0054] Correspondingly, the processing unit is also used to respond to the detection of the header value and tail value of the descriptor of the second virtual network device end. If they are inconsistent, search for the physical address of the message in the descriptor corresponding to the header value, and read the message from the physical address to the corresponding memory space in a direct memory access manner.

[0055] According to a fourth aspect of the present disclosure, a data interaction device based on a shared memory is provided, which is applied to a second virtual network device, and the device includes:

[0056] A detection unit, configured to detect a tail value of a shared descriptor in a polling manner in response to occurrence of a detection event;

[0057] A processing unit is used to search for the physical address of the message in the descriptor corresponding to the changed tail value when the tail value changes, and read the message from the physical address to the corresponding memory space in a direct memory access manner; wherein the physical address is obtained by the first virtual network device mapping the storage address of the message through a direct memory access mapping interface, and is filled in the corresponding position of the descriptor of the first virtual network device; the shared descriptor is shared by the second virtual network device and the first virtual network device.

[0058] According to a fifth aspect of the present disclosure, a virtual electronic device is provided, comprising:

[0059] at least one processor; and

[0060] a memory communicatively connected to the at least one processor; wherein,

[0061] The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the steps of the shared memory-based data interaction method.

[0062] According to a sixth aspect of the present disclosure, a non-temporary computer-readable storage medium is provided, and when instructions in the storage medium are executed by a processor of an electronic device, the electronic device is enabled to perform the steps of the shared memory-based data interaction method.

[0063] The data interaction method and device based on shared memory, virtual electronic device, and storage medium disclosed in the present invention can register RC and EP as virtual network cards through network driver technology, thereby realizing the function of communicating through PCIE slots and with the help of PCIE connecting lines, without the need for peripherals such as network cards to realize data message transmission, which not only increases the stability of data transmission, but also saves hardware configuration costs. With the help of descriptor rings and polling technical means, the present invention speeds up the transmission speed of data messages, and its one-way data transmission rate is about 1.5Gbps, which greatly meets the data transmission needs in an environment where a network card is not needed or cannot be used.

[0064] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it intended to limit the scope of the present disclosure. Other features of the present disclosure will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0065] The above and other objects, features and advantages of the exemplary embodiments of the present disclosure will become readily understood by reading the detailed description below with reference to the accompanying drawings. In the accompanying drawings, several embodiments of the present disclosure are shown in an exemplary and non-limiting manner, in which:

[0066] In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0067] Figure 1 A schematic diagram of a process flow of a data interaction method based on shared memory according to an embodiment of the present disclosure is shown;

[0068] Figure 2 A schematic diagram of a process flow of a data interaction method based on shared memory according to an embodiment of the present disclosure is shown;

[0069] Figure 3 A schematic diagram of the hardware support structure of RC and EP in an embodiment of the present disclosure;

[0070] Figure 4 A schematic diagram of the communication link between RC and EP in an embodiment of the present disclosure;

[0071] Figure 5 A schematic diagram of data message interaction between the RC side and the EP side according to an embodiment of the present disclosure is shown;

[0072] Figure 6 A schematic diagram of the process of RC sending a data message in an embodiment of the present disclosure is shown;

[0073] Figure 7 A schematic diagram of a process of RC receiving a data message in an embodiment of the present disclosure is shown;

[0074] Figure 8 A schematic diagram showing the composition structure of a data interaction device based on a shared memory according to an embodiment of the present disclosure is shown;

[0075] Fig. 9 A schematic diagram showing the composition structure of a data interaction device based on a shared memory according to an embodiment of the present disclosure is shown;

[0076] Fig.10 A schematic diagram of the structure of an electronic device according to an embodiment of the present disclosure is shown. DETAILED DESCRIPTION

[0077] In order to make the purpose, features, and advantages of the present disclosure more obvious and easy to understand, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, not all of the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0078] Figure 1 A flow chart of a data interaction method based on shared memory according to an embodiment of the present disclosure is shown. Figure 1As shown, the data interaction method based on shared memory in the embodiment of the present disclosure is applied to the first virtual network device, and the data interaction method based on shared memory includes the following processing steps:

[0079] Step 101: In response to detecting a packet sending request from a first application to a first protocol stack of the first virtual network device, calling a first packet sending function.

[0080] In the disclosed embodiment, the first application includes various applications installed in the electronic device, such as instant messaging applications, text applications that require network authentication and information interaction, etc. The first protocol stack may be an RC protocol stack, which enables the electronic device inserted into the PCIE slot to have an RC function, so that the electronic device can communicate data with the opposite end device such as EP through the PCIE slot. The first protocol stack is loaded into the electronic device by means of a configuration file or a driver installation, so that the electronic device has an RC function.

[0081] The first packet sending function includes a message sending function, as well as tx_poll, rx_poll and other functions. The main functions of these two functions are to release the address space of the message that has been sent.

[0082] In the disclosed embodiment, DMA packet transmission is mainly performed between RC and EP based on the New Application Programming Interface (NAPI). NAPI adopts a combination of interrupt and polling. It interrupts when the first packet arrives, then turns off the interrupt and starts polling. If there is no data after a poll is completed, it is assumed that the data transmission is completed, polling is stopped, and interrupts are reopened, which will reduce multiple interrupts. The disclosed embodiment introduces the New Application Programming Interface (NAPI) mechanism to switch the virtual network card packet receiving mode to the poll mode, thereby improving the sending and receiving performance of network communication.

[0083] Step 102: based on the first packet sending function, encapsulate the data to be sent into a first data packet.

[0084] In the disclosed embodiment, the first data packet at least includes the destination MAC address and cyclic redundancy check (CRC) data information. The data packet is encapsulated in a message frame format, and the data packet at least includes information such as a packet header, a source address, a destination address, and CRC data.

[0085] Step 103, obtaining the storage address of the first data packet, mapping the storage address through a DMA mapping interface, and obtaining a mapped physical address.

[0086] Specifically, RC obtains the tail value of the send descriptor ring, at which time tail = 0. Modify the control value of the descriptor, that is, the used bit, fill in the length and checksum of the message to be sent, and map the address of the data of the message to be sent through the DMA stream mapping interface to obtain the mapped physical address.

[0087] Step 104: fill the physical address into the corresponding position of the descriptor of the first virtual network device, and update the position of the tail pointer of the descriptor.

[0088] Specifically, the cyclic redundancy check data is filled into a shared descriptor of the first virtual network device and the second virtual network device; wherein the second virtual network device accesses the shared descriptor through the message transceiver network port.

[0089] Fill the physical address obtained in step 103 into the corresponding descriptor ring of tail=0 to ensure that EP can read the message. After modifying the ctrl value of the descriptor, move the position of the descriptor to tail=1. EP polls the tail value of the descriptor by means of a timer, and finds that the tail value has changed. At this time, EP finds the physical address of the message in the descriptor corresponding to tail, and then starts the DMA mode to transfer the message from the physical address to the memory corresponding to EP by DMA.

[0090] In the disclosed embodiment, when a second interrupt signal is detected, the second interrupt signal is turned off; and the NAPI message receiving mode of the first virtual network device is enabled. In response to detecting the header value and tail value of the descriptor at the second virtual network device end, if they are inconsistent, the physical address of the message is searched in the descriptor corresponding to the header value, and the message is read from the physical address to the corresponding memory space in a direct memory access manner. When the first virtual network device detects that the second virtual network device has a message update, it is necessary to receive its message from the second virtual network device to realize the sending of data messages from the second virtual network device to the first virtual network device.

[0091] Figure 2 A flow chart of a data interaction method based on shared memory according to an embodiment of the present disclosure is shown. Figure 2 As shown, the data interaction method based on shared memory in the embodiment of the present disclosure is applied to the first virtual network device, and the data interaction method based on shared memory includes the following processing steps:

[0092] Step 201: In response to detecting a change in an electrical signal of a PCIE slot, calling a first driver application of the first virtual network device, and configuring a pdev device for the first virtual network device based on an identification table of a PCI device.

[0093] In the disclosed embodiment, multiple electronic devices communicate data based on PCIE slots, wherein each electronic device is installed with a configuration file or driver of a virtual network card, which can realize the function of an RC device or an EP device, so that the RC device and the EP device can communicate data based on the PCIE slot. The change of the electrical signal is caused by the insertion of the first virtual network device into the PCIE slot, that is, when an electronic device is inserted into the PCIE slot, a physical link is established between the electronic devices based on the configuration parameters or driver of the virtual network card.

[0094] Step 202: configure the first physical device so that the general network device is associated with the configured pdev device.

[0095] In the disclosed embodiment, the first physical device is represented by pdev, and the general network device is represented by netdev. When the electronic device is inserted into the PCIE slot, it is enabled as a PCI device. Specifically, the electronic device scans the RC as the physical device (pdev) of the PCI device through the identification list (id_table) of the PCI device, and applies for a general network device (netdev) for pdev, associates the general network device netdev with the PCI device pdev, and at the same time, fills in the MAC address of the general network device, sets the maximum transmission unit (Maximum Transmission Unit, MTU) of the general network device; and maps the address register (Base Address Register, BAR) space of the PCI device pdev, takes BAR0 and BAR2 as the sending and receiving queues of RC respectively, and EP can also access these two queues, in preparation for the subsequent design of the queue shared by the EP and RC into a shared descriptor ring.

[0096] At the same time, netdev is registered as a general network device, and the two functions tx_poll and rx_poll are added to the napi->poll_list queue, the netdev network device is closed, and the registration of the RC device is completed. Among them, the main function of tx_poll and rx_poll is to release the address space of the message that has been sent.

[0097] Those skilled in the art should understand that step 201 and step 202 are the initial registration process of the electronic device, which are only the prerequisites for executing the technical solution of the embodiment of the present disclosure, and are not necessary steps for executing the technical solution of the embodiment of the present disclosure every time.

[0098] In the disclosed embodiment, it is also necessary to configure the first memory space for the first virtual network device to store the address of the sent message, configure the first transmission physical address linked list to store the physical address of the sent message; configure the second memory space for the first virtual network device to store the address of the received message, configure the third memory space to store the received message; map the third memory space with the received message to obtain the physical address of the received message, and configure the second transmission physical address linked list to store the physical address of the received message. After detecting the first interrupt signal, turn off the first interrupt signal; enable the NAPI message sending mode of the first virtual network device, open the netdev device, and start the message sending and receiving network port.

[0099] Specifically, after associating the netdev device with the pdev device, the netdev device needs to be initialized. First, a queue initialization request is sent to apply for a socket buffer (tx_skbuff) for transmission and sending to store the message address (ie, skb (socket buffers) address), and apply for a transmission physical geographic list (tx_phys_addr_list) to store the message physical address.

[0100] Next, the receiving queue is initialized, rx_skbuff is applied for receiving, which is used to store the message address (i.e. skb address). The skb address space is applied for storing data packets, and skb->data is mapped to obtain the physical address, and rx_phys_addr_list is applied for storing these physical addresses.

[0101] Apply for interruption, enable NAPI sending and receiving functions, and at the same time, open the network device netdev and link the network port so that the network port is in the link working state and is ready for work.

[0102] Step 203: In response to detecting a packet sending request from a first application to a first protocol stack of the first virtual network device, a first packet sending function is called.

[0103] In the embodiment of the present disclosure, the first protocol stack may be an RC protocol stack, which enables the electronic device inserted into the PCIE slot to have an RC function, so that the electronic device can communicate data with the opposite end device such as EP through the PCIE slot. The first protocol stack is loaded into the electronic device by way of a configuration file or a driver installation, so that the electronic device has the RC function.

[0104] The first packet sending function includes message sending function, tx_poll, rx_poll and other functions. The main functions of these two functions are to release the address space of the message that has been sent.

[0105] In the disclosed embodiment, DMA packets are mainly sent between RC and EP based on the New Application Programming Interface (NAPI). NAPI uses a combination of interrupts and polling. It interrupts when the first packet arrives, then turns off the interrupt and starts polling. If there is no data after a poll is completed, it is assumed that the data transmission is completed, polling is stopped, and interrupts are reopened, which will reduce multiple interrupts. The disclosed embodiment introduces the NAPI mechanism to switch the virtual network card packet receiving mode to the poll mode, thereby improving the sending and receiving performance of network communication.

[0106] Step 204: based on the first packet sending function, encapsulate the data to be sent into a first data packet.

[0107] In the disclosed embodiment, the first data packet at least includes the destination MAC address and cyclic redundancy check (CRC) data information. The data packet is encapsulated in a message frame format, and the data packet at least includes information such as a packet header, a source address, a destination address, and CRC data.

[0108] Step 205: Acquire the storage address of the first data packet, map the storage address through a DMA mapping interface, and obtain a mapped physical address.

[0109] Specifically, RC obtains the tail value of the send descriptor ring, at which time tail = 0. Modify the control value of the descriptor, that is, the used bit, fill in the length and checksum of the message to be sent, and map the address of the data of the message to be sent through the DMA stream mapping interface to obtain the mapped physical address.

[0110] Step 206: fill the physical address into the corresponding position of the descriptor of the first virtual network device, and update the position of the tail pointer of the descriptor.

[0111] The physical address obtained in step 205 is filled into the corresponding descriptor ring of tail=0 to ensure that EP can read the message. After modifying the ctrl value of the descriptor, the position of the move descriptor is tail=1. EP polls the tail value of the descriptor by means of a timer, and finds that the tail value has changed. At this time, EP finds the physical address of the message in the descriptor corresponding to tail, and then starts the DMA mode to transfer the message from the physical address to the memory corresponding to EP by DMA.

[0112] The essence of the technical solution of the embodiment of the present disclosure is further illustrated below through specific examples.

[0113] Figure 3 FIG. 1 is a schematic diagram of the hardware support structure of RC and EP of the embodiment of the present disclosure, such as Figure 3 As shown, the hardware support structure of the embodiment of the present disclosure mainly includes a CPU, a MEM memory module and a PCIE slot, wherein the CPU is used to control the MEM memory module and the PCIE slot, especially to provide the electronic device connected through the PCIE slot with the configuration information and driver files of RC or EP, so that it can be enabled with RC and / or EP, and establish a communication link based on the PCIE slot. The CPU includes but is not limited to server chips and embedded series CPUs, etc.

[0114] After the electronic device is inserted into the PCIE slot, it is enabled as a PCI device. Specifically, the electronic device scans the RC as the pdev of the PCI device through the identification list (id_table) of the PCI device, and applies for a general network device (netdev) for pdev, associates the general network device netdev with the PCI device pdev, and at the same time, fills in the MAC address of the network device, sets the maximum transmission unit (Maximum Transmission Unit, MTU) of the network device; and maps the BAR space of the PCI device pdev, taking BAR0 and BAR2 as the sending and receiving queues of RC respectively, and EP can also access these two queues, in preparation for the subsequent design of the queues shared by the EP and RC into a shared descriptor ring.

[0115] At the same time, netdev is registered as a general network device, and the two functions tx_poll and rx_poll are added to the napi->poll_list queue, the netdev device is closed, and the registration of the RC device is completed. Among them, the main function of tx_poll and rx_poll is to release the address space of the message that has been sent.

[0116] After associating the netdev device with the pdev device, the netdev device needs to be initialized. First, a queue initialization request is sent to apply for a socket buffer (tx_skbuff) for transmission and sending to store the message address (ie, skb (socket buffers) address), and a transmission physical geographic list (tx_phys_addr_list) is applied to store the message physical address.

[0117] Next, the receiving queue is initialized, rx_skbuff is applied for receiving, which is used to store the message address (i.e. skb address). The skb address space is applied for storing data packets, and skb->data is mapped to obtain the physical address, and rx_phys_addr_list is applied for storing these physical addresses.

[0118] Apply for interruption, enable NAPI sending and receiving functions, and at the same time, open the network device netdev and link the network port so that the network port is in the link working state and is ready for work.

[0119] Figure 4 FIG. 1 is a schematic diagram of the communication link between RC and EP in an embodiment of the present disclosure, as shown in FIG. Figure 4 As shown, the RC and EP of the embodiment of the present disclosure are interconnected based on the PCIE slot, and data communication interaction is achieved based on the physical link.

[0120] Figure 5 A schematic diagram of data message interaction between the RC side and the EP side in an embodiment of the present disclosure is shown. Figure 5 As shown in the figure, by configuring the inbound and outbound register groups, the RC side and the EP side can enable the EP and RC to access each other's storage domain. Inbound is the PCI domain accessing the memory domain; Outbound is the memory domain accessing the PCI domain. Out means going out, and the side initiating the access needs to perform outbound to access the other side. In means coming in, and the side being accessed needs to perform inbound so that the other side can access it.

[0121] like Figure 5 As shown in the figure, the path from the RC side to the EP side is:

[0122] RC memory domain->outbound->RC PCI domain->EP PCI domain->inbound->EP memory domain.

[0123] The path from the EP side to the RC side is: EP memory domain->outbound->EP PCI domain->RC PCI domain->inbound->RC memory domain.

[0124] The path sample for EP to access RC is: Figure 5 As shown by the black arrows in the figure, it includes:

[0125] First, EP needs to configure outbound, and RC needs inbound register group (RC side does not need to be configured), so that the mapping from EP side 0x20000000 to RC side 0x60100000 is established;

[0126] If you change the content of 0x60100000 on the RC side, the EP side will see the corresponding change. Reading / writing 0x20000000 from the EP side and reading / writing 0x60100000 from the RC side, the path results are the same regardless of reading or writing.

[0127] The path from the RC side to the EP side, Figure 5 As shown by the blue arrow, it includes:

[0128] The RC side needs to configure the outbound register group (usually configured in memory), and the EP side needs the inbound register group, so that the mapping from 0x40100000 (BAR2) on the RC side to 0x50000000 on the EP side is established.

[0129] If you change the content of memory 0x50000000 on the EP side, you can see the corresponding change at 0x40100000 on the RC side. Reading / writing 0x40100000 from the RC side and reading / writing 0x50000000 from the EP side have the same result.

[0130] The disclosed embodiment registers RC as a virtual network device. At this time, RC has all the properties of a network device and can send and receive data packets through the network through related data lines. A descriptor ring mechanism is designed for the RC end. EP and RC can share the descriptor ring by configuring inbound and outbound register groups and transfer data through DMA.

[0131] After completing the network device initialization process on the RC side, link up the network port. If the RC needs to send data packets to the RC side, Figure 6 The schematic diagram of the process of RC sending data packets in the embodiment of the present disclosure is shown. At this time, the packet sending process is:

[0132] The RC protocol stack sends a message to trigger the packet sending process;

[0133] Call the RC packet sending function to send the packet.

[0134] The RC end completes the destination MAC address filling and CRC check calculation.

[0135] Check whether the EP is online. If not, return to the step of triggering the packet sending process. If online, check whether there is an available descriptor. If there is no available descriptor, the data message cannot be sent. Return to the step of triggering the packet sending process. If there is an available descriptor, obtain the tail value of the descriptor ring, and tail = 0.

[0136] RC obtains the tail value of the send descriptor ring, at which time tail = 0. Modify the control value of the descriptor, that is, the used bit, and fill the check code into the descriptor shared by EP and RC.

[0137] The address of the data of the message to be sent is mapped through the DMA stream mapping interface to obtain the mapped physical address, and the physical address is filled in the corresponding position of the descriptor. Ensure that the EP can read it. After completion, the position of the descriptor is moved to the tail.

[0138] At this time, the EP polls the tail value of the descriptor through a timer and finds that the tail value of the shared descriptor has changed. At this time, tail = 1, but its head = 0, and tail is not equal to head. The EP finds the physical address of the message in the descriptor corresponding to the tail, and then starts DMA to DMA the message from the physical address to the memory corresponding to the EP end.

[0139] Figure 7 FIG. 4 shows a flow chart of the RC receiving data message according to an embodiment of the present disclosure, as shown in FIG. Figure 7 As shown, when RC receives a packet, it moves the descriptor ring position through the EP end, moves the data through DMA, and notifies the RC end of the arrival of the message by triggering an RC end interrupt, and the RC end completes the message reception. The process is as follows:

[0140] The EP protocol stack sends a message to trigger the packet sending process.

[0141] The network port of the EP is in the link state. Waiting for interruption. The EP completes the destination MAC address filling and CRC check calculation. The triggering method of its data message is the same as that of the RC end, and its implementation details are not repeated here.

[0142] When an interrupt is triggered, RC first enters the interrupt processing function and turns off the interrupt. If a new data packet arrives at this time, the network card will no longer trigger the interrupt, because the interrupt processing function of the network card that supports NAPI will poll the cache queue until there are no unprocessed data packets before turning on the interrupt. This design can avoid frequent interrupts of the network card under high throughput conditions, thereby saving CPU resources.

[0143] After disabling interrupts, call the scheduling function __napi_schedule, which will then call the rx_poll function.

[0144] rx_poll will call the packet receiving function to receive packets and read the head and tail values ​​of the shared descriptor. At this time, head=0, tail=1, and the head value and tail value are not equal. Then the physical address of the message is found in the descriptor corresponding to the head value, and then DMA is started to DMA the message from the physical address to the memory corresponding to the RC end. The maximum number of messages processed by RC at one time is 64. If 64 messages are processed, it returns and continues to receive the next round of packets. If it does not reach 64 messages (that is, the number of messages in the descriptor ring is small), the interrupt is turned on at this time, and the interrupt is triggered when the EP end sends a message, and this cycle continues.

[0145] The embodiment of the present disclosure also records a data interaction method based on shared memory, which is applied to a second virtual network device such as EP. The method includes:

[0146] In response to the occurrence of a detection event, the tail value of the shared descriptor is detected in a polling manner. If the tail value changes, the physical address of the message is searched in the descriptor corresponding to the changed tail value, and the message is read from the physical address to the corresponding memory space in a direct memory access manner; wherein the physical address is obtained by the first virtual network device mapping the storage address of the message through a direct memory access mapping interface, and is filled in the corresponding position of the descriptor of the first virtual network device; the shared descriptor is shared by the second virtual network device and the first virtual network device.

[0147] For more information about EP data transmission and reception methods, please refer to Figure 5 and Figure 6 The implementation details are not repeated here.

[0148] The disclosed embodiment can register RC and EP as virtual network cards through network driver technology, thereby realizing the function of communicating through PCIE slots and with the help of PCIE connection lines, without the need for peripherals such as network cards to realize data message transmission, which not only increases the stability of data transmission, but also saves hardware configuration costs. The disclosed embodiment accelerates the transmission speed of data messages by means of descriptor rings and polling technical means, and its one-way data transmission rate is about 1.5Gbps, which greatly meets the data transmission needs in an environment where a network card is not needed or cannot be used.

[0149] Figure 8 The schematic diagram of the structure of the data interaction device based on shared memory in the embodiment of the present disclosure is shown as follows: Figure 8 As shown, the data interaction device based on shared memory in the embodiment of the present disclosure is applied to the first virtual network device, and the device includes:

[0150] A first calling unit 80 is configured to call a first packet sending function in response to detecting a packet sending request of a first application for a first protocol stack of the first virtual network device;

[0151] The encapsulation unit 81 is used to encapsulate the data to be sent into a first data packet based on the first packet sending function; the first data packet at least includes the destination MAC address and cyclic redundancy check data information;

[0152] A mapping unit 82, configured to obtain a storage address of the first data packet, and map the storage address through a direct memory access mapping interface to obtain a mapped physical address;

[0153] The processing unit 83 is used to fill the physical address into the corresponding position of the descriptor of the first virtual network device, and update the position of the tail pointer of the descriptor.

[0154] In some executable embodiments, Figure 7 The data interaction device based on shared memory shown in the figure also includes:

[0155] The second calling unit ( Figure 8 (not shown), for in response to detecting a change in the electrical signal of the PCIE slot, calling a first driver application of the first virtual network device, configuring a pdev device for the first virtual network device based on an identification table of a PCI device; configuring a netdev device to associate the netdev device with the configured pdev device; wherein the change in the electrical signal is caused by the first virtual network device being inserted into the PCIE slot;

[0156] The first configuration unit ( Figure 8 ), which is used to configure a BAR space for storage of the pdev device and map the BAR space into a data transceiver space.

[0157] In some executable embodiments, Figure 8 The data interaction device based on shared memory shown in the figure also includes:

[0158] The second configuration unit ( Figure 8 ), which is used to configure a MAC address for the netdev device and a maximum transmission unit of data for the netdev device.

[0159] In some executable embodiments, Figure 8 The data interaction device based on shared memory shown in the figure also includes:

[0160] Registration Unit( Figure 8), for registering the first virtual network device as a netdev device in response to a registration request of the netdev device;

[0161] The third configuration unit ( Figure 8 ), which is used to configure a release function of the address space for the first virtual network device to release the address space of the sent message after the data is received or sent.

[0162] In some executable embodiments, Figure 8 The data interaction device based on shared memory shown in the figure also includes:

[0163] The fourth configuration unit ( Figure 8 ), configured to configure a first memory space for the first virtual network device to store a message sending address, and to configure a first transmission physical address linked list to store a physical address of a message sending;

[0164] The fifth configuration unit ( Figure 8 (not shown) is used to configure a second memory space for the first virtual network device to store the address of the received message, configure a third memory space to store the received message; map the third memory space with the received message to obtain the physical address of the received message, and configure a second transmission physical address linked list to store the physical address of the received message.

[0165] In some executable embodiments, Figure 8 The data interaction device based on shared memory shown in the figure also includes:

[0166] The first closing unit ( Figure 8 ), for detecting a first interrupt signal and turning off the first interrupt signal;

[0167] The first enabling unit ( Figure 8 ), used to enable the NAPI message sending mode of the first virtual network device, open the netdev device, and start the message sending and receiving network port.

[0168] In some executable embodiments, the encapsulation unit 81 is further configured to:

[0169] Fill the cyclic redundancy check data into the shared descriptor of the first virtual network device and the second virtual network device; wherein the second virtual network device accesses the shared descriptor through the message transceiver network port.

[0170] In some executable embodiments, Figure 8 The data interaction device based on shared memory shown in the figure also includes:

[0171] The second closing unit ( Figure 8 (not shown) for detecting a second interrupt signal and turning off the second interrupt signal;

[0172] The second enabling unit ( Figure 8 ), used to enable the NAPI message receiving mode of the first virtual network device;

[0173] Correspondingly, the processing unit 83 is also used to respond to the detection of the header value and tail value of the descriptor of the second virtual network device end. If they are inconsistent, search for the physical address of the message in the descriptor corresponding to the header value, and read the message from the physical address to the corresponding memory space in a direct memory access manner.

[0174] In an exemplary embodiment, the aforementioned units and the like may be implemented by one or more central processing units (CPU), graphics processing units (GPU), application specific integrated circuits (ASIC), DSPs, programmable logic devices (PLD), complex programmable logic devices (CPLD), field programmable gate arrays (FPGA), general-purpose processors, controllers, microcontrollers (MCU), microprocessors, or other electronic components.

[0175] Regarding the device in the above embodiment, the specific manner in which each module and unit performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0176] Fig. 9 The schematic diagram of the structure of the data interaction device based on shared memory in the embodiment of the present disclosure is shown as follows: Fig. 9 As shown, the data interaction device based on shared memory in the embodiment of the present disclosure is applied to the second virtual network device, and the device includes:

[0177] A detection unit 90, configured to detect the tail value of the shared descriptor in a polling manner in response to the occurrence of a detection event;

[0178] The processing unit 91 is used to search for the physical address of the message in the descriptor corresponding to the changed tail value when the tail value changes, and read the message from the physical address to the corresponding memory space in a direct memory access manner; wherein the physical address is obtained by the first virtual network device mapping the storage address of the message through a direct memory access mapping interface, and is filled in the corresponding position of the descriptor of the first virtual network device; the shared descriptor is shared by the second virtual network device and the first virtual network device.

[0179] Those skilled in the art will appreciate that although Figure 8 and Fig. 9 The data interaction device based on shared memory shown shows different structures, but for RC and EP, the difference is only in the initiation method of the data interaction structure, so their structures are corresponding in principle.

[0180] In an exemplary embodiment, the aforementioned units and the like may be implemented by one or more central processing units (CPU), graphics processing units (GPU), application specific integrated circuits (ASIC), DSPs, programmable logic devices (PLD), complex programmable logic devices (CPLD), field programmable gate arrays (FPGA), general-purpose processors, controllers, microcontrollers (MCU), microprocessors, or other electronic components.

[0181] Regarding the device in the above embodiment, the specific manner in which each module and unit performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0182] According to an embodiment of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0183] Fig.10 8 is a schematic block diagram of an example network element 800 that can be used to implement an embodiment of the present disclosure. Fig.10As shown, the network element 800 includes a computing unit 801, which can perform various appropriate actions and processes according to a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 to a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of the network element 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0184] Multiple components in the network element 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a disk, an optical disk, etc.; and a communication unit 809, such as a network card, a modem, a data processing transceiver, etc. The communication unit 809 allows the network element 800 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0185] The computing unit 801 may be a variety of general and / or special processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, digital signal processors (DSPs), and any appropriate processors, controllers, microcontrollers, etc. The computing unit 801 performs the various methods and processes described above, such as a data interaction method based on shared memory. For example, in some embodiments, the data interaction method based on shared memory may be implemented as a computer software program, which is tangibly included in a machine-readable medium, such as a storage unit 808. In some embodiments, part or all of the computer program may be loaded and / or installed on the network element 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of the data interaction method based on shared memory described above may be performed. Alternatively, in other embodiments, the computing unit 801 may be configured to execute a shared memory-based data interaction method in any other appropriate manner (eg, by means of firmware).

[0186] Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

[0187] The program code for implementing the method of the present disclosure may be written in any combination of one or more programming languages. These program codes may be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

[0188] In the context of the present disclosure, a machine-readable medium may be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, device, or equipment. A machine-readable medium may be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, or equipment, or any suitable combination of the foregoing. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0189] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and pointing device (e.g., a mouse or trackball) through which the user can provide input to the computer. Other types of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0190] The systems and techniques described herein may be implemented in a computing system that includes back-end components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes front-end components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such back-end components, middleware components, or front-end components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), and the Internet.

[0191] A computer system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The relationship of client and server is generated by computer programs running on respective computers and having a client-server relationship with each other. The server may be a cloud server, a server of a distributed system, or a server combined with a blockchain.

[0192] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps recorded in this disclosure can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solutions disclosed in this disclosure can be achieved, and this document does not limit this.

[0193] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include at least one of the features. In the description of the present disclosure, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0194] The above is only a specific embodiment of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A data interaction method based on shared memory, applied to a first virtual network device, characterized in that: The method comprises: In response to detecting a packet sending request from a first application to a first protocol stack of the first virtual network device, calling a first packet sending function; Based on the first packet sending function, encapsulate the data to be sent into a first data packet; the first data packet at least includes the destination MAC address and cyclic redundancy check data information; Acquire the storage address of the first data packet, and map the storage address by means of a direct memory access mapping interface to obtain a mapped physical address; Fill the physical address into the corresponding position of the descriptor of the first virtual network device, and update the position of the tail pointer of the descriptor. Fill the physical address into the corresponding position of the descriptor of the first virtual network device, and update the position of the tail pointer of the descriptor.

2. The method according to claim 1, characterized in that Before responding to detecting a packet sending request of the first application to the first protocol stack of the first virtual network device, the method further includes: In response to detecting a change in the electrical signal of the PCIE slot, calling a first driver application of the first virtual network device, configuring a first physical device for the first virtual network device based on an identification table of a PCI device; configuring a general network device so that the general network device is associated with the first physical device; wherein the change in the electrical signal is caused by the first virtual network device being inserted into the PCIE slot; An address storage space is configured for the first physical device, and the address storage space is mapped to a data transceiver space.

3. The method according to claim 2, characterized in that After configuring the universal network device, the method further includes: A MAC address is configured for the universal network device, and a maximum transmission unit of data is configured for the universal network device.

4. The method according to claim 2 or 3, characterized in that: The method further comprises: In response to a registration request of the universal network device, registering the first virtual network device as a universal network device; A release function of the address space is configured for the first virtual network device to release the address space of the sent message after the data is received or sent.

5. The method according to claim 4, characterized in that After registering the first virtual network device as a general network device, the method further includes: Configuring a first memory space for the first virtual network device to store a message sending address, and configuring a first transmission physical address linked list to store a physical address of the message sending; Configure a second memory space for the first virtual network device to store the address of the received message, and configure a third memory space to store the received message; map the third memory space with the received message to obtain the physical address of the received message, and configure a second transmission physical address linked list to store the physical address of the received message.

6. The method according to claim 5, characterized in that The method further comprises: A first interrupt signal is detected and the first interrupt signal is turned off; a new application programming interface message sending mode of the first virtual network device is enabled, the universal network device is turned on, and the message sending and receiving network port is started.

7. The method according to claim 6, characterized in that The method further comprises: Fill the cyclic redundancy check data into the shared descriptor of the first virtual network device and the second virtual network device; wherein the second virtual network device accesses the shared descriptor through the message transceiver network port.

8. The method according to claim 1, characterized in that: The method further comprises: Detecting a second interrupt signal, turning off the second interrupt signal; enabling a new application programming interface message receiving mode of the first virtual network device; In response to detecting the header value and tail value of the descriptor at the second virtual network device end, if they are inconsistent, the physical address of the message is searched in the descriptor corresponding to the header value, and the message is read from the physical address to the corresponding memory space in a direct memory access manner.

9. A data interaction method based on shared memory, applied to a second virtual network device, characterized in that: The method comprises: In response to the occurrence of a detection event, the tail value of the shared descriptor is detected in a polling manner. If the tail value changes, the physical address of the message is searched in the descriptor corresponding to the changed tail value, and the message is read from the physical address to the corresponding memory space in a direct memory access manner; wherein the physical address is obtained by the first virtual network device mapping the storage address of the message through a direct memory access mapping interface, and is filled in the corresponding position of the descriptor of the first virtual network device; the shared descriptor is shared by the second virtual network device and the first virtual network device.

10. A data interaction device based on shared memory, applied to a first virtual network device, characterized in that: The device comprises: A first calling unit, configured to call a first packet sending function in response to detecting a packet sending request of a first application for a first protocol stack of the first virtual network device; An encapsulation unit, configured to encapsulate the data to be sent into a first data packet based on the first packet sending function; the first data packet at least includes information of a destination MAC address and cyclic redundancy check data; A mapping unit, used for acquiring a storage address of the first data packet, mapping the storage address by means of a direct memory access mapping interface, and obtaining a mapped physical address; The processing unit is used to fill the physical address into the corresponding position of the descriptor of the first virtual network device, and update the position of the tail pointer of the descriptor.

11. A data interaction device based on shared memory, applied to a second virtual network device, characterized in that: The device comprises: A detection unit, configured to detect a tail value of a shared descriptor in a polling manner in response to occurrence of a detection event; A processing unit is used to search for the physical address of the message in the descriptor corresponding to the changed tail value when the tail value changes, and read the message from the physical address to the corresponding memory space in a direct memory access manner; wherein the physical address is obtained by the first virtual network device mapping the storage address of the message through a direct memory access mapping interface, and is filled in the corresponding position of the descriptor of the first virtual network device; the shared descriptor is shared by the second virtual network device and the first virtual network device.

12. A virtual electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to the at least one processor; wherein, The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform the steps of the shared memory-based data interaction method described in any one of claims 1 to 9.

13. A non-temporary computer-readable storage medium, when the instructions in the storage medium are executed by a processor of an electronic device, enables the electronic device to execute the steps of the shared memory-based data interaction method as described in any one of claims 1 to 9.

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