Automatic traversal test circuit, automatic traversal test device, interrupt request test method and interrupt request test system

Abstract

The invention discloses an automatic traversal test circuit, an automatic traversal test device, an interrupt request test method and an interrupt request test system, and the automatic traversal test circuit comprises a multiplexer which comprises N test pins, and the total number N of the test pins is the same as the number of to-be-tested interfaces of a to-be-tested chip; the chip to be tested and the multiplexer form multi-channel connection; the multiplexer further comprises at least one first control interface and a selection input end; the truth value state of the first control interface is changed under the action of the first control instruction, so that the selection input end is controlled to select a path corresponding to the target test pin to be conducted. According to the invention, the multichannel multiplexer analog switch is added in the test circuit to replace the function of manually plugging and switching pins. The multi-interface interrupt request automatic test of the chip to be tested can be realized.

Description

Technical Field

[0001] The present application relates to the field of automated testing, and in particular to an automatic traversal test circuit, device, interrupt request test method and system. Background Art

[0002] The microcontroller (MCU) provides an interrupt controller (EXTI) module. The EXTI module includes an edge detector that can generate an interrupt request or a wake-up event. The edge detector can be set to a rising edge trigger, a falling edge trigger, or a double edge trigger. All interfaces under test of the MCU support configuration as a trigger source of EXTI. An MCU usually contains several interfaces under test.

[0003] At present, when testing the interrupt request function of the EXTI module, the test interface is usually switched by manually plugging and unplugging the pins. This test method is not only inefficient but also prone to errors. Due to human interference, it is difficult to troubleshoot when an error occurs. Summary of the invention

[0004] In order to solve the above technical problems, the present application provides an automatic traversal test circuit, device, interrupt request test method and system. The present application adds a multi-channel multiplexer analog switch to the test circuit to replace the function of manually plugging and unplugging the switching pins. It can realize the automatic test of multi-interface interrupt requests of the chip under test.

[0005] Specifically, the technical solution of this application is as follows:

[0006] In a first aspect, the present application discloses an automatic traversal test circuit, comprising a multiplexer;

[0007] The multiplexer includes N test pins, and the total number N of the test pins is the same as the number of test interfaces of the chip to be tested; so that the chip to be tested forms a multi-channel connection with the multiplexer;

[0008] The multiplexer also includes at least one first control interface and a selection input terminal; the first control interface changes its true value state under the action of the first control instruction, thereby controlling the selection input terminal to select the path corresponding to the target test pin to be turned on.

[0009] In some implementations, the number of the multiplexer is at least one, and each of the multiplexers is connected in parallel;

[0010] The number of the test pins on each of the multiplexers is evenly distributed; the total number N of the test pins remains unchanged.

[0011] In some embodiments, the test circuit further includes: a driving circuit module; an output terminal of the driving circuit module is connected to a selection input terminal of the multiplexer;

[0012] The driving circuit module includes at least one second control interface and at least one transistor; the second control interface turns on or off the transistor under the action of a second control instruction, thereby controlling the opening or closing of at least one of the multiplexers.

[0013] In some embodiments, the multiplexer further includes a positive power supply voltage pin and a negative power supply voltage pin;

[0014] The selection input terminal is connected to an enable voltage; when the selection input terminal is turned on and connected to a target test pin, a path corresponding to the target test pin is turned on.

[0015] In a second aspect, the present application further discloses an automatic traversal test device, comprising the test circuit described in any one of the above embodiments, and also comprising a base, and a chip to be tested;

[0016] All pins of the chip to be tested are led out by a pin arrangement device so as to connect the chip to be tested with the test circuit through the base.

[0017] In some embodiments, the chip under test includes an interrupt controller, and the interrupt controller is set to be triggered by a specified edge; the interface under test of the chip under test is connected to an interface peripheral; the interface peripheral controls the corresponding interface under test as a trigger source of the interrupt controller to generate an interrupt input;

[0018] The N test pins in the test circuit are connected to the interface to be tested of the chip to be tested in sequence; the path corresponding to the target test pin is selected to be turned on, so as to test whether the interface to be tested connected to the target test pin can enable the interrupt controller to generate a normal interrupt request.

[0019] In some implementations, the automatic traversal test device further includes a J-link debugger;

[0020] The J-link debugger is connected to the test circuit to realize direct reading and writing of registers in the chip under test, and data transmission and reception between the chip under test and an upper-level terminal.

[0021] In a third aspect, the present application further discloses an interrupt request testing method, the implementation of which is based on the automatic traversal testing device described in any one of the above embodiments; comprising:

[0022] Write a test case template for the interrupt controller; obtain a configuration file for each interface to be tested; combine the test case template with the configuration file, and use a script to generate all test cases corresponding to all the interfaces to be tested;

[0023] Automatically download the test cases to the chip to be tested, start and run the test script; obtain the test results of the corresponding interface to be tested within the preset test time;

[0024] Controlling pin switching of the test circuit based on the test case;

[0025] The J-Link debugger sends the test results to the upper terminal, which summarizes them to obtain a final test report.

[0026] In some implementations, the configuration file of each interface to be tested is obtained from the production data manual of the chip to be tested; the test case includes a case title, preconditions, test steps and expected results.

[0027] In a fourth aspect, the present application further discloses an automatic traversal testing system, comprising a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the automatic traversal testing method described in any one of the above embodiments.

[0028] Compared with the prior art, the present invention has at least one of the following beneficial effects:

[0029] 1. This application adds a multi-channel multiplexer analog switch to the test circuit, and can select the channel corresponding to the target test pin to be turned on based on the true value state of its control interface. This replaces the function of manually plugging and unplugging the switching pin. It can realize automatic testing of multi-interface interrupt requests of the chip under test. Automatic testing can quickly execute a large number of test cases, much faster than manual testing, and automated test scripts can accurately execute test steps, reduce manual operation errors, ensure the consistency of each test, and improve the reliability of the test.

[0030] 2. Based on the implementation of different scenarios, the number of multiplexers in the test circuit in this application can be set to multiple, and can adapt to various models and chips under test with different numbers of pins. In the case of multiple multiplexers, the test circuit in this application also includes a driving circuit module, which selects one of the multiplexers to be turned on based on the true value state of the control interface in the driving circuit module; and then based on the true value state of the control interface in the multiplexer, the path corresponding to one of the test pins can be selected to be turned on. Complete the selection and switching of the channel. In actual usage scenarios, selecting an appropriate number of multiplexers can effectively reduce the production cost of the test circuit and has a wider range of applications.

[0031] 3. In this application, the interrupt request testing method can realize automatic testing of the target interface by writing a test case template and running the corresponding script program. The test is efficient and reliable. The automatic traversal test device based on this application can also realize: under specific edge conditions, each interface to be tested of the MCU serves as a trigger source for the interrupt controller, and whether the interrupt controller can generate a normal interrupt request; automatic testing of the project.

[0032] 4. In this application, the J-link debugger is used to send and receive data. J-link integrates a segger_rtt (Real-Time Transfer) tool for real-time information transmission. This tool is different from the existing communication module. It does not occupy the communication interface of the chip under test and can save communication interfaces similar to UART. At the same time, it will not affect the real-time behavior of the chip under test. The J-Link device can realize direct read and write operations on the MCU registers and realize information transmission and reception with the upper terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The preferred implementation scheme will be described below in a clear and understandable manner with reference to the accompanying drawings to further illustrate the above-mentioned characteristics, technical features, advantages and implementation methods of the present application.

[0034] Figure 1 A circuit pin switching diagram of an embodiment of an automatic traversal test circuit of the present application;

[0035] Figure 2 A schematic diagram of the connection between the test pins of a multiplexer and the test interface of a chip under test in one embodiment of an automatic traversal test circuit of the present application;

[0036] Figure 3 This is a structural schematic diagram of an embodiment of an automatic traversal test device of the present application;

[0037] Figure 4 A flowchart of an embodiment of an interrupt request testing method of the present application;

[0038] Figure 5 This is a flowchart of another embodiment of an interrupt request testing method of the present application. DETAILED DESCRIPTION

[0039] In the following description, specific details such as specific system structures, technologies, etc. are provided for the purpose of illustration rather than limitation, so as to provide a thorough understanding of the embodiments of the present application. However, it should be clear to those skilled in the art that the present application may also be implemented in other embodiments without these specific details. In other cases, detailed descriptions of well-known systems, devices, circuits, and methods are omitted to prevent unnecessary details from obstructing the description of the present application.

[0040] It should be understood that when used in this specification and the appended claims, the term "comprising" indicates the presence of the described features, integers, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or collections.

[0041] In order to simplify the drawings, only the parts related to the invention are schematically shown in each figure, and they do not represent the actual structure of the product. In addition, in order to simplify the drawings and facilitate understanding, in some figures, only one of the parts with the same structure or function is schematically drawn or marked. In this article, "one" not only means "only one", but also means "more than one".

[0042] It should be further understood that the term “and / or” used in the specification and appended claims refers to any combination and all possible combinations of one or more of the associated listed items, and includes these combinations.

[0043] In this document, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, or it can be the internal communication of two components. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0044] In a specific implementation, the terminal device described in the embodiments of the present application includes, but is not limited to, other portable devices such as mobile phones, laptop computers, tutoring machines, or tablet computers with touch-sensitive surfaces (e.g., touch screen displays and / or touch pads). It should also be understood that in some embodiments, the terminal device is not a portable communication device, but a desktop computer with a touch-sensitive surface (e.g., touch screen displays and / or touch pads).

[0045] In addition, in the description of the present application, the terms "first", "second", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance.

[0046] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the specific implementation methods of the present application will be described below with reference to the accompanying drawings. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings and other implementation methods can be obtained based on these drawings without creative work.

[0047] The interrupt controller (EXTI) module of a microcontroller (MCU) is often referred to as the "external interrupt / event controller". It is responsible for managing the external interrupt and event circuits of the microcontroller, and can detect changes in external signals, such as changes in the level of the interface to be tested, and generate interrupts or events based on these changes, so that the microcontroller can respond to external signals or events.

[0048] Each interrupt / event line has an edge detector that can be set to rising edge trigger, falling edge trigger, or both edge triggers. Through configuration, a specific interface to be tested can be used as an interrupt input, and then the corresponding processing logic is executed in the interrupt service program. This mechanism is very important for embedded system applications that need to respond quickly to changes in external signals.

[0049] The GPIO (General-purpose input / output) of a microcontroller is an important interface for the microcontroller to interact with the outside world. When used as a test interface, the GPIO port can be configured as input mode, output mode or analog mode to meet different application requirements.

[0050] The interfaces under test are the physical connection points on the microcontroller, while the interface peripherals are the internal hardware logic and registers that control the behavior of these interfaces. Interface peripherals allow developers to configure the functions of the interfaces under test through programming, thereby achieving communication and control with external devices.

[0051] Interrupt Request Test usually refers to the process of verifying the functionality and responsiveness of the interrupt system during software and hardware development. An interrupt request (IRQ) is a signal in a computer system or embedded system that indicates that a hardware device or software event requires the processor to perform an interrupt. The purpose of testing this mechanism is to ensure that when an external or internal event triggers an interrupt request, the system can correctly respond and execute the corresponding interrupt service routine (ISR).

[0052] In the prior art, when testing the interrupt request function of a target microprocessor chip, it is necessary to test each interface to be tested in turn to see whether it can generate a normal interrupt request event. Pin switching is usually performed by manually plugging and unplugging the DuPont line. This testing method is not only inefficient but also prone to errors. Due to human interference, it is difficult to troubleshoot when an error occurs.

[0053] In order to solve this problem. This application adds a multi-channel multiplexer analog switch to the test circuit to replace the function of manually plugging and unplugging the switching pins, perform fully automatic testing and judge the test results. Since there is no human interference in the test, human factors are eliminated. The test results are automatically generated and summarized by the script, which can quickly locate the test problems.

[0054] An embodiment of an automatic traversal test circuit provided by the present application includes a multiplexer.

[0055] The multiplexer includes N test pins, and the total number N of the test pins is the same as the number of test interfaces of the chip under test, so that the chip under test forms a multi-channel connection with the multiplexer.

[0056] The multiplexer also includes at least one first control interface and a selection input terminal. The first control interface changes its true value state under the action of the first control instruction, thereby controlling the selection input terminal to select the path corresponding to the target test pin to be turned on.

[0057] Specifically, the multiplexer / demultiplexer device is used to implement the analog switch function. One channel is selected to be turned on at the same time, and each channel is connected to the interface to be tested of the MCU. When one channel is selected to be turned on, it can be understood that the current interface to be tested provides an edge, and the other pins are still in the default state. By switching the level of the control interface in the multiplexer, the automatic switching function of the pin can be realized. Thereby realizing the automatic traversal test of GPIO as EXTI source.

[0058] Another embodiment of an automatic traversal test circuit of the present application, based on the above embodiment of an automatic traversal test circuit, includes at least one multiplexer, and each multiplexer is connected in parallel.

[0059] The number of test pins on each multiplexer is evenly distributed, and the total number of test pins N remains unchanged.

[0060] Specifically, if there is only one multiplexer in the circuit, N test pins are provided on the multiplexer. If there are two multiplexers in the circuit, N / 2 test pins are provided on each multiplexer. N is generally an even number. In the present application, the number of multiplexers in the test circuit can be set to multiple, and can be adapted to various models and chips to be tested with different numbers of pins. In the case of multiple multiplexers, the test circuit in the present application also includes a drive circuit module, which selects one of the multiplexers to be turned on based on the true value state of the control interface in the drive circuit module; and then based on the true value state of the control interface in the multiplexer, the path corresponding to one of the test pins can be selected to be turned on. The selection and switching of the channel is completed. In actual use scenarios, selecting an appropriate number of multiplexers can effectively reduce the production cost of the test circuit and has a wider range of applications.

[0061] Another embodiment of an automatic traversal test circuit of the present application, based on the above embodiment of an automatic traversal test circuit, further comprises: a driving circuit module. The output end of the driving circuit module is connected to the selection input end of the multiplexer.

[0062] The driving circuit module includes at least one second control interface and at least one transistor. The second control interface turns the transistor on or off under the action of the second control instruction, thereby controlling the opening or closing of at least one multiplexer.

[0063] Specifically, the driving circuit outputs a driving signal to each multiplexer, and the corresponding selection input terminal receiving the driving signal of 0 is turned on, that is, the corresponding multiplexer is turned on. The corresponding selection input terminal receiving the driving signal of 1 is not turned on, that is, the corresponding multiplexer is turned off. When testing the chip to be tested, each interface to be tested needs to be tested one by one. Therefore, in the case of multiple multiplexers, only one multiplexer is turned on each time the test is performed. The others are all turned off.

[0064] Another embodiment of the method of the present application is based on an embodiment of any of the above-mentioned automatic traversal test circuits. Optionally, in this embodiment, an automatic traversal test circuit includes: a driving circuit module and two multiplexers. The output terminals X0 and X1 of the driving circuit module are connected to the selection input terminal X of the multiplexer. Figure 1 shown.

[0065] The chip to be tested is an MCU chip, which includes 16 test interfaces to be tested, namely PB0 to PB15. The driving circuit module includes a second control interface PA4 and two transistors Q1 and Q2.

[0066] The second control interface PA4 is connected to the base of the transistor Q1 through the resistor R2, the collector of the transistor Q1 is connected to the first output terminal X0, and the emitter is grounded. The base of the transistor Q2 is connected to the collector of the transistor Q1 through the resistor R3, the collector is connected to the second output terminal X1, and the emitter is grounded. The forward voltage of 5V is connected to the collector of the transistor Q1 through the resistor R1 and to the collector of the transistor Q2 through the resistor R2.

[0067] The second control interface PA4 is high or low level under the second control instruction, so that the transistors Q1 and Q2 are turned on or off, thereby controlling the opening or closing of the selection input terminal X of the multiplexer. Further controlling the opening or closing of the multiplexer. Specifically, the transistors Q1 and Q2 shown in the figure are both triodes. In other embodiments, the triodes can also be replaced by MOS tubes.

[0068] The number of test pins in the two multiplexers U1 and U2 is the same, so that the chip to be tested forms a multi-path connection with the multiplexer. Each multiplexer also includes three first control interfaces PA0, PA1, PA2 and a selection input terminal X. The first control interfaces PA0, PA1, PA2 change their true value states under the action of the first control instruction, thereby controlling the selection input terminal X to select the path corresponding to the target test pin to be turned on.

[0069] Specifically, Figure 1 In the example, the first multiplexer U1 is connected in parallel with the second multiplexer U2. The first multiplexer U1 includes test pins P0-P7, and the second multiplexer U2 includes test pins P8-P15. The total number of test pins is 16, which is the same as the number of test interfaces of the chip under test. Use Dupont wires to connect the test pins P0-P15 of the multiplexer to the test interfaces PB0-PB15 of the chip under test one by one. For specific wiring, refer to the attached manual. Figure 2 .

[0070] The following is an example of the logic of path switching, in one implementation of this embodiment:

[0071] When the second control interface PA4=0, the transistor Q1 is turned off, the first output terminal X0 of the driving circuit module is 1, and the first multiplexer U1 is turned off. The transistor Q2 is turned on, the second output terminal X1 of the driving circuit module is 0, and the second multiplexer U2 is turned on.

[0072] When the second multiplexer U2 is turned on, the P8-P15 channels and the selection input terminal X are sequentially connected through the logic combination of the first control interfaces: PA0, PA1, and PA2.

[0073] When the second control interface PA4=1, the transistor Q1 is turned on, the first output terminal X0 of the driving circuit module is 0, and the first multiplexer U1 is turned on. The transistor Q2 is turned off, the second output terminal X1 of the driving circuit module is 1, and the second multiplexer U2 is turned off.

[0074] When the first multiplexer U1 is turned on, the P0-P7 channels and the selection input terminal X are sequentially connected by controlling the logical combination of the first control interfaces: PA0, PA1, and PA2.

[0075] Set the first control interface: the channel conduction truth table of PA0, PA1, PA2 is as follows:

[0076]

[0077] The control of the second multiplexer U2 is the same as the above table.

[0078] In another implementation of the above embodiment, the control interfaces (PA0, PA1, PA2, PA4) in the test circuit are all connected to some IO interfaces of the MCU, and receive the first control instruction or the second control instruction from the MCU to implement channel switching.

[0079] It should be noted that all the pins of the MCU include not only 16 test interfaces (PB0-PB15) and 4 IO interfaces for connecting control interfaces (PA0, PA1, PA2, PA4). It also includes power pins, clock pins, and several control pins. The test interfaces are not all the pins of the chip to be tested. The number of test interfaces is determined by the model of the specific chip to be tested. This application does not specifically limit its number.

[0080] The number of control interfaces is determined based on the number of interfaces to be tested and the number of multiplexers. As long as the channel switching function of all interfaces to be tested can be realized. In different usage scenarios, the number of control interfaces can be changed, and this application does not specifically limit its number.

[0081] The multiplexer further includes a positive power supply voltage pin VDD connected to a +5V power supply, and a negative power supply voltage pin VEE and a ground terminal VSS connected to the ground.

[0082] The selection input terminal is connected to an enable voltage. When the selection input terminal is turned on and connected to the target test pin, the path corresponding to the target test pin is turned on. Optionally, in this embodiment, the input voltage of the selection input terminal X is 3.3V. When the target channel is connected to the selection input terminal X, a rising edge will be generated on the interface to be tested corresponding to the target channel. When the channel is switched, a falling edge will be generated in the current channel. In this way, the generation of any edge can be satisfied. Since the connected channel is connected to the selection input terminal X, the selection input terminal X can also input other waveforms, and the connected channel is also the same wave as the selection input terminal X, which is used for testing other peripheral functions. Therefore, as long as there is a need for pin traversal switching, this method can be used to automatically switch pins, thereby realizing functional tests that depend on different pins.

[0083] Based on the same technical concept, the present application also discloses an automatic traversal test device, see the attached manual for details. Figure 3 The test circuit includes any one of the above embodiments, and further includes a base and a chip to be tested.

[0084] like Figure 3 The PC is used for monitoring and issuing commands. The test device is used to execute specific commands, and Python is used to realize the interaction between the test device and the PC.

[0085] In this embodiment, the test device is composed of B1 and B2 modules. The B1 module only contains the chip to be tested, and B2 is the main test circuit. The B1 and B2 modules are connected through a base.

[0086] For the chip to be tested, use a pin header to lead out all the pins. The number of pins can be as many as possible and inserted into the socket through a socket (test base) or a daughter board to be compatible with the testing of chips with different pins or different packages.

[0087] Specifically, the chip test socket is used to test and verify the performance of the integrated circuit chip, and is a bridge connecting the test equipment and the chip to be tested. Its main functions include signal transmission, thermal management, mechanical support, and programmability. This module leads out all the pins of the chip to be tested, and the pin spacing designed after the lead-out is a universal spacing, which is convenient for adapting to the different pin spacings of different chips.

[0088] Usually, a single pin point-to-point operation can be completed using a robotic arm, but for testing a small number of samples, it is overkill and wastes resources. The circuit design in this application only requires a few devices to complete. Since all pins are brought out, they are compatible with different pin numbers and packages. Therefore, it not only reduces material costs, but also improves reusability.

[0089] The B2 module includes the test circuit in any of the above embodiments, including a basic drive circuit module and a multiplexer module. This module is used to test the interface to be tested as a trigger source for the interrupt controller, and modules such as UART and I2C will occupy the interface resources of the chip, so there is no need to use a communication module for data transmission in this module. Instead, data transmission is performed through j-link, including transmission of trigger information.

[0090] In this application, the J-link debugger is used to send and receive data. J-link integrates a segger_rtt (Real-Time Transfer) tool for real-time information transmission. This tool is different from the existing communication module. It does not occupy the communication interface of the chip under test and can save communication interfaces similar to UART. At the same time, it will not affect the real-time behavior of the chip under test. The J-Link device can realize direct read and write operations on the MCU registers and realize information transmission and reception with the upper terminal.

[0091] In other embodiments, the test circuit B2 further includes a housing, a signal light, etc. The housing is mainly used to resist external loads and protect the internal test circuit. The signal light can display the current state of the test device, such as operation, standby, failure, or test completion. Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

[0092] Based on the same technical concept, the present application also discloses an interrupt request test method, which is implemented based on the automatic traversal test device in any of the above embodiments. Figure 4 Shown: Included:

[0093] S1. Write a test case template for the interrupt controller. Obtain the configuration file for each interface to be tested. Combine the test case template with the configuration file and use the script to generate all test cases corresponding to all interfaces to be tested.

[0094] S2. Automatically download individual test cases to the chip under test, start and run the test script, and obtain the test results of the corresponding interface under test within the preset test time.

[0095] S3. Control the pin switching of the test circuit based on the test case.

[0096] S4. The J-Link debugger sends the test results to the upper terminal, which summarizes the test results to obtain a final test report.

[0097] Specifically, the configuration file of each interface to be tested is obtained from the production data manual of the chip to be tested. The test case includes the case title, preconditions, test steps and expected results.

[0098] Specifically, a test case is a set of test inputs, execution conditions, and expected results compiled for a specific purpose in order to test a program path or verify whether a specific requirement is met. The test case title is a number or name that uniquely identifies a test case. Preconditions are conditions that must be met before the test case is executed, such as specific software or hardware configuration, database status, user permissions, etc. The test steps include detailed operation steps, including input data, user actions, system responses, etc. These steps should be clear and repeatable. The expected result is the expected system behavior or output result after executing the test steps. Optionally, the test case also includes: specific data that needs to be used during the test, which should be able to cover normal conditions as well as boundary conditions and abnormal conditions. And test priorities, etc.

[0099] Optionally, Python scripts are used in this application to achieve automatic testing and automatic summary and analysis of results. Test cases are edited through Python, and J-Link is used to read and write MCU. When the test is completed, Python scripts are used to analyze and summarize the test results. In this process, all test processes and results are processed using Python, so there is no need to involve data conversion between different tools.

[0100] Use Python scripts to obtain the actual output test results observed after running the corresponding script to actually execute the test steps. Compare with the expected results to determine whether the test of the current interface is successful or failed.

[0101] Based on an interrupt request test method in the above embodiment, the present application also discloses another embodiment of the method, Figure 5 As shown: Specifically including:

[0102] 1. Write EXTI functional test case set, write test case templates, and special configuration files for different examples, and use scripts to generate and test all test cases.

[0103] 2. Use the script to automatically download a single test file to the target MCU to start and run.

[0104] 3. Run the test script to control the pin switching of the above circuit diagram, read the test flag within a certain period of time, determine the test results and record them.

[0105] 4. After the pin is switched, repeat steps 2-3 until all test cases are completed.

[0106] 5. Summarize the test results and distribute them to testers.

[0107] The debugger used in this solution is J-Link, which integrates a segger_rtt (Real-Time Transfer) tool for real-time information transmission. This tool will not affect the real-time behavior of the target chip and can also save communication interfaces such as UART.

[0108] Integrate the segger_rtt function in the test case and set the program running output information. This information will be used as the judgment basis for the current test case and also as the trigger signal for subsequent test steps.

[0109] In this solution, there is only one system, and there is no functional system or target test system, so there is no question of whether there will be problems in the communication between the two systems. This makes it easier to quickly locate the problem.

[0110] The present application also discloses another embodiment of the method, which exemplifies the contents of the above embodiments and specifically includes:

[0111] The 15 pins of GPIOB can all be used as trigger sources for EXTO and generate interrupt functions.

[0112] The analysis function shows that the GPIO clock enable is a variable, so the template file and parameter configuration file are very simple. You only need to switch the corresponding clock. Use the python file to fill the configuration file parameters into the template file, and then start the execution file to generate a downloadable binary file.

[0113] In the Python script file, first download the executable file to the target MCU, then start the channel switching function, and implement single channel switching by configuring PA0, PA1, PA2, and PA4. Use the pylink driver to implement direct read and write operations on the MCU registers through the J-Link device.

[0114] For example, in the test case, all GPIOB pins are configured as rising edge triggered interrupts, and the current trigger interrupt pin is determined in the interrupt handling function, and this pin number is written in the specified memory in the non-code area, and then the test script polls, determines the results and switches the channel pins.

[0115] When PA0-PA2 in the test script is configured as 000, if PB0 can be used as an EXTI trigger source, the MCU will detect that a rising edge trigger interrupt has occurred on PB0, and write 00 to the specified memory. The test script polls and reads the specified memory in the MCU within the specified time. If the data read within the specified time is 00, the test passes. If it is within the specified time, or the read data is not 00, the test fails. After the test fails, PB0 is turned on again to provide a rising edge for PB0. And continue to judge the results. Regardless of whether it fails or succeeds this time, the channel is switched. Test the subsequent channels in sequence.

[0116] In this application, a multi-channel multiplexer analog switch is added to the test circuit, and the channel corresponding to the target test pin can be selected to be turned on based on the true value state of its control interface, thereby replacing the function of manually plugging and unplugging the switching pin.

[0117] Only one line is connected at a time. All pins can be connected at one time, and the pins can be automatically switched. There is no need to switch pins by plugging and unplugging DuPont wires. Manual plugging and unplugging may cause problems such as missing pins, which reduces losses and saves time, improves efficiency, and saves labor resources. Use scripts to automatically analyze data results to avoid omissions and errors in manual analysis.

[0118] Based on the same concept, the present application also discloses an automatic traversal test system, including a memory, a processor and a computer program stored in the memory, and the processor executes the computer program to implement the steps of the automatic traversal test method in any of the above embodiments.

[0119] Specifically, the present application provides an embodiment of an automatic traversal test system, which includes:

[0120] The test case generation module is used to write the test case template for the interrupt controller. Obtain the configuration file of each interface to be tested. Combine the test case template with the configuration file and use the script to generate all test cases corresponding to all interfaces to be tested. The configuration file of each interface to be tested is obtained from the production data manual of the chip to be tested. The test case includes the case title, preconditions, test steps and expected results.

[0121] The test case running module is used to automatically download individual test cases to the chip under test, start and run the test script, and obtain the test results of the corresponding interface under test within the preset test time.

[0122] The test case module is used to control the pin switching of the test circuit based on the test case.

[0123] The result summary module is used to obtain the test results of all interfaces to be tested, summarize the test results and send them to the upper terminal through the J-link debugger.

[0124] The automatic traversal test circuit, device, interrupt request test method and system of the present application have the same technical concept, and the technical details of the four embodiments are applicable to each other. In order to reduce repetition, they will not be repeated here.

[0125] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, only the division of the above-mentioned program modules is used as an example for illustration. In actual applications, the above-mentioned functions can be assigned to different program modules as needed, that is, the internal structure of the device can be divided into different program units or modules to complete all or part of the functions described above. The program modules in the embodiment can be integrated into a processing unit, or each unit can exist physically separately, or two or more units can be integrated into a processing unit, and the above-mentioned integrated unit can be implemented in the form of hardware or in the form of software program units. In addition, the specific names of the program modules are only for the convenience of distinguishing each other, and are not used to limit the scope of protection of this application.

[0126] Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

Claims

1. An automatic traversal test circuit, characterized in that: Includes multiplexer; The multiplexer includes N test pins, and the total number N of the test pins is the same as the number of test interfaces of the chip to be tested; so that the chip to be tested forms a multi-channel connection with the multiplexer; The multiplexer also includes at least one first control interface and a selection input terminal; the first control interface changes its true value state under the action of the first control instruction, thereby controlling the selection input terminal to select the path corresponding to the target test pin to be turned on.

2. An automatic traversal test circuit as claimed in claim 1, characterized in that: The number of the multiplexers is at least one, and the multiplexers are connected in parallel; The number of the test pins on each of the multiplexers is evenly distributed; the total number N of the test pins remains unchanged.

3. An automatic traversal test circuit as claimed in claim 2, characterized in that: The test circuit further comprises: a driving circuit module; an output end of the driving circuit module is connected to a disable input end of the multiplexer; The driving circuit module includes at least one second control interface and at least one transistor; the second control interface turns on or off the transistor under the action of a second control instruction, thereby controlling the opening or closing of at least one of the multiplexers.

4. An automatic traversal test circuit as claimed in any one of claims 1 to 3, characterized in that: The multiplexer also includes a positive power supply voltage pin and a negative power supply voltage pin; The selection input terminal is connected to an enable voltage; when the selection input terminal is turned on and connected to a target test pin, a path corresponding to the target test pin is turned on.

5. An automatic traversal test device, characterized in that: include: The test circuit according to any one of claims 1 to 4, further comprising: a base, and a chip to be tested; All pins of the chip to be tested are led out by a pin arrangement device so as to connect the chip to be tested with the test circuit through the base.

6. An automatic traversal test device as claimed in claim 5, characterized in that: The chip under test includes an interrupt controller, which is set to be triggered by a specified edge; the interface under test of the chip under test is connected to an interface peripheral; the interface peripheral controls the corresponding interface under test as a trigger source of the interrupt controller to generate an interrupt input; The N test pins in the test circuit are connected to the interface to be tested of the chip to be tested in sequence; the path corresponding to the target test pin is selected to be turned on, so as to test whether the interface to be tested connected to the target test pin can enable the interrupt controller to generate a normal interrupt request.

7. An automatic traversal test device as claimed in claim 5 or 6, characterized in that: Also includes: J-link debugger; The J-link debugger is connected to the test circuit to realize direct reading and writing of registers in the chip under test, and data transmission and reception between the chip under test and an upper-level terminal.

8. An interrupt request testing method, characterized in that: The test method is implemented based on the test device described in any one of claims 5 to 7; comprising: Write a test case template for the interrupt controller; obtain a configuration file for each interface to be tested; combine the test case template with the configuration file, and use a script to generate all test cases corresponding to all interfaces to be tested; Automatically download the test cases to the chip to be tested, start and run the test script; obtain the test results of the corresponding interface to be tested within the preset test time; Controlling pin switching of the test circuit based on the test case; The J-Link debugger sends the test results to the upper terminal, which summarizes them to obtain a final test report.

9. An interrupt request testing method as claimed in claim 8, characterized in that: The configuration file of each interface to be tested is obtained from the production data manual of the chip to be tested; the test case includes a case title, preconditions, test steps and expected results.

10. An automatic traversal test system, characterized in that: The invention comprises a memory, a processor and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the testing method according to claim 8 or 9.

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