Integrated circuit, method and electronic device for distributing interrupt signal

Abstract

The invention provides an integrated circuit, a method and electronic equipment for distributing interrupt signals. The integrated circuit comprises at least one interrupt mask unit and at least one interrupt distribution unit in one-to-one correspondence with the interrupt mask unit, each interrupt mask unit acquires at least one interrupt signal generated by at least one interrupt source in the system on chip, and determines to transmit the at least one interrupt signal to the interrupt distribution unit corresponding to the interrupt mask unit based on pre-stored identification information; and each interrupt distribution unit determines target hardware corresponding to each interrupt signal based on operation information of at least one piece of hardware in the system on chip, and transmits the interrupt signal to the target hardware. The interrupt mask unit determines whether to continue to transmit the interrupt signal to the interrupt distribution unit based on the identification information, and the interrupt distribution unit determines the target hardware by using the interrupt signal and the operation information of the hardware, so that the target hardware suitable for processing the interrupt signal can be determined, and the interrupt signal can be processed in time.

Description

Technical Field

[0001] The present disclosure relates to the technical field of integrated circuits, and in particular to an integrated circuit, method and electronic device for distributing interrupt signals. Background Art

[0002] With the development of computer technology, the application of system-on-chip is becoming more and more extensive. In addition, in order to improve the ability of system-on-chip to process tasks in parallel, a single system-on-chip is usually equipped with multiple processor cores. Each processor core is used to implement different functions, such as the safety braking function in the autonomous driving system or the intelligent navigation function in the cockpit system. However, when multiple hardware implement different functions, different interrupt signals will be continuously generated, but how to achieve efficient processing of multiple interrupt signals has become a solution that needs to be solved urgently. Summary of the invention

[0003] In order to solve the above technical problems, the present disclosure provides an integrated circuit, a method and an electronic device for distributing an interrupt signal.

[0004] According to a first aspect of the present disclosure, an integrated circuit for distributing an interrupt signal is provided, the integrated circuit comprising:

[0005] At least one interrupt mask unit, and at least one interrupt distribution unit corresponding one-to-one to the interrupt mask unit;

[0006] Each of the interrupt mask units is used to obtain at least one interrupt signal generated by at least one interrupt source in the system on chip, and based on pre-stored identification information, determine to transmit at least one of the interrupt signals to an interrupt distribution unit corresponding to the interrupt mask unit;

[0007] Each of the interrupt distribution units is used to determine the target hardware corresponding to each interrupt signal based on the operation information of at least one hardware in the system on chip and at least one interrupt signal, and transmit at least one interrupt signal to the target hardware corresponding to the interrupt signal.

[0008] A second aspect of the present disclosure provides a method for distributing an interrupt signal, the method comprising:

[0009] Each interrupt mask unit in the integrated circuit obtains at least one interrupt signal generated by at least one interrupt source in the system on chip, and determines to transmit at least one of the interrupt signals to an interrupt distribution unit corresponding to the interrupt mask unit based on pre-stored identification information;

[0010] Each interrupt distribution unit in the integrated circuit determines the target hardware corresponding to each interrupt signal based on the operation information of at least one hardware in the system on chip and at least one interrupt signal, and transmits at least one interrupt signal to the target hardware corresponding to the interrupt signal.

[0011] A third aspect of the present disclosure provides an electronic device, comprising: the integrated circuit for distributing interrupt signals as described in the first aspect;

[0012] or, a processor;

[0013] a memory for storing instructions executable by the processor;

[0014] The processor is used to read the executable instructions from the memory and execute the instructions to enable the integrated circuit to execute the method for distributing interrupt signals described in the second aspect.

[0015] Through the solution provided by the embodiment of the present disclosure, the interrupt signal generated by the interrupt source can be transmitted to the target hardware, that is, the distribution of the interrupt signal is realized.

[0016] Furthermore, in the process of distributing interrupt signals, the interrupt mask unit in the integrated circuit determines whether it is necessary to transmit the received interrupt signal to the interrupt distribution unit corresponding to the interrupt mask unit based on the pre-stored identification information; the interrupt mask unit in the integrated circuit determines whether to continue transmitting the interrupt signal to the interrupt distribution unit based on the pre-stored identification information. In addition, after receiving the interrupt signal, the interrupt distribution unit will comprehensively utilize the interrupt signal and the operating information of the hardware in the integrated circuit to determine the target hardware corresponding to the interrupt signal. Therefore, the cooperation of the interrupt mask unit and the interrupt distribution unit included in the integrated circuit disclosed in the embodiment of the present disclosure helps to determine the target hardware suitable for processing the interrupt signal, thereby processing the interrupt signal in a timely manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 The present invention is a circuit structure diagram of the prior art.

[0018] Figure 2 It is a circuit structure diagram of an integrated circuit for distributing interrupt signals provided by an exemplary embodiment of the present disclosure.

[0019] Figure 3 4 is a schematic diagram of a circuit structure of an integrated circuit for distributing interrupt signals provided by another exemplary embodiment of the present disclosure.

[0020] Figure 4 4 is a schematic diagram of a circuit structure of an integrated circuit for distributing interrupt signals provided by another exemplary embodiment of the present disclosure.

[0021] Figure 5 4 is a schematic diagram of a circuit structure of an integrated circuit for distributing interrupt signals provided by another exemplary embodiment of the present disclosure.

[0022] Figure 6 It is a flowchart of a method for distributing interrupt signals provided by an exemplary embodiment of the present disclosure.

[0023] Figure 7 It is a schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION

[0024] To explain the present disclosure, example embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all of the embodiments. It should be understood that the present disclosure is not limited to the example embodiments.

[0025] It should be noted that the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure unless specifically stated otherwise.

[0026] Application Overview

[0027] Currently, a system on chip usually has multiple processor cores, so that a system on chip can execute multiple tasks simultaneously through multiple processor cores, improving the ability of the system on chip to process tasks in parallel. However, how to efficiently handle multiple interrupt signals generated during the execution of multiple tasks by multiple processing cores is a technical problem that needs to be solved urgently.

[0028] Generally, see Figure 1 As shown in the circuit diagram, in order to realize the interruption of the system on chip, the current system on chip generally includes at least one interrupt source 100 for generating an interrupt signal. In addition, the system on chip also includes at least one interrupt processing unit 200 corresponding to the interrupt source 100, and each interrupt processing unit 200 may include at least one hardware 210, and the hardware 210 may be a processor core.

[0029] The interrupt source 100 is used to generate an interrupt signal, and after generating the interrupt signal, the interrupt source 100 transmits the interrupt signal to the corresponding interrupt processing unit 200. After receiving the interrupt signal, the interrupt processing unit 200 processes the interrupt signal through the hardware included in the interrupt processing unit 200.

[0030] However, in Figure 1 In the structure shown, the interrupt source 100 may transmit an interrupt signal to any one or more processor cores in each interrupt processing unit 200, and some of the processor cores may not be able to process the interrupt signal, resulting in the interrupt signal not being processed in time.

[0031] For example, if there are multiple pending tasks waiting to be processed by a processor core, the processor core may process the interrupt signal only after processing the multiple pending tasks. However, the processor core takes time to process the multiple pending tasks, resulting in the interrupt signal not being processed in time.

[0032] Or, in another case, the operating system of the processor core that receives the interrupt signal is incompatible with the operating system of the interrupt signal. For example, in a cabin-and-cockpit integrated scenario, the cockpit system and the autonomous driving system of the vehicle are integrated, and the operating system running on a certain processor core is the operating system corresponding to the autonomous driving system, and the interrupt signal received by the processor core needs to be processed by the processor core running the operating system corresponding to the cockpit system. Therefore, the processor core cannot process the interrupt signal, and the interrupt source 100 needs to generate an interrupt signal again and transmit the interrupt signal to other processor cores running the operating system corresponding to the cockpit system so that the interrupt signal can be processed.

[0033] In order to solve the problem in the prior art that interrupt signals cannot be processed in a timely manner, the present disclosure provides an integrated circuit, method and electronic device for distributing interrupt signals to improve the timeliness of processing interrupt signals by a system on chip.

[0034] Exemplary Systems

[0035] The embodiment of the present disclosure provides an integrated circuit, method and electronic device for distributing interrupt signals. The integrated circuit for distributing interrupt signals is arranged in a system on chip to improve the timeliness of the system on chip in processing interrupt signals.

[0036] See also Figure 2 As shown in the circuit structure diagram, the integrated circuit includes an interrupt source 100 and an interrupt processing unit 200. The interrupt source 100 is used to generate an interrupt signal, so the interrupt source 100 can also be called an interrupt generating module.

[0037] Each interrupt processing unit 200 includes at least one hardware 210, and the hardware 210 is used to process the interrupt signal. In a feasible implementation, the hardware 210 is a processor core. Generally, the security level of at least one processor core included in the same interrupt processing unit 200 is usually the same. In addition, the processor cores included in the same interrupt processing unit 200 can run the same operating system or different operating systems.

[0038] Furthermore, as the functions of the SoC become more powerful, a SoC can support running multiple operating systems, which can run on different processor cores of the SoC so that different processor cores can perform corresponding functions. For example, in a cabin-driver integration scenario, the vehicle's cockpit system and autonomous driving system are integrated, and different processor cores in the vehicle's SoC can respectively perform safety braking functions in the autonomous driving system, as well as intelligent navigation functions in the cockpit system.

[0039] If a certain interrupt processing unit 200 includes at least two processor cores, the at least two processor cores may run the same operating system, or the at least two processor cores may run different operating systems. For example, if a certain interrupt processing unit 200 includes n processor cores, the first processor core to the mth processor core may run a first operating system, and the m+1th processor core to the nth processor core may run a second operating system, the first operating system and the second operating system are two different operating systems, m and n are both positive integers, and m is less than n.

[0040] The integrated circuit provided by the embodiment of the present disclosure further includes at least one interrupt mask unit 310, and at least one interrupt distribution unit 320 corresponding to the interrupt mask unit 310. After generating at least one interrupt signal, at least one interrupt source 100 may transmit the at least one interrupt signal to the interrupt mask unit 310, and the interrupt mask unit 310 determines to transmit the at least one interrupt signal to the interrupt distribution unit 320 corresponding to the interrupt mask unit 310 based on the pre-stored identification information. Each interrupt distribution unit 320 determines the target hardware 210 corresponding to each interrupt signal based on the operation information of at least one hardware in the system on chip and at least one interrupt signal, and transmits at least one interrupt signal to the target hardware 210 in the interrupt processing unit 200, so that the target hardware 210 processes the interrupt signal after receiving the interrupt signal, thereby realizing the distribution of the interrupt signal.

[0041] Through the solution provided by the embodiment of the present disclosure, it is possible to determine the target hardware 210 suitable for processing the interrupt signal with the cooperation of the interrupt mask unit 310 and the interrupt distribution unit 320, so that the interrupt signal can be processed by the target hardware. Compared with the prior art, the solution provided by the embodiment of the present disclosure can process the interrupt signal in a timely manner.

[0042] Exemplary Devices

[0043] Figure 2 FIG. 1 is a schematic diagram of a structure of an integrated circuit for distributing interrupt signals provided by an exemplary embodiment of the present disclosure. Figure 2The integrated circuit includes: at least one interrupt mask unit 310, and at least one interrupt distribution unit 320 corresponding to the interrupt mask unit 310. Figure 2 In the figure, the portion marked by the dotted frame is the integrated circuit for distributing the interrupt signal provided by the embodiment of the present disclosure.

[0044] Each interrupt mask unit 310 is used to obtain at least one interrupt signal generated by at least one interrupt source 100 in the system on chip, and based on pre-stored identification information, determine to transmit the at least one interrupt signal to the interrupt distribution unit 320 corresponding to the interrupt mask unit 310 .

[0045] In the present disclosure, the interrupt mask unit 310 may pre-store identification information, which corresponds to the interrupt source 100 and is used to indicate whether the interrupt signal generated by the interrupt source 100 is allowed to be transmitted to the interrupt distribution unit 320 corresponding to the interrupt mask unit 310 .

[0046] In a feasible implementation, the identification information includes two types, namely, a first identification and a second identification. Among them, if the interrupt signal generated by a certain interrupt source 100 does not need to be transmitted by the interrupt mask unit 310 to the corresponding interrupt distribution unit 320, the interrupt mask unit 310 pre-stores the identification information corresponding to the interrupt source 100 as the first identification; if the interrupt signal generated by a certain interrupt source 100 needs to be transmitted by the interrupt mask unit 310 to the corresponding interrupt distribution unit 320, the interrupt mask unit 310 pre-stores the identification information corresponding to the interrupt source 100 as the second identification.

[0047] Each interrupt distribution unit 320 is used to determine the target hardware 210 corresponding to each interrupt signal based on the operation information of at least one hardware 210 in the system on chip and at least one interrupt signal, and transmit at least one interrupt signal to the target hardware 210 corresponding to the interrupt signal.

[0048] The hardware 210 includes hardware capable of processing interrupt signals. Exemplarily, the hardware 210 may include a processor core.

[0049] The embodiment of the present disclosure provides an integrated circuit for distributing interrupt signals, the integrated circuit includes at least one interrupt mask unit 310, and at least one interrupt distribution unit 320 corresponding to the interrupt mask unit 310; each interrupt mask unit 310 obtains at least one interrupt signal generated by at least one interrupt source 100 in the system on chip, and based on the pre-stored identification information, determines to transmit the at least one interrupt signal to the interrupt distribution unit 320 corresponding to the interrupt mask unit 310; each interrupt distribution unit 320 determines the target hardware 210 corresponding to each interrupt signal based on the operation information of at least one hardware 210 in the system on chip and at least one interrupt signal, and transmits at least one interrupt signal to the target hardware 210 corresponding to the interrupt signal. That is to say, through the integrated circuit provided by the embodiment of the present disclosure, the interrupt signal generated by the interrupt source 100 can be transmitted to the target hardware 210, that is, the distribution of the interrupt signal is realized.

[0050] Furthermore, in the process of distributing interrupt signals in the integrated circuit disclosed in the embodiment of the present disclosure, the interrupt mask unit 310 will determine whether it is necessary to transmit the received interrupt signal to the interrupt distribution unit 320 corresponding to the interrupt mask unit 310 based on the pre-stored identification information, that is, the interrupt mask unit 310 in the integrated circuit will determine whether to continue to transmit the interrupt signal to the interrupt distribution unit 320 based on the pre-stored identification information. In addition, after receiving the interrupt signal, the interrupt distribution unit 320 will comprehensively utilize the interrupt signal and the operation information of the hardware 210 to determine the target hardware 210 corresponding to the interrupt signal. Therefore, the cooperation of the interrupt mask unit 310 and the interrupt distribution unit 320 included in the integrated circuit disclosed in the embodiment of the present disclosure is helpful to determine the target hardware 210 suitable for processing the interrupt signal, which is helpful to improve the timeliness of processing the interrupt signal compared with the prior art.

[0051] In a feasible implementation of the present disclosure, after the interrupt mask unit 310 receives at least one interrupt signal generated by at least one interrupt source 100, it determines to transmit the at least one interrupt signal to the interrupt distribution unit 320 corresponding to the interrupt mask unit 310 based on the pre-stored identification information, and then the interrupt distribution unit 320 determines the target hardware 210 in the interrupt processing unit 200, and the interrupt distribution unit 320 transmits the at least one interrupt signal to the target hardware 210.

[0052] Among them, Figure 2 In the schematic diagram shown, each interrupt mask unit 310 is connected to all interrupt sources 100 . In an actual integrated circuit, each interrupt mask unit 310 may be connected to only some interrupt sources 100 , which is not limited in the present disclosure.

[0053] In addition, Figure 2In the schematic diagram shown, each interrupt distribution unit 320 is connected to all interrupt processing units 200 , and each interrupt mask unit 310 may also be connected to only some interrupt processing units 200 , which is not limited in the present disclosure.

[0054] In another embodiment provided by the present disclosure, the interrupt mask unit 310 is used to determine, based on pre-stored identification information, that at least one interrupt signal is transmitted to the interrupt distribution unit 320 corresponding to the interrupt mask unit 310, including:

[0055] The interrupt mask unit 310 is used to transmit the interrupt signal corresponding to the interrupt source 100 to the interrupt distribution unit 320 corresponding to the interrupt mask unit 310 in response to the identification information corresponding to the at least one interrupt source 100 stored in advance being the first identification;

[0056] The interrupt mask unit 310 is used for stopping transmitting the interrupt signal corresponding to the interrupt source 100 to the interrupt distribution unit 320 corresponding to the interrupt mask unit 310 in response to the identification information corresponding to the stored interrupt source 100 being the second identification.

[0057] In the embodiment of the present disclosure, according to whether the interrupt signal generated by the interrupt source 100 is allowed to be transmitted by the interrupt mask unit 310, identification information corresponding to the interrupt source 100 is pre-stored in the interrupt mask unit 310. The identification information can distinguish which interrupt signals generated by the interrupt source 100 need to be processed and which interrupt signals generated by the interrupt source 100 should be ignored.

[0058] The identification information corresponding to the interrupt source includes a first identification and a second identification. The first identification is used to indicate that the interrupt signal generated by the interrupt source 100 needs to be processed; the second identification is used to indicate that the interrupt signal generated by the interrupt source 100 does not need to be processed. For example, if the identification information corresponding to an interrupt source 100 pre-stored in a certain interrupt mask unit 310 is the first identification, then the interrupt mask unit 310 will transmit the interrupt signal to the interrupt distribution unit 320 corresponding to itself after receiving the interrupt signal transmitted by the interrupt source 100. If the identification information corresponding to a certain interrupt source 100 is the second identification, then the interrupt mask unit 310 will no longer transmit the interrupt signal to the interrupt distribution unit 320 corresponding to itself after receiving the interrupt signal transmitted by the interrupt source 100.

[0059] In a feasible implementation, the first identifier may be 0, and the second identifier may be 1. Of course, the first identifier and the second identifier may also be represented in other forms, which is not limited in the embodiment of the present disclosure.

[0060] Through the solution provided by the embodiment of the present disclosure, the interrupt mask unit 310 can distinguish the interrupt signal that needs to be processed and the interrupt signal that should be ignored based on the identification information corresponding to the pre-stored interrupt source 100, and transmit the interrupt signal that needs to be processed to the corresponding interrupt distribution unit 320, and terminate the transmission of the interrupt signal that should be ignored. In this case, since the interrupt mask unit 310 does not need to continue to transmit the interrupt signal that should be ignored to the interrupt distribution unit 320, the amount of data transmitted by the interrupt mask unit 310 can be reduced, and the energy consumption is correspondingly reduced.

[0061] Furthermore, this embodiment can prevent the interrupt distribution unit 320 from receiving interrupt signals that should be ignored, reduce the interference of interrupt signals that should be ignored on the interrupt distribution unit 320, help the interrupt distribution unit 320 to distribute the interrupt signals that need to be processed as quickly as possible, thereby improving the distribution efficiency of the interrupt signals, and further help the target hardware 210 to receive and process the interrupt signals as quickly as possible, thereby improving the interrupt processing efficiency.

[0062] In a feasible implementation manner of the present disclosure, the interrupt mask unit 310 includes at least one mask register corresponding to the interrupt source 100 , and the mask register is used to store identification information corresponding to the at least one interrupt source 100 .

[0063] In an optional embodiment, the interrupt mask unit 310 may include a mask register. In this case, if each identification information is identified by a bit of data, each bit of identification information stored in the mask register corresponds to an interrupt source 100. For example, the first identification is 0, the second identification is 1, and there are 8 interrupt sources 100, then the mask register includes 8 bits of identification information, wherein the identification information of the 0th bit corresponds to the first interrupt source 100, the identification information of the 1st bit corresponds to the second interrupt source 100, and so on, the identification information of the 7th bit corresponds to the eighth interrupt source 100. According to business requirements, if the interrupt mask unit 310 is required to prohibit the transmission of the interrupt signals generated by the second interrupt source 100 and the fifth interrupt source 100 to the interrupt distribution unit 320, and the interrupt mask unit 310 is required to transmit the interrupt signals generated by other interrupt sources 100 to the interrupt distribution unit 320, the identification information of the 1st and 4th bits can be set to 1, and the identification information of other bits can be set to 0.

[0064] In an optional embodiment, the interrupt mask unit 310 may include n mask registers, where n is a positive integer and n is the number of interrupt sources 100. The identification information stored in the first mask register corresponds to the first interrupt source 100, the identification information stored in the second mask register corresponds to the second interrupt source 100, and so on. The identification information stored in the nth mask register corresponds to the nth interrupt source 100.

[0065] Through the scheme provided by the embodiment of the present disclosure, it is possible to store identification information corresponding to the interrupt source 100 according to at least one mask register corresponding to the interrupt source 100 included in the interrupt mask unit 310, thereby facilitating determination of whether an interrupt signal needs to be transmitted to the interrupt distribution unit 320 based on the identification information stored in the mask register.

[0066] In an optional implementation, the interrupt distribution unit 320 is used to determine the target hardware 210 corresponding to each interrupt signal based on the operation information and interrupt signal of at least one hardware 210 in the system on chip, and transmit the interrupt signal to the target hardware 210 corresponding to the interrupt signal, including:

[0067] The interrupt distribution unit 320 is used to determine the target hardware 210 corresponding to the interrupt signal from at least one hardware 210 based on the operating system information in the running information of at least one hardware 210 in the on-chip system and the target identifier in the interrupt signal, and transmit the interrupt signal to the target hardware 210 corresponding to the interrupt signal.

[0068] An interrupt signal generally includes a target identifier, a type identifier, an interrupt vector, etc. Among them, the target identifier is used to indicate the operating system corresponding to the processing interrupt signal, the type identifier is used to indicate the type of the interrupt signal, such as a hardware interrupt or a software interrupt, etc., and the interrupt vector is used to indicate the entry of the interrupt service routine. In addition, the operation information of the hardware 210 generally includes operating system information for indicating the operating system running on the hardware 210. Furthermore, the operation information of the hardware 210 may also include the load condition of the hardware 210 and / or the number of tasks to be executed, etc., wherein the load condition of the hardware 210 may include the utilization rate, etc.

[0069] The interrupt distribution unit 320 identifies the hardware 210 of the operating system corresponding to the target identifier based on the target identifier in the interrupt signal, so as to respond to the interrupt signal through the hardware 210. For example, in the cabin-to-cabin integrated scenario, if the target identifier in a certain interrupt signal indicates that the interrupt signal needs to be processed by the hardware 210 of the operating system running the automatic driving system, the interrupt distribution unit 320 determines the target hardware 210 that supports the operating system running the automatic driving system from the multiple hardware 210.

[0070] Through the solution of the embodiment of the present disclosure, when determining the target hardware 210 in at least one hardware 210, the interrupt distribution unit 320 comprehensively considers the operation information of multiple hardware 210 and whether each hardware supports the operating system of the interrupt signal based on the operating system corresponding to the target identifier in the interrupt signal, so that the determined target hardware 210 can support processing the interrupt signal. Compared with the prior art, the solution provided by the embodiment of the present disclosure can improve the timeliness of processing the interrupt signal.

[0071] See also Figure 3 As shown in the schematic diagram, in the integrated circuit provided in another embodiment of the present disclosure, the interrupt distribution unit 320 includes: a first interrupt controller 321 and at least one first information register 322. The first information register 322 stores the operation information of at least one hardware 210 in the system on chip, and a mapping table of the correspondence between at least one identifier and the operating system in the operation information of at least one hardware 210.

[0072] In a feasible implementation manner, each interrupt distribution unit 320 includes a first information register 322, and the first information register 322 stores the operation information of all hardware 210 corresponding to the interrupt distribution unit 320. Alternatively, in another feasible implementation manner, each interrupt distribution unit 320 includes a plurality of first information registers 322, and each of the first information registers 322 stores the operation information of one of the hardware 210.

[0073] In the case where the interrupt distribution unit 302 includes a second interrupt controller 323 and at least one second information register 324, the interrupt distribution unit 320 is used to determine the target hardware 210 corresponding to the interrupt signal from at least one hardware 210 based on the operating system information in the running information of at least one hardware 210 in the system-on-chip and the target identifier in the interrupt signal, including: the first interrupt controller 321 is used to determine the target operating system having a corresponding relationship with the target identifier based on the operating system information in the running information of at least one hardware 210 stored in the first information register 322 and the target identifier in the interrupt signal, and based on the mapping table; the first interrupt controller 321 is used to determine at least one hardware 210 running the target operating system based on the target operating system; the first interrupt controller 321 is used to determine the target hardware 210 corresponding to the interrupt signal based on the load condition in the running information of the at least one hardware 210.

[0074] Specifically, since the mapping table is stored in the first information register 322, the first interrupt controller 321 can read the mapping table stored in the first information register 322 after receiving the interrupt signal transmitted by the interrupt mask unit 310, and determine the target operating system having a corresponding relationship with the target identifier included in the interrupt signal based on the mapping table. The target operating system is the operating system adapted to the interrupt signal, that is, the interrupt signal needs to be processed by the hardware 210 running the target operating system.

[0075] Furthermore, since the first information register 322 stores the operating information of at least one hardware 210, and the operating information includes the operating system information running on the hardware 210, the first interrupt controller 321 can determine the operating system running on at least one hardware 210 by accessing the first information register 322. Furthermore, the first interrupt controller 321 can determine at least one hardware 210 running the target operating system from the at least one hardware 210.

[0076] Furthermore, the operation information of at least one hardware 210 stored in the first information register 322 also includes the load condition of the hardware 210. In this case, after determining the at least one hardware 210 running the target operating system, the first interrupt controller 321 can also determine the load condition of at least one hardware 210 running the target operating system by accessing the first information register 322, and then determine the target hardware 210 from the at least one hardware 210 running the target operating system based on the load condition.

[0077] Among them, when the first interrupt controller 321 determines the target hardware 210 from the at least one hardware 210 running the target operating system based on the load condition, it can determine that among the at least one hardware 210 running the target operating system, the m hardware 210 with the smallest load is the target hardware 210, where m is a preset positive integer. If m is 1, the first interrupt controller 321 will select the hardware 210 with the smallest load as the target hardware 210.

[0078] Through the scheme of the embodiment of the present disclosure, the first interrupt controller 321 in the interrupt distribution unit 320 can determine at least one hardware 210 running the target operating system based on the target identifier in the interrupt signal, and then determine the target hardware 210 from the at least one hardware 210 running the target operating system based on the load condition of the hardware 210. Therefore, the operating system running on the target hardware 210 determined by the first interrupt controller 321 corresponds to the target identifier in the interrupt signal, thereby ensuring that the target hardware 210 can process the interrupt signal. Furthermore, the first interrupt controller 321 takes into account the load condition of the hardware 210 when determining the target hardware 210, so the determined target hardware 210 is usually a hardware 210 with a smaller load, thereby further ensuring that the target hardware 210 can process the interrupt signal in a timely manner, that is, further improving the timeliness of processing the interrupt signal.

[0079] The interrupt distribution unit 320 may also be implemented by other structures, see Figure 4As shown in the schematic diagram, in the integrated circuit provided by the embodiment of the present disclosure, the interrupt distribution unit 320 includes: a second interrupt controller 323 and at least one second information register 324. The second information register 324 stores the operation information of at least one hardware 210 in the system on chip, and a mapping table of the correspondence between at least one identifier and the operating system in the operation information of at least one hardware 210.

[0080] In the case where the interrupt distribution unit 302 includes a second interrupt controller 323 and at least one second information register 324, the interrupt distribution unit 320 is used to determine the target hardware 210 corresponding to the interrupt signal from at least one hardware 210 based on the operating system information in the running information of at least one hardware 210 in the system-on-chip and the target identifier in the interrupt signal, including: the second interrupt controller 323 is used to determine the target operating system having a corresponding relationship with the target identifier based on the operating system information in the running information of at least one hardware 210 stored in the second information register 324 and the target identifier in the interrupt signal, and based on a mapping table; the second interrupt controller 323 is used to determine at least one hardware 210 running the target operating system based on the target operating system; the second interrupt controller 323 is used to determine the target hardware 210 corresponding to the interrupt signal based on the number of tasks to be executed in the running information of the at least one hardware 210.

[0081] In one embodiment, since a mapping table is stored in the second information register 324, after receiving the interrupt signal transmitted by the interrupt mask unit 310, the second interrupt controller 323 can read the mapping table stored in the second information register 324, and based on the mapping table, determine the target operating system that has a corresponding relationship with the target identifier included in the interrupt signal.

[0082] Furthermore, since the second information register 324 stores the operating information of at least one hardware 210, and the operating information includes the operating system information running on the hardware 210, the second interrupt controller 323 can determine the operating system running on at least one hardware 210 by accessing the second information register 324. Furthermore, the second interrupt controller 323 can determine at least one hardware 210 running the target operating system from at least one hardware 210.

[0083] Furthermore, the operation information of at least one hardware 210 stored in the second information register 324 also includes the number of tasks to be executed of the hardware 210. In this case, after determining the at least one hardware 210 running the target operating system, the second interrupt controller 323 can also determine the number of tasks to be executed of the at least one hardware 210 running the target operating system by accessing the second information register 324, and then determine the target hardware 210 from the at least one hardware 210 running the target operating system based on the number of tasks to be executed.

[0084] When the second interrupt controller 323 determines the target hardware 210 from at least one hardware 210 running the target operating system based on the number of tasks to be executed, it can determine s hardware 210 with the least number of tasks to be executed as the target hardware 210, where s is a preset positive integer. If s is 1, the second interrupt controller 323 will select a hardware 210 with the least number of tasks to be executed as the target hardware 210.

[0085] Through the scheme of the embodiment of the present disclosure, the second interrupt controller 323 in the interrupt distribution unit 320 can determine at least one hardware 210 running the target operating system based on the target identifier in the interrupt signal, and then determine the target hardware 210 from the at least one hardware 210 running the target operating system based on the tasks to be executed of the hardware 210. Therefore, the operating system running on the target hardware 210 determined by the second interrupt controller 323 corresponds to the target identifier in the interrupt signal, thereby ensuring that the target hardware 210 can process the interrupt signal. Furthermore, when the second interrupt controller 323 determines the target hardware 210, the number of tasks to be executed of the hardware 210 is taken into consideration, so the determined target hardware 210 is usually the hardware 210 with a small number of tasks to be executed, thereby further ensuring that the target hardware 210 can process the interrupt signal in a timely manner, that is, further improving the timeliness of processing the interrupt signal.

[0086] In another embodiment of the present disclosure, the interrupt distribution unit 320 may include a third interrupt controller and at least one third information register.

[0087] The third information register stores the operation information of at least one hardware 210 in the system on chip, and a mapping table of the correspondence between at least one identifier and the operating system in the operation information of at least one hardware 210.

[0088] In the case where the interrupt distribution unit 302 includes a third interrupt controller and at least one third information register, the interrupt distribution unit 320 is used to determine the target hardware 210 corresponding to the interrupt signal from the at least one hardware 210 based on the operating system information in the running information of the at least one hardware 210 in the system on chip and the target identifier in the interrupt signal, including:

[0089] The third interrupt controller is used to determine a target operating system having a corresponding relationship with the target identifier based on the operating system information in the operation information of at least one hardware 210 in the system on chip and the target identifier in the interrupt signal, and based on the mapping table;

[0090] The third interrupt controller is used to determine at least one target hardware 210 running the target operating system based on the target operating system.

[0091] In this embodiment, since a mapping table is stored in the third information register, after receiving the interrupt signal transmitted by the interrupt mask unit 310, the third interrupt controller can read the mapping table stored in the third information register, and based on the mapping table, determine a target operating system that has a corresponding relationship with the target identifier included in the interrupt signal, and determine at least one hardware 210 running the target operating system as the target hardware 210.

[0092] Through the solution of the embodiment of the present disclosure, the third interrupt controller in the interrupt distribution unit 320 can determine at least one hardware 210 running the target operating system as the target hardware 210 based on the target identifier in the interrupt signal. Therefore, the operating system running on the target hardware 210 determined by the third interrupt controller 323 corresponds to the target identifier in the interrupt signal, thereby ensuring that the target hardware 210 can process the interrupt signal, and correspondingly improving the timeliness of processing the interrupt signal.

[0093] Further, based on the above embodiments, the present disclosure also provides another embodiment. Figure 5 As shown in the schematic diagram, in the integrated circuit provided by the embodiment of the present disclosure, the integrated circuit further includes: at least one register controller 330. Each interrupt distribution unit 320 is used to transmit at least one interrupt signal to the target hardware 210 corresponding to the interrupt signal, including: each interrupt distribution unit 320 is used to transmit at least one interrupt signal to the register controller 330; the register controller 330 is used to transmit at least one interrupt signal to the target hardware 210 corresponding to the interrupt signal.

[0094] On the basis of the above-mentioned embodiments, the integrated circuit of the embodiment of the present disclosure is further provided with at least one register controller 330, and the register controller 330 is provided between the interrupt distribution unit 320 and the hardware 210. After receiving the interrupt signal, the interrupt distribution unit 320 may transmit the interrupt signal to the register controller 330. After receiving the interrupt signal, the register controller 330 may transmit all or part of the received interrupt signal to the target hardware 210, that is, selectively transmit the interrupt signal to the target hardware 210, thereby optimizing the distribution of the interrupt signal.

[0095] In the integrated circuit disclosed in each embodiment of the present disclosure, after an interrupt source 100 generates an interrupt signal, it is possible to simultaneously transmit the same interrupt signal to multiple interrupt mask units 310, thereby causing multiple interrupt mask units 310 to receive the same interrupt signal at the same time or at a relatively close time, and further, it may cause multiple interrupt distribution units 320 to receive the same interrupt signal at the same time or at a relatively close time.

[0096] In view of this situation, the register controller 330 is used to transmit at least one interrupt signal to the target hardware 210 corresponding to the interrupt signal, including:

[0097] The register controller 330 is used to receive multiple interrupt signals transmitted by multiple interrupt distribution units 320 within a target duration;

[0098] The register controller 330 is configured to transmit at least one of the same interrupt signals to the target hardware 210 corresponding to the interrupt signal when it is determined that the multiple interrupt signals are the same and the target hardware 210 corresponding to the interrupt signals are the same.

[0099] In one embodiment, if the register controller 330 receives multiple interrupt signals transmitted by multiple interrupt distribution units 320 within the target duration, and the multiple interrupt signals are the same, and the target hardware 210 corresponding to the interrupt signals are the same, it indicates that the register controller 330 receives multiple identical interrupt signals in a relatively short period of time, and the target hardware 210 corresponding to the multiple identical interrupt signals determined by the interrupt distribution unit 320 are the same. In this case, the register controller 330 selects to transmit at least one of the identical interrupt signals to the target hardware 210 corresponding to the interrupt signal, that is, it selects some of the interrupt signals to be transmitted to the target hardware 210, thereby avoiding the target hardware 210 from receiving and processing multiple identical interrupt signals in a relatively short period of time, which can correspondingly reduce the number of interrupt signals processed by the target hardware 210, reduce the operations performed by the target hardware 210, and correspondingly reduce the power consumption of the target hardware 210.

[0100] Exemplary Methods

[0101] The following is a method embodiment of the present disclosure, which can be applied to an integrated circuit for executing the distribution of interrupt signals provided by the above-mentioned various embodiments of the present disclosure. For details not disclosed in the method embodiment of the present disclosure, please refer to the circuit embodiment of the present disclosure.

[0102] The present disclosure embodiment discloses a method for distributing interrupt signals, see Figure 6 The workflow diagram shown in FIG. 1 includes the following steps:

[0103] Step 201, each interrupt mask unit in the integrated circuit obtains at least one interrupt signal generated by at least one interrupt source in the system on chip, and determines to transmit the at least one interrupt signal to an interrupt distribution unit corresponding to the interrupt mask unit based on pre-stored identification information;

[0104] In step 202, each interrupt distribution unit in the integrated circuit determines the target hardware corresponding to each interrupt signal based on the operation information of at least one hardware in the system on chip and at least one interrupt signal, and transmits at least one interrupt signal to the target hardware corresponding to the interrupt signal.

[0105] In a feasible implementation, the interrupt mask unit of the integrated circuit performs an operation of determining, based on pre-stored identification information, to transmit at least one interrupt signal to an interrupt distribution unit corresponding to the interrupt mask unit, including:

[0106] The interrupt mask unit transmits an interrupt signal corresponding to the interrupt source to an interrupt distribution unit corresponding to the interrupt mask unit in response to the identification information corresponding to the at least one interrupt source stored in advance being the first identification;

[0107] In response to the identification information corresponding to the stored interrupt source being the second identification, the interrupt mask unit stops transmitting the interrupt signal corresponding to the interrupt source to the interrupt distribution unit corresponding to the interrupt mask unit.

[0108] Exemplarily, the interrupt mask unit includes at least one mask register corresponding to an interrupt source, and the mask register is used to store identification information corresponding to the at least one interrupt source.

[0109] In a feasible implementation, an interrupt distribution unit in an integrated circuit determines target hardware corresponding to each interrupt signal based on operation information and an interrupt signal of at least one hardware in a system on chip, and transmits the interrupt signal to the target hardware corresponding to the interrupt signal, including:

[0110] The interrupt distribution unit determines the target hardware corresponding to the interrupt signal from at least one hardware based on the operating system information in the operation information of at least one hardware in the system on chip and the target identifier in the interrupt signal;

[0111] The interrupt distribution unit transmits the interrupt signal to target hardware corresponding to the interrupt signal.

[0112] The interrupt distribution unit can be implemented in a variety of ways. In a feasible implementation, the interrupt distribution unit includes: a first interrupt controller and at least one first information register;

[0113] The first information register stores operation information of at least one hardware in the system on chip, and a mapping table of the correspondence between at least one identifier and the operating system in the at least one hardware operation information;

[0114] The interrupt distribution unit determines the target hardware corresponding to the interrupt signal from at least one hardware based on the operating system information in the running information of at least one hardware in the system on chip and the target identifier in the interrupt signal, including:

[0115] The first interrupt controller determines a target operating system having a corresponding relationship with the target identifier based on the operating system information in the operation information of at least one hardware stored in the first information register and the target identifier in the interrupt signal, and based on the mapping table;

[0116] The first interrupt controller determines, based on the target operating system, at least one hardware running the target operating system;

[0117] The first interrupt controller determines the target hardware corresponding to the interrupt signal based on the load condition in the operation information of at least one hardware.

[0118] In another feasible implementation, the interrupt distribution unit includes: a second interrupt controller and at least one second information register;

[0119] The second information register stores operation information of at least one hardware in the system on chip, and a mapping table of the correspondence between at least one identifier and the operating system in the at least one hardware operation information;

[0120] The interrupt distribution unit determines the target hardware corresponding to the interrupt signal from the at least one hardware based on the operating system information in the running information of the at least one hardware in the system on chip and the target identifier in the interrupt signal, including:

[0121] The second interrupt controller determines a target operating system corresponding to the target identifier based on the operating system information in the operation information of the at least one hardware stored in the second information register and the target identifier in the interrupt signal, and based on the mapping table;

[0122] The second interrupt controller determines, based on the target operating system, at least one hardware running the target operating system;

[0123] The second interrupt controller determines the target hardware corresponding to the interrupt signal based on the number of tasks to be executed in the operation information of at least one hardware.

[0124] Furthermore, the integrated circuit also includes: at least one register controller.

[0125] In this case, each interrupt distribution unit transmits at least one interrupt signal to the target hardware corresponding to the interrupt signal, including:

[0126] Each interrupt distribution unit transmits at least one interrupt signal to the register controller;

[0127] The register controller transmits at least one interrupt signal to target hardware corresponding to the interrupt signal.

[0128] In a feasible implementation, the register controller transmits at least one interrupt signal to target hardware corresponding to the interrupt signal, including:

[0129] The register controller receives a plurality of interrupt signals transmitted by a plurality of interrupt distribution units within a target duration;

[0130] When it is determined that the multiple interrupt signals are the same and the target hardware corresponding to the interrupt signals are the same, the register controller transmits at least one of the same interrupt signals to the target hardware corresponding to the interrupt signal.

[0131] Through the method provided by the embodiment of the present disclosure, the interrupt signal generated by the interrupt source can be transmitted to the target hardware, that is, the distribution of the interrupt signal is realized. Furthermore, in the process of distributing the interrupt signal, the interrupt mask unit in the integrated circuit will determine whether it is necessary to transmit the received interrupt signal to the interrupt distribution unit corresponding to the interrupt mask unit based on the pre-stored identification information, that is, the interrupt mask unit in the integrated circuit will determine whether to continue to transmit the interrupt signal to the interrupt distribution unit based on the pre-stored identification information. In addition, after receiving the interrupt signal, the interrupt distribution unit will comprehensively utilize the interrupt signal and the operating information of the hardware to determine the target hardware corresponding to the interrupt signal. Therefore, with the cooperation of the interrupt mask unit and the interrupt distribution unit included in the integrated circuit disclosed in the embodiment of the present disclosure, it is helpful to determine the target hardware suitable for processing the interrupt signal, so as to process the interrupt signal in time.

[0132] Exemplary Electronic Devices

[0133] The present disclosure provides an electronic device that can be used in a vehicle, such as an intelligent networked car. The electronic device can be, for example, an on-board computing device, an on-board computing platform, an on-board computing unit, an intelligent driving computing platform, etc.

[0134] In one embodiment, the electronic device may include an integrated circuit for distributing interrupt signals provided in an embodiment of the present disclosure, and the integrated circuit may run at least two operating systems, such as an intelligent driving system and a cockpit system, to implement relevant functions of the cabin-cockpit integrated system.

[0135] In one embodiment, the electronic device may further include:

[0136] The housing is used to accommodate and install various hardware units of the electronic equipment, protect the various hardware units from being affected by dust and water, and improve the reliability of the electronic equipment.

[0137] The power module is used to supply power to various hardware units of the electronic device.

[0138] The heat dissipation module, such as a heat dissipation fan, a liquid cooling device, etc., is used to dissipate heat for the hardware units of the electronic equipment, reduce the operating temperature of each hardware unit, and improve the operating stability of each hardware unit.

[0139] External interfaces are used to connect various sensors on the vehicle, such as cameras, lidar, millimeter-wave radar, ultrasonic radar, etc., to transmit instructions to each sensor or receive data sent back by the sensor. External interfaces can also be connected to various actuators of the vehicle, such as the drive system, brake system, steering system, etc., to transmit control instructions to each system and receive feedback from each system.

[0140] Another embodiment of the present disclosure provides an electronic device, see Figure 7 As shown in the structural diagram, the electronic device 11 includes at least one processor 111 and a memory 112.

[0141] The processor 111 may be a central processing unit or other forms of processing units having data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device 11 to perform desired functions.

[0142] The memory 112 may include one or more computer program products, which may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, flash memory, etc. One or more processor 112 executable instructions may be stored on the memory 112, and the processor 111 may run one or more executable instructions to enable the integrated circuit to implement the interrupt signal distribution method and / or other desired functions of the various embodiments of the present disclosure described above.

[0143] In one example, the electronic device 11 may further include: an input device 113 and an output device 114 , and these components are interconnected via a bus system and / or other forms of connection mechanisms (not shown).

[0144] The input device 113 may also include, for example, a keyboard, a mouse, etc. Exemplarily, the interrupt source may generate an interrupt signal according to the operation received by the keyboard, the mouse, etc., and the integrated circuit may execute the method for distributing the interrupt signal provided by the above-mentioned embodiments of the present disclosure.

[0145] The output device 114 can output various information to the outside, and may include, for example, a display, a speaker, a printer, a communication network and its connected remote output devices, etc.

[0146] Of course, to simplify, Figure 7 Only some of the components related to the present disclosure in the electronic device 11 are shown, and components such as a bus, an input / output interface, etc. are omitted. In addition, according to specific application situations, the electronic device 11 may also include any other appropriate components.

[0147] Exemplary computer program products and computer-readable storage media

[0148] In addition to the above-mentioned methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, which, when executed by a processor, enable the processor to execute the steps in the method for distributing interrupt signals according to various embodiments of the present disclosure described in the above-mentioned "Exemplary Method" section of this specification.

[0149] The computer program product may be written in any combination of one or more programming languages ​​to write program code for performing the operations of the disclosed embodiments, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0150] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium having computer program instructions stored thereon, which, when executed by a processor, enables the processor to execute the steps of the method for distributing interrupt signals according to various embodiments of the present disclosure described in the above “Exemplary Method” section of this specification.

[0151] Computer readable storage media can adopt any combination of one or more readable media. The readable medium can be a readable signal medium or a readable storage medium. The readable storage medium can include, for example, but is not limited to, a system, device or device of electricity, magnetism, light, electromagnetic, infrared, or semiconductor, or any combination of the above. More specific examples (non-exhaustive list) of readable storage media include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical memory device, a magnetic memory device, or any suitable combination of the above.

[0152] The basic principles of the present disclosure are described above in conjunction with specific embodiments. However, it should be noted that the advantages, strengths, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, strengths, effects, etc. are required by each embodiment of the present disclosure. In addition, the specific details disclosed above are only for the purpose of illustration and ease of understanding, and are not limitations. The above details do not limit the present disclosure to the necessity of adopting the above specific details to be implemented.

[0153] The block diagrams of the devices, apparatuses, equipment, and systems involved in this disclosure are only illustrative examples and are not intended to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As will be appreciated by those skilled in the art, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "including," "comprising," "having," and the like are open words, referring to "including but not limited to," and can be used interchangeably therewith. The words "or" and "and" used herein refer to the words "and / or," and can be used interchangeably therewith. The word "such as" used herein refers to the phrase "such as but not limited to," and can be used interchangeably therewith.

[0154] It should also be noted that in the apparatus, device and method of the present disclosure, each component or each step can be decomposed and / or recombined. Such decomposition and / or recombination should be regarded as equivalent solutions of the present disclosure.

[0155] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein may be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

[0156] The above description has been given for the purpose of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the forms disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, changes, additions and sub-combinations thereof.

Claims

1. An integrated circuit for distributing an interrupt signal, the integrated circuit comprising: At least one interrupt mask unit, and at least one interrupt distribution unit corresponding one-to-one to the interrupt mask unit; Each of the interrupt mask units is used to obtain at least one interrupt signal generated by at least one interrupt source in the system on chip, and based on pre-stored identification information, determine to transmit at least one of the interrupt signals to an interrupt distribution unit corresponding to the interrupt mask unit; Each of the interrupt distribution units is used to determine the target hardware corresponding to each interrupt signal based on the operation information of at least one hardware in the system on chip and at least one interrupt signal, and transmit at least one interrupt signal to the target hardware corresponding to the interrupt signal.

2. The integrated circuit according to claim 1, wherein: The interrupt mask unit is used to determine, based on pre-stored identification information, that at least one of the interrupt signals is transmitted to an interrupt distribution unit corresponding to the interrupt mask unit, including: The interrupt mask unit is used for transmitting the interrupt signal corresponding to the interrupt source to the interrupt distribution unit corresponding to the interrupt mask unit in response to the identification information corresponding to the at least one interrupt source stored in advance being the first identification; The interrupt mask unit is used for terminating the transmission of the interrupt signal corresponding to the interrupt source to the interrupt distribution unit corresponding to the interrupt mask unit in response to the identification information corresponding to the stored interrupt source being the second identification.

3. The integrated circuit according to claim 1, wherein: The interrupt mask unit includes at least one mask register corresponding to an interrupt source, and the mask register is used to store identification information corresponding to the at least one interrupt source.

4. The integrated circuit according to claim 1, wherein: The interrupt distribution unit is used to determine the target hardware corresponding to each interrupt signal based on the operation information of at least one hardware in the system on chip and the interrupt signal, and transmit the interrupt signal to the target hardware corresponding to the interrupt signal, including: The interrupt distribution unit is used to determine the target hardware corresponding to the interrupt signal from the at least one hardware based on the operating system information in the running information of the at least one hardware in the system on chip and the target identifier in the interrupt signal; The interrupt distribution unit is used to transmit the interrupt signal to the target hardware corresponding to the interrupt signal.

5. The integrated circuit according to claim 4, wherein: The interrupt distribution unit includes: a first interrupt controller and at least one first information register; The first information register stores the operation information of at least one of the hardware in the system on chip, and a mapping table of the correspondence between at least one identifier and the operating system in the at least one of the hardware operation information; The interrupt distribution unit is used to determine the target hardware corresponding to the interrupt signal from the at least one hardware based on the operating system information in the running information of the at least one hardware in the system on chip and the target identifier in the interrupt signal, including: The first interrupt controller is used to determine a target operating system having a corresponding relationship with the target identifier based on the operating system information in the operation information of at least one of the hardware stored in the first information register and the target identifier in the interrupt signal, and based on the mapping table; The first interrupt controller is used to determine at least one hardware running the target operating system based on the target operating system; The first interrupt controller is used to determine the target hardware corresponding to the interrupt signal based on the load condition in the operation information of the at least one hardware.

6. An integrated circuit according to claim 4 or 5, wherein: The interrupt distribution unit includes: a second interrupt controller and at least one second information register; The second information register stores the operation information of at least one of the hardware in the system on chip, and a mapping table of the correspondence between at least one identifier and the operating system in the at least one of the hardware operation information; The interrupt distribution unit is used to determine the target hardware corresponding to the interrupt signal from the at least one hardware based on the operating system information in the running information of the at least one hardware in the system on chip and the target identifier in the interrupt signal, including: The second interrupt controller is used to determine a target operating system having a corresponding relationship with the target identifier based on the operating system information in the operation information of at least one of the hardware stored in the second information register and the target identifier in the interrupt signal, and based on the mapping table; The second interrupt controller is used to determine at least one hardware running the target operating system based on the target operating system; The second interrupt controller is used to determine the target hardware corresponding to the interrupt signal based on the number of tasks to be executed in the operation information of the at least one hardware.

7. The integrated circuit according to claim 1, wherein: The integrated circuit further comprises: at least one register controller; Each of the interrupt distribution units is used to transmit at least one of the interrupt signals to the target hardware corresponding to the interrupt signal, including: Each of the interrupt distribution units is used to transmit at least one of the interrupt signals to the register controller; The register controller is used to transmit at least one of the interrupt signals to target hardware corresponding to the interrupt signal.

8. The integrated circuit according to claim 7, wherein: The register controller is used to transmit at least one of the interrupt signals to target hardware corresponding to the interrupt signal, including: The register controller is used for receiving a plurality of the interrupt signals transmitted by a plurality of the interrupt distribution units within a target duration; The register controller is used for transmitting at least one of the same interrupt signals to the target hardware corresponding to the interrupt signal when it is determined that the multiple interrupt signals are the same and the target hardware corresponding to the interrupt signals are the same.

9. A method for distributing an interrupt signal, the method comprising: Each interrupt mask unit in the integrated circuit obtains at least one interrupt signal generated by at least one interrupt source in the system on chip, and determines to transmit at least one of the interrupt signals to an interrupt distribution unit corresponding to the interrupt mask unit based on pre-stored identification information; Each interrupt distribution unit in the integrated circuit determines the target hardware corresponding to each interrupt signal based on the operation information of at least one hardware in the system on chip and at least one interrupt signal, and transmits at least one interrupt signal to the target hardware corresponding to the interrupt signal.

10. An electronic device comprising: An integrated circuit for distributing interrupt signals as claimed in any one of claims 1 to 8; or, The electronic device comprises: processor; a memory for storing instructions executable by the processor; The processor is configured to read the executable instructions from the memory and execute the instructions to enable the integrated circuit to execute the method for distributing interrupt signals as claimed in claim 9.

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