Method, device and equipment for obtaining interested edge cutting time sequence path and storage medium

Abstract

The invention discloses a method, device and equipment for obtaining an interested edge cutting time sequence path and a storage medium, and relates to the field of netlist files. Analyzing the netlist file, and establishing a delayed network topology structure among the ports according to a hardware circuit structure; determining an initial node and an interested cut edge of the time sequence path, and tracing and marking the interested cut edge according to the netlist file of the memory; starting to trace from the starting node of each divided FPGA and the selected interested cut edge, and recording the maximum path and delay for reaching the ending node and the next interested cut edge; and obtaining permutation and combination of paths of all interested edge cutting, screening out a target time sequence path which passes through the most edge cutting times, and printing out a path report containing the target edge cutting path. According to the scheme, through a method of taking out the full path of the interested cut edge, only one worst condition is reserved in the FPGA internal time sequence path between the cut edges, the concept of an original key time sequence path is replaced, the calculation amount is reduced, and the purpose of obtaining all time sequence paths can be achieved.

Description

Technical Field

[0001] Embodiments of the present application relate to the field of netlist files, and in particular, to a method, apparatus, device, and storage medium for obtaining an edge cutting timing path of interest. Background Art

[0002] In chip design and FPGA development, hardware engineers design circuits by writing VHDL, and then generate EDIF netlist-level files, i.e., netlist files, through synthesis. The netlist files then need to be functionally verified. In the IC verification stage, users can choose Simulator (software simulator) or Emulator (hardware simulation accelerator) to perform functional simulation. In order to increase the speed of verification convergence, Emulator is increasingly becoming the first choice for IC verification teams. As the scale of chips continues to increase, the single-chip FPGA component resources can no longer accommodate the entire design under test (DUT), and it is necessary to split the original netlist into multiple FPGAs for functional simulation.

[0003] In the related art, the Hypergraph Partitioning technology is used to perform functional simulation on the entire DUT. The hypergraph is a description of the original netlist. The node of the graph is an original device or a collection of multiple original devices, and the edge of the graph is the net that connects the original devices. The goal of the hypergraph partitioning program is to have as few cut edges as possible and as high a clock operating frequency as possible under the conditions of satisfying various external constraints after the partitioning program. As mentioned in the paper "Multi-objective Circuit Partitioning for Cutsize and Path-Based DelayMinimization", only considering the minimum number of cut edges without considering the length of the timing path may lead to a longer delay, resulting in a lower operating frequency of the entire system. The related technology is to obtain the first K timing paths with the largest delay, only look at the first K timing paths, or through an iterative method, and wait until the next time to take out the first K timing paths with the largest delay, to ensure that the delay in the original design is the largest, and the delay of the timing path after the partitioning program will not be too bad. However, this method only looks at the first K paths, which can only ensure that the first K timing paths with the largest delay are not too bad, without considering that the original timing paths with small delays may become the worst after being cut. The iterative method of taking the first K paths will reduce the program running speed, and the iterative method may have the problem of not being able to converge. Summary of the invention

[0004] The embodiments of the present application provide a method, apparatus, device and storage medium for obtaining an edge cutting timing path of interest, which solves the problem that related technologies cannot exhaust all timing paths and improve simulation efficiency.

[0005] In one aspect, the present application provides a method for obtaining an edge cutting timing path of interest, the method comprising:

[0006] Analyze the edf netlist file and establish the network topology structure of the delay between each port according to the hardware circuit structure;

[0007] Determine the starting node and interested edges of the timing path in the network topology, and trace and mark the interested edges according to the EDF netlist file in the memory;

[0008] Start tracing back from the start node of each partitioned FPGA and the selected interested cut edge, and record the maximum path and delay to the end node and the next interested cut edge;

[0009] Trace the entire network topology to obtain all path combinations of interest in the edge cutting, filter out the target timing path that passes the most edge cutting times, and print out a path report containing the target edge cutting path.

[0010] Specifically, the starting node includes the register clk port of each timing path, and the ending node includes the register D port of each timing path; the interested cut edge is the cut edge connection between different FPGAs in the network topology structure of the hypergraph.

[0011] Specifically, the tracing starts from the starting node of each partitioned FPGA and the selected interested cut edge, and records the maximum path and delay to reach the end node or the next interested cut edge, including:

[0012] Determine all the interested cut edges according to the divided FPGA structure, and number the starting nodes and the interested cut edges respectively;

[0013] Select the starting node or the interested cut edge of each partitioned FPGA in sequence as the tracing starting point according to the numbering sequence, and use the interested cut edge or the output node of the network topology structure that reaches the next partitioned FPGA as the tracing end point, and trace back along the register input and output relationship;

[0014] During the tracing process, the accumulated delay when tracing back to each node of the partitioned FPGA is recorded, and the output delay path with the maximum delay inside each partitioned FPGA is determined.

[0015] Specifically, the tracing process in partitioning FPGA includes:

[0016] According to the number value, trace back the initial traceback starting point, a complete initial delay path, and record the node information passed;

[0017] When tracing back the delay path of the subsequent tracing starting point, the traced node is compared with the historical node of the traced delay path; when tracing back to the same node, the current tracing path and the same delay path are compared with the accumulated delay from their respective tracing starting points to the current same node;

[0018] If the cumulative delay of the current tracing path is not less than the cumulative delay of the path with the same delay, continue to trace back and record the node information; if the cumulative delay of the current tracing path is less than the cumulative delay of the path with the same delay, discard the current tracing path.

[0019] Specifically, when the same tracing starting point includes multiple branch delay paths, first trace the initial branch path number and calculate the branch path delay, then trace the other branch paths respectively according to the principle of the highest delay, and determine the branch path with the highest cumulative delay as the delay path of the current tracing starting point;

[0020] Within the same partitioned FPGA, the delay path with the highest cumulative delay is determined as the output delay path.

[0021] Specifically, tracing back the entire network topology to obtain the path combinations of all interested cut edges includes:

[0022] The interested cut edges formed between the different partitioned FPGAs are spliced ​​according to the topological structure to obtain several timing paths containing the cut edges, and the delay information of each timing path is calculated.

[0023] Specifically, when the interested cut edge reaching the next partitioned FPGA is used as the tracing end point, the delay traced to the end of the interested cut edge is used as the accumulated delay; when tracing to the output node of the network topology, the delay reaching the output node is used as the accumulated delay.

[0024] On the other hand, the present application provides a device for obtaining an edge cutting timing path of interest, the device comprising:

[0025] The analysis module is used to analyze the EDF netlist file and establish the network topology structure of the delay between each port according to the hardware circuit structure;

[0026] A determination module is used to determine the starting node and the interested cutting edge of the timing path in the network topology structure, and trace and mark the interested cutting edge according to the EDF netlist file in the memory;

[0027] A recording module is used to trace back from the starting node of each partitioned FPGA and the selected interested cut edge, and record the maximum path and delay to the end node and the next interested cut edge;

[0028] The output module is used to trace the entire network topology, obtain the path combinations of all interested edge cuts, filter out the target timing path with the most edge cuts, and print out a path report containing the target edge cut path.

[0029] On the other hand, the present application provides a computer device, comprising a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the method for obtaining the cutting edge timing path of interest described in the above aspects.

[0030] On the other hand, the present application provides a computer-readable storage medium, which stores at least one instruction, at least one program, code set or instruction set. The at least one instruction, the at least one program, the code set or instruction set is loaded and executed by a processor to implement the method of obtaining the cutting edge timing path of interest described in the above aspects.

[0031] The beneficial effects brought about by the technical solution provided by the embodiment of the present application include at least the following: when the present application is combined with STA, there is only the delay information data of the DUT, and the number of original devices inside the DUT is particularly large, so it is almost impossible to obtain all the timing paths. When doing the Partition segmentation process, it is necessary to pay attention to all timing paths, and they are all related to edge cutting. The Partition process does not care about all the timing conditions inside each FPGA. In this context, by combining the STA and partition segmentation processes, by taking out the full path of the edge cutting of interest, the internal FPGA timing path between the edge cuttings only needs to retain one worst case scenario, replacing the concept of the original critical timing path, greatly reducing the amount of calculation, thereby achieving the purpose of obtaining all timing paths. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram describing the effect of the number of cut edges on latency proposed in the background technology paper;

[0033] Figure 2 is a flow chart of a method for obtaining an edge cutting timing path of interest provided in an embodiment of the present application;

[0034] Figure 3 A schematic diagram of the network topology after dividing the FPGA structure is shown;

[0035] Figure 4 A possible network topology diagram is shown;

[0036] Figure 5 The network topology diagram inside the same partitioned FPGA is shown;

[0037] Figure 6 A structural block diagram of a device for obtaining an edge cutting timing path of interest is shown;

[0038] Figure 7 A structural block diagram of a computer device provided by an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0039] In order to make the objectives, technical solutions and advantages of the present application clearer, the implementation methods of the present application will be further described in detail below with reference to the accompanying drawings.

[0040] The term "multiple" as used herein refers to two or more than two. "And / or" describes the relationship between related objects, indicating that three relationships can exist. For example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the related objects are in an "or" relationship.

[0041] Figure 1 A schematic diagram describing the effect of the number of cut edges on latency proposed in the background technology paper. Figure 1 The same number of edge cuts (3 times, edge cuts are connections across different FPGAs), the left side a) is cut on the same timing path, while b) is cut on different timing paths. Usually due to hardware resource limitations, edge cutting uses TDM (time-division multiplexing) technology. The delay of each added TDM edge cut will be more than 60ns. This numerical magnitude is much larger than the original internal delay of the DUT, and edge cutting becomes the biggest factor affecting the delay. The existence of multiple edge cuts on the same timing path will cause a large delay. It is necessary to consider allocating the edge cuts to different timing paths as much as possible, and try to avoid multiple edge cuts on the same timing path. This means that the program needs to be segmented as much as possible into the results of b) and not the results of a).

[0042] In order to consider the problem of a timing path not being split too many times (reducing delay), when using hypergraph segmentation, it is necessary to obtain the timing path where each edge is located, and put the paths with more cut edges and larger delay values ​​(i.e., critical paths) on the same FPGA. Or, the stronger the requirement for as few cut edges as possible, the impact of these timing paths is considered during segmentation to avoid this problem.

[0043] Figure 2 : is a flowchart of a method for obtaining an edge cutting timing path of interest provided in an embodiment of the present application, comprising the following steps:

[0044] S1. Analyze the edf netlist file and establish the network topology structure of the delay between each port according to the hardware circuit structure;

[0045] The edf netlist file is a data file produced according to the network topology during the hardware development phase. Computer equipment, etc. can build a network topology based on the hardware circuit structure and parameters read from the netlist file. The network topology can be large or small depending on the size of the system. The larger the system, the more complex the topology, the more port information and connection paths are presented, and the more complex the analysis.

[0046] S2, determine the starting node and the interested cut edge of the timing path in the network topology structure, and trace and mark the interested cut edge according to the edf netlist file in the memory;

[0047] Figure 2 A possible network topology is listed, which usually includes various registers reg and intermediate logic devices. Each register reg contains a single or multiple clk input terminals and output terminals D. The optional netlist file also records the delay information between various input and output nodes during hardware design, such as Figure 2 The delay from point c0 to point clk is 1ns, and the delay from point c1 to point n1 is 565ps. The AT value represents the cumulative delay from the initial position c0 to this point. For example, c0→clk→c1→n1, AT=1000ps+10ps+565ps=1575ps. In this topology, point K1 can be used as the final output point, so it is necessary to calculate the path and delay information from c0→K1 to analyze and optimize the structure of the hardware circuit.

[0048] The application of the full timing path in System Route determines the edge connections that need to be made between FPGAs after the partition splitting process. Different connection methods need to be selected for bypass connection according to the hardware resource conditions between FPGAs, or TDM connection methods are used to achieve edge connection. The delay of bypass direct connection is small, but the number of signals that can be passed will be small. TDM connection has different multiplexing ratios. The higher the multiplexing ratio, the greater the delay of the connection method, and the more signals that can be passed at the same time. The general System route strategy will choose the method with the smallest overall delay (all signals are treated equally and evenly distributed) to make routing connections. If all timing reports are available, the System Route stage can arrange different connection routing methods according to the delay priority of the connection signal to achieve the best performance (maximum operating frequency) of the entire system.

[0049] As the circuit becomes more complex, all timing paths will grow exponentially. General static timing analysis will only retain the worst (largest delay) limited timing paths. In related technologies, when doing static timing analysis (STA), each timing path is extracted based on the circuit routing of the original netlist. The timing path in this article specifically refers to the path from the C end (clock port) of the previous register to the D end (input port) of the next register. This type of timing path is the most common in the circuit, and there will be situations where the program cannot obtain all timing paths.

[0050] However, this application fully considers the impact of edge cutting during design, and learns in advance how the FPGA will be divided after edge cutting. Figure 3 FIG. 4 shows a schematic diagram of the network topology after the FPGA structure is divided, where the entire circuit system is divided into three FPGAs. Then the cutting edge of interest is the connection across the FPGA, such as Figure 3 Among them, n1→n4 is an interesting cut edge, n2→n5 is an interesting cut edge, n3→n8, n6→n7 are also interesting cut edges.

[0051] S3, trace back from the starting node of each partitioned FPGA and the selected interested cut edge, and record the maximum path and delay to the end node and the next interested cut edge;

[0052] The starting node of the system includes the register clk port of each timing path, the ending node includes the register D port of each timing path, and the interested cut edge is the cut edge connection between different FPGAs in the network topology structure of the hypergraph. Figure 3 For FPGA-A, the starting node refers to the c1, c2, and c3 nodes (as input terminals) for tracing. For FPGA-B and FPGA-C, the interested cut edge can also represent the starting point for tracing, but it is calculated in the form of an edge.

[0053] For a certain partitioned FPGA, the internal topology has been analyzed in the early stage, so at this time, only the path with the maximum internal delay needs to be traced. Because an FPGA may contain multiple register circuit structures, multiple paths will be generated. This step is to find the path with the longest delay. In order to take into account the problem of wasting computing power in full search, this application can first use the delay comparison and accumulation method to abandon some paths in time and quickly find the path with the maximum delay.

[0054] S4. Trace back the entire network topology, obtain all path combinations of interest in the edge cutting, select the target timing path that has passed the most edge cutting times, and print out a path report containing the target edge cutting path.

[0055] For independently divided FPGA structures, such as FPGA-A, the tracing stops after tracing to the cut edge of interest. For FPGA structures output at the end of the circuit structure, such as FPGA-C, the tracing ends automatically after tracing to the end node K1. During this period, all traced single delay paths are spliced ​​and combined. After the combination is completed, the target timing path with the most cut edges can be selected and then printed out.

[0056] In summary, when the present application is combined with STA, there is only the delay information data of the DUT. The number of original devices inside the DUT is particularly large, and it is almost impossible to obtain all the timing paths. When doing the Partition segmentation process, it is necessary to pay attention to all timing paths, and they are all related to the cut edges. The Partition process does not care about all the timing conditions inside each FPGA. In this context, by combining the STA and partition segmentation processes, by taking out the full path of the cut edge of interest, the internal FPGA timing path between the cut edges only needs to retain one worst case, replacing the concept of the original critical timing path, greatly reducing the amount of calculation, so as to achieve the purpose of obtaining all timing paths.

[0057] by Figure 3 Taking the segmentation diagram as an example, the following is an introduction and explanation through examples.

[0058] If the original STA process is used as an example:

[0059] Start chasing from point C1:

[0060] After reaching n1, the previous node c1 is recorded, with a maximum delay of 565ps.

[0061] After reaching n4, the previous node n1 is recorded, and the maximum delay is 565ps+572ps=1137ps;

[0062] After reaching n6, the previous node n4 is recorded, and the maximum delay is 1410ps;

[0063] After reaching n7, the previous node n6 is recorded, with a maximum delay of 1529ps.

[0064] Tracing to n9, recording the previous node n7, the maximum delay is 1752ps;

[0065] Catch up to K1, record the previous node n9, and the maximum delay is 2071ps; end.

[0066] Start chasing from point C2:

[0067] After reaching n2, the previous node c2 is recorded, with a maximum delay of 565ps.

[0068] After reaching n5, the previous node n2 is recorded, and the maximum delay is 1354ps;

[0069] Catch up to n6 and record the previous node n5. The maximum delay is 1627ps, which is larger than 1410ps. Update the maximum delay and the previous node.

[0070] Catch up to n7 and record the previous node n6. The maximum delay is 1746ps, which is larger than 1529ps. Update the maximum delay and the previous node.

[0071] Track n9 and record the previous node n7. The maximum delay is 1969ps, which is larger than 1752ps. Update the maximum delay and the previous node.

[0072] Catch up to K1, record the previous node n9, the maximum delay is 2288ns, which is larger than 2071ps, update the maximum delay and the previous node; end.

[0073] Start chasing from point C3:

[0074] After reaching n3, the previous node c3 is recorded, with a maximum delay of 565ps.

[0075] Tracing to n8, recording the previous node n3, the maximum delay is 1017ps;

[0076] After tracing to n9, the previous node n8 is recorded, and the maximum delay is 1240ps, which is smaller than 1969ps. This value is abandoned and tracing stops; end.

[0077] Finally, K1<-n9<-n7<-n6<-n5<-n2<-c2 is recorded. This timing path is the worst timing path. This path only passes through two interesting cut edges, and the other two are directly ignored.

[0078] If this application scheme is used for tracing:

[0079] Start chasing from point C1:

[0080] Catch up to n1, add the record start node c1, the maximum delay is 565ps, it is not the cutting edge of interest, continue.

[0081] Track to n4, add record start node c1, maximum delay 565ps+572ps=1137ps, which is the cutting edge of interest, and end.

[0082] At this time, the memory records one more record, the previous starting node of the n1->n4 cut edge is c1, and the maximum delay is 1137ps.

[0083] Start chasing from point C2:

[0084] Catch up to n2, add record start node c2, the maximum delay is 565ps, it is not the cutting edge of interest, continue.

[0085] Catch up to n5, add record start node c2, the maximum delay is 1354ps, which is the cutting edge of interest, and end.

[0086] At this time, there is one more record in the memory. The previous starting node of the n2->n5 cut edge is c2, and the maximum delay is 1354ps.

[0087] Start chasing from point C3:

[0088] Catch up to n3, add record start node c3, the maximum delay is 565ps, it is not the cutting edge of interest, continue.

[0089] Track to n8, add record start node c3, the maximum delay is 1017ps, which is the cutting edge of interest, and end.

[0090] At this time, there is one more record in the memory. The previous starting node of the n3->n8 edge cut is c3, and the maximum delay is 1017ps.

[0091] Start chasing from the cut edge n1->n4:

[0092] After reaching n6, we added records and started cutting edge n1->n4. The maximum delay was 273ps. We were not interested in cutting edge, so we continued.

[0093] After reaching n7, we added records and started cutting edge n1->n4. The maximum delay was 392ps, which was the cutting edge of interest. We ended.

[0094] At this time, there is one more record in the memory. The previous edge cut of the n6->n7 edge cut is n1->n4, and the maximum delay is 392ps.

[0095] Start chasing from the n2->n5 cut edge:

[0096] After reaching n6, we added records and started cutting edge n2->n5. The maximum delay was 273ps. We were not interested in cutting edge, so we continued.

[0097] After reaching n7, we added records and started cutting edge n2->n5. The maximum delay was 392ps, which was the cutting edge of interest. We ended.

[0098] There is one more record, the previous edge cut of n6->n7 is n2->n5, with a maximum delay of 392ps. At this time, n6->n7 has two records of the previous edge cut.

[0099] Start chasing from the n3->n8 cut edge:

[0100] After reaching n9, we added records and started cutting edge n3->n8. The maximum delay was 223ps. We were not interested in cutting edge, so we continued.

[0101] Catch up to K1, add records and start cutting edge n3->n8, the maximum delay is 542ps, it is not the cutting edge of interest, but the end node, end.

[0102] At this time, there is one more record in the memory. The previous cut edge of the end node K1 is n3->n8, and the maximum delay is 542ps.

[0103] Start chasing from the n6->n7 cut edge:

[0104] After reaching n9, we added records and started cutting edge n6->n7. The maximum delay was 223ps. We were not interested in cutting edge, so we continued.

[0105] Catch up to K1, add records and start cutting edge n6->n7, the maximum delay is 542ps, it is not the cutting edge of interest, but the end node, end.

[0106] At this time, there is one more record in the memory. The previous edge cut of the end node K1 is n6->n7, with a maximum delay of 542ps. At this time, the end node K1 has two records of the previous edge cut.

[0107] It can be calculated from the previous records that all the timing paths passing through the cut edge are:

[0108] K1<-edge cutting (n6->n7)<-edge cutting (n1->n4)<-c1, the delay is 542ps+392ps+1137ps=2071ps, and the number of edge cutting is 2 times.

[0109] K1<-edge cutting (n6->n7)<-edge cutting (n2->n5)<-c2, the delay is 542ps+392ps+1354ps=2288ps, and the number of edge cutting is 2 times.

[0110] K1<-edge cutting (n3->n8)<-c3, the delay is 542ps+1017ps=1559ps, and the number of edge cutting is 1.

[0111] If there are too many cutting edges of interest, resulting in a large report, you can skip printing the report and directly retrieve the timing information (maximum delay information) of the cutting edges of interest from the memory.

[0112] The method is: input the cut edge of interest, such as cut edge (n6->n7), and from the memory information, it can be known that this cut edge appears multiple times. Since the number of cut edges is a decisive factor for the delay in the DUT, it is only necessary to take out the highest value of the DUT delay in the timing paths with the largest number of cut edges. The delay information of the cut edge (n6->n7) is 2288ps + 2 cut edge delays.

[0113] In some embodiments, tracing back from the start node of each partitioned FPGA and the selected interested cut edge, and recording the maximum path and delay to the end node or the next interested cut edge, may specifically include the following steps:

[0114] A, determine all the interested edges according to the divided FPGA structure, and number the starting nodes and the interested edges respectively;

[0115] The numbering here is mainly to distinguish the case of multiple outputs, especially when a partitioned FPGA contains multiple starting output nodes and subsequently connects multiple interested cut edges.

[0116] B. Select the starting node or the interested cut edge of each partitioned FPGA in sequence as the tracing starting point according to the numbering sequence, and use the interested cut edge of the next partitioned FPGA or the output node of the network topology structure as the tracing end point, and trace back along the register input and output relationship;

[0117] C. During the tracing process, the accumulated delay when tracing back to each node of the partitioned FPGA is recorded, and the output delay path with the maximum delay inside each partitioned FPGA is determined.

[0118] Figure 4 A possible network topology diagram is shown, which is divided into two parts: FPGA-D and FPGA-E. From the input and output end, it contains 8 numbered (starting nodes) starting traceback points, four interesting cut edges (e21, e22, e23, e23), and an end node D1. Because there are two FPGAs cascaded front and back, the traceback end point includes four interesting cut edges (relative to FPGA-D) and the end node D1 (relative to FPGA-D or the entire topology output).

[0119] The traceability process can be described as follows:

[0120] 1. Tracing back the initial delay path from the starting point according to the serial number value, and recording the node information passed;

[0121] Assuming that the numbering is traced in the order of C1-C8, the initial traceback starting point is C1, the initial delay path can be expressed as C1→e1→e9→e15→e21→e25, and the node information can be expressed as C1+e1+e9+e15+(e21+e25). The specific delay numbers are omitted in the figure. In particular, when the end point of the traceback is the cut edge of interest that reaches the next partitioned FPGA, the delay traced to the end of the cut edge of interest is used as the accumulated delay; when the traceback is to the output node of the network topology, the delay to the output node is used as the accumulated delay.

[0122] 2. When tracing the delayed path of the subsequent tracing starting point, the traced node is compared with the historical node of the traced delayed path;

[0123] Because the initial delay path of C1 has been determined, the initial delay path is used for comparison when calculating the C2 node. When the traced path delay is higher than the initial delay path, the path must be given priority as the subsequent output path.

[0124] However, considering the complexity of the circuit structure, if the same node is traced back during the C2 tracing process, it is necessary to compare the accumulated delays of the current tracing path and the same delay path from their respective tracing starting points to the current same node.

[0125] Figure 4 e9 is a common node in the traceback paths of C1 and C2, and e21 is a common node in the traceback paths of C3, C1, and C2. Assuming that C1→e1→e9→e15→e21→e25 is used for comparison, when the traceback path of C3 reaches C3→e3→e10→e16→e21, the same node appears, and it is necessary to compare the accumulated delay of C1+e1+e9+e15+e21 with the accumulated delay of C3+e3+e10+e16+e21.

[0126] 3. If the cumulative delay of the current tracing path is not less than the cumulative delay of the path with the same delay, continue to trace back and record the node information; if the cumulative delay of the current tracing path is less than the cumulative delay of the path with the same delay, discard the current tracing path.

[0127] Assuming that the accumulated delay of the current C3 traceback path at the same node e21 is larger, it means that the previous record is not optimal, and the current path will be recorded. On the contrary, if the current recorded delay is smaller, there is no need to trace back further and it can be discarded directly. The rest of the tracebacks are similar.

[0128] Assuming that the same delay is not considered, theoretically this method will find a unique path with the maximum delay in FPGA-D, such as C6→e6→e13→e19→e24→e28.

[0129] If we assume that we use tracing back one by one, it will inevitably lead to

[0130] In particular, for some highly complex network structures, the same starting traceability point may contain multiple traceability paths, such as Figure 5 Shown is the network topology diagram inside the same partitioned FPGA.

[0131] When the same tracing starting point includes multiple branch delay paths, first trace the initial branch path number and calculate the branch path delay, then continue to trace other branch paths separately according to the principle of highest delay, and determine the branch path with the highest cumulative delay as the delay path of the current tracing starting point.

[0132] Figure 5 In the tracing path starting from the starting tracing point C1, an intersection (i.e., the same node) is formed at n1. Theoretically, it can be divided into three paths, namely C1→e1→e2→e5→e7→n1, C1→e1→e3→e10→n1, and C1→e1→e4→e8→e11→n1. At this time, the branches (e2, e3, and e4) can be numbered, and then the delay of the first branch path can be calculated first, and then the second and third branches can be traced back. Based on the above principles, within the same partitioned FPGA, the delay path with the highest cumulative delay is determined as the output delay path.

[0133] After tracing back all the partitioned FPGAs, all possible connection paths are spliced ​​and arranged, and the overall spliced ​​path is all possible complete delay paths, and then the target timing path with the most edge cuts is selected. There are two specific operation schemes here.

[0134] Method 1: Printing a report is required. Starting from the end node, you can trace all the way back to the start node from the list of all edges of interest. Cut the paths with repeated edges, leaving the longest series of paths, which is the entire timing path.

[0135] Method 2: If you do not need to print a report, you can directly fetch data from the memory. You can use the edge of interest as the function input and directly output all timing path combinations from the memory. Starting from this input, trace forward to each previous edge of interest and finally to the start node to obtain a series of paths. Trace backward to the next edge of interest and finally to the end node. All timing paths for this edge of interest are obtained.

[0136] In summary, the beneficial effects brought about by this application include the following:

[0137] The timing path inside the FPGA is replaced with a maximum delay, saving computation and memory usage;

[0138] All paths of the cut edges of interest are recorded, and information on the timing paths of interest will not be lost;

[0139] For segmentation projects that consider timing, taking all the timing paths of interest can provide better guidance for segmentation, thereby increasing the maximum operating frequency of the chip;

[0140] For System Route projects that consider timing, taking all the timing paths of interest can provide better guidance for System Route, thereby increasing the maximum operating frequency of the chip.

[0141] Figure 6 A structural block diagram of a device for obtaining an edge cutting timing path of interest provided in an embodiment of the present application is shown, and the device includes:

[0142] An analysis module 610 is used to analyze the EDF netlist file and establish a network topology structure of delays between ports according to the hardware circuit structure;

[0143] A determination module 620 is used to determine the starting node and the interested cut edge of the timing path in the network topology structure, and trace and mark the interested cut edge according to the EDF netlist file in the memory;

[0144] Recording module 630, used to trace back from the start node of each partitioned FPGA and the selected interested cut edge, and record the maximum path and delay to the end node and the next interested cut edge;

[0145] The output module 640 is used to trace the entire network topology, obtain all paths of interest with cut edges, select the target timing path with the most cut edges, and print out a path report containing the target cut edge path.

[0146] The device for obtaining an edge cutting timing path of interest provided in the embodiment of the present application can be applied to the method for obtaining an edge cutting timing path of interest provided in the above embodiment. For relevant details, refer to the above method embodiment. The implementation principle and technical effect are similar and will not be repeated here.

[0147] It should be noted that the device for obtaining the cutting edge timing path of interest provided in the embodiment of the present application is only illustrated by the division of the above-mentioned functional modules / functional units. In practical applications, the above-mentioned functions can be assigned to different functional modules / functional units as needed, that is, the internal structure of the device for obtaining the cutting edge timing path of interest is divided into different functional modules / functional units to complete all or part of the functions described above. In addition, the implementation method of the method for obtaining the cutting edge timing path of interest provided in the above method embodiment and the implementation method of the device for obtaining the cutting edge timing path of interest provided in this embodiment belong to the same concept. The specific implementation process of the device for obtaining the cutting edge timing path of interest provided in this embodiment is detailed in the above method embodiment, and will not be repeated here.

[0148] Figure 7 The block diagram of a computer device provided by an exemplary embodiment of the present application is shown. It is a computer device such as a desktop computer, a laptop computer, a PDA, and a cloud server. The computer device may include, but is not limited to, a processor and a memory. Among them, the processor and the memory may be connected by a bus or in other ways. Among them, the processor may be a central processing unit (CPU). The processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA) or other programmable logic devices, graphics processors (GPU), embedded neural network processors (NPU) or other dedicated deep learning coprocessors, discrete gates or transistor logic devices, discrete hardware components and other chips, or a combination of the above-mentioned various chips.

[0149] The processor may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The processor may be implemented in at least one hardware form of DSP (Digital Signal Processing), FPGA (Field-Programmable Gate Array), and PLA (Programmable Logic Array). The processor may also include a main processor and a coprocessor. The main processor is a processor for processing data in the awake state, also known as a CPU (Central Processing Unit); the coprocessor is a low-power processor for processing data in the standby state. In some embodiments, the processor may be integrated with a GPU (Graphics Processing Unit), which is responsible for rendering and drawing the content that needs to be displayed on the display screen. In some embodiments, the processor may also include an AI (Artificial Intelligence) processor, which is used to process computing operations related to machine learning.

[0150] As a non-transient computer-readable storage medium, the memory can be used to store non-transient software programs, non-transient computer executable programs and modules, such as program instructions / modules corresponding to the methods in the above-mentioned embodiments of the present application. The processor executes various functional applications and data processing of the processor by running the non-transient software programs, instructions and modules stored in the memory, that is, the method in the above-mentioned method implementation is realized. The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created by the processor, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the processor via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network and a combination thereof.

[0151] In some embodiments, the computer device may further optionally include: a peripheral device interface and at least one peripheral device. The processor, the memory and the peripheral device interface may be connected via a bus or a signal line. Each peripheral device may be connected to the peripheral device interface via a bus, a signal line or a circuit board. Specifically, the peripheral device includes: at least one of a radio frequency circuit, a display screen and a keyboard.

[0152] The peripheral device interface can be used to connect at least one peripheral device related to I / O (Input / Output) to the processor and the memory. In some embodiments, the processor, the memory, and the peripheral device interface are integrated on the same chip or circuit board; in some other embodiments, any one or two of the processor, the memory, and the peripheral device interface can be implemented on a separate chip or circuit board, which is not limited in this embodiment.

[0153] The display screen is used to display the UI (User Interface). The UI may include graphics, text, icons, videos and any combination thereof. When the display screen is a touch screen, the display screen also has the ability to collect touch signals on the surface or above the surface of the display screen. The touch signal can be input to the processor as a control signal for processing. At this time, the display screen can also be used to provide virtual buttons and / or virtual keyboards, also known as soft buttons and / or soft keyboards. In some embodiments, the display screen can be one, arranged on the front panel of the computer device; in other embodiments, the display screen can be at least two, respectively arranged on different surfaces of the computer device or in a folding design; in other embodiments, the display screen can be a flexible display screen, arranged on a curved surface or a folding surface of the computer device. Even, the display screen can be set to a non-rectangular irregular shape, that is, a special-shaped screen. The display screen can be made of materials such as LCD (Liquid Crystal Display), OLED (Organic Light-Emitting Diode) and the like.

[0154] The power supply is used to power various components in the computer device. The power supply can be AC, DC, a disposable battery, or a rechargeable battery. When the power supply includes a rechargeable battery, the rechargeable battery can be a wired rechargeable battery or a wireless rechargeable battery. A wired rechargeable battery is a battery that is charged through a wired line, and a wireless rechargeable battery is a battery that is charged through a wireless coil. The rechargeable battery can also be used to support fast charging technology.

[0155] Those skilled in the art will appreciate that the structure shown in this embodiment does not constitute a limitation on the computer device, and may include more or fewer components than shown in the figure, or combine certain components, or adopt a different component arrangement.

[0156] The embodiment of the present application also discloses a computer-readable storage medium. Specifically, the computer-readable storage medium is used to store a computer program, and when the computer program is executed by the processor, the method in the above-mentioned method implementation is implemented. Those skilled in the art can understand that the implementation of all or part of the process in the above-mentioned implementation method of the present application can be completed by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium, and when the program is executed, it can include the process of the implementation of the above-mentioned methods. Among them, the storage medium can be a disk, an optical disk, a read-only memory (ROM), a random access memory (RAM), a flash memory (Flash Memory), a hard disk (Hard Disk Drive, abbreviated as: HDD) or a solid-state drive (SSD), etc.; the storage medium can also include a combination of the above-mentioned types of memory.

[0157] This specific embodiment is merely an explanation of the present invention and is not a limitation of the present invention. After reading this specification, those skilled in the art may make non-creative modifications to the present embodiment as needed. However, as long as they are within the scope of the claims of the present invention, they are protected by the patent law.

Claims

1. A method for obtaining an interesting edge cutting timing path, characterized in that: The method comprises: Analyze the edf netlist file and establish the network topology structure of the delay between each port according to the hardware circuit structure; Determine the starting node and interested edges of the timing path in the network topology, and trace and mark the interested edges according to the EDF netlist file in the memory; Start tracing back from the start node of each partitioned FPGA and the selected interested cut edge, and record the maximum path and delay to the end node and the next interested cut edge; Trace the entire network topology to obtain all path combinations of interested edge cuts, filter out the target timing path that has passed the most edge cuts, and print out a path report containing the target edge cut paths.

2. The method according to claim 1, characterized in that The starting node includes the register clk port of each timing path, and the ending node includes the register D port of each timing path; the interested cut edge is the cut edge connection between different FPGAs in the network topology structure of the hypergraph.

3. The method according to claim 2, characterized in that The tracing starts from the starting node of each partitioned FPGA and the selected interested cut edge, and records the maximum path and delay to the end node or the next interested cut edge, including: Determine all the interested cut edges according to the divided FPGA structure, and number the starting nodes and the interested cut edges respectively; Select the starting node or the interested cut edge of each partitioned FPGA in sequence as the tracing starting point according to the numbering sequence, and use the interested cut edge or the output node of the network topology structure that reaches the next partitioned FPGA as the tracing end point, and trace back along the register input and output relationship; During the tracing process, the accumulated delay when tracing back to each node of the partitioned FPGA is recorded, and the output delay path with the maximum delay inside each partitioned FPGA is determined.

4. The method according to claim 3, characterized in that: The tracing process in partitioning FPGA includes: According to the number value, trace back the initial traceback starting point, a complete initial delay path, and record the node information passed; When tracing back the delay path of the subsequent tracing starting point, the traced node is compared with the historical node of the traced delay path; when tracing back to the same node, the current tracing path and the same delay path are compared with the accumulated delay from their respective tracing starting points to the current same node; If the cumulative delay of the current tracing path is not less than the cumulative delay of the path with the same delay, continue to trace back and record the node information; if the cumulative delay of the current tracing path is less than the cumulative delay of the path with the same delay, discard the current tracing path.

5. The method according to claim 4, characterized in that When the same tracing starting point includes multiple branch delay paths, first trace the initial branch path number and calculate the branch path delay, then trace the other branch paths separately according to the principle of the highest delay, and determine the branch path with the highest cumulative delay as the delay path of the current tracing starting point; Within the same partitioned FPGA, the delay path with the highest cumulative delay is determined as the output delay path.

6. The method according to claim 1, characterized in that The entire network topology is traced back to obtain the path combinations of all interested cut edges, including: The interested cut edges formed between the different partitioned FPGAs are spliced ​​according to the topological structure to obtain several timing paths containing the cut edges, and the delay information of each timing path is calculated.

7. The method according to any one of claims 3 to 5, characterized in that: When the interested cut edge reaching the next partitioned FPGA is used as the tracing end point, the delay traced to the end of the interested cut edge is used as the accumulated delay; when tracing to the output node of the network topology, the delay reaching the output node is used as the accumulated delay.

8. A device for obtaining an edge cutting timing path of interest, characterized in that: The device comprises: The analysis module is used to analyze the EDF netlist file and establish the network topology structure of the delay between each port according to the hardware circuit structure; A determination module is used to determine the starting node and the interested cut edge of the timing path in the network topology structure, and trace and mark the interested cut edge according to the EDF netlist file in the memory; A recording module is used to trace back from the starting node of each partitioned FPGA and the selected interested cut edge, and record the maximum path and delay to the end node and the next interested cut edge; The output module is used to trace the entire network topology, obtain the path combinations of all interested edge cuts, filter out the target timing path with the most edge cuts, and print out a path report containing the target edge cut path.

9. A computer device, characterized in that: The computer device includes a processor and a memory, wherein the memory stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set is loaded and executed by the processor to implement the method for obtaining a cutting edge timing path of interest as described in any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that: The readable storage medium stores at least one instruction, at least one program, a code set or an instruction set, and the at least one instruction, the at least one program, the code set or the instruction set are loaded and executed by the processor to implement the method for obtaining the cutting edge timing path of interest as described in any one of claims 1 to 7.

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