Semiconductor structure and preparation method thereof

Abstract

The embodiment of the invention relates to a semiconductor structure and a preparation method thereof, and the semiconductor structure comprises a substrate which comprises an array region and a peripheral region; the bit line structure is located in the array region, and the bit line structure comprises a bit line contact structure in contact with the substrate; the gate structure is located in the peripheral region, the gate structure comprises a first conductive layer located on the substrate, and the top surface of the bit line contact structure is not higher than the top surface of the first conductive layer in the direction parallel to the surface of the substrate. The semiconductor structure provided by the embodiment of the invention at least can improve the performance of the semiconductor structure.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for preparing the same. Background Art

[0002] DRAM (Dynamic Random Access Memory) memory is a common semiconductor memory, usually consisting of two parts: a core array area and a peripheral area.

[0003] The array region is provided with a bit line and a bit line contact structure, and the bit line transmits signals to different transistors through the bit line contact structure. The peripheral region is provided with a gate structure, and the gate structure is used to control the conduction of the transistors in the peripheral region. In the preparation process of the semiconductor structure, the bit line and the gate structure of the peripheral region are usually prepared based on the film layer formed in the same step, and the film layers in the peripheral region and the array region are patterned respectively to form a gate structure in the peripheral region and a bit line in the array region.

[0004] However, the performance of current semiconductor structures needs to be further improved. Summary of the invention

[0005] The embodiments of the present disclosure provide a semiconductor structure and a method for preparing the same, which are at least beneficial to improving the performance of the semiconductor structure.

[0006] An embodiment of the present disclosure provides a semiconductor structure, comprising: a substrate, the substrate comprising an array region and a peripheral region; a bit line structure, located in the array region, the bit line structure comprising a bit line contact structure in contact with the substrate; a gate structure, located in the peripheral region, the gate structure comprising a first conductive layer located on the substrate, wherein in a direction perpendicular to the surface of the substrate, a top surface of the bit line contact structure is not higher than a top surface of the first conductive layer.

[0007] In some embodiments, the bit line structure further includes a bit line conductive layer, which is located on the bit line contact structure, and the gate structure further includes a second conductive layer, and in a direction perpendicular to the substrate surface, the height of the bit line conductive layer is less than the height of the second conductive layer.

[0008] In some embodiments, the second conductive layer includes: a diffusion barrier layer and a gate conductive layer stacked in sequence in a direction away from the substrate.

[0009] In some embodiments, the material of the first conductive layer is ion-implanted doped polysilicon, and the bit line contact structure is in-situ doped polysilicon.

[0010] In some embodiments, the bit line conductive layer includes a first bit line conductive layer, and in a direction perpendicular to the substrate, the thickness of the first bit line conductive layer is not greater than the thickness of the diffusion barrier layer, the thickness range of the first bit line conductive layer is 2-10nm, and the thickness range of the diffusion barrier layer is 5-20nm.

[0011] In some embodiments, a material of the diffusion barrier layer is different from a material of the first bit line conduction layer.

[0012] In some embodiments, the substrate of the peripheral region includes a first active region, the first active region includes a first channel region, the first conductive layer is electrically connected to the first channel region, the first conductive layer has first doped ions, the first channel region has second doped ions, and the conductivity type of the first doped ions is the same as the conductivity type of the second doped ions; the substrate of the array region includes a second active region, the second active region includes a second channel region and second source and drain regions located on both sides of the second channel region, the bit line contact structure is electrically connected to one of the second source and drain regions, wherein the second channel region has third doped ions, the type of the third doped ions is different from the type of the second doped ions; the bit line contact structure has fourth doped ions, and the conductivity type of the fourth doped ions is the same as the conductivity type of the third doped ions.

[0013] In some embodiments, the method further includes a gate oxide layer, wherein the gate oxide layer is located between the first conductive layer and the first channel region, and an equivalent gate oxide thickness of the gate oxide layer is 0.4A to 1A.

[0014] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, comprising: providing a substrate, the substrate having an array region and a peripheral region; forming a bit line contact structure in contact with the substrate in the array region, the bit line structure comprising a bit line contact structure in contact with the substrate; forming a gate structure in the peripheral region, the gate structure comprising a first conductive layer located on the substrate, wherein in a direction perpendicular to the surface of the substrate, the top surface of the bit line contact structure is not higher than the top surface of the first conductive layer; wherein the process of forming the first conductive layer is different from the process of forming the bit line contact structure.

[0015] In some embodiments, a substrate in a peripheral region is formed with a first active region, the first active region includes a first channel region, the first conductive layer is electrically connected to the first channel region, the first conductive layer has first doped ions, the conductivity type of the first doped ions is the same as the conductivity type of the doped ions in the first channel region, and the formation of the first conductive layer includes: forming an initial first conductive layer on the surface of the substrate in the peripheral region; performing a first doping process on the initial first conductive layer to form first doped ions in the initial first conductive layer; and performing a patterning process on the initial first conductive layer to form the first conductive layer electrically in contact with the first channel region.

[0016] In some embodiments, the first doping process includes an ion implantation process.

[0017] In some embodiments, a second active region is formed in the substrate of the array region, the second active region includes a second channel region and second source and drain regions located on both sides of the second channel region, the bit line contact structure is electrically connected to one of the second source and drain regions, the initial first conductive layer is also formed on the surface of the substrate of the array region, and the process of forming the bit line contact structure includes: after the step of forming the first conductive layer, etching a portion of the initial first conductive layer of the array region to expose the substrate surface, and continuing to etch a portion of the thickness of the substrate along the substrate surface to form a bit line contact hole, the second source and drain region is exposed at the bottom of the bit line contact hole; forming the bit line contact structure filled in the bit line contact hole.

[0018] In some embodiments, the bit line contact structure has a fourth doped ion, and the conductivity type of the fourth doped ion is the same as the conductivity type of the doped ion in the second channel region; the method for forming the bit line contact structure includes: forming the bit line contact structure using a deposition process, and in the step of depositing the bit line contact structure, performing an in-situ doping process on the bit line contact structure to form a fourth doped ion in the bit line contact structure.

[0019] In some embodiments, after the step of forming the first conductive layer and before the step of forming the bit line contact structure, the method further includes: forming a diffusion barrier layer on the top surface of the first conductive layer, wherein the material of the diffusion barrier layer includes: silicon-doped metal nitride.

[0020] In some embodiments, after the step of forming the bit line contact structure, it also includes: forming a first conductive material layer and a second conductive material layer stacked in sequence along a direction away from the substrate surface, the first conductive material layer and the second conductive material layer covering the surface of the bit line contact structure and covering the surface of the diffusion barrier layer; patterning the first conductive material layer and the second conductive material layer located on the surface of the bit line contact structure to form a bit line conductive layer, the bit line conductive layer is in electrical contact with the bit line contact structure; patterning the first conductive material layer and the second conductive material layer located on the surface of the diffusion barrier layer to form a gate conductive layer, the gate conductive layer, the diffusion barrier layer and the first conductive layer constitute the gate structure.

[0021] The technical solution provided by the embodiments of the present disclosure has at least the following advantages:

[0022] In the semiconductor structure provided by the embodiment of the present disclosure, the top surface of the bitline contact structure of the bitline conductive layer is set lower than the top surface of the first conductive layer, so that the overall height of the bitline structure is relatively low, thereby lowering the relative position of the overall bitline structure compared to the substrate surface. On the one hand, in the actual step of preparing the bitline structure, it is possible to prevent the bitline structure from easily collapsing or distorting due to the large height-to-width ratio of the bitline structure, thereby ensuring that the bitline structure has a relatively straight morphology. On the other hand, since the overall position of the bitline structure is lowered, that is, the number of bitline structures located above the substrate is relatively small, the overlapping area between the bitline structure and other conductive lines in the semiconductor structure located above the substrate becomes smaller, thereby reducing the parasitic capacitance between the bitline structure and other conductive lines, thereby improving the performance of the semiconductor structure.

[0023] The gate structure is located on the substrate in the peripheral area, which can ensure that the process for actually preparing the gate structure has a large process window, so that the morphology of the gate structure meets expectations and maintains good performance of the gate structure. While ensuring good performance of the gate structure, the parasitic capacitance of the array area is reduced, thereby improving the performance of the semiconductor structure as a whole. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings, and these exemplified descriptions do not constitute a limitation on the embodiments. Unless otherwise specified, the pictures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0025] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0026] Figure 2 A schematic cross-sectional view of another semiconductor structure provided by an embodiment of the present disclosure;

[0027] Figures 3 to 14 A schematic diagram of cross-sectional structures corresponding to different steps in a method for preparing a semiconductor structure provided in another embodiment of the present disclosure. DETAILED DESCRIPTION

[0028] As can be seen from the background technology, the performance of the current semiconductor structure needs to be further improved. Analysis has found that one of the reasons why the performance of the semiconductor structure needs to be further improved is that, at present, in the preparation process of the semiconductor structure, it is usually necessary to deposit the same film layer in the peripheral area and the array area in the same step. The film layer located in the array area is patterned to form the conductive part of the bit line structure in the array area, and the film layer located in the peripheral area is patterned to form the conductive part of the gate structure in the peripheral area. However, since the bit line structure in the array area also has a bit line contact structure that plays an electrical connection role. If the height of the bit line contact structure is too high, it will cause the height of the bit line structure located on the substrate to be too high, thereby increasing the overlap between the bit line structure and other conductive lines located on the substrate in the semiconductor structure, and the overlapping area is too large, which leads to excessive parasitic capacitance between the two, so that the overall performance of the semiconductor structure is poor. For example, a capacitor structure is usually formed in the semiconductor structure, and a contact pad for electrically connecting the substrate and the capacitor structure is formed between the capacitor structure and the substrate. The bit line structure located on the substrate may also be arranged in an interlaced manner with the contact pads. If the interlaced area is too large, the parasitic capacitance between the two may be too large, resulting in poor performance of the semiconductor structure.

[0029] The disclosed embodiment provides a semiconductor structure, in which the top surface of the bitline contact structure is set lower than the top surface of the first conductive layer, so that the overall height of the bitline structure is relatively low, thereby lowering the relative position of the overall bitline structure compared to the substrate surface. On the one hand, in the actual step of preparing the bitline structure, it is possible to prevent the bitline structure from easily collapsing or distorting due to the large aspect ratio of the bitline structure, thereby ensuring that the bitline structure has a relatively straight morphology. On the other hand, since the overall position of the bitline structure is lowered, that is, the number of bitline structures located above the substrate is relatively small, the overlapping area between the bitline structure and other conductive lines in the semiconductor structure located above the substrate becomes smaller, thereby reducing the parasitic capacitance between the bitline structure and other conductive lines, thereby improving the performance of the semiconductor structure.

[0030] The following will describe the various embodiments of the present disclosure in detail with reference to the accompanying drawings. However, it will be appreciated by those skilled in the art that in the various embodiments of the present disclosure, many technical details are provided in order to enable the reader to better understand the present disclosure. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented.

[0031] Figure 1 A schematic cross-sectional structure diagram of a semiconductor structure provided in accordance with an embodiment of the present disclosure.

[0032] refer to Figure 1 , the semiconductor structure includes: a substrate 101, the substrate 101 includes an array region 1 and a peripheral region 2. The semiconductor structure also includes: a bit line structure, located in the array region 1, the bit line structure includes a bit line contact structure 105 in contact with the substrate 101. The semiconductor structure also includes: a gate structure, located in the peripheral region 2, the gate structure includes a first conductive layer 102 located on the substrate 101, wherein in a direction parallel to and perpendicular to the surface of the substrate 101, the top surface of the bit line contact structure 105 is not higher than the top surface of the first conductive layer 102.

[0033] The top surface of the bitline contact structure 105 is lower than the top surface of the first conductive layer 102, so that the overall height of the bitline structure is relatively low, and the relative position of the overall bitline structure relative to the surface of the substrate 101 is lowered. On the one hand, in the actual step of preparing the bitline structure, it is possible to prevent the bitline structure from easily collapsing or distorting due to the large aspect ratio of the bitline structure, and ensure that the bitline structure has a relatively straight morphology. On the other hand, since the overall position of the bitline structure is lowered, that is, the number of bitline structures located on the substrate 101 is relatively small, the overlapping area between the bitline structure and other conductive lines in the semiconductor structure located on the substrate 101 is reduced, thereby reducing the parasitic capacitance between the bitline structure and other conductive lines, for example, reducing the overlapping area between the contact pad used to electrically connect the capacitor structure and the substrate 101, thereby reducing the parasitic capacitance between the two, and improving the performance of the semiconductor structure.

[0034] The gate structure is located on the substrate 101 of the peripheral area 2, which can ensure that the process for actually preparing the gate structure has a larger process window, so that the morphology of the gate structure meets expectations. While ensuring better performance of the gate structure, the parasitic capacitance of the array area 1 is reduced, thereby improving the overall performance of the semiconductor structure.

[0035] The height of the top surface of the bit line contact structure 105 and the height of the first conductive layer 102 mentioned here are both relative to the same surface of the substrate 101 .

[0036] In some embodiments, part of the bit line contact structure 105 is located in the substrate 101, and the top surface of the bit line contact structure 105 is higher than the surface of the substrate 101. In some embodiments, the bit line contact structure 105 is entirely located in the substrate 101, and the top surface of the bit line contact structure 105 is flush with the surface of the substrate 101.

[0037] In some embodiments, the material of the substrate 101 may be a semiconductor material. In some embodiments, the material of the substrate 101 may be silicon. In some embodiments, the substrate 101 may also be germanium, germanium silicon, or silicon on insulator.

[0038] refer to Figure 2 In some embodiments, the bit line structure further includes a bit line conductive layer 130 , which is located on the bit line contact structure 105 , and the gate structure further includes a second conductive layer 110 , and in a direction perpendicular to the surface of the substrate 101 , a height of the bit line conductive layer 130 is less than a height of the second conductive layer 110 .

[0039] The height of the bit line conductive layer 130 and the height of the second conductive layer 110 are both relative to the same surface of the substrate 101. In other words, the thickness of the bit line conductive layer 130 in a direction perpendicular to the surface of the substrate 101 is smaller than the thickness of the second conductive layer 110 in a direction perpendicular to the surface of the substrate 101.

[0040] The height of the bit line conductive layer 130 is relatively small, which reduces the risk of the bit line conductive layer 130 being easily collapsed or distorted due to the excessively large aspect ratio of the bit line conductive layer 130, so that the formed bit line conductive layer 130 has a straight morphology, thereby improving the electrical performance of the bit line structure. In other words, the semiconductor structure provided by the embodiment of the present disclosure can improve the morphology of the bit line structure while reducing the parasitic capacitance of the array area 1, thereby improving the electrical performance of the semiconductor structure.

[0041] In some embodiments, the material of the first conductive layer is ion-implanted doped polysilicon, and the bit line contact structure 105 is in-situ doped polysilicon. That is, the process of actually forming the first conductive layer 102 and the process of forming the bit line contact structure 105 are different, so that different process parameters can be used in different process steps, so that the performance of the formed bit line contact structure 105 and the performance of the first conductive layer 102 are optimized.

[0042] The first conductive layer 102 is formed by an ion implantation process, which can accurately control the total dose, depth distribution and diffusion uniformity of the first doping ions, so that the first doping ions in the formed first conductive layer 102 have good uniformity, thereby being able to better suppress the gate depletion effect. The bit line contact structure 105 is formed by an in-situ doping process, and the formed bit line contact structure 105 has high compactness, which can effectively prevent the formation of holes in the deposited bit line contact structure 105, thereby reducing the resistance of the bit line contact structure 105 itself and improving the electrical performance of the bit line contact structure 105.

[0043] refer to Figure 2 In some embodiments, the second conductive layer 110 includes: a diffusion barrier layer 103 and a gate conductive layer stacked in sequence in a direction away from the substrate 101 .

[0044] The diffusion barrier layer 103 can prevent the mutual diffusion problem between the first conductive layer 102 and the gate conductive layer, thereby reducing the parasitic capacitance of the gate structure. Since the mutual diffusion problem between the first conductive layer 102 and the gate conductive layer is improved by providing the diffusion barrier layer 103, a gate conductive layer with a relatively small thickness can be provided, thereby reducing the overall thickness of the gate structure.

[0045] In some embodiments, since the bit line conductive layer 130 and the gate conductive layer are formed simultaneously, the thickness of the bit line conductive layer 130 is the same or approximately the same as the thickness of the gate conductive layer. Therefore, the thickness of the bit line conductive layer 130 can also be correspondingly smaller, further reducing the risk of the bit line conductive layer 130 being easily collapsed or distorted due to the excessively large aspect ratio of the bit line conductive layer 130, so that the formed bit line conductive layer 130 has a straight morphology, thereby improving the electrical performance of the bit line structure.

[0046] refer to Figure 2 In some embodiments, the bit line conductive layer includes a first bit line conductive layer 131. In a direction perpendicular to the substrate 101, the thickness of the first bit line conductive layer 131 is not greater than the thickness of the diffusion barrier layer 103. The thickness of the first bit line conductive layer 131 is in the range of 2-10 nm, and the thickness of the diffusion barrier layer 103 is in the range of 5-20 nm.

[0047] In some embodiments, the bit line structure further includes: a second bit line conductive layer 132 , and the gate conductive layer includes a first gate conductive layer 111 and a second gate conductive layer 112 sequentially stacked in a direction away from the surface of the substrate 101 .

[0048] In some embodiments, the material of the first bit line conductive layer 131 may be the same as the material of the first gate conductive layer 111, and the material of the second bit line conductive layer 132 may be the same as the material of the second gate conductive layer 112. That is, the first bit line conductive layer 131 and the first gate conductive layer 111 may be formed in the same process step, and the second bit line conductive layer 132 and the gate conductive layer may be formed in the same process step, which greatly simplifies the process. In these embodiments, the thickness of the first bit line conductive layer 131 formed in the same process step is equal to or substantially equal to the thickness of the first gate conductive layer 111, and the thickness of the second bit line conductive layer 132 formed in the same process step is equal to or substantially equal to the thickness of the second gate conductive layer 112.

[0049] In some embodiments, the materials of the first bit line conductive layer 131 and the first gate conductive layer 111 are both titanium nitride, and the materials of the second bit line conductive layer 132 and the second gate conductive layer 112 are both titanium.

[0050] In some embodiments, the material of the second bit line conductive layer 132 and the material of the second gate conductive layer 112 may also be any one of tungsten, copper or nickel.

[0051] In some embodiments, the material of the diffusion barrier layer is different from that of the first bit line conduction layer 131 .

[0052] In a specific example, the material of the first bit line conductive layer 131 includes titanium nitride, and the material of the diffusion barrier layer 103 includes silicon-doped metal nitride (TSN).

[0053] Compared with silicon-doped metal nitride, titanium nitride has a smaller dielectric constant, thereby being able to reduce the parasitic capacitance between the bit line structure and the substrate 101 .

[0054] Silicon-doped metal nitride is a metal nitride doped with silicon. As an excellent dielectric material, silicon-doped metal silicon nitride has excellent electrical conductivity, ensuring good electrical connection performance between the first conductive layer 102 and the gate conductive layer. In addition, silicon-doped metal nitride can also effectively prevent the diffusion of doped ions in the first conductive layer 102.

[0055] Furthermore, by using silicon-doped metal nitride as the diffusion barrier layer 103 , even if the thickness of the diffusion barrier layer 103 is small, the diffusion barrier layer 103 can still exert its beneficial barrier performance, thereby ensuring that the overall thickness of the gate structure is small.

[0056] It can be understood that, in some embodiments, the material of the diffusion barrier layer 103 may also include any one of TiN, Ta, TaN or WN.

[0057] refer to Figure 2In some embodiments, the substrate 101 of the peripheral region includes a first active region 11, the first active region 11 includes a first channel region, the first conductive layer 102 is electrically connected to the first channel region, the first conductive layer 102 has first doped ions, the first channel region has second doped ions, and the conductivity type of the first doped ions is the same as the conductivity type of the second doped ions.

[0058] The first conductive layer 102 is located above the first channel region, and the first channel region is electrically connected to transmit an external control signal to the first channel region, thereby controlling the conduction of the first channel region.

[0059] In some embodiments, the first doping ion and the second doping ion may both be N-type doping ions, and the N-type doping ions may be any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0060] In some embodiments, the first doping ions and the second doping ions may both be P-type doping ions, and the P-type doping ions may be any one of boron ions, aluminum ions, gallium ions, or indium ions.

[0061] The first conductive layer 102 is doped with the same type of doping ions as those in the first channel region, which can reduce the accumulation of carriers in the gate structure when the first channel region is turned on, and can improve the gate depletion effect.

[0062] The diffusion barrier layer 103 is provided between the first conductive layer 102 and the gate conductive layer, which can prevent the first doping ions in the first conductive layer 102 from diffusing into the gate conductive layer. On the one hand, it can ensure that the doping ion concentration in the first conductive layer 102 is relatively high, so that the first conductive layer 102 can better improve the gate depletion effect. On the other hand, due to the provision of the diffusion barrier layer 103, it is not necessary to provide a thicker gate conductive layer in order to prevent the diffusion of the first doping ions in the first conductive layer 102, that is, the thickness of the gate conductive layer can be reduced, for example, the thickness of the first gate conductive layer 111 in the gate conductive layer can be reduced, so that the thickness of the bit line conductive layer 130 is also reduced accordingly, preventing the bit line structure from collapsing or being distorted due to the excessively large aspect ratio of the bit line conductive layer 130, ensuring that the bit line conductive layer 130 has a straight morphology, so that the electrical performance of the bit line structure is better.

[0063] In some embodiments, the gate oxide layer 114 is further included. The gate oxide layer 114 is located between the first conductive layer 102 and the first channel region. The equivalent gate oxide thickness of the gate oxide layer is 0.4A to 1A.

[0064] The gate oxide layer 114 is used to isolate the first conductive layer 102 from the first channel region. The gate oxide layer 114 is located on the surface of the first channel region, and the first conductive layer 102 is located on the surface of the gate oxide layer. The gate oxide layer 114 is located on the surface of the first channel region, which is equivalent to adding an electric field on the surface of the first channel region, so that the minority carriers of the substrate 101 are adsorbed to the surface of the first channel region, accumulate and invert, so that the first channel region is turned on. The existence of the gate oxide layer 114 allows a smaller voltage to be applied to the first channel region, that is, the first channel region can be turned on, which is beneficial to improving the performance of the semiconductor structure. In addition, the gate oxide layer 114 is located between the first conductive layer 102 and the first channel region, and can also reduce parasitic capacitance. In some embodiments, the material of the gate oxide layer 114 may include at least one of silicon oxide, silicon nitride, or silicon oxynitride.

[0065] It can be understood that the diffusion barrier layer 103 can effectively prevent the mutual diffusion between the first conductive layer 102 and the gate conductive layer, thereby greatly reducing the parasitic capacitance of the gate structure. When the parasitic capacitance of the gate structure is reduced by providing the diffusion barrier layer 103, the thickness of the gate oxide layer 114 can be made thinner. In other words, when the thickness of the gate oxide layer 114 is small, the parasitic capacitance of the gate structure can also be ensured to be small.

[0066] In some embodiments, the gate structure further includes a gate capping layer 113, which is located on a surface of the gate conductive layer away from the substrate 101 and is used to protect the gate conductive layer. In some embodiments, the gate capping layer 113 may be made of silicon nitride or silicon oxynitride.

[0067] In some embodiments, the semiconductor structure further includes: a spacer structure 120, which is located on the sidewalls of the first conductive layer 102, the diffusion barrier layer 103, the gate conductive layer, and the gate cap layer 113. The spacer structure 120 can protect the first conductive layer 102, the diffusion barrier layer 103, and the gate conductive layer from the side.

[0068] In some embodiments, the spacer structure 120 may include a first spacer layer 121, a second spacer layer 122, and a third spacer layer 123 arranged in sequence in a direction away from the side wall of the gate structure, wherein the material of the first spacer layer 121 may be the same as the material of the third spacer layer 123, and the material of the second spacer layer 122 is different from the material of the first spacer layer 121. In some embodiments, the materials of the first spacer layer 121 and the third spacer layer 123 may both be silicon nitride, and the material of the second spacer layer 122 may be silicon oxide. The spacer structure 120 with a sandwich structure can improve the hardness of the spacer structure 120, thereby enhancing the protective effect of the spacer structure 120 on the gate structure.

[0069] In some embodiments, the substrate 101 of the array region includes a second active region 10, the second active region 10 includes a second channel region and second source and drain regions located on both sides of the second channel region, and the bit line contact structure 105 is electrically connected to one of the second source and drain regions, wherein the second channel region has third doping ions, and the third doping ion type is different from the second doping ion type; the bit line contact structure 105 has fourth doping ions, and the conductivity type of the fourth doping ions is the same as the conductivity type of the third doping ions.

[0070] The second channel region and the second source and drain regions located on both sides of the second channel region together constitute a transistor. In some embodiments, the second source and drain regions located on both sides of the second channel region include a second source region and a second drain region, wherein the second source region is used to form a source of the transistor, and the second drain region is used to form a drain of the transistor. In some embodiments, the bit line contact structure 105 can be electrically connected to the second source region.

[0071] The third doping ion type is different from the second doping ion type, so that the transistor formed in the peripheral area 2 is different from the transistor formed in the array area 1. In some embodiments, the third doping ion type can be P-type, the transistor formed in the array area 1 is an NMOS tube, and the P-type doping ion can be any one of boron ions, aluminum ions, gallium ions, or indium ions. The second doping ion type can be N-type, the transistor formed in the peripheral area 2 is an NMOS tube, and the N-type doping ion can be any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0072] The bit line contact structure 105 has a fourth doping ion of the same type as the doping ion of the second channel region. In the actual step of preparing the bit line contact structure 105, it is possible to avoid the formation of holes when depositing the bit line contact structure 105, thereby forming a denser bit line contact structure 105, so that the resistance of the bit line contact structure 105 is smaller, thereby reducing the contact resistance between the bit line contact structure 105 and the second channel region.

[0073] In some embodiments, the material of the bit line contact structure 105 may include any one of polysilicon, amorphous silicon, or microcrystalline silicon.

[0074] In some embodiments, the number of second active regions 10 in the array region 1 is multiple, and the multiple second active regions 10 are arranged at intervals. The semiconductor structure may further include: an isolation structure 20, which is located between adjacent second active regions 10 and is used to isolate adjacent second active regions 10.

[0075] In some embodiments, there are multiple first active regions 11 in the substrate 101 of the peripheral region 2, and the multiple first active regions 11 are arranged at intervals. The isolation structure 20 is also located in the substrate 101 of the peripheral region 2 and between adjacent first active regions 11, so as to isolate the adjacent first active regions 11.

[0076] In some embodiments, the material of the isolation structure 20 may be silicon oxide.

[0077] In some embodiments, the thickness of the first conductive layer 102 is less than the thickness of the bit line contact structure 105. In other words, the thickness of the first conductive layer 102 is relatively small, so that the thickness of the gate structure can still be kept small after the diffusion barrier layer 103 is set. It is not difficult to find that the first conductive layer 102 is located on the surface of the substrate 101, that is, in the step of forming the first conductive layer 102, the sidewall of the first conductive layer 102 has no structure that can be used to support the first conductive layer 102. Therefore, setting the thickness of the first conductive layer 102 to be less than the thickness of the bit line contact structure 105 can avoid the problem of distortion or even collapse of the gate structure due to the excessive thickness of the gate structure in the actual step of forming the gate structure.

[0078] The first conductive layer 102 is doped with the same type of doping ions as the first channel region, thereby improving the gate depletion effect of the gate structure. The bit line contact structure 105 is doped with the same type of doping ions as the second channel region, thereby avoiding the formation of holes when the bit line contact structure 105 is deposited, thereby improving the electrical performance of the bit line contact structure 105. In some embodiments, the doping ion type of the first channel region is different from the doping ion type of the second channel region, that is, the doping ion type in the first conductive layer 102 is different from the doping ion type in the bit line contact structure 105. The thickness of the first conductive layer 102 is set to be smaller than the thickness of the bit line contact structure 105, that is, the first conductive layer 102 and the bit line contact structure 105 may not be formed in the same process step, thereby forming the first conductive layer 102 and the bit line contact structure 105 separately, so that different process parameters can be used in different process steps, so that the performance of the formed bit line contact structure 105 and the performance of the first conductive layer 102 are optimized.

[0079] In the semiconductor structure provided in the above embodiment, the top surface of the bit line contact structure 105 is set lower than the top surface of the first conductive layer 102, so that the overall height of the bit line structure is relatively low, and the relative position of the overall bit line structure is lowered compared to the surface of the substrate 101. Since the overall position of the bit line structure is lowered, that is, the number of bit line structures located on the substrate 101 is relatively small, the overlapping area between the bit line structure and other conductive lines located on the substrate 101 in the semiconductor structure is reduced, thereby reducing the parasitic capacitance between the bit line structure and other conductive lines, and improving the performance of the semiconductor structure.

[0080] Correspondingly, an embodiment of the present disclosure also provides a method for preparing a semiconductor structure, which can be used to prepare the semiconductor structure provided by the above embodiment. The semiconductor structure provided by an embodiment of the present disclosure will be described in detail below in conjunction with the accompanying drawings.

[0081] refer to Figures 3 to 14 , the method for preparing the semiconductor structure comprises:

[0082] refer to Figures 3 to 10 , providing a substrate 101, the substrate 101 having an array area 1 and a peripheral area 2, a bit line contact structure 105 in contact with the substrate 101 is formed in the array area 1, and the bit line structure includes the bit line contact structure 105 in contact with the substrate 101; the gate structure includes a first conductive layer 102 located on the substrate 101, wherein in a direction perpendicular to the surface of the substrate 101, the top surface of the bit line contact structure 105 is not higher than the top surface of the first conductive layer 102; wherein the process of forming the first conductive layer 102 is different from the process of forming the bit line contact structure 105.

[0083] In some embodiments, the material of the substrate 101 may be a semiconductor material. In some embodiments, the material of the substrate 101 may be silicon. In some embodiments, the substrate 101 may also be germanium, germanium silicon, or silicon on insulator.

[0084] refer to Figure 2 In some embodiments, the substrate 101 of the peripheral region 2 is formed with a first active region 11, the first active region 11 includes a first channel region, the first conductive layer 102 is electrically connected to the first channel region, the first conductive layer 102 has first doped ions, and the conductivity type of the first doped ions is the same as the conductivity type of the doped ions in the first channel region.

[0085] In some embodiments, the substrate 101 of the peripheral region 2 further includes first source and drain regions located on both sides of the first channel region, and the first channel region and the first source and drain region form a transistor. In some embodiments, the first source and drain region includes a first source region and a first drain region, the first source region is used to form a source of the transistor, and the first drain region is used to form a drain of the transistor.

[0086] In some embodiments, the doping ion type of the first channel region is opposite to the doping ion type of the first source and drain region. For example, the doping ion type of the first channel region may be P-type, and the doping ion type of the first source and drain region may be N-type. Alternatively, the doping ion type of the first channel region may be N-type, and the doping ion type of the first source and drain region may be P-type.

[0087] In some embodiments, the substrate 101 of the array region 1 further includes a second active region 10, the second active region 10 includes a second channel region and second source and drain regions located on both sides of the second channel region, and the second channel region and the second source and drain region form a transistor. In some embodiments, the second source and drain region includes a second source region and a second drain region, the second source region is used to form a source of the transistor, and the second drain region is used to form a drain of the transistor.

[0088] In some embodiments, the doping ion type of the second channel region is opposite to the doping ion type of the second source and drain region. For example, the doping ion type of the second channel region may be P-type, and the doping ion type of the second source and drain region may be N-type. Alternatively, the doping ion type of the second channel region may be N-type, and the doping ion type of the second source and drain region may be P-type.

[0089] In some embodiments, the doping ion type of the first channel region is different from the doping ion type of the second channel region, the doping ion type of the first channel region may be P type, and the doping ion type of the second channel region may be N type. In some embodiments, the doping ion type of the first channel region may also be N type, and the doping ion type of the second channel region may also be P type.

[0090] The P-type doping ions may be any one of boron ions, aluminum ions, gallium ions, or indium ions, and the N-type doping ions may be any one of phosphorus ions, bismuth ions, antimony ions, or arsenic ions.

[0091] In some embodiments, the method of forming the first active region 11 and the second active region 10 includes:

[0092] An initial substrate is provided, which is a substrate 101 that has not been doped and etched, and includes a peripheral region 2 and an array region 1. A patterning process is performed on the surface of the initial substrate to define the position of the first active region 11 and the position of the second active region 10. In some embodiments, the surface of the initial substrate can be patterned by using either a SADP (Self-aligned Double Patterning) process or a SAQP (Self-Aligned Quadruple Patterning) process. Afterwards, an etching process is performed on the patterned surface of the initial substrate, and a partial thickness of the initial substrate is etched to form a plurality of first grooves arranged at intervals in the substrate 101 of the peripheral region 2, and the initial first active regions 11 separated by the first grooves. A partial thickness of the initial substrate is etched to form a plurality of second grooves arranged at intervals in the substrate 101 of the array region 1, and the initial second active regions 10 separated by the second grooves, and the remaining portion of the initial substrate is used as the substrate 101. In some embodiments, the etching process may be any one of a dry etching process or a wet etching process.

[0093] Next, an isolation material is deposited in the first trench and the second trench to form an isolation structure 20 filling the first trench and an isolation structure 20 filling the second trench in the first trench. In some embodiments, the isolation structure 20 can be formed by either an atomic layer deposition process or a chemical vapor deposition process. In some embodiments, the material of the isolation structure 20 can be silicon oxide.

[0094] In some embodiments, after forming the initial first active region 11 and the initial second active region 10, a doping process is performed on the initial first active region 11 and the initial second active region 10 to respectively inject doping ions into the initial first active region 11 and the initial second active region 10 to form the first active region 11 and the second active region 10.

[0095] In some embodiments, the initial first active region 11 includes a first region, a second region, and a third region arranged in sequence along a direction parallel to the surface of the substrate 101. The method for forming the first active region 11 may include: forming a first sacrificial layer on the surface of the initial first active region 11, the first sacrificial layer having a first opening, the first opening exposing the surface of the second region, and the first sacrificial layer covering the surfaces of the first region and the third region. Performing a doping process on the second region along the first opening, and injecting doping ions into the second region to form a first channel region. In some embodiments, the doping process may be an ion implantation process, and the material of the first sacrificial layer may be a photoresist.

[0096] After forming the first channel region, the first sacrificial layer is removed, and a second sacrificial layer is formed on the surface of the initial first active region 11, the second sacrificial layer having a second opening, the second opening exposing the surface of the first region and the third region, and the second sacrificial layer also covers the second region. A doping process is performed on the first region and the third region along the second opening, and doping ions are injected into the first region and the third region to convert the first region and the third region into first source and drain regions, respectively. It is worth noting that the type of doping ions injected into the second region is different from the type of doping ions injected into the first region and the third region.

[0097] In some embodiments, the method for forming the second active region 10 may refer to the above description of the method for forming the first active region 11 .

[0098] In some embodiments, the substrate 101 of the peripheral region is formed with a first active region 11, the first active region 11 includes a first channel region, the first conductive layer 102 is electrically connected to the first channel region, the first conductive layer 102 has first doping ions, and the conductivity type of the first doping ions is the same as the conductivity type of the doping ions in the first channel region, and the process of forming the first conductive layer 102 includes:

[0099] refer to Figure 3 , an initial first conductive layer 141 is formed on the surface of the substrate 101 in the peripheral area 2. It can be understood that in the step of forming the initial first conductive layer 141 on the surface of the substrate 101 in the peripheral area 2, the initial first conductive layer 141 can also be formed on the surface of the substrate 101 in the array area 1. However, the initial first conductive layer 141 in the peripheral area 2 is subsequently used to form the first conductive layer 102 as a part of the gate structure, and the initial first conductive layer 141 in the array area 1 needs to be removed in the subsequent steps. In some embodiments, before the step of forming the initial first conductive layer 141 on the surface of the substrate 101 in the array area 1, a dielectric layer 21 can be formed on the surface of the substrate 101 in the array area 1. In some embodiments, the material of the dielectric layer 21 can be silicon nitride.

[0100] In some embodiments, the initial first conductive layer 141 may be formed by a deposition process, and the material of the initial first conductive layer 141 may be a semiconductor material, for example, any one of polycrystalline silicon, amorphous silicon, or microcrystalline silicon.

[0101] The initial first conductive layer 141 is subjected to a first doping process to form first doping ions in the initial first conductive layer 141. The first doping ions have the same doping ion type as the first channel region, and the doping ion type of the first conductive layer 102 formed in this way is the same as the doping ion type of the first channel region, so that the first conductive layer 102 can improve the gate depletion effect.

[0102] In some embodiments, the first doping process includes an ion implantation process. In some embodiments, the first channel region is of P type, and the first doping ions may be P type doping ions, for example, any one of boron ions, aluminum ions, gallium ions, or indium ions. The ion implantation process is used to dope the initial first conductive layer 141, and the total dose, depth distribution, and diffusion uniformity of the first doping ions can be precisely controlled, so that the first doping ions in the formed first conductive layer 102 have better uniformity, thereby better suppressing the gate depletion effect.

[0103] In some embodiments, after the step of forming the first conductive layer 102 and before the step of forming the bit line contact structure 105, the method further includes:

[0104] A diffusion barrier layer 103 is formed on the top surface of the first conductive layer 102 . The material of the diffusion barrier layer 103 includes silicon-doped metal nitride.

[0105] refer to Figure 4 In some embodiments, before forming the first conductive layer 102, an initial diffusion barrier layer 142 can be formed on the surface of the initial first conductive layer 141, and then the initial first conductive layer 141 and the initial diffusion barrier layer 142 are patterned in the same process step to form the first conductive layer 102 and the diffusion barrier layer 103.

[0106] In some embodiments, in the step of forming the initial diffusion barrier layer 142 , the initial diffusion barrier layer 142 is simultaneously formed on the surface of the initial first conductive layer 141 in the array region 1 and the surface of the initial first conductive layer 141 in the peripheral region 2 .

[0107] In some embodiments, the initial diffusion barrier layer 142 may be formed using an atomic layer deposition method.

[0108] In order to ensure that the height-width ratio of the subsequently formed bit line structure is small, it is necessary to remove the initial diffusion barrier layer 142 located in the array region 1. Figure 6 After the initial diffusion barrier layer 142 is formed, the initial diffusion barrier layer 142 of the array region 1 is removed, and the initial first conductive layer 141 of the array region 1 is thinned.

[0109] refer to Figure 5In order to prevent the process of removing the initial diffusion barrier layer 142 of the array region 1 from damaging the initial diffusion barrier layer 142 of the peripheral region 2, a protective layer may be formed on the surface of the initial diffusion barrier layer 142 of the peripheral region 2. The protective layer may include a first protective layer 143 and a second protective layer 25 stacked in sequence away from the surface of the substrate 101. The material of the first protective layer 143 may be silicon oxide, and the material of the second protective layer 25 may be photoresist. Silicon oxide has a relatively thick hardness and can provide a good protective effect on the initial diffusion barrier layer 142 of the peripheral region 2.

[0110] In some embodiments, the first protection layer 143 is also formed on the surface of the initial diffusion barrier layer 142 in the array region 1 .

[0111] In some embodiments, the protective layer may also be a single-layer structure, and the material of the protective layer is photoresist.

[0112] refer to Figure 6 , removing the initial diffusion barrier layer 142 of the array region 1 and removing a portion of the initial first conductive layer 141 to thin the initial first conductive layer 141 .

[0113] In some embodiments, a dry etching process may be used to etch the initial diffusion barrier layer 142 of the array region 1 and to etch a partial thickness of the initial first conductive layer 141 .

[0114] It can be understood that, in some embodiments, if the formed protective layer includes a first protective layer 143 and a second protective layer 25, and the material of the first protective layer 143 is silicon oxide, and the material of the second protective layer 25 is photoresist, then before removing the initial diffusion barrier layer 142 of the array area 1 and thinning the initial first conductive layer 141 of the array area 1, the second protective layer 25 is removed, and only the first protective layer 143 of the peripheral area 2 is retained to protect the initial diffusion barrier layer 142 of the peripheral area 2.

[0115] In some embodiments, if the formed protective layer is a single-layer structure and the material is photoresist, in order to better protect the initial diffusion barrier layer 142 of the peripheral area 2 in the steps of removing the initial diffusion barrier layer 142 of the array area 1 and thinning the initial first conductive layer 141 of the array area 1, before removing the initial diffusion barrier layer 142 of the array area 1 and thinning the initial first conductive layer 141 of the array area 1, the photoresist of the peripheral area 2 is removed and a silicon oxide layer is formed on the surface of the initial diffusion layer of the peripheral area 2.

[0116] refer to Figures 7 and 8 , a bit line contact structure 105 is formed in the substrate 101 of the array region 1.

[0117] In some embodiments, a second active region 10 is formed in the substrate 101 of the array region, the second active region 10 includes a second channel region and second source and drain regions located on both sides of the second channel region, the bit line contact structure 105 is electrically connected to one of the second source and drain regions, and the initial first conductive layer 141 is also formed on the surface of the substrate 101 of the array region 1. The process of forming the bit line contact structure 105 includes:

[0118] After the step of forming the initial first conductive layer 141, a portion of the initial first conductive layer 141 of the array region 1 is etched to expose the surface of the substrate 101, and a portion of the thickness of the substrate 101 is further etched along the surface of the substrate 101 to form a bit line contact hole, and the second source and drain region is exposed at the bottom of the bit line contact hole. Specifically, after the initial first conductive layer 141 of the array region 1 is subjected to a thinning process, a portion of the initial first conductive layer 141 of the array region 1 can be etched.

[0119] In some embodiments, a method of forming a bit line contact hole includes:

[0120] refer to Figure 7 , the initial first conductive layer 141 of the array region 1 is patterned. In some embodiments, the initial first conductive layer 141 of the array region 1 may be patterned using a SAQP process. The method may include:

[0121] A silicon oxide layer 22, a first mask layer 30, and a first photoresist layer 12 are sequentially formed on the surface of the initial first conductive layer 141 of the array region 1. In some embodiments, in the step of forming the first mask layer 30 and the first photoresist layer 12 on the surface of the initial first conductive layer 141 of the array region 1, the first mask layer 30 and the first photoresist layer 12 may also be formed on the surface of the first protective layer 143 of the peripheral region 2. In this way, the first mask layer 30 and the first photoresist layer 12 located in the peripheral region 2 may protect the peripheral region 2.

[0122] In some embodiments, the first mask layer 30 may include a first hard mask layer 31, a first etch stop layer 32, a sacrificial layer 33, a second hard mask layer 34, and a second etch stop layer 35, which are sequentially stacked in a direction away from the substrate 101. In a specific example, the material of the first hard mask layer 31 may be an APF (Advanced Patterning Film) mask, the material of the first etch stop layer 32 may be silicon oxynitride, the material of the sacrificial layer 33 may be silicon oxide, the material of the second hard mask layer 34 may be a spin-on hard mask, and the material of the second etch stop layer 35 may be silicon oxynitride.

[0123] The first photoresist layer 12 of the array area 1 is subjected to a patterning process, and the pattern of the first photoresist layer 12 of the array area 1 is used to define the opening shape of the bit line contact hole. The first mask layer 30 is etched based on the first photoresist layer 12 to pattern the initial first conductive layer 141 of the array area 1. The patterned initial first conductive layer 141 is etched until the top surface of a portion of the isolation structure 20 is exposed, and the isolation structure 20 of a partial thickness and the second active area 10 of a partial thickness are continuously etched to form a bit line contact hole.

[0124] refer to Figure 8 , forming a bit line contact structure 105 filled in the bit line contact hole. In some embodiments, the method of forming the bit line contact structure 105 may include: forming the bit line contact structure 105 filling the bit line contact hole in the bit line contact hole by a deposition process. In some embodiments, the bit line contact structure 105 may be formed by atomic layer deposition, and the material of the bit line contact structure 105 may be polysilicon.

[0125] In some embodiments, the bit line contact structure 105 has fourth doping ions, and the conductivity type of the fourth doping ions is the same as the conductivity type of the doping ions in the second channel region; the method of forming the bit line contact structure 105 includes:

[0126] The bit line contact structure 105 is formed by a deposition process, and in the step of depositing the bit line contact structure 105, an in-situ doping process is performed on the bit line contact structure 105 to form fourth doping ions in the bit line contact structure 105. The bit line contact structure 105 is formed by the in-situ doping process, and the formed bit line contact structure 105 has high compactness, which can effectively prevent the occurrence of holes in the deposited bit line contact structure 105, thereby reducing the resistance of the bit line contact structure 105 itself and improving the electrical performance of the bit line contact structure 105.

[0127] It is not difficult to find that in the embodiment of the present disclosure, the bit line contact structure 105 and the initial first conductive layer 141 are deposited and formed in different steps respectively, that is, the bit line contact structure 105 and the first conductive layer 102 are not etched from the same film layer respectively. In this way, the processes of forming the bit line contact structure 105 and forming the first conductive layer 102 can be separately regulated, so that the formed bit line contact structure 105 and the first conductive layer 102 have the best morphology and performance respectively, thereby improving the performance of the semiconductor structure.

[0128] refer to Figures 9 and 10After the step of forming the bit line contact structure 105, the initial first conductive layer 141 is patterned to form the first conductive layer 102 electrically contacting the first channel region. In some embodiments, in the step of patterning the initial first conductive layer 141, the initial diffusion barrier layer 142 is patterned. The method of patterning the initial first conductive layer 141 and the initial diffusion barrier layer 142 includes a SADP process, and the method includes:

[0129] refer to Fig. 9 , a first conductive material layer 41, a second conductive material layer 42 and an initial cap layer 43 are deposited on the surface of the initial diffusion barrier layer 142 of the peripheral region 2 and are stacked in sequence in a direction away from the surface of the substrate 101, the first conductive material layer 41 is used to form a first gate conductive layer 111, the second conductive material layer 42 is used to form a second gate conductive layer 112, and the initial cap layer 43 is used to form a gate cap layer 113, so that the initial first conductive layer 141, the initial diffusion barrier layer 142, the first conductive material layer 41, the second conductive material layer 42 and the initial cap layer 43 can be patterned in the same process step to form a gate structure. In some embodiments, the deposition process may include an atomic layer deposition process.

[0130] After the step of forming the initial capping layer 43, a second mask layer 50 and a second photoresist layer 13 are sequentially formed on the surface of the initial capping layer 43. The material of the second mask layer 50 may include a third hard mask layer 51 and a third etch stop layer 52 sequentially stacked in a direction away from the substrate 101, the material of the third hard mask layer 51 may be a spin-on hard mask layer, and the material of the third etch stop layer 52 may be silicon oxynitride.

[0131] The second photoresist layer 13 is patterned, and the pattern of the second photoresist layer 13 is used to define the shape of the gate structure. Fig.10 , the second mask layer 50 is etched based on the pattern of the second photoresist layer 13 to expose the surface of the initial capping layer 43, and the initial capping layer 43, the second conductive material layer 42, the first conductive material layer 41, the initial diffusion barrier layer and the initial first conductive layer 141 are further etched to form a first conductive layer 102, a diffusion barrier layer 103, a first gate conductive layer 111, a second gate conductive layer 112 and a gate capping layer 113 stacked in sequence in a direction away from the substrate 101, and the first conductive layer 102, the diffusion barrier layer 103, the first gate conductive layer 111, the second gate conductive layer 112 and the gate capping layer 113 form a gate structure.

[0132] refer to Fig.11In some embodiments, after forming the gate cap layer 113, the method further includes: forming a spacer structure 120 on the sidewall of the gate structure. In some embodiments, the method of forming the spacer structure 120 may include: using a deposition process to sequentially form a first spacer layer 121, a second spacer layer 122, and a third spacer layer 123 on the sidewall of the gate structure, for example, an atomic layer deposition process may be used. In some embodiments, the materials of the first spacer layer 121 and the third spacer layer 123 may both be silicon nitride, and the material of the second spacer layer 122 may be silicon oxide.

[0133] In some embodiments, after forming the spacer structure 120, the process further includes: forming a filling layer 115, wherein the filling layer 115 covers the surface of the spacer structure 120 and is flush with the top surface of the spacer structure 120. The filling layer 115 can be used to support other structures formed on the top surface of the spacer structure 120 in subsequent steps, for example, it can provide support for a third mask layer formed subsequently.

[0134] In some embodiments, after the step of forming the gate structure, a bit line conductive layer 130 is formed on the surface of the bit line contact structure 105, and a second conductive layer 110 is formed on the side of the first conductive layer 102 away from the surface of the substrate 101. The first conductive layer 102 and the second conductive layer 110 are used to form the gate structure, and the bit line conductive layer 130 is used to form the bit line structure.

[0135] refer to Fig. 9 In some embodiments, the first conductive material layer 41 and the second conductive material layer 42 not only cover the surface of the diffusion barrier layer 103 in the peripheral area 2, but also cover the surface of the bit line contact structure 105 in the array area 1. The first conductive material layer 41 in the array area 1 is used to form the first bit line conductive layer 131, and the second conductive material layer 42 in the array area 1 is used to form the second bit line conductive layer 130. In other words, the first gate conductive layer 111 and the first bit line conductive layer 131 are both formed by etching the same first conductive material layer 41, and the second gate conductive layer 112 and the second bit line conductive layer 130 are both formed by etching the same second conductive material layer 42, so that the process can be greatly simplified and the cost can be saved. In some embodiments, the material of the first conductive material layer 41 includes titanium nitride, and the material of the second conductive material layer 42 includes titanium.

[0136] In some embodiments, the initial capping layer 43 formed in the peripheral region 2 may also be formed on the surface of the second conductive material layer 42 in the array region 1 , and the initial capping layer 43 in the array region 1 is used to form the bit line capping layer 133 .

[0137] refer to Fig. 9In some embodiments, in the step of forming the second mask layer 50 and the second photoresist layer 13 in the peripheral region 2 , the second mask layer 50 and the second photoresist layer 13 are also formed in the array region 1 to protect the array region 1 .

[0138] refer to Fig.10 In the step of removing the second mask layer 50 in the peripheral area 2, the second mask layer 50 in the array area 1 is also removed.

[0139] refer to Figure 12 to Figure 14 , the first conductive material layer 41 and the second conductive material layer 42 on the surface of the bit line contact structure 105 are patterned to form a bit line conductive layer 130, and the bit line conductive layer 130 is in electrical contact with the bit line contact structure 105. In some embodiments, the first conductive material layer 41, the second conductive material layer 42 and the capping layer of the array region 1 can be patterned in the same process step.

[0140] In some embodiments, a SAQP process may be used to pattern the first conductive material layer 41, the second conductive material layer 42, and the initial capping layer 43 located on the surface of the bit line contact structure 105, and the method includes:

[0141] refer to Fig.12 A sub-capping layer 44 is formed on the surface of the initial capping layer 43 of the array region 1. The material of the sub-capping layer 44 is the same as that of the initial capping layer 43. The sub-capping layer 44 of the array region 1 is used to form a bit line capping layer together with the initial capping layer 43. In this way, the thickness of the bit line capping layer 133 is greater than the thickness of the gate capping layer 113. In other words, the thickness of different film layers can be adjusted according to different requirements of the bit line structure and the gate to achieve the best performance of the bit line structure and the gate structure.

[0142] In some embodiments, the formed sub-capping layer 44 is also located on the top surfaces of the filling layer 115 and the spacer structure 120 in the peripheral region 2 .

[0143] Continue to refer Fig.12 After forming the sub-capping layer 44, a third mask layer 60 and a third photoresist layer 14 are formed on the surface of the sub-capping layer 44. In some embodiments, the third mask layer 60 and the third photoresist layer 14 are formed on the surface of the sub-capping layer 44 in the peripheral region 2 and the surface of the sub-capping layer 44 in the array region 1.

[0144] In some embodiments, the third mask layer 60 includes a fourth hard mask layer 61, a fourth etch stop layer 62, a fifth hard mask layer 63, and a fifth etch stop layer 64 which are sequentially stacked in a direction away from the substrate 101. In some embodiments, the material of the fourth hard mask layer 61 may include APF, the material of the fourth etch stop layer 62 may include silicon oxynitride, the material of the fifth hard mask layer 63 may include a spin-on hard mask, and the material of the fifth etch stop layer 64 may include silicon oxynitride.

[0145] refer to Fig.12 , a patterning process is performed on the third photoresist layer 14 of the array area 1.

[0146] refer to Fig.13 , the fifth etch stop layer 64 and the fifth hard mask layer 63 not covered by the third photoresist layer 14 are etched to form the first sub-hard mask layer 152 of the fifth etch stop layer 64, the fifth hard mask layer 63 forms the second sub-hard mask layer 151, and the third photoresist layer 14 is removed.

[0147] In some embodiments, in the step of removing the third photoresist layer 14 in the array region 1 , the third photoresist layer 14 in the peripheral region 2 is removed.

[0148] After the step of removing the third photoresist layer 14, a fourth mask layer 15 is formed, and the fourth mask layer 15 covers the side surface of the first sub-hard mask layer 152, the side surface of the second sub-hard mask layer 151, and the top surface of the second sub-hard mask layer 151. In some embodiments, the material of the fourth mask layer 15 can be silicon oxide. In some embodiments, the fourth mask layer 15 can be formed on the side surface of the first sub-hard mask layer 152, the side surface of the second sub-hard mask layer 151, and the top surface of the second sub-hard mask layer 151 by a deposition process, for example, an atomic layer deposition process can be used.

[0149] In some embodiments, the fourth mask layer 15 is further formed on the top surface of the fifth etch stop layer 64 in the peripheral region 2 .

[0150] refer to Fig.14 After forming the fourth mask layer 15, the fourth mask layer 15 located on the top surface of the second sub-hard mask layer 151 is removed, and the fourth mask layer 15 located on the side of the first sub-hard mask layer 152 and the side of the second sub-hard mask layer 151 is retained as the third sub-hard mask layer 16, and the first sub-hard mask layer 152 and the second sub-hard mask layer 151 are removed.

[0151] The pattern of the third sub-hard mask layer 16 is used to define the shape of the bit line structure.

[0152] refer to Figure 2, based on the pattern of the third sub-hard mask layer 16, the fourth etch barrier layer 62 of the array area 1 and the fourth hard mask layer 61 of the array area 1 are etched until the top surface of the sub-cap layer 44 is exposed, and the sub-cap layer 44, the cap layer, the second conductive material layer 42 and the first conductive material layer 41 are further etched. The remaining sub-cap layer 44 and the cap layer form a bit line cap layer 133, the remaining second conductive material layer 42 of the array area 1 forms a second bit line conductive layer 130, and the remaining first conductive material layer 41 of the array area 1 forms a first bit line conductive layer 131.

[0153] In some embodiments, in the step of etching the first conductive material layer 41, the top surface of the bit line contact structure 105 is exposed, and the bit line contact structure 105 is etched so that the bit line contact structure 105 has the same shape as the formed first bit line conductive layer 131. In other words, the orthographic projection of the formed bit line contact structure 105 on the substrate 101 coincides with the orthographic projection of the first bit line conductive layer 131 on the substrate 101.

[0154] After the bit line structure is formed, the remaining third mask layer 60 is removed, and a portion of the sub-capping layer 44 in the peripheral region 2 is removed.

[0155] In the method for preparing the semiconductor structure provided in the above embodiment, different processes are used to form the first conductive layer 102 and the bit line contact structure 105, respectively, so that the process parameters for forming the first conductive layer 102 and the process parameters for forming the bit line contact structure 105 can be adjusted respectively, so that the first conductive layer 102 and the bit line contact structure 105 formed by different processes have the best performance respectively, thereby improving the performance of the semiconductor structure.

[0156] Those skilled in the art can understand that the above-mentioned embodiments are specific examples for realizing the present disclosure, and in practical applications, various changes can be made to them in form and details without departing from the spirit and scope of the present disclosure. Any person skilled in the art can make their own changes and modifications without departing from the spirit and scope of the present disclosure, so the protection scope of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A semiconductor structure, characterized in that: include: A substrate, the substrate comprising an array region and a peripheral region; A bit line structure, located in the array region, the bit line structure comprising a bit line contact structure in contact with the substrate; A gate structure is located in the peripheral region, the gate structure includes a first conductive layer located on the substrate, wherein in a direction perpendicular to the surface of the substrate, a top surface of the bit line contact structure is not higher than a top surface of the first conductive layer.

2. The semiconductor structure according to claim 1, characterized in that: The bit line structure further includes a bit line conductive layer, which is located on the bit line contact structure. The gate structure further includes a second conductive layer, and in a direction perpendicular to the substrate surface, the height of the bit line conductive layer is smaller than the height of the second conductive layer.

3. The semiconductor structure according to claim 2, characterized in that: The second conductive layer includes: a diffusion barrier layer and a gate conductive layer stacked in sequence in a direction away from the substrate.

4. The semiconductor structure according to claim 1, characterized in that: The material of the first conductive layer is ion-implanted doped polysilicon, and the bit line contact structure is in-situ doped polysilicon.

5. The semiconductor structure according to claim 3, characterized in that: The bit line conductive layer comprises a first bit line conductive layer. In a direction perpendicular to the substrate, the thickness of the first bit line conductive layer is not greater than the thickness of the diffusion barrier layer. The thickness of the first bit line conductive layer ranges from 2 to 10 nm, and the thickness of the diffusion barrier layer ranges from 5 to 20 nm.

6. The semiconductor structure according to claim 5, characterized in that: A material of the diffusion barrier layer is different from a material of the first bit line conduction layer.

7. The semiconductor structure according to claim 4, characterized in that: The substrate of the peripheral region includes a first active region, the first active region includes a first channel region, the first conductive layer is electrically connected to the first channel region, the first conductive layer has first doped ions, the first channel region has second doped ions, and the conductivity type of the first doped ions is the same as the conductivity type of the second doped ions; the substrate of the array region includes a second active region, the second active region includes a second channel region and second source and drain regions located on both sides of the second channel region, the bit line contact structure is electrically connected to one of the second source and drain regions, wherein the second channel region has third doped ions, the type of the third doped ions is different from the type of the second doped ions; the bit line contact structure has fourth doped ions, and the conductivity type of the fourth doped ions is the same as the conductivity type of the third doped ions.

8. The semiconductor structure according to claim 7, characterized in that: It also includes a gate oxide layer, wherein the gate oxide layer is located between the first conductive layer and the first channel region, and the equivalent gate oxide thickness of the gate oxide layer is 0.4A to 1A.

9. A method for preparing a semiconductor structure, characterized in that: include: Providing a substrate, the substrate having an array region and a peripheral region; forming a bit line contact structure in contact with the substrate in the array region, the bit line structure comprising a bit line contact structure in contact with the substrate; A gate structure is formed in the peripheral region, the gate structure comprising a first conductive layer located on the substrate, wherein in a direction perpendicular to the surface of the substrate, a top surface of the bit line contact structure is not higher than a top surface of the first conductive layer; wherein a process for forming the first conductive layer is different from a process for forming the bit line contact structure.

10. The method for preparing a semiconductor structure according to claim 9, characterized in that: The substrate of the peripheral region is formed with a first active region, the first active region includes a first channel region, the first conductive layer is electrically connected to the first channel region, the first conductive layer has first doping ions, the conductivity type of the first doping ions is the same as the conductivity type of the doping ions in the first channel region, and the process of forming the first conductive layer includes: forming an initial first conductive layer on the surface of the substrate in the peripheral region; A first doping process is performed on the initial first conductive layer to form first doping ions in the initial first conductive layer; and a patterning process is performed on the initial first conductive layer to form the first conductive layer electrically contacting the first channel region.

11. The method for preparing a semiconductor structure according to claim 10, characterized in that: The first doping process includes an ion implantation process.

12. The method for preparing a semiconductor structure according to claim 10, characterized in that: A second active region is formed in the substrate of the array region, the second active region includes a second channel region and second source and drain regions located on both sides of the second channel region, the bit line contact structure is electrically connected to one of the second source and drain regions, the initial first conductive layer is also formed on the surface of the substrate of the array region, and the process of forming the bit line contact structure includes: After the step of forming the first conductive layer, a portion of the initial first conductive layer in the array region is etched to expose the substrate surface, and a portion of the thickness of the substrate is further etched along the substrate surface to form a bit line contact hole, wherein the second source and drain region is exposed at the bottom of the bit line contact hole; The bit line contact structure filled in the bit line contact hole is formed.

13. The method for preparing a semiconductor structure according to claim 12, characterized in that: The bit line contact structure has fourth doping ions, and the conductivity type of the fourth doping ions is the same as the conductivity type of the doping ions in the second channel region; The method of forming the bit line contact structure includes: The bit line contact structure is formed by a deposition process, and in the step of depositing the bit line contact structure, an in-situ doping process is performed on the bit line contact structure to form fourth doping ions in the bit line contact structure.

14. The method for preparing a semiconductor structure according to any one of claims 9 to 13, characterized in that: After the step of forming the first conductive layer and before the step of forming the bit line contact structure, the method further includes: A diffusion barrier layer is formed on the top surface of the first conductive layer. The material of the diffusion barrier layer includes silicon-doped metal nitride.

15. The method for preparing a semiconductor structure according to claim 14, characterized in that: After the step of forming the bit line contact structure, the method further comprises: Forming a first conductive material layer and a second conductive material layer stacked in sequence in a direction away from the substrate surface, wherein the first conductive material layer and the second conductive material layer cover the surface of the bit line contact structure and the surface of the diffusion barrier layer; Performing a patterning process on the first conductive material layer and the second conductive material layer located on the surface of the bit line contact structure to form a bit line conductive layer, wherein the bit line conductive layer is in electrical contact with the bit line contact structure; The first conductive material layer and the second conductive material layer located on the surface of the diffusion barrier layer are subjected to a patterning process to form a gate conductive layer. The gate conductive layer, the diffusion barrier layer and the first conductive layer constitute the gate structure.

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