Three-dimensional dynamic random access memory and manufacturing method thereof

Abstract

The invention discloses a three-dimensional dynamic random access memory and a manufacturing method thereof, relates to the technical field of memories, and aims to improve the storage density of the dynamic random access memory, increase the contact area between a source region and a contact structure or between a drain region included in a transistor and a capacitor, reduce contact resistance and improve electric leakage. The three-dimensional dynamic random access memory comprises a plurality of memory units distributed in a three-dimensional array and a medium structure used for separating different memory units. Each memory cell includes a transistor and a capacitor. The transistor comprises a grid electrode, a grid dielectric layer, a channel region, a source region and a drain region, the length direction of the channel region is parallel to the second direction, and the two side walls of the channel region in the length direction are recessed inwards relative to the side walls of the corresponding first medium parts to form notches. And the source region and the drain region cover the inner wall of the notch. The manufacturing method of the three-dimensional dynamic random access memory is used for manufacturing the three-dimensional dynamic random access memory.

Description

Technical Field

[0001] The present invention relates to the field of memory technology, and in particular to a three-dimensional dynamic random access memory and a manufacturing method thereof. Background Art

[0002] In computer systems, memory is a key component for storing data and programs. As an important type of memory, dynamic random access memory (DRAM) plays a key role in modern computer architecture. DRAM includes a 1T1C memory cell structure. The memory cell of this dynamic random access memory consists of a transistor and a capacitor connected to the source or drain of the transistor. The capacitor is used to store charge, and the transistor is used to control access to the capacitor. This dynamic random access memory also includes a word line connected to the gate of the transistor and a bit line connected to the source or drain of the transistor. When accessing data to a certain memory cell, the word line connected to the memory cell is selected, and a voltage that turns on the transistor is input on the word line. The transistor is turned on, and then the bit line connected to the memory cell is selected to complete the gating of the memory cell, allowing access to the charge in the capacitor. However, since the capacitor will gradually leak electricity, resulting in a decrease in the stored charge, the dynamic random access memory needs to be refreshed regularly (usually every few milliseconds) to maintain the validity of the data. The refresh operation reads the data in each memory cell and rewrites it, thereby replenishing the charge lost in the capacitor.

[0003] In the prior art, the storage units of the dynamic random access memory are arranged in an array along the horizontal direction of the wafer, that is, a two-dimensional dynamic random access memory. However, the development of computer systems has put forward higher requirements on the density of dynamic random access memory, and the density of two-dimensional dynamic random access memory is limited by the process and cannot meet the density requirements. Summary of the invention

[0004] The object of the present invention is to provide a three-dimensional dynamic random access memory and a manufacturing method thereof, which are used to improve the storage density of the dynamic random access memory and increase the contact area between the source region and the drain region included in the transistor and the contact structure or capacitor respectively, reduce the contact resistance, and improve the leakage.

[0005] In order to achieve the above-mentioned object, in a first aspect, the present invention provides a three-dimensional dynamic random access memory, which includes: a plurality of storage units distributed in a three-dimensional array, and a dielectric structure for isolating different storage units. The plurality of storage units distributed in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer includes multiple storage groups spaced apart along a second direction, and each storage group includes multiple storage units distributed along a third direction. The first direction, the second direction and the third direction are different from each other. Each storage unit includes: a transistor and a capacitor. The dielectric structure includes a first dielectric portion located between two transistors spaced apart along the first direction. The transistor includes: a gate, a gate dielectric layer, a channel region, a source region and a drain region. The length direction of the channel region is parallel to the second direction, and the two side walls of the channel region along the length direction are indented inward relative to the side walls of the corresponding first dielectric portion to form a notch. The source region and the drain region are respectively arranged on both sides along the length direction and cover the inner wall of the notch; the gate dielectric layer is located between the gate and the channel region, the source region and the drain region respectively. The capacitor is electrically connected to the source region or the drain region of the transistor.

[0006] When the above technical solution is adopted, the three-dimensional dynamic random access memory provided by the present invention not only has a plurality of storage groups spaced apart along the second direction in the same layer, but also includes a plurality of storage layers spaced apart along the first direction, and the plurality of storage units are distributed in a three-dimensional array. Compared with a two-dimensional dynamic random access memory having only a single storage layer, each storage layer in the present invention can form a structure similar to that of a two-dimensional dynamic random access memory in the prior art, and the plurality of storage layers stacked along the first direction in the present invention can multiply the storage density of the three-dimensional dynamic random access memory provided by the present invention, effectively solving the problem of low density of the two-dimensional dynamic random access memory.

[0007] In addition, in the memory cell included in the three-dimensional dynamic random access memory provided by the present invention, the two side walls of the channel region included in the transistor along the length direction are indented inward relative to the side walls of the corresponding first dielectric portion, forming a notch. The source region and the drain region are respectively arranged on both sides along the length direction and cover the inner wall of the notch. In other words, the source region and the drain region of the transistor are not only arranged on the inner wall of the notch along the length direction of the channel region, but also cover the inner wall of the notch along the first direction. In this way, compared with the size of the source region and the drain region of the transistor in the prior art that only extends relative to the length direction of the channel region, the source region and the drain region of the transistor provided by the present invention can also additionally have a portion covering the inner wall of the notch along the first direction, that is, it has a larger geometric size in the second direction, and has a larger area of ​​the source region and the drain region, thereby increasing the contact area between the source region and the drain region and the contact structure or the capacitor, which is conducive to reducing the contact resistance between the source region and the drain region and the contact structure or the capacitor, improving the speed of the transistor, improving the storage performance of each memory cell, and improving the leakage current.

[0008] As a possible implementation, the ratio of the height of the notch to the width of the notch is greater than or equal to 0.1 and less than or equal to 10. The height of the notch is parallel to the first direction, and the width of the notch is parallel to the second direction.

[0009] In the case of adopting the above technical solution, when the height of the notch and the width of the notch are within the above range, the notch has a larger surface area. Since the source region and the drain region are respectively covered on the inner wall of the notch, compared with the prior art, the source region and the drain region in the present invention have additional surface areas in the height direction of the notch, that is, in the first direction, thereby increasing the contact area between the source region and the drain region and the contact structure or capacitor, which is beneficial to reduce the contact resistance between the source region and the drain region and the contact structure or capacitor, improve the speed of the transistor, and improve the leakage current. In addition, the size of the notch can be prevented from being too large, ensuring that in the process of manufacturing the three-dimensional dynamic random access memory provided by the present invention, when the notch is formed, the lateral etching width of the first dielectric layer and the gate layer arranged on the first dielectric layer (i.e., the width of the notch) is not too large, reducing the difficulty of lateral etching, thereby improving the yield of the three-dimensional dynamic random access memory provided by the manufacturing.

[0010] As a possible implementation manner, a ratio of the length of the channel region to the thickness of the channel region is greater than or equal to 10 and less than or equal to 1000. A thickness direction of the channel region is parallel to the first direction.

[0011] When the above technical solution is adopted, the source region and the drain region in the prior art extend only along the second direction from the side wall of the channel region. When the ratio of the length and the width of the channel region is within the above range, if the source region and the drain region extend only along the second direction, the size of the source region and the drain region is small. If the size of the source region and the drain region is increased by simply increasing the extension length of the source region and the drain region along the second direction, it is very easy to cause the source region and the drain region to collapse. Based on this, the source region and the drain region in the present invention can not only cover the inner wall of the recess along the second direction, but also cover the inner wall of the recess along the first direction. At this time, not only the area of ​​the source region and the drain region can be increased, but also the risk of collapse of the source region and the drain region can be prevented, thereby further improving the yield of the three-dimensional dynamic random access memory.

[0012] As a possible implementation manner, a ratio of the thickness of the channel region to the width of the notch is greater than or equal to 0.1 and less than or equal to 10. The width of the notch is parallel to the second direction.

[0013] When the above-mentioned technical scheme is adopted, the transistor provided by the present invention still has the source area and the drain area arranged at both ends of the length direction of the channel region in the prior art. Combined with the foregoing, the transistor provided by the present invention also includes the source area and the drain area along the first direction. The source area and the drain area of ​​the transistor provided by the present invention are larger than the source area and the drain area of ​​the transistor in the prior art. Please refer to the foregoing for its beneficial effects, which will not be repeated here.

[0014] As a possible implementation, the material of the channel region includes indium gallium zinc oxide.

[0015] In the case of adopting the above technical solution, indium gallium zinc oxide has a relatively high carrier mobility, which can make the transistor provided by the present invention have faster signal transmission and switching speed, thereby improving the working efficiency and response speed of the three-dimensional dynamic random access memory provided by the present invention. In addition, the current of the transistor whose channel region material includes indium gallium zinc oxide in the off state is very small, which helps to reduce the power consumption of the three-dimensional dynamic random access memory provided by the present invention and improve the battery life of the electronic device using the three-dimensional dynamic random access memory provided by the present invention. It can also reduce the demand for the heat dissipation system, thereby improving the reliability and stability of the electronic device using the three-dimensional dynamic random access memory provided by the present invention. At the same time, when manufacturing the three-dimensional dynamic random access memory provided by the present invention, the channel region of the indium gallium zinc oxide material can be made by a low-temperature process, which can reduce the demand for expensive high-temperature equipment and complex process steps, and can reduce costs; it can also reduce the risk of thermal damage to the three-dimensional memory, thereby improving the yield of the chip. In addition, although the structural strength of the channel region is low when the channel region material is indium gallium zinc oxide, the channel region manufactured by the present invention is not suspended during the manufacturing process, and will not collapse due to the low structural strength of the channel region.

[0016] As a possible implementation, the source region, the drain region and the channel region are integrally continuous.

[0017] When the above technical solution is adopted, when manufacturing the three-dimensional dynamic random access memory provided by the present invention, the source region, the drain region, and the channel region can be formed in the same process step, which can reduce the process steps, reduce the manufacturing cost, and improve the yield.

[0018] As a possible implementation manner, the gate includes a first gate and a second gate arranged at two sides of the channel region along a first direction.

[0019] When the above technical solution is adopted, the transistor provided by the present invention is a dual-gate transistor. A conventional transistor has only one gate to control the current in the channel region, while the transistor provided by the present invention has two gates. The dual-gate transistor can have twice the gate control area under the same channel region area, which can effectively improve the gate's control over the channel region, which makes the gate's control over carriers in the channel region more refined and flexible, and can more effectively adjust the conduction and cutoff of the current, thereby improving the switching performance of the transistor provided by the present invention, and can effectively suppress the short channel effect, which is conducive to further reducing the size of the transistor provided by the present invention, thereby improving the storage density of the three-dimensional dynamic random access memory provided by the present invention. For example, under low-voltage operation, the dual-gate transistor can control the current more accurately and achieve faster switching conversion, which is conducive to reducing the power consumption of the three-dimensional dynamic random access memory provided by the present invention.

[0020] As a possible implementation, the three-dimensional dynamic random access memory further includes a contact structure. Wherein, when the source region and the drain region included in the transistor are electrically connected to the capacitor, the drain region is electrically connected to the contact structure; or, when the drain region and the capacitor are electrically connected to the source region and the drain region included in the transistor, the source region is electrically connected to the contact structure. The dielectric structure further includes a second dielectric portion and a third dielectric portion. The second dielectric portion is located between two capacitors spaced apart along a third direction and between two contact structures spaced apart along the third direction. The third dielectric portion is located between two transistors spaced apart along the third direction.

[0021] When the above technical solution is adopted, the second dielectric part and the third dielectric part electrically isolate the multiple storage units spaced apart along the second direction, so that the multiple storage units spaced apart along the second direction can be accessed individually.

[0022] As a possible implementation, the capacitor includes a first electrode, a dielectric layer, and a second electrode. The dielectric layer is located between the first electrode and the second electrode. Each first electrode is filled in a corresponding notch. The dielectric layer and the second electrode are arranged between two adjacent transistors spaced apart along the second direction. The dielectric layers included in different capacitors spaced apart along the first direction are continuous as a whole, and the second electrodes included in different capacitors spaced apart along the first direction are continuous as a whole.

[0023] When the above technical solution is adopted, the first electrode can also be reused as the source electrode or drain electrode of the transistor provided by the present invention, and also as a plate of the capacitor included in the storage unit provided by the present invention, connecting the transistor and the capacitor to form a storage unit of a dynamic random access memory of one transistor and one capacitor (1T1C). In addition, the integrated and continuous second electrode and dielectric layer can make the dielectric layers of different capacitors and the second electrodes of different capacitors formed at the same time when manufacturing the three-dimensional dynamic random access memory provided by the present invention, reducing the process steps of separately forming the dielectric layers and second electrodes of different capacitors, which is conducive to reducing costs and improving productivity.

[0024] In a second aspect, the present invention further provides a method for manufacturing a three-dimensional dynamic random access memory, the method comprising: forming a plurality of storage cells distributed in a three-dimensional array; the plurality of storage cells distributed in a three-dimensional array comprise a plurality of storage layers spaced apart along a first direction, each storage layer comprises a plurality of storage groups spaced apart along a second direction, each storage group comprises a plurality of storage cells distributed along a third direction; the first direction, the second direction and the third direction are different from each other; each storage cell comprises: a transistor and a capacitor; forming a dielectric structure for isolating different storage cells; the dielectric structure comprises a first dielectric portion located between two transistors spaced apart along the first direction; the transistor comprises: a gate, a gate dielectric layer, a channel region, a source region and a drain region; the length direction of the channel region is parallel to the second direction, and the two side walls of the channel region along the length direction are indented inwardly relative to the side walls of the corresponding first dielectric portion to form a notch; the source region and the drain region are respectively arranged on both sides along the length direction and cover the inner wall of the notch; the gate dielectric layer is respectively located between the gate and the channel region, the source region and the drain region.

[0025] Compared with the prior art, the beneficial effects of the method for manufacturing the three-dimensional dynamic random access memory provided by the present invention are the same as the beneficial effects of the three-dimensional dynamic random access memory of the above technical solution, which will not be described in detail here.

[0026] As a possible implementation, forming a plurality of storage units distributed in a three-dimensional array and forming a dielectric structure for isolating different storage units includes: forming a stacking structure and a second dielectric part penetrating the stacking structure; the stacking structure includes a plurality of stacking units stacked in a first direction; each stacking unit includes a first dielectric layer and a stack located on the first dielectric layer; the stack includes a stacked second dielectric layer and a gate; the material of the first dielectric layer is different from the material of the second dielectric layer; a first through hole group and a second through hole group are provided in the stacking structure and are spaced apart in the second direction; the first through hole group and the second through hole group both include a plurality of through holes spaced apart in a third direction; the second dielectric part is disposed between two through holes adjacent to each other in the first direction in the same first through hole group, and between two through holes adjacent to each other in the first direction in the same second through hole group; the first dielectric part includes a first dielectric layer. Next, the edge portion of each gate layer is selectively removed to form a notch. Next, the second dielectric layer is selectively etched so that the remaining second dielectric layer forms a third dielectric part; the third dielectric part is located between two transistors spaced apart in the third direction; the dielectric structure includes a first dielectric part, a second dielectric part and a third dielectric part. Next, a gate dielectric layer covering the periphery of the gate is deposited; and a channel region, a source region, and a drain region are deposited on the gate dielectric layer. Next, a contact structure is formed in each through hole included in the first through hole group, and a first electrode included in the capacitor is formed in a portion corresponding to a notch of each through hole included in the second through hole group. Next, a dielectric layer and a second electrode are sequentially formed in each through hole included in the second through hole group; the capacitor includes a first electrode, a dielectric layer, and a second electrode.

[0027] In the case of adopting the above technical solution, the first dielectric part includes the entire first dielectric layer, and the second dielectric part that is completely removed serves as a pre-occupying structure of the channel region. After being removed, a gate dielectric layer covering the periphery of the gate is deposited in sequence, and a channel region, a source region, and a drain region are deposited on the gate dielectric layer. In the prior art, in the process of manufacturing a transistor, the sacrificial layer stacked on both sides of the channel region is first removed, and then a gate dielectric layer and a gate are formed on both sides of the channel region along the first direction and the second direction. At this time, the channel region is suspended, and the channel region is a semiconductor material with a lower structural strength. When the memory cell has a smaller geometric size, the channel region of the semiconductor material with a larger length-to-width ratio along the second direction will collapse, causing the transistor to deform, thereby reducing the performance of the memory cell and even failing to work normally, reducing the yield. Based on this, in the present invention, when manufacturing a three-dimensional dynamic random access memory, after the second dielectric layer is selectively etched so that the remaining second dielectric layer forms the third dielectric part, the gate is suspended. Compared with the channel region material, the gate material has a higher structural strength and is less likely to collapse due to the larger length-to-width ratio along the second direction when the memory cell has a smaller geometric size. The manufacturing method of the three-dimensional dynamic random access memory provided by the present invention can ensure the regular structure of the transistor, thereby ensuring the normal operation and stable performance of the storage unit manufactured by the manufacturing method of the three-dimensional dynamic random access memory provided by the present invention, thereby improving the yield.

[0028] As a possible implementation, forming a stacked structure and a second dielectric portion penetrating the stacked structure includes: forming a stacked material layer. Next, forming a third through hole group and a fourth through hole group penetrating the stacked material layer; the orifice pattern of the third through hole group is the same as the top pattern of the second dielectric layer. Next, forming a second dielectric portion filled in the third through hole group and the fourth through hole group.

[0029] When the above technical solution is adopted, compared with the prior art, the beneficial effects of the manufacturing method of the three-dimensional dynamic random access memory provided by the present invention are the same as the beneficial effects of the three-dimensional dynamic random access memory of the above technical solution, which will not be repeated here.

[0030] As a possible implementation manner, the diameter of each through hole included in the first through hole group is greater than or equal to 30 nm and less than or equal to 3000 nm.

[0031] When the above technical solution is adopted, it can avoid that the process requirements for etching and photolithography are too high due to the small aperture, which leads to high cost, and it is helpful to reduce the cost; it can also avoid that the contact structure is difficult to form evenly on the hole wall or difficult to form the contact structure due to the small aperture. It can also avoid that the aperture is too large and occupies too much area, thereby reducing the storage density of the three-dimensional dynamic random access memory manufactured by the present invention.

[0032] As a possible implementation manner, the diameter of each through hole included in the second through hole group is greater than or equal to 50 nm and less than or equal to 5000 nm.

[0033] When the above technical solution is adopted, it can avoid that the process requirements for etching and photolithography are too high due to the small aperture, which leads to too high cost, and it is conducive to reducing costs; it can also avoid that the capacitor area formed by the small aperture is small, thereby reducing the retention time of the capacitor, resulting in a higher refresh frequency and increased power consumption, thereby reducing the power consumption of the three-dimensional dynamic random access memory manufactured by the present invention. It can also avoid that the aperture is too large and occupies too much area, thereby reducing the storage density of the three-dimensional dynamic random access memory manufactured by the present invention. In addition, when manufacturing the first electrode and the contact structure, a material layer of the first electrode and the contact structure is formed by depositing on the surface of the three-dimensional dynamic random access memory manufactured by the present invention, and then the material layer is etched to form the first electrode and the contact structure; since the aperture of each through hole included in the first through hole group is smaller than the aperture of each through hole included in the second through hole group, the material layer fills each through hole included in the first through hole group, but is only formed on the inner wall of each through hole included in the second through hole group. During subsequent etching, only the material layer on the top of each through hole included in the first through hole group and the material layer on the inner wall of each through hole included in the second through hole group will be removed. In this process, the first electrode and the contact structure can be formed without using a mask, which reduces the process steps, reduces costs and improves productivity. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The drawings described herein are used to provide a further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute an improper limitation of the present invention. In the drawings:

[0035] Figure 1 A schematic diagram of a three-dimensional dynamic random access memory provided by an embodiment of the present invention;

[0036] Figure 2 A schematic diagram of forming a stacked material layer in an embodiment of the present invention;

[0037] Figure 3 A schematic diagram of forming a third through hole group and a fourth through hole group in an embodiment of the present invention;

[0038] Figure 4 A schematic diagram of forming a second dielectric portion in an embodiment of the present invention;

[0039] Figure 5 A schematic diagram of forming a first through hole group and a second through hole group in an embodiment of the present invention;

[0040] Figure 6 A schematic diagram of forming a notch in an embodiment of the present invention;

[0041] Figure 7 A schematic diagram of removing the second dielectric layer in an embodiment of the present invention;

[0042] Figure 8 is a schematic diagram of forming a gate dielectric layer in an embodiment of the present invention;

[0043] Fig. 9 is a cross-sectional view along a first direction and a second direction of forming a channel layer in an embodiment of the present invention;

[0044] Fig.10 is a cross-sectional view along a first direction and a second direction of forming an electrode layer in an embodiment of the present invention;

[0045] Fig.11 A cross-sectional view along a first direction and a second direction of forming a first electrode and a contact structure in an embodiment of the present invention;

[0046] Fig.12 It is a schematic diagram of forming a dielectric layer and forming a second electrode in an embodiment of the present invention.

[0047] Reference numerals:

[0048] 100 - memory cell, 101 - channel region, 102 - source region, 103 - drain region, 104 - notch, 105 - channel layer, 110 - gate, 111 - first gate, 112 - second gate, 120 - gate dielectric layer, 130 - contact structure, 140 - transistor;

[0049] 200 - capacitor, 201 - first electrode, 202 - dielectric layer, 203 - second electrode, 204 - electrode layer;

[0050] 310 - first dielectric portion, 311 - first dielectric layer, 320 - second dielectric portion, 331 - second dielectric layer, 332 - third dielectric portion;

[0051] 410 - a first through hole group, 420 - a second through hole group, 430 - a third through hole group, 440 - a fourth through hole group. DETAILED DESCRIPTION

[0052] In order to make the technical problems, technical solutions and beneficial effects to be solved by the embodiments of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present invention and are not used to limit the embodiments of the present invention.

[0053] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0054] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined. "Several" means one or more, unless otherwise clearly and specifically defined.

[0055] In the description of the embodiments of the present invention, it should be understood that the directions or positional relationships indicated by the terms "up", "down", "front", "back", "left", "right", etc. are based on the directions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the embodiments of the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific direction, be constructed and operated in a specific direction, and therefore cannot be understood as a limitation on the embodiments of the present invention.

[0056] In the description of the embodiments of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the embodiments of the present invention can be understood according to specific circumstances.

[0057] In computer systems, memory is a key component for storing data and programs. As an important type of memory, dynamic random access memory (DRAM) plays a key role in modern computer architecture. Dynamic random access memory includes a 1T1C storage cell structure. The storage cell of this dynamic random access memory consists of a transistor and a capacitor connected to the source or drain of the transistor. The capacitor is used to store charge, and the transistor is used to control access to the capacitor. This dynamic random access memory also includes a word line connected to the gate of the transistor, and a bit line connected to the source or drain region of the transistor that is not connected to the capacitor. When accessing data to a certain storage cell, the word line connected to the storage cell is selected, and a voltage that turns on the transistor is input on the word line. The transistor is turned on, and then the bit line connected to the storage cell is selected to complete the gating of the storage cell, allowing access to the charge in the capacitor. However, since the capacitor will gradually leak electricity, resulting in a decrease in the stored charge, the dynamic random access memory needs to be refreshed regularly (usually every few milliseconds) to maintain the validity of the data. The refresh operation reads the data in each memory cell and rewrites it, thereby replenishing the charge lost in the capacitor.

[0058] In the prior art, the storage cells of the dynamic random access memory are arranged in an array along the horizontal direction of the wafer, that is, a two-dimensional dynamic random access memory. In a two-dimensional dynamic random access memory, transistors are arranged in an array on the wafer, and capacitors can be distributed in the same plane as transistors in the same way, or they can be arranged above or below the transistors to increase the storage density. However, the development of computer systems has put forward higher requirements on the density of dynamic random access memory, and the density of the above two types of two-dimensional dynamic random access memory is limited by the process, and both transistors and capacitors cannot be infinitely reduced to meet the density requirements.

[0059] To solve the above problems, please refer to Figure 1The embodiment of the present invention provides a three-dimensional dynamic random access memory, which includes: a plurality of storage units 100 distributed in a three-dimensional array, and a dielectric structure for isolating different storage units 100; the plurality of storage units 100 distributed in a three-dimensional array include multiple storage layers distributed along a first direction, each storage layer includes multiple storage groups distributed along a second direction, each storage group includes multiple storage units 100 distributed along a third direction; the first direction, the second direction and the third direction are different from each other. Each storage unit 100 includes: a transistor 140 and a capacitor 200; the dielectric structure includes a first dielectric portion 310 located between two transistors 140 distributed along the first direction. The transistor 140 includes: a gate 110, a gate dielectric layer 120, a channel region 101, a source region 102 and a drain region 103; the length direction of the channel region 101 is parallel to the second direction, and the two side walls of the channel region 101 along the length direction are indented inward relative to the side walls of the corresponding first dielectric portion 310 to form a notch 104; the source region 102 and the drain region 103 are respectively arranged on both sides along the length direction and cover the inner wall of the notch 104; the gate dielectric layer 120 is respectively located between the gate 110 and the channel region 101, the source region 102 and the drain region 103. The capacitor 200 is electrically connected to the source region 102 or the drain region 103 of the transistor 140.

[0060] When using the above technical solution, please refer to Figure 1 , multiple storage units 100 are distributed along the third direction to form a storage group, multiple storage groups are distributed along the second direction at intervals to form a storage layer, and multiple storage layers are distributed along the first direction at intervals to form multiple storage units 100 distributed in a three-dimensional array, forming a three-dimensional dynamic random access memory provided by an embodiment of the present invention. Compared with the prior art, the storage layer forms a structure that is analogous to the two-dimensional dynamic random access memory of the prior art, but multiple stacked storage layers are stacked in the first direction, so that the storage density of a three-dimensional dynamic random access memory provided by an embodiment of the present invention is doubled, effectively solving the problem of low density of the two-dimensional dynamic random access memory.

[0061] In addition, please refer to Figure 1In the memory cell 100 included in the three-dimensional dynamic random access memory provided by the embodiment of the present invention, the two side walls of the channel region 101 included in the transistor 140 along the length direction are recessed inward relative to the side walls of the corresponding first dielectric portion 310, forming a notch 104; the source region 102 and the drain region 103 are respectively arranged on both sides along the length direction and cover the inner wall of the notch 104. In other words, the source region 102 and the drain region 103 of the transistor 140 are not only arranged on the inner wall of the notch 104 along the length direction of the channel region 101, but also cover the inner wall of the notch 104 along the first direction. With such a configuration, compared with the dimensions of the source region 102 and the drain region 103 of the transistor 140 in the prior art which only extend in the length direction relative to the channel region 101, the source region 102 and the drain region 103 of the transistor 140 provided in the embodiment of the present invention can also additionally have a portion covering the inner wall of the recess 104 along the first direction, that is, having a larger geometric dimension in the second direction, having a larger area of ​​the source region 102 and the drain region 103, thereby increasing the contact area between the source region 102 and the drain region 103 and the contact structure 130 or the capacitor 200, respectively, which is beneficial to reducing the contact resistance between the source region 102 and the drain region 103 and the contact structure 130 or the capacitor 200, respectively, improving the speed of the transistor 140, and improving the leakage current.

[0062] In actual application, the embodiment of the present invention does not specifically limit the specific arrangement direction and distribution of different storage units 100, as long as the different storage units 100 are distributed in a three-dimensional array. As for the specific directions referred to by the first direction, the second direction and the third direction, no specific limitation is made here, as long as the directions of any two of the above three directions are different.

[0063] For example, the first direction is the height direction of the 3D DRAM provided by the embodiment of the present invention, and the second direction and the third direction can be determined according to the distribution of different storage units 100 in the same storage layer. Figure 1 , when different storage units 100 in the same storage layer are distributed in a rectangular array, the second direction and the third direction may be the directions of the length and width of the rectangular array, respectively. For another example: when different storage units 100 in the same storage layer are distributed in a parallelogram array, the second direction and the third direction may be the directions of two adjacent sides of the parallelogram array, respectively. In another example, for another example: when different storage units 100 in the same storage layer are distributed in a concentric circle array, the second direction and the third direction may be the radial direction and the circumferential direction of the concentric circle array, respectively. It can be understood that when the storage units in the same storage layer are distributed differently, the second direction and the third direction may be changed along with its distribution.

[0064] In actual application, the embodiment of the present invention does not impose any specific limitation on the specific shape and distribution of the medium structure, as long as different storage units 100 can be isolated.

[0065] For details, please refer to Figure 1 The dielectric structure includes a first dielectric portion 310 located between two transistors 140 spaced apart along the first direction. The first dielectric portion 310 protrudes from the channel region 101 in the second direction to form a notch 104 .

[0066] In actual application, the embodiment of the present invention does not impose any specific restrictions on the material of the first dielectric portion 310, as long as it can isolate and insulate the gates 110 included in two transistors 140 adjacent to each other along the first direction. For example, the first dielectric portion 310 can be made of silicon oxide or silicon nitride. The first dielectric layer 311 can also be made of a combination of multiple materials, as long as it can be realized in terms of process.

[0067] As for the distance between two adjacent first dielectric portions 310, it can be understood that it is determined by the size of the transistor located between the two adjacent first dielectric portions 310 along the first direction. For example, the distance between two adjacent first dielectric portions 310 can be 5nm to 500nm.

[0068] As for the thickness of the first dielectric portion 310 , the embodiment of the present invention does not impose any specific limitation thereon, as long as it can isolate and insulate the gates 110 included in two transistors 140 adjacent to each other along the first direction. For example, the thickness of the first dielectric portion 310 may be 10 nm to 1000 nm.

[0069] For details about the shape of the notch 104, please refer to Figure 1 The bottom of the recess 104 is composed of the gate 110 and the side walls of the channel region 101 along the first direction; the side walls of the recess 104 are composed of the relative surfaces of the protruding parts of the first dielectric portion 310 located on both sides of the transistor 140 in the first direction, and are composed of a structure arranged to isolate the two storage units 100 along the third direction in the third direction.

[0070] It can be understood that the three-dimensional dynamic random access memory provided by the embodiment of the present invention further includes a plurality of contact structures 130 that can be used as data lines or bit lines, and a second dielectric portion 320 that isolates the contact structures 130 distributed along the third direction. Each contact structure 130 is connected to the source region 102 or drain region 103 of the transistor 140 included in the plurality of memory cells 100 along the first direction, and connects the source region 102 or drain region 103 of the transistor 140 included in two adjacent memory cells 100 along the second direction. The second dielectric portion 320 runs through the three-dimensional dynamic random access memory provided by the embodiment of the present invention to completely isolate the two adjacent contact structures 130 along the third direction.

[0071] In actual application, the embodiment of the present invention does not specifically limit the material of the contact structure 130, which can be determined according to the performance and manufacturing process requirements of the three-dimensional dynamic random access memory provided by the embodiment of the present invention. Exemplarily, the material of the contact structure 130 can be at least one of copper, aluminum, chromium, and tungsten.

[0072] In actual application, the embodiment of the present invention does not specifically limit the material of the second dielectric portion 320, and only needs to meet the requirements of structural insulation provided in two adjacent through holes of the first through hole group 410 arranged on both sides of the second dielectric portion 320 in the third direction, and the requirements of structural insulation provided in two adjacent through holes of the second through hole group 420 arranged on both sides of the second dielectric portion 320 in the third direction.

[0073] It should be noted that the material of the first dielectric portion 310 and the material of the second dielectric portion 320 may be the same or different, which may be determined according to the manufacturing process.

[0074] Understandably, please refer to Figure 1 , along the third direction, the dielectric structure includes a third dielectric portion 332, and the third dielectric portion 332 is located between two transistors 140 spaced apart along the third direction. The third dielectric portion 332 at least electrically isolates the channel regions 101 of the two transistors 140 spaced apart along the third direction, so as to facilitate separate access to two adjacent storage cells 100 including two adjacent transistors 140 spaced apart along the third direction. The gates 110 of the two transistors 140 spaced apart along the third direction are connected to each other to form a word line of the three-dimensional dynamic random access memory provided by the embodiment of the present invention. In addition, along the third direction, the gate 110 region between the two transistors 140 spaced apart is not recessed into the first dielectric portion 310, and together with the sidewall of the third dielectric portion 332, forms the sidewall of the recess 104 along the third direction, and the gate dielectric layer 120 is also arranged on the sidewall of the recess 104 along the third direction, thereby further increasing the contact area between the source region 102 and the drain region 103 and the capacitor 200 or the contact structure 130.

[0075] Regarding the material of the third dielectric part 332, it is different from the material of the first dielectric part 310 and the material of the second dielectric part 320. Please refer to the following content to facilitate the selective etching of the third dielectric part 332. For example, when the materials of the first dielectric part 310 and the second dielectric part 320 are the same and both are silicon oxide, the third dielectric part 332 can be silicon nitride.

[0076] Please refer to Figure 1Each memory cell 100 included in the three-dimensional dynamic random access memory provided by the embodiment of the present invention includes a transistor 140 and a capacitor 200 to form a 1T1C dynamic random access memory structure.

[0077] In actual application, the connection relationship between the transistor 140 and the capacitor 200 included in the storage unit 100 is not specifically limited in the embodiment of the present invention, and can be determined according to the conductivity type of the transistor 140 and actual needs. For example, when the source region 102 and the drain region 103 included in the transistor 140, the source region 102 is electrically connected to the capacitor 200, and the drain region 103 is electrically connected to the contact structure 130; or, please refer to Figure 1 When the transistor 140 includes a source region 102 and a drain region 103 , and the drain region 103 is electrically connected to the capacitor 200 , the source region 102 is electrically connected to the contact structure 130 .

[0078] It should be noted that the drawings provided in the embodiments of the present invention only illustrate the case where the drain region 103 is electrically connected to the capacitor 200 and the source region 102 is electrically connected to the contact structure 130, but it does not mean that only the above connection relationship can be used. The specific connection relationship between the source region 102 and the drain region 103 in the transistor 140 and the contact structure 130 and the capacitor 200, respectively, can be referred to in the above text. When the drain region 103 is electrically connected to the capacitor, the source region 102 is electrically connected to the contact structure.

[0079] It can be understood that, in the third direction, the second dielectric portion 320 also isolates the capacitors 200 included in the plurality of storage units 100 , so as to achieve isolation of the data stored in the plurality of storage units 100 .

[0080] Please refer to Figure 1 The transistor 140 includes a gate 110 , a gate dielectric layer 120 , a channel region 101 , a source region 102 and a drain region 103 .

[0081] From the structural aspect, the length direction of the channel region 101 is parallel to the second direction, and the two side walls of the channel region 101 along the length direction are indented inward relative to the side walls of the corresponding first dielectric portion 310 to form a notch 104; the source region 102 and the drain region 103 are respectively arranged on both sides along the length direction and cover the inner wall of the notch 104; the gate dielectric layer 120 is located between the gate 110 and the channel region 101, the source region 102 and the drain region 103 respectively. Since the channel region 101, the source region 102 and the drain region 103 are formed later relative to the gate 110, they will not be suspended when manufacturing the three-dimensional dynamic random access memory provided by the embodiment of the present invention, which is conducive to preventing the collapse of the channel region 101, the source region 102 and the drain region 103 due to the low structural strength, thereby ensuring the regular structure of the transistor 140, thereby ensuring the normal operation and stable performance of the storage unit 100 manufactured by the manufacturing method of the three-dimensional dynamic random access memory provided by the present invention, thereby improving the yield.

[0082] In actual application, the embodiment of the present invention does not specifically limit the structure of the gate 110 of the transistor 140, and can be determined according to the performance requirements of the three-dimensional dynamic random access memory of the embodiment of the present invention. The gate 110 structure of the transistor 140 can be a traditional single-gate transistor or a double-gate transistor, or other possible gate 110 structures.

[0083] Illustratively, transistor 140 is a conventional single-gate transistor. Along a first direction, gate 110 is disposed on first dielectric portion 310 , gate dielectric layer 120 is disposed on gate 110 , channel region 101 , source region 102 and drain region 103 are disposed on gate 110 and first dielectric portion 310 .

[0084] Exemplarily, transistor 140 is a dual-gate transistor. Figure 1In the first direction, the first gate 111 and the second gate 112 included in the gate 110 are respectively arranged on two adjacent layers of the first dielectric part 310, and the edges of the first gate 111 and the second gate 112 are recessed between the first dielectric part 310 along the second direction to form a notch 104, that is, the projections of the first gate 111 and the second gate 112 in the second direction are smaller than the projections of the first dielectric part 310 in the second direction. Between the two adjacent layers of the first dielectric part 310, a gate dielectric layer 120 covering the periphery of the gate 110 is arranged on the first gate 111, the second gate 112 and the inner wall of the notch 104, and a channel region 101, a source region 102 and a drain region 103 covering the periphery of the gate dielectric layer 120 are arranged on the gate dielectric layer 120. The gate 110, the gate dielectric layer 120, the channel region 101, the source region 102 and the drain region 103 constitute a transistor 140. The transistor 140 provided in the embodiment of the present invention has two gates 110. The dual-gate transistor can have a larger gate control area under the condition of the same channel region 101 area, and can effectively improve the control ability of the gate 110 over the channel region 101, which makes the gate 110 more precise and flexible in controlling the carriers in the channel region 101, and can more effectively adjust the conduction and cutoff of the current, thereby improving the switching performance of the transistor 140 provided in the embodiment of the present invention. For example, under low-voltage operation, the dual-gate transistor can control the current more accurately and achieve faster switching conversion, which is beneficial to reducing the power consumption of the three-dimensional dynamic random access memory provided in the embodiment of the present invention. In addition, the transistor 140 provided in the embodiment of the present invention is a dual-gate transistor, which can effectively suppress the short channel effect, which is beneficial to further reduce the size of the transistor 140 provided in the embodiment of the present invention, thereby improving the storage density of the three-dimensional dynamic random access memory provided in the embodiment of the present invention.

[0085] Regarding the connection relationship between the source region 102, the drain region 103 and the channel region 101, they can be manufactured simultaneously and be continuous as a whole; the source region 102, the drain region 103 and the channel region 101 can also be formed separately, the source region 102 and the channel region 101 are connected at the bottom of a recess 104 included in the transistor 140, and the drain region 103 and the channel region 101 are connected at the bottom of another recess 104.

[0086] Optionally, the source region 102, the drain region 103 and the channel region 101 are continuous as one. In this case, when manufacturing the three-dimensional dynamic random access memory provided by the embodiment of the present invention, the source region 102, the drain region 103, and the channel region 101 can be formed in the same process step, which can reduce the process steps, reduce the manufacturing cost, and improve the yield.

[0087] In actual application, the embodiment of the present invention does not specifically limit the material of the channel region 101, as long as the performance of the material can meet the speed requirements of the three-dimensional dynamic random access memory provided by the embodiment of the present invention. The material of the channel region 101 can be a common silicon material, or a material with high electron mobility such as germanium, silicon germanium, and indium gallium zinc oxide to reduce the resistivity of the channel region 101 and increase the speed of the transistor 140.

[0088] Optionally, the material of the channel region 101 includes indium gallium zinc oxide. In this case, indium gallium zinc oxide has a relatively high carrier mobility, which means that the electrons move faster in the material, which can make the transistor 140 provided in the embodiment of the present invention have faster signal transmission and switching speed, thereby improving the working efficiency and response speed of the three-dimensional dynamic random access memory provided in the embodiment of the present invention. And the current of the transistor 140 whose channel region 101 material is indium gallium zinc oxide in the off state is very small, which helps to reduce the power consumption of the three-dimensional dynamic random access memory provided in the embodiment of the present invention and improve the battery life of the electronic device using the three-dimensional dynamic random access memory provided in the embodiment of the present invention. It can also reduce the demand for the heat dissipation system, thereby improving the reliability and stability of the electronic device using the three-dimensional dynamic random access memory provided in the embodiment of the present invention. At the same time, when manufacturing the three-dimensional dynamic random access memory provided in the embodiment of the present invention, the channel region 101 of the indium gallium zinc oxide material can be made by a low-temperature process, which can reduce the demand for expensive high-temperature equipment and complex process steps, and can reduce costs; it can also reduce the risk of thermal damage to the three-dimensional memory, thereby improving the yield of the chip.

[0089] In actual application, the material of the source region 102 and the drain region 103 may be different from that of the channel region 101, or may be the same as that of the channel region 101. The embodiment of the present invention does not impose any specific restrictions thereon, as long as the design requirements and process requirements of the three-dimensional dynamic random access memory provided by the embodiment of the present invention are met. When the material of the source region 102 and the drain region 103 is the same as that of the channel region 101, it is conducive to forming an integrated and continuous source region 102, drain region 103 and channel region 101, and the source region 102, drain region 103 and channel region 101 may also be formed separately. When the material of the source region 102 and the drain region 103 is different from that of the channel region 101, it is conducive to forming the source region 102, drain region 103 and channel region 101 separately.

[0090] In actual application, the embodiment of the present invention does not specifically limit the material of the gate dielectric layer 120, as long as it can be applied to the three-dimensional dynamic random access memory provided by the embodiment of the present invention. For example, a high dielectric constant material including hafnium dioxide can be used to reduce the thickness of the gate dielectric layer 120, thereby reducing the height of the suspended transistor 140 provided by the embodiment of the present invention when manufacturing, effectively avoiding structural damage caused by the suspended transistor, thereby improving the yield; the thickness of the transistor 140 can also be reduced to improve the storage density.

[0091] In actual application, the embodiment of the present invention does not impose any specific restrictions on the material of the gate 110, as long as the parameters of the material of the gate 110 meet the design requirements and process requirements of the three-dimensional dynamic random access memory provided by the embodiment of the present invention. For example, the material of the gate 110 can be copper, aluminum or tungsten. Optionally, the material of the gate 110 is tungsten, because tungsten is stable in nature and is not easy to diffuse to other structures, and tungsten is not easily affected by the high-temperature process steps when manufacturing the three-dimensional dynamic random access memory provided by the embodiment of the present invention, resulting in changes in shape, which can ensure the performance of the three-dimensional dynamic random access memory provided by the embodiment of the present invention.

[0092] In addition, please refer to Figure 1 Regarding the notch 104, since the source region 102 and the drain region 103 are arranged on the inner wall of the notch 104, the inner wall surface area of ​​the notch 104 is also the contact area between the source region 102 and the drain region 103 and the contact structure or capacitor, respectively. Therefore, in order to reduce the contact resistance between the source region 102 and the drain region 103 and the contact structure or capacitor, respectively, the embodiment of the present invention defines its shape as follows:

[0093] For details, please refer to Figure 1, the ratio of the height of the notch 104 to the width of the notch 104 is greater than or equal to 0.1 and less than or equal to 10. The height of the notch 104 is parallel to the first direction, and the width of the notch 104 is parallel to the second direction. In this case, when the height of the notch 104 and the width of the notch 104 are within the above range, the notch 104 has a larger surface area. Because the source region 102 and the drain region 103 are respectively covered on the inner wall of the notch 104, compared with the prior art, the source region 102 and the drain region 103 in the present invention have additional surface areas in the height direction of the notch 104, that is, in the first direction, thereby increasing the contact area between the source region 102 and the drain region 103 and the contact structure 130 or the capacitor 200, which is beneficial to reduce the contact resistance between the source region 102 and the drain region 103 and the contact structure 130 or the capacitor 200, thereby increasing the speed of the transistor 140 and improving the leakage current. Furthermore, the size of the notch 104 is prevented from being too large, ensuring that in the process of manufacturing the three-dimensional dynamic random access memory provided by the embodiment of the present invention, when the notch 104 is formed, the lateral etching width of the first dielectric portion 310 and the gate 110 layer arranged on the first dielectric portion 310 (i.e., the width of the notch 104) is not too large, thereby reducing the difficulty of lateral etching, thereby improving the yield of the three-dimensional dynamic random access memory provided by the manufacturing.

[0094] For further information, please refer to Figure 1 , the ratio of the length of the channel region 101 to the thickness of the channel region 101 is greater than or equal to 10 and less than or equal to 1000. The thickness direction of the channel region 101 is parallel to the first direction. In this case, the source region 102 and the drain region 103 in the prior art extend from the sidewall of the channel region 101 along the second direction. When the ratio of the length and the width of the channel region 101 is within the above range, if the source region 102 and the drain region 103 only extend along the second direction, the size of the source region 102 and the drain region 103 is small. If the size of the source region 102 and the drain region 103 is increased by simply increasing the extension length of the source region 102 and the drain region 103 along the second direction, it is very easy to cause the source region 102 and the drain region 103 to collapse. Based on this, in the embodiment of the present invention, the source region 102 and the drain region 103 can not only cover the inner wall of the recess 104 along the second direction, but also cover the inner wall of the recess 104 along the first direction. At this time, not only the area of ​​the source region 102 and the drain region 103 can be increased, but also the risk of collapse of the source region 102 and the drain region 103 can be prevented, thereby further improving the yield of the three-dimensional dynamic random access memory.

[0095] Further, the ratio of the thickness of the channel region 101 to the width of the notch 104 is greater than or equal to 0.1 and less than or equal to 10. The width of the notch 104 is parallel to the second direction. In this case, the transistor 140 provided in the embodiment of the present invention still has the area of ​​the source region 102 and the area of ​​the drain region 103 arranged at both ends of the length direction of the channel region 101 in the prior art. In combination with the foregoing, the transistor 140 provided in the embodiment of the present invention also includes the area of ​​the source region 102 and the area of ​​the drain region 103 along the first direction. The area of ​​the source region 102 and the area of ​​the drain region 103 of the transistor 140 provided in the embodiment of the present invention are greater than the area of ​​the source region 102 and the area of ​​the drain region 103 of the transistor 140 in the prior art. Please refer to the foregoing for its beneficial effects, which will not be repeated here.

[0096] Furthermore, each transistor 140 includes two notches 104 distributed along the second direction, and an active region 102 and a drain region 103 are respectively formed in the two notches 104 , as well as other structures respectively connected to the source region 102 or the drain region 103 .

[0097] Please refer to Figure 1 The capacitor 200 includes a first electrode 201, a dielectric layer 202, and a second electrode 203. The dielectric layer 202 is located between the first electrode 201 and the second electrode 203; each first electrode 201 is filled in a corresponding notch 104. The dielectric layer 202 and the second electrode 203 are arranged between two adjacent transistors 140 spaced apart along the second direction.

[0098] Please refer to Figure 1 , the drain region 103 is in electrical contact with the contact structure 130 , and the source region 102 is in electrical contact with the first electrode 201 .

[0099] Please refer to Figure 1 The first electrode 201 can be reused as the source electrode or drain electrode of the transistor 140 provided in the embodiment of the present invention, connecting the transistor 140 and the capacitor 200.

[0100] It can be understood that if the ratio of the height of the recess 104 to the width of the recess 104 is large, the dielectric layer 202 and the second electrode 203 can also be arranged in the recess 104 to increase the area of ​​the capacitor 200 and thus increase the amount of the capacitor 200, which is beneficial to reduce the refresh frequency of the three-dimensional dynamic random access memory provided by the present invention, thereby reducing power consumption.

[0101] As for the material of the first electrode 201 and the material of the contact structure 130, they can be different or the same, and can be determined according to the performance and manufacturing process requirements of the three-dimensional dynamic random access memory provided by the embodiment of the present invention. Optionally, the material of the first electrode 201 and the material of the contact structure 130 are the same, and can be formed in the same step when manufacturing the three-dimensional dynamic random access memory provided by the embodiment of the present invention, so as to reduce the process steps, improve the yield and reduce the cost. In addition, the material of the first electrode 201 and the material of the contact structure 130 can be selected from one or more of all metal materials that can be used for semiconductor manufacturing, including copper, aluminum, and tungsten.

[0102] In addition, the dielectric layers 202 included in the different capacitors 200 spaced apart along the first direction can be separated from each other or can be continuous as a whole; the second electrodes 203 included in the different capacitors 200 spaced apart along the first direction can be separated from each other or can be continuous as a whole. The relationship between the dielectric layers 202 included in the different capacitors 200 spaced apart along the first direction and the relationship between the second electrodes 203 included in the different capacitors 200 spaced apart along the first direction can be determined according to the area requirements of the capacitors 200 and the manufacturing process, and the present invention does not specifically limit this.

[0103] For example, please refer to Figure 1 The dielectric layers 202 of the different capacitors 200 spaced apart and distributed along the first direction are continuous as a whole, and the second electrodes 203 of the different capacitors 200 spaced apart and distributed along the first direction are continuous as a whole. The second dielectric portion 320 is disposed between two capacitors 200 spaced apart and distributed along the third direction, and between two contact structures 130 spaced apart and distributed along the third direction. In this case, the dielectric layer 202 included in the different capacitors 200 spaced apart and distributed along the first direction is continuous as a whole, and the second electrodes 203 included in the different capacitors 200 spaced apart and distributed along the first direction are continuous as a whole, and there is no need to form an insulating layer of the different capacitors 200 spaced apart and distributed in the first direction, thereby reducing the volume occupied by the insulating layer, which is beneficial to further reduce the size of the storage unit 100 provided in the embodiment of the present invention, thereby improving the storage density of the three-dimensional dynamic random access memory provided in the embodiment of the present invention; at the same time, the second electrode 203 and the dielectric layer 202 that are continuous as a whole can make the dielectric layers 202 of different capacitors 200 and the second electrodes 203 of different capacitors 200 formed at the same time when manufacturing the three-dimensional dynamic random access memory provided in the embodiment of the present invention, thereby reducing the process steps of separately forming the dielectric layers 202 and the second electrodes 203 of different capacitors 200, which is beneficial to reducing costs and improving productivity.

[0104] In addition, please refer to Figure 1The sizes of the transistors 140 and the capacitors 200 included in the different memory cells 100 provided in the embodiment of the present invention may be the same or different, which may be determined according to the design of the performance of the different memory cells 100. Optionally, the sizes of the transistors 140 and the capacitors 200 included in the different memory cells 100 provided in the embodiment of the present invention are the same, so that the different memory cells 100 provided in the embodiment of the present invention have the same performance, which is beneficial for the electronic system using the three-dimensional dynamic random access memory provided in the embodiment of the present invention to perform access operations on the three-dimensional dynamic random access memory provided in the embodiment of the present invention.

[0105] Regarding the sizes of other parts of the three-dimensional dynamic random access memory provided by the embodiment of the present invention, the embodiment of the present invention does not impose any specific restrictions on the sizes of other parts as long as the process accuracy and other performance requirements such as insulation performance are met.

[0106] In a second aspect, an embodiment of the present invention further provides a method for manufacturing a three-dimensional dynamic random access memory, which is used to manufacture the three-dimensional dynamic random access memory provided in the first aspect, comprising: forming a plurality of storage units 100 distributed in a three-dimensional array; the plurality of storage units 100 distributed in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer includes multiple storage groups spaced apart along a second direction, each storage group includes multiple storage units 100 distributed along a third direction; the first direction, the second direction and the third direction are different from each other; each storage unit 100 includes: a transistor 140 and a capacitor 200; forming a circuit for connecting different storage units 100 is isolated from each other; the dielectric structure includes a first dielectric portion 310 located between two transistors 140 spaced apart along a first direction; the transistor 140 includes: a gate 110, a gate dielectric layer 120, a channel region 101, a source region 102 and a drain region 103; the length direction of the channel region 101 is parallel to the second direction, and the two side walls of the channel region 101 along the length direction are concave inward relative to the side walls of the corresponding first dielectric portion 310 to form a notch 104; the source region 102 and the drain region 103 are respectively arranged on both sides along the length direction and cover the inner wall of the notch 104; the gate dielectric layer 120 is located between the gate 110 and the channel region 101, the source region 102 and the drain region 103 respectively.

[0107] Specifically, in the manufacturing method provided in the embodiment of the present invention, the order of forming the storage unit 100 and the dielectric structure is not specifically limited, and the two may also be formed at the same time.

[0108] Compared with the prior art, the beneficial effects of the method for manufacturing a three-dimensional dynamic random access memory provided by the embodiment of the present invention are the same as the beneficial effects of the three-dimensional dynamic random access memory of the above technical solution, which will not be described in detail here.

[0109] The following will be based on Figures 2 to 12 The schematic diagram of the operation shown in the figure describes the process of manufacturing a three-dimensional dynamic random access memory. Exemplarily, the manufacturing method of the three-dimensional dynamic random access memory includes the following steps:

[0110] like Figure 5 As shown, a stacking structure and a second dielectric portion 320 that penetrates the stacking structure are formed; the stacking structure includes a plurality of stacking units stacked along a first direction; each stacking unit includes a first dielectric layer 311 and a stack located on the first dielectric layer 311; the stack includes a stacked second dielectric layer 331 and a gate 110; the material of the first dielectric layer 311 is different from the material of the second dielectric layer 331; a first through hole group 410 and a second through hole group 420 are provided in the stacking structure and are spaced apart along the second direction; the first through hole group 410 and the second through hole group 420 both include a plurality of through holes spaced apart along the third direction; the second dielectric portion 320 is provided between two through holes adjacent to each other in the first direction in the same first through hole group 410, and between two through holes adjacent to each other in the first direction in the same second through hole group 420; the first dielectric portion 310 includes a first dielectric layer 311.

[0111] Specifically, the first dielectric layer 311 is used to form the first dielectric portion 310 to isolate the storage unit 100 along the first direction. For information on the material and thickness of the first dielectric layer 311, please refer to the relevant description of the first dielectric portion 310, which will not be repeated here.

[0112] Regarding the stacked layers included in the stacked structure, the stacked layers include a stacked second dielectric layer 331 and a gate 110. The second dielectric layer 331 serves as a sacrificial layer to occupy the channel region 101 and the gate dielectric layer 120 in advance, so as to facilitate the subsequent formation of the channel region 101 and the gate dielectric layer 120. The second dielectric layer 331 also serves as an isolation layer to insulate and isolate the channel region 101 and the gate dielectric layer 120 of the adjacent transistors 140 distributed along the third direction after the third dielectric portion 332 is subsequently formed. Regarding the materials of the first gate 111 and the second gate 112 included in the second dielectric layer 331 and the gate 110 and their beneficial effects, please refer to the relevant description of the first aspect, which will not be repeated here.

[0113] Exemplarily, the stack includes a first gate 111, a second dielectric layer 331 and a second gate 112 arranged along a first direction. The first gate 111 and the second gate 112 constitute a gate 110 to facilitate the subsequent formation of a double-gate transistor structure.

[0114] It is understandable that the stack may also include only one gate 110 and one second dielectric layer 331 to form a conventional transistor 140 or a back-gate transistor. The specific structure of the stack may be formed according to the requirements of the transistor 140 structure in the first aspect, and will not be described in detail here.

[0115] It should be noted that along the first direction, the two outermost layers of the stacking structure are the first dielectric layer 311, and the thickness of the two outermost layers of the stacking structure can be greater than the first dielectric layer 311 located inside the stacking structure, so as to protect the stacking structure and other structures formed subsequently.

[0116] Each through hole included in the first through hole group 410 is used to form a contact structure 130 in the through hole. Each through hole included in the second through hole group 420 is used to form a capacitor 200 in the through hole.

[0117] Each through hole in the first through hole group 410 may be in a cylindrical hole, a prism hole or other possible shapes. The embodiment of the present invention does not specifically limit the size of each through hole in the first through hole group 410, as long as the contact structure 130 can be formed in the first through hole.

[0118] Optionally, the aperture of each through hole included in the first through hole group 410 may be greater than or equal to 30 nm and less than or equal to 3000 nm. In this case, it can be avoided that the process requirements for etching and photolithography are too high due to the aperture being too small, resulting in too high a cost, which is conducive to reducing costs; it can also be avoided that the contact structure 130 is difficult to form uniformly on the hole wall or difficult to form the contact structure 130 due to the aperture being too small. It can also be avoided that the aperture is too large and occupies too much area, thereby reducing the storage density of the three-dimensional dynamic random access memory manufactured by the embodiment of the present invention.

[0119] It should be noted that the contact structure 130 formed in each through hole included in the first through hole group 410 can be set in a barrel shape on the inner wall of the through hole to form a barrel-shaped bit line; the contact structure 130 can also be set in a columnar shape to fill each through hole included in the first through hole group 410 to form a columnar bit line.

[0120] Each through hole included in the second through hole group 420 may be in a cylindrical hole, a prism hole or other possible shapes. The embodiment of the present invention does not specifically limit the size of each through hole included in the second through hole group 420, as long as the capacitor 200 can be formed in the second through hole.

[0121] The aperture of each through hole included in the second through hole group 420 is greater than or equal to 50nm and less than or equal to 5000nm. In this case, it can be avoided that the process requirements for etching and photolithography are too high due to the small aperture, resulting in excessive cost, which is conducive to reducing costs; it can also be avoided that the capacitor 200 formed due to the small aperture is small in area, thereby reducing the retention time of the capacitor 200, resulting in a higher refresh frequency and increased power consumption, thereby reducing the power consumption of the three-dimensional dynamic random access memory manufactured by the embodiment of the present invention. It can also be avoided that the aperture is too large and occupies too much area, thereby reducing the storage density of the three-dimensional dynamic random access memory manufactured by the embodiment of the present invention.

[0122] It should be noted that the dielectric layer 202 and the second electrode 203 formed in each through hole included in the second through hole group 420 can be both arranged in a barrel shape on the inner wall of the through hole; or the dielectric layer 202 is arranged in a barrel shape on the inner wall of the through hole, and the second electrode 203 is arranged in a columnar shape to fill each through hole included in the first through hole group 410.

[0123] It should be noted that the aperture of the above-mentioned through hole is defined as the aperture of a cylindrical hole having the same radial cross-sectional area as the through hole.

[0124] Along the third direction, the second dielectric portion 320 separates each through hole included in the first through hole group 410 and also isolates the contact structure 130 formed in the subsequent process steps. Along the third direction, the second dielectric portion 320 separates each through hole included in the second through hole group 420 and also isolates the capacitor 200 formed in the subsequent process steps.

[0125] In the actual application process, the embodiment of the present invention does not specifically limit the aperture of each through hole included in the first through hole group 410 and the aperture of each through hole included in the second through hole group 420, as long as the performance requirements of the structure set in the through hole can be met.

[0126] In actual application, the embodiment of the present invention does not specifically limit the method of forming the stacked structure and the second dielectric portion 320 penetrating the stacked structure, which can be determined according to the number of storage layers and the manufacturing process of the three-dimensional dynamic random access memory provided by the embodiment of the present invention.

[0127] In one example, the forming of the stacked structure and the second dielectric portion 320 penetrating the stacked structure may include the following steps:

[0128] For the first step, please refer to Figure 2 The stacked material layer is formed by a deposition process or an epitaxial process. The stacked material layer includes a stacked structure including a plurality of stacked units stacked along a first direction, each stacked unit including a first dielectric layer 311 and a stacked layer located on the first dielectric layer 311 .

[0129] For the second step, please refer to Figure 3, photolithography and etching processes are used to form a third through hole group 430 and a fourth through hole group 440 that penetrate the stacked material layers, the hole pattern of the third through hole group 430 is the same as the top pattern of the second dielectric layer 331 between two through holes adjacent to each other along the first direction in the same first through hole group 410; the hole pattern of the fourth through hole group 440 is the same as the top pattern of the second dielectric layer 331 between two through holes adjacent to each other along the first direction in the same second through hole group 420. The third through hole group 430 and the fourth through hole group 440 are formed in order to form the second dielectric portion 320 in the subsequent step. The second dielectric portion 320 is used to isolate two through holes adjacent to each other in the first direction of the same first through hole group 410 and to isolate two through holes adjacent to each other in the first direction of the same second through hole group 420. It can be understood that the hole pattern of the first through hole group 410 closest to each other in the second direction and the hole pattern of the third through hole group 430 are alternately arranged, and the hole pattern of the second through hole group 420 closest to each other in the second direction and the hole pattern of the fourth through hole group 440 are alternately arranged.

[0130] For the third step, please refer to Figure 4 The second dielectric portion 320 filled in the third through hole group 430 and the fourth through hole group 440 is formed by, for example, a deposition process. The material of the second dielectric portion 320 is described in the first aspect, and will not be described again.

[0131] Step 4, please refer to Figure 5 , photolithography and etching processes are used to form a first through hole group 410 and a second through hole group 420 that penetrate the stacked material layer, thereby forming a stacked structure.

[0132] In another example, the above-mentioned method of forming the stacking structure and the second dielectric portion 320 that penetrates the stacking structure may also be to first form a portion of the stacking material layer and form the first through hole group 410 and the second through hole group 420, and then form another portion of the stacking material layer and form the first through hole group 410 and the second through hole group 420; and repeat the aforementioned process to finally form the stacking structure.

[0133] Next, please refer to Figure 6 , selectively remove the edge portions of the first gate 111 and the second gate 112 by a process such as selective etching to form a notch 104 and form a stacked structure. The size of the notch 104 and its beneficial effects are described in the first aspect, which will not be repeated here.

[0134] Next, please refer to Figure 7The second dielectric layer 331 is selectively removed by a process such as selective etching, so that the remaining second dielectric layer 331 forms a third dielectric portion 332, and forms a suspended region for forming the channel region 101. The suspended region is located along the first direction between the two layers of the third dielectric portion 332 and the two transistors 140 spaced apart along the third direction.

[0135] Next, please refer to Figure 8 , a gate dielectric layer 120 is deposited on the entire surface of the stacked structure by a thin film deposition process. The material of the gate dielectric layer 120 and its beneficial effects are described in the first aspect, which will not be repeated here.

[0136] Next, please refer to Fig. 9 , a thin film deposition process is used to deposit a channel layer 105 on the entire surface of the stacked structure. The channel layer 105 completely fills the suspended area and forms a channel region 101. The material of the channel layer 105 and its beneficial effects refer to the corresponding description of the channel region 101 in the first aspect, which will not be repeated here.

[0137] Next, please refer to Fig.10 , using a thin film deposition process, an electrode layer 204 is deposited on the entire surface of the stacked structure. The electrode layer 204 is processed into the first electrode 201 and the contact structure 130 in subsequent steps. The material of the electrode layer 204 and its beneficial effects are described in the corresponding description of the channel region 101 in the first aspect, which will not be repeated here.

[0138] Next, please refer to Fig.11 , using processes such as photolithography and etching, the channel layer 105, the gate dielectric layer 120 and the electrode layer 204 located in each through hole included in the second through hole group 420 are removed, and only the portion located in the recess 104 close to each through hole included in the second through hole group 420 is retained. The portion of the channel layer 105 located in the recess 104 close to each through hole included in the second through hole group 420 forms the drain region 103, and the portion of the electrode layer 204 located in the recess 104 close to each through hole included in the second through hole group 420 forms the first electrode 201. The portion of the channel layer 105 located in the recess 104 close to each through hole included in the first through hole group 410 forms the source region 102, and the electrode layer 204 located in each through hole included in the first through hole group 410 forms the contact structure 130.

[0139] It should be noted that the drawings provided in the embodiments of the present invention only illustrate the case where the drain region 103 is electrically connected to the capacitor 200 and the source region 102 is electrically connected to the contact structure 130, but it does not mean that only the above connection relationship can be used. The specific connection relationship between the source region 102 and the drain region 103 in the transistor 140 and the contact structure 130 and the capacitor 200, respectively, can be referred to in the above text. When the drain region 103 is electrically connected to the capacitor, the source region 102 is electrically connected to the contact structure.

[0140] Next, please refer to Fig.12 , a dielectric layer 202 is formed in each through hole included in the second through hole group 420 by using a thin film deposition process.

[0141] Next, please refer to Fig.12 , a thin film deposition process is used to form a second electrode 203 in each through hole included in the second through hole group 420 , and the second electrode 203 is also formed on the dielectric layer 202 .

[0142] Please note that when a thin film deposition process is used to form the gate dielectric layer 120, the channel layer 105, the electrode layer 204, the dielectric layer 202 and the second electrode 203, the same process including, for example, atomic layer deposition can be used, which is conducive to continuous processing using the same equipment, thereby reducing damage to the three-dimensional dynamic random access memory manufactured by the embodiment of the present invention when transferring it from equipment used for different processes, thereby improving the yield.

[0143] When using the above technical solution, please refer to Fig.12, the first dielectric portion 310 includes a second dielectric layer 331 from which all the first dielectric layers 31 are partially removed as a pre-occupying structure of the channel region 101. After being removed, a gate dielectric layer 120 covering the periphery of the gate 110 is deposited in sequence, and the channel region 101, the source region 102 and the drain region 103 are deposited on the gate dielectric layer 120. In the prior art, in the process of manufacturing the transistor 140, the sacrificial layers stacked on both sides of the channel region 101 are first removed, and then the gate dielectric layer 120 and the gate 110 are formed on both sides of the channel region 101 along the first direction and the second direction. At this time, the channel region 101 is suspended, and the channel region 101 is a semiconductor material with a relatively low structural strength. In the case where the memory cell 100 has a relatively small geometric size, the channel region 101 of the semiconductor material with a large aspect ratio along the second direction will collapse, causing the transistor 140 to deform, thereby reducing the performance of the memory cell 100 or even failing to work normally, thereby reducing the yield. Based on this, when manufacturing a three-dimensional dynamic random access memory, the present invention selectively etches the second dielectric layer 331 so that the remaining second dielectric layer 331 forms the third dielectric portion 332, and the gate 110 is suspended. Compared with the material of the channel region 101, the gate 110 material has a higher structural strength and is less likely to collapse due to a large aspect ratio along the second direction when the memory cell 100 has a smaller geometric size. The manufacturing method of the three-dimensional dynamic random access memory provided by the present invention can ensure that the structure of the transistor 140 is regular, thereby ensuring the normal operation and stable performance of the memory cell 100 manufactured by the manufacturing method of the three-dimensional dynamic random access memory provided by the present invention, thereby improving the yield.

[0144] In addition, please refer to Fig.12 After forming the second electrode 203 in each through hole included in the second through hole group 420 by using a thin film deposition process, a planarization process including chemical mechanical polishing can be used to polish the outer surface of the three-dimensional dynamic random access memory manufactured by the embodiment of the present invention along the first direction, the second direction and the third direction to remove the gate dielectric layer 120, the channel layer 105, the electrode layer 204, the dielectric layer 202 and the second electrode 203, so as to ensure that the multiple storage units 100 distributed in a three-dimensional array provided by the embodiment of the present invention are insulated from each other on the outer surface of the three-dimensional dynamic random access memory.

[0145] In the description of the above embodiments, specific features, structures, materials or characteristics may be combined in a suitable manner in any one or more embodiments or examples.

[0146] The above are only specific implementations of the embodiments of the present invention, but the protection scope of the embodiments of the present invention is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the embodiments of the present invention, which should be included in the protection scope of the embodiments of the present invention. Therefore, the protection scope of the embodiments of the present invention should be based on the protection scope of the claims.

Claims

1. A three-dimensional dynamic random access memory, characterized in that: include: A plurality of storage units distributed in a three-dimensional array, and a medium structure for isolating different storage units; the plurality of storage units distributed in a three-dimensional array include multiple storage layers spaced apart along a first direction, each storage layer includes multiple storage groups spaced apart along a second direction, and each storage group includes multiple storage units distributed along a third direction; The first direction, the second direction and the third direction are different from each other; Each of the storage units comprises: a transistor and a capacitor; the dielectric structure comprises a first dielectric portion located between two of the transistors spaced apart and distributed along the first direction; The transistor comprises: a gate, a gate dielectric layer, a channel region, a source region and a drain region; the length direction of the channel region is parallel to the second direction, and the two side walls of the channel region along the length direction are indented inward relative to the side walls of the corresponding first dielectric portion to form a notch; the source region and the drain region are respectively arranged on both sides of the channel region along the length direction and cover the inner wall of the notch; the gate dielectric layer is located between the gate and the channel region, the source region and the drain region respectively; The capacitor is electrically connected to a source region or a drain region of the transistor.

2. The three-dimensional dynamic random access memory according to claim 1, characterized in that: The ratio of the height of the notch to the width of the notch is greater than or equal to 0.1 and less than or equal to 10; the height of the notch is parallel to the first direction, and the width of the notch is parallel to the second direction; And / or, a ratio of the length of the channel region to the thickness of the channel region is greater than or equal to 10 and less than or equal to 1000; and a thickness direction of the channel region is parallel to the first direction; And / or, a ratio of the thickness of the channel region to the width of the recess is greater than or equal to 0.1 and less than or equal to 10; and the width of the recess is parallel to the second direction.

3. The three-dimensional dynamic random access memory according to claim 1, characterized in that: The material of the channel region includes indium gallium zinc oxide; And / or, the source region, the drain region and the channel region are integrally continuous.

4. The three-dimensional dynamic random access memory according to claim 1, characterized in that: The gate includes a first gate and a second gate disposed at both sides of the channel region along the first direction.

5. The three-dimensional dynamic random access memory according to claim 1, characterized in that: The three-dimensional dynamic random access memory further includes a contact structure; Wherein, when the source region and the drain region included in the transistor are electrically connected to the capacitor, the drain region is electrically connected to the contact structure; or, when the drain region and the capacitor are electrically connected to the transistor, the source region is electrically connected to the contact structure; The dielectric structure also includes a second dielectric portion and a third dielectric portion; the second dielectric portion is located between the two capacitors spaced apart along the third direction, and between the two contact structures spaced apart along the third direction; the third dielectric portion is located between the two transistors spaced apart along the third direction.

6. The three-dimensional dynamic random access memory according to claim 5, characterized in that: The capacitor comprises a first electrode, a dielectric layer and a second electrode; the dielectric layer is located between the first electrode and the second electrode; each of the first electrodes is filled in the corresponding notch; the dielectric layer and the second electrode are arranged between two adjacent transistors spaced apart along the second direction; The dielectric layers included in different capacitors distributed at intervals along the first direction are continuous as a whole, and the second electrodes included in different capacitors distributed at intervals along the first direction are continuous as a whole.

7. A method for manufacturing a three-dimensional dynamic random access memory, characterized in that: include: Forming a plurality of storage units distributed in a three-dimensional array; the plurality of storage units distributed in a three-dimensional array comprises a plurality of storage layers spaced apart along a first direction, each storage layer comprises a plurality of storage groups spaced apart along a second direction, and each storage group comprises a plurality of storage units distributed along a third direction; The first direction, the second direction and the third direction are different from each other; each of the storage units comprises: a transistor and a capacitor; A dielectric structure is formed for isolating different storage units; the dielectric structure includes a first dielectric portion located between two transistors spaced apart along the first direction; the transistor includes: a gate, a gate dielectric layer, a channel region, a source region and a drain region; the length direction of the channel region is parallel to the second direction, and the two side walls of the channel region along the length direction are recessed inward relative to the side walls of the corresponding first dielectric portion to form a notch; the source region and the drain region are respectively arranged on both sides along the length direction and cover the inner wall of the notch; the gate dielectric layer is located between the gate and the channel region, the source region and the drain region respectively.

8. The method for manufacturing a three-dimensional dynamic random access memory according to claim 7, characterized in that: Forming a plurality of the storage units distributed in a three-dimensional array, and forming the medium structure for isolating different storage units comprises: A stacking structure and a second dielectric part that penetrates the stacking structure are formed; the stacking structure comprises a plurality of stacking units stacked in a first direction; each of the stacking units comprises a first dielectric layer and a stack located on the first dielectric layer; the stack comprises a stacked second dielectric layer and a gate; the material of the first dielectric layer is different from the material of the second dielectric layer; a first through hole group and a second through hole group are provided in the stacking structure and are spaced apart along the second direction; the first through hole group and the second through hole group both comprise a plurality of through holes spaced apart along the third direction; the second dielectric part is disposed between two adjacent through holes in the same first through hole group along the first direction, and is disposed between two adjacent through holes in the same second through hole group along the first direction; the first dielectric part comprises the first dielectric layer; Selectively removing the edge portion of each layer of the gate to form the notch; The second dielectric layer is selectively etched so that the remaining second dielectric layer forms a third dielectric portion; the third dielectric portion is located between the two transistors spaced apart along the third direction; the dielectric structure includes the first dielectric portion, the second dielectric portion and the third dielectric portion; Depositing a gate dielectric layer covering the periphery of the gate; and depositing a channel region, a source region, and a drain region on the gate dielectric layer; forming a contact structure in each through hole included in the first through hole group, and forming a first electrode included in the capacitor at a portion of each through hole included in the second through hole group corresponding to the notch; A dielectric layer and a second electrode are sequentially formed in each of the through holes included in the second through hole group; and the capacitor includes the first electrode, the dielectric layer and the second electrode.

9. The method for manufacturing a three-dimensional dynamic random access memory according to claim 8, characterized in that: The stacking structure is formed, and the second dielectric part that penetrates the stacking structure includes: forming a stacked material layer; A third through hole group and a fourth through hole group are formed to penetrate the stacked material layer; the aperture pattern of the third through hole group is the same as the top pattern of the second dielectric layer between two through holes adjacent to each other in the first direction in the same first through hole group; the aperture pattern of the fourth through hole group is the same as the top pattern of the second dielectric layer between two through holes adjacent to each other in the first direction in the same second through hole group; forming the second dielectric portion filled in the third through hole group and the fourth through hole group; The first through hole group and the second through hole group are formed penetrating the stacked material layer.

10. The method for manufacturing a three-dimensional dynamic random access memory according to claim 8, characterized in that: The aperture of each through hole included in the first through hole group is greater than or equal to 30 nm and less than or equal to 3000 nm; And / or, the aperture of each through hole included in the second through hole group is greater than or equal to 50 nm and less than or equal to 5000 nm.

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