Preparation method of semiconductor structure, semiconductor structure, device and equipment

Abstract

The invention provides a preparation method of a semiconductor structure, the semiconductor structure, a device and equipment, and the method comprises the steps: forming a first semiconductor structure on a substrate, the first semiconductor structure at least comprises a first active structure and a second active structure, and the first active structure is far away from the substrate relative to the second active structure; forming a complementary metal oxide semiconductor (CMOS) transistor based on the first active structure; performing wafer reversing on the CMOS transistor, and exposing the second active structure; based on the second active structure, a memory cell is formed, and a channel of a transistor in the memory cell is a curved channel. According to the invention, homogeneous integration of the CMOS circuit with a logic function and the memory unit with the curved channel can be realized, and the curved channel can increase the equivalent gate length, so that electric leakage is reduced, the retention time is prolonged, and the power consumption is reduced.

Description

Technical Field

[0001] The present application relates to the field of integrated semiconductors, and in particular to a method for preparing a semiconductor structure, a semiconductor structure, a device and an apparatus. Background Art

[0002] Various emerging application scenarios have put forward higher demands on data storage capacity, efficiency, liquidity and security, and storage technology is also showing a multi-dimensional development trend.

[0003] Embedded storage technology is of great significance for complex computing scenarios such as high-performance computing, in-memory computing, and large artificial intelligence (AI) models. However, existing embedded storage technologies have problems such as high process difficulty, high complexity, and poor performance of the manufactured devices. Summary of the invention

[0004] The present application provides a method for preparing a semiconductor structure, a semiconductor structure, a device and equipment, which can reduce the process difficulty and complexity of the semiconductor structure and improve the performance of the device.

[0005] In a first aspect, an embodiment of the present application provides a method for preparing a semiconductor structure, the method comprising: forming a first semiconductor structure on a substrate, the first semiconductor structure comprising at least a first active structure and a second active structure, the first active structure being away from the substrate relative to the second active structure; based on the first active structure, forming a complementary metal oxide semiconductor (CMOS) transistor; flipping the CMOS transistor and exposing the second active structure; based on the second active structure, forming a memory cell, the channel of the transistor in the memory cell being a curved channel.

[0006] In a possible embodiment, the first semiconductor structure also includes an isolation layer located between the first active structure and the second active structure. The first semiconductor structure is formed on a substrate, including: providing a substrate, the substrate including a bottom substrate, a sacrificial layer and a top substrate stacked in sequence along a first direction; etching the top substrate, the sacrificial layer and the bottom substrate in sequence to form a first active structure and a second active structure, wherein the first active structure is the etched top substrate and the second active structure is the etched bottom substrate; removing the etched sacrificial layer to form a first groove; filling the first groove with a dielectric material to form an isolation layer, the isolation layer being used to isolate the CMOS transistor from the storage unit.

[0007] In one possible implementation, a CMOS transistor is formed based on a first active structure, including: epitaxially growing a first source-drain structure on the first active structure; forming a first gate structure based on the first active structure; and depositing a metal material on the first source-drain structure to form a first source-drain metal.

[0008] In one possible implementation, a storage unit is formed based on the second active structure, including: forming a transistor based on the second active structure; performing a back-end process on the transistor to form an interconnection layer, the interconnection layer including: at least one interconnection dielectric layer, and an interconnection metal structure located within the interconnection dielectric layer; etching a portion of the interconnection dielectric layer to form a through hole; forming a capacitor structure based on the through hole, the capacitor structure being in contact with the second source-drain metal of the transistor, or the capacitor structure being in contact with the second source-drain metal through the interconnection metal structure.

[0009] In one possible embodiment, a transistor is formed based on a second active structure, including: etching a portion of the second active structure corresponding to the gate region of the transistor to form a second groove; depositing semiconductor material in the gate region and the second groove to form a dummy gate structure; epitaxially growing a second source-drain structure on the second active structure; removing the dummy gate structure to expose the second groove; forming a second gate structure based on the second groove; and depositing metal material on the second source-drain structure to form a second source-drain metal.

[0010] In one possible embodiment, a transistor is formed based on the second active structure, including: depositing semiconductor material in the gate region to form a dummy gate structure; epitaxially growing a second source-drain structure on the second active structure; removing the dummy gate structure to expose the gate region and the second active structure in the channel region; etching the second active structure in the channel region to form a second groove; forming a second gate structure based on the second groove and the exposed gate region; and depositing metal material on the second source-drain structure to form a second source-drain metal.

[0011] In a possible implementation, a capacitor structure is formed based on a through hole, including: sequentially forming a first electrode, a capacitor dielectric layer, and a second electrode in the through hole to form a capacitor structure through the first electrode, the capacitor dielectric layer, and the second electrode, wherein the first electrode is in contact with an interconnected metal structure.

[0012] In a second aspect, an embodiment of the present application provides a semiconductor structure, which is manufactured using the preparation method described in the first aspect and any one of its embodiments, and includes: a CMOS transistor; a memory cell, the memory cell is arranged back to back with the CMOS transistor, and the channel of the transistor in the memory cell is a curved channel.

[0013] In a third aspect, an embodiment of the present application provides a semiconductor device, which includes: a semiconductor structure as described in the second aspect above.

[0014] In a fourth aspect, an embodiment of the present application provides an electronic device, comprising: a circuit board and a semiconductor device as described in the third aspect above, wherein the semiconductor device is arranged on the circuit board.

[0015] In the present application, a CMOS transistor is formed based on the first active structure away from the substrate by forming a first active structure and a second active structure on a substrate; then the CMOS transistor is flipped and the second active structure is exposed; based on the second active structure, a storage unit with a curved channel is formed. On the one hand, the present application can realize the homogeneous integration of a CMOS circuit with a logic function and a storage unit with a curved channel, and the storage unit to the logic circuit is monolithically integrated, and the distance between the two is shortened, which helps to reduce communication delay to improve chip performance. On the other hand, the storage unit partially applies a curved channel, which helps to increase the equivalent gate length to reduce leakage, increase retention time, and reduce power consumption. Moreover, since the CMOS transistor and the transistor in the storage unit are integrated in a "back-to-back" manner, they do not occupy additional plane size, which is conducive to further scaling of the plane size of the semiconductor device; the manufacturing process of the transistor in the logic circuit and the manufacturing process of the transistor in the storage unit can be independent of each other, and there is no need to consider the complex and cumbersome logic circuit and storage unit process compatibility issues, which is conducive to reducing the process difficulty and complexity of the semiconductor structure.

[0016] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0018] Figure 1 A schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application;

[0019] Figure 2 A schematic top view of a semiconductor structure in an embodiment of the present application;

[0020] Figures 3 to 7 This is a schematic diagram of the structure of the semiconductor structure in the first preparation process in an embodiment of the present application;

[0021] Figure 8 This is a schematic diagram of the first structure of the semiconductor structure in the embodiment of the present application;

[0022] Figures 9 to 11 This is a schematic diagram of the structure of the semiconductor structure in the second preparation process in the embodiment of the present application;

[0023] Fig.12 This is a schematic diagram of a second structure of a semiconductor structure in an embodiment of the present application;

[0024] Fig.13 This is a schematic diagram of a third structure of a semiconductor structure in an embodiment of the present application;

[0025] Fig.14 This is a schematic diagram of the fourth structure of the semiconductor structure in the embodiment of the present application.

[0026] The above pictures:

[0027] 10. semiconductor structure; 11. CMOS; 111. first fin structure; 112. first source-drain structure; 113. first interlayer dielectric layer; 114. first gate structure; 115. first source-drain metal; 116. first metal interconnect layer; 12. memory cell; 121. second fin structure; 122. second source-drain structure; 123. second interlayer dielectric layer; 124. second gate structure; 125. second source-drain metal; 126. second metal interconnect layer; 1261. interconnect dielectric layer ; 1262, interconnected metal structure; 20, substrate; 201, bottom substrate; 202, sacrificial layer; 203, top substrate; 21, sacrificial layer after etching; 22, isolation structure; 23, isolation layer; 24, first side wall; 25, insulating layer; 26, carrier wafer; 27, second groove; 28, second side wall; 29, capacitor structure; 291, first electrode; 292, capacitor dielectric layer; 293, second electrode; 30, second pseudo-gate structure; 31, gate groove; 32, SOI layer. DETAILED DESCRIPTION

[0028] Here, exemplary embodiments will be described in detail, and examples thereof are shown in the accompanying drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application.

[0029] As Moore's Law continues to deepen, continuing to promote the miniaturization of transistor size is a hot issue in the current industry research and development. Stacked transistors can achieve the integration of two or more layers of transistors in a vertical space through three-dimensional transistor stacking, which helps to further improve the integration density of transistors and improve circuit performance. It is considered to be one of the important technologies for continuing the miniaturization of integrated circuit size. With the continuous development of transistor technology, flip-chip stacking technology has emerged. Flip-chip stacking technology can realize the homogeneous integration of logic circuits and storage units (i.e. embedded storage), which can shorten the distance between storage units and logic circuits and reduce signal delays. Homogeneous integration includes at least the following two solutions:

[0030] The first solution: In the front end of line (FEOL), a plurality of transistors are first formed, a part of the plurality of transistors constitutes a logic unit, and another part of the plurality of transistors constitutes a switch transistor of a memory unit; in the back end of line (BEOL), a capacitor structure connected to the switch transistor is formed, and the capacitor structure and the switch transistor constitute a memory unit. The switch transistor includes a source structure, a channel, a drain structure and a gate structure, the gate structure is located on the channel, a gate dielectric layer is provided between the gate structure and the channel, and the capacitor structure is respectively connected to the bit line and the drain structure of the switch transistor.

[0031] The second solution is to form multiple metal oxide semiconductor field effect transistors (MOSFET) in the front-end process, and multiple MOS tubes constitute a logic unit; in the back-end process, a thin film transistor (TFT) and a capacitor structure are formed, and the capacitor structure and the thin film transistor constitute a storage unit, and the thin film transistor is a switch transistor of the storage unit.

[0032] Both of the above solutions can realize embedded storage, thereby reducing signal delay. However, both solutions have their own disadvantages: the preparation process of the first solution is complicated, and it is necessary to realize the coexistence of logic circuits and storage units on the same wafer, which is difficult to process; the second solution is to prepare transistors in the back-end process, so it is no longer possible to use MOS transistor structures, and only TFT and other transistor structures can be used. The quality of transistors is generally poor, and the device fluctuations are large, which is not conducive to large-scale integration.

[0033] Based on this, the embodiment of the present application provides a method for preparing a semiconductor structure, which can realize the homogeneous integration of a CMOS circuit with a logic function and a memory cell with a curved channel. The manufacturing process of the transistor in the CMOS circuit and the manufacturing process of the transistor in the memory cell can be independent of each other, and there is no need to consider the complex and cumbersome logic circuit and memory cell process compatibility issues, which is beneficial to reducing the process difficulty and complexity of the semiconductor structure. The memory cell part adopts a curved channel, which helps to increase the equivalent channel length, thereby reducing leakage, increasing the retention time, and reducing power consumption.

[0034] In the embodiments of the present application, the semiconductor structure described above can be applied to semiconductor devices such as processors and logic devices.

[0035] In some embodiments, the semiconductor structure may include a CMOS transistor and a memory cell. The memory cell is disposed opposite to the CMOS transistor, and a channel of the transistor in the memory cell is a curved channel.

[0036] As can be understood, CMOS transistors include two types of transistors, N-type metal oxide semiconductor (N metal oxide semiconductor, NMOS) and P-type metal oxide semiconductor (P metal oxide semiconductor, PMOS), which together constitute the basic unit of CMOS logic circuits. In CMOS circuits, NMOS transistors and PMOS transistors are complementary, which means that they work under different voltage conditions to produce the required logic output. NMOS transistors are turned on at logic "1" (high voltage) and turned off at logic "0" (low voltage). In contrast, PMOS transistors are turned on at logic "0" (low voltage) and turned off at logic "1" (high voltage). This complementarity gives CMOS circuits the advantages of low power consumption, high integration, and good noise performance. In CMOS circuits, when the input signal is stable, one of the NMOS transistor and the PMOS transistor will be in the off state, consuming almost no power. This feature makes CMOS circuits extremely low in power consumption when static, making them very suitable for portable devices and battery-powered systems. In addition, CMOS technology also allows a large number of transistors and other circuit elements to be integrated on a single chip, thereby improving the integration and performance of the circuit. This high integration makes CMOS technology widely used in digital circuits such as microprocessors, microcontrollers, and memories. Therefore, NMOS and PMOS transistors are the core components of CMOS technology, which together realize the low power consumption, high integration, and good performance characteristics of CMOS circuits.

[0037] In some embodiments, the storage unit may include a transistor and a capacitance structure (capacitor), wherein the capacitance structure is electrically connected to the transistor. In some embodiments, the transistor may include a gate structure, a source structure, and a drain structure, and the capacitance structure and the transistor may be electrically connected by the source structure of the transistor and the capacitance structure, or by the drain structure of the transistor and the capacitance structure, and the transistor controls the writing, modification, or reading of information in the capacitance structure. That is, the transistor acts as a selection device (or a switching device) to control the writing, modification, or reading of information in the capacitance structure.

[0038] In some embodiments, the capacitor structure may include a first electrode, a second electrode, and a capacitor dielectric layer located between the first electrode and the second electrode. Exemplarily, the first electrode may be electrically connected to the drain structure of the transistor, and the second electrode may be grounded.

[0039] In some embodiments, the type of transistor may include but is not limited to: finfield effect transistor (FinFET), gate-all-around field effect transistor (GAAFET), planar transistor, vertical field effect transistor (VFET), forksheet transistor, etc.

[0040] Figure 1 FIG. 1 is a schematic diagram of an implementation process of a method for preparing a semiconductor structure in an embodiment of the present application. Figure 1 As shown, the method for preparing the semiconductor structure in the embodiment of the present application may include:

[0041] Step S110: forming a first semiconductor structure on a substrate.

[0042] In some embodiments, the first semiconductor structure includes at least a first active structure and a second active structure, and the first active structure is farther from the substrate than the second active structure.

[0043] In some embodiments, the implementation process of step S110 may be: providing a substrate, the substrate comprising a bottom substrate, a sacrificial layer and a top substrate stacked in sequence along a first direction; etching the top substrate, the sacrificial layer and the bottom substrate in sequence to form a first active structure and a second active structure, wherein the first active structure is the etched bottom substrate, and the second active structure is the etched top substrate; removing the etched sacrificial layer to form a first groove; filling the first groove with a dielectric material to form an isolation layer, the isolation layer being used to isolate the CMOS transistor from the storage unit.

[0044] It can be understood that the preparation process of the substrate can be: epitaxially grow a layer of sacrificial layer material on the original substrate (i.e., the bottom substrate) to form a sacrificial layer; then epitaxially grow the same semiconductor material as the bottom substrate on the sacrificial layer to form a top substrate. The substrate formed by the above preparation method includes a top substrate, a sacrificial layer, and a bottom substrate stacked in sequence. Among them, the top substrate is used to prepare the CMOS transistor on the front side, and the bottom substrate is used to prepare the storage unit on the back side.

[0045] In some embodiments, the sacrificial layer material may be silicon germanium (SiGe) material, or other semiconductor materials, which is not specifically limited in the embodiments of the present application.

[0046] In some embodiments, when the type of transistor is different, the arrangement of the substrate is also different accordingly. For example, when the transistor is any one of a fin field effect transistor, a planar transistor, and a vertical field effect transistor, the bottom substrate and the top substrate may be silicon (Si) material. When the transistor is a nanosheet field effect transistor, the bottom substrate and the top substrate may be a stack formed by alternating deposition of silicon and silicon germanium.

[0047] After obtaining the substrate, the substrate can be etched to form a plurality of active structures standing upright on the substrate. In one example, the active structure can be obtained by anisotropically etching the substrate. The etching process can be, for example, at least one of dry etching, wet etching, reactive ion etching, and chemical oxide removal process, which is not specifically limited in the embodiments of the present application.

[0048] It is understandable that the active structure can be patterned through a standardized process, and the top substrate, sacrificial layer and bottom substrate can be etched in sequence, and the etched top substrate can be used as the first active structure and the etched bottom substrate can be used as the second active structure.

[0049] In some embodiments, after etching the substrate, a groove may be formed at the etched position, and an insulator may be filled at the groove to form an isolation structure. For example, the isolation structure may also be referred to as a shallow trench isolation (STI) structure. The insulator forming the isolation structure may be, for example, silicon nitride (SiN, Si3N4), silicon dioxide (SiO2), or silicon oxycarbide (SiCO), etc.

[0050] In some embodiments, in order to facilitate subsequent processing, after the isolation structure is formed, the isolation structure can be polished or chemical-mechanical planarization (CMP) is performed, so that when the isolation structure is subsequently etched, different areas of the isolation structure have the same etching depth, thereby making the top height of the exposed active structure the same.

[0051] In some embodiments, a portion of the isolation structure may be etched first to expose the first active structure, wherein the solvent used to etch the isolation structure may be, for example, a dilute hydrofluoric acid (DHF) solution or a buffered oxide etch (BOE) solution.

[0052] Step S120: forming a CMOS transistor based on the first active structure.

[0053] It can be understood that a CMOS transistor includes two transistors with complementary polarities, and the two second transistors are arranged side by side in a second direction, and the second direction is perpendicular to the first direction. Therefore, when the polarity of one transistor is N-type, the polarity of the other transistor is P-type. Since the preparation process of the two transistors is the same, the preparation of the first transistor is taken as an example for explanation below.

[0054] In some embodiments, the implementation process of step S120 may be: epitaxially growing a first source-drain structure on the first active structure; forming a first gate structure based on the first active structure; and depositing a metal material on the first source-drain structure to form a first source-drain metal.

[0055] It is understandable that after forming the isolation structure, a semiconductor material may be deposited in the gate region of the first transistor in the semiconductor structure to form a first dummy gate structure; a first spacer is formed on both sides of the first dummy gate structure; and a first source-drain structure is formed on the first active structure on both sides of the first dummy gate structure and the first spacer. The first spacer is used to isolate the first source-drain structure from the first gate structure, and the structure of the first spacer may be set according to actual needs, and the embodiment of the present application does not specifically limit this.

[0056] In some embodiments, the semiconductor material forming the first dummy gate structure may be polysilicon (Poly Si), amorphous silicon, etc. For example, the first spacer may have a single layer structure, and the entire structure may be made of the same material, such as porous silicon carbon oxyhydride (SiCOH).

[0057] In some embodiments, after forming the first pseudo-gate structure, the etched sacrificial layer between the first active structure and the second active structure can be selectively removed to form a first groove. Then, a dielectric material is filled in the first groove to form an isolation layer. Since the first pseudo-gate structure can provide structural support to the first active structure during the selective removal process, the position of the first active structure in the first transistor does not change, and the first active structure and the second active structure remain self-aligned. Among them, the dielectric material can be, for example, a lowK material. The isolation layer can achieve electrical isolation between the CMOS transistor and the memory cell by isolating the first active structure and the second active structure.

[0058] In addition, in some embodiments, when the substrate is silicon-on-insulator (SOI), since the SOI substrate includes a three-layer structure: a thin top silicon layer, a buried oxide (BOX) layer, and a supporting bottom silicon wafer (base silicon) layer. That is, a BOX layer is provided between the top silicon layer and the bottom silicon substrate, and the SOI substrate can achieve dielectric isolation of components in the integrated circuit and eliminate the parasitic latch effect in the bulk silicon CMOS circuit. Therefore, after the active structure is formed, the middle BOX layer does not need to be etched and filled with dielectric materials, and can be directly used as an isolation layer between the first active structure and the second active structure.

[0059] In both of the above methods, an isolation layer is provided between the first active structure and the second active structure. The embodiment of the present application may also not provide an isolation layer. In this way, the substrate may be an original silicon substrate, and the first active structure and the second active structure are formed by etching the silicon substrate. After the active structure is formed, an isolation structure that wraps the second active structure may be formed so that a CMOS transistor can be subsequently formed based on the exposed first active structure.

[0060] In some embodiments, the implementation process of forming the first source-drain structure on the first dummy gate structure and the first active structure on both sides of the first sidewall may be: etching the first active structure of the first transistor in the source-drain region to form a first source-drain groove, performing source-drain epitaxial growth at the first source-drain groove to form the first source-drain structure.

[0061] It is understandable that strained materials such as silicon germanium or silicon carbide can be formed in the source and drain grooves by selective epitaxial growth to fill the source and drain grooves of the first transistor, and then a first source and drain structure is formed on the strained material by a heavy doping process.

[0062] In some embodiments, ion implantation may be performed on a portion of the first active structure on both sides of the first dummy gate structure and the first sidewall to form a first source-drain structure. Here, the implanted ions may include n-type ions or p-type ions, such as nitrogen ions, phosphorus ions, arsenic ions, etc.

[0063] In some embodiments, after the first source-drain structure is formed, an interlayer dielectric may be deposited on the first source-drain structure to form a first interlayer dielectric layer.

[0064] For example, an insulating material (such as silicon dioxide) may be deposited on the first source-drain structure and the first active structure and planarized to form a first interlayer dielectric layer, and the first interlayer dielectric layer may cover the first source-drain structure and the first active structure.

[0065] After the first source-drain structure is formed, a gate structure of the first transistor, that is, a first gate structure, may be formed.

[0066] In some embodiments, the first dummy gate structure formed above can be removed by an etching process to obtain a gate groove, an insulating material can be deposited at the gate groove to form a first gate dielectric layer, and a metal material can be deposited on the first gate dielectric layer to form a first gate electrode layer. The first gate dielectric layer and the first gate electrode layer together constitute a first gate structure.

[0067] For example, the first gate dielectric layer can be composed of a silicon oxide layer plus a hafnium oxide layer with a high K value, and the thickness of the silicon oxide layer and the hafnium oxide layer can be determined according to the polarity and performance of the transistor. For example, the first gate electrode layer can be composed of multiple layers of electrode materials, and the electrode material of each layer includes but is not limited to hafnium, zirconium, titanium, tantalum, aluminum, alloys of these metals, and carbides of these metals (for example, hafnium carbide, zirconium carbide, titanium carbide, tantalum carbide and aluminum carbide).

[0068] After forming the first gate structure, a metal material may be deposited on the first source-drain structure formed above to form a first source-drain metal.

[0069] In some embodiments, when the first interlayer dielectric layer is formed after the first source-drain structure is formed, a portion of the first interlayer dielectric layer can be etched to expose the first source-drain structure, and a metal material is filled on the first source-drain structure to form a first source-drain metal.

[0070] For ease of explanation, the first source-drain structure mentioned in the embodiments of the present application is an abbreviation, specifically referring to the first source structure and / or the first drain structure. In addition, the first source-drain metal, the first source-drain groove, the second source-drain structure, the second source-drain metal, the second source-drain groove, etc. are similar to the first source-drain structure, where "source-drain" is an abbreviation for "source and / or drain".

[0071] In addition, in some embodiments, after the first transistor is manufactured, a first metal interconnection layer may be formed on the first transistor.

[0072] It is understood that a first metal interconnect layer may be formed by performing back-end processes (such as dielectric deposition between interconnect lines, metal line formation, lead pad formation, etc.) on the first transistor. The first metal interconnect layer may include at least one interconnect dielectric layer and an interconnect metal structure located in the interconnect dielectric layer.

[0073] It should be noted that the first source-drain structure, the first interlayer dielectric layer, the first gate structure, the first source-drain metal and the first metal interconnection layer can all be formed by standard steps of the semiconductor manufacturing process, and the embodiments of the present application do not specifically limit this.

[0074] Step S130: flipping the CMOS transistor and exposing the second active structure.

[0075] In some embodiments, an insulating material (such as silicon oxide) may be deposited on the first metal interconnect layer formed above to form an insulating layer, and the insulating layer is bonded to a carrier wafer. The CMOS transistor is then flipped over and the substrate is placed on top.

[0076] In some embodiments, the process of exposing the second active structure in step S130 may be: removing the substrate; thinning the isolation structure to a preset height to expose the second active structure, and the thinned isolation structure is used to isolate the CMOS transistor and the memory cell.

[0077] In one example, after flipping, the substrate may be removed by polishing or chemical mechanical planarization.

[0078] It is understandable that after removing the substrate, the top of the second active structure is flush with the top of the isolation structure, so the isolation structure can be thinned to a preset height to expose the peripheral side of the second active structure, so that the second transistor in the memory cell can be formed later according to the second active structure exposed on the peripheral side. The preset height can be set according to actual needs, and the embodiment of the present application is not limited to this.

[0079] Step S140: forming a memory cell based on the second active structure.

[0080] In some embodiments, the implementation process of step S140 may include the following four steps: based on the second active structure, forming a transistor (second transistor); step two: performing a back-end process on the second transistor to form an interconnection layer, the interconnection layer including: at least one interconnection dielectric layer, and an interconnection metal structure located in the interconnection dielectric layer; step three: etching a portion of the interconnection dielectric layer to form a through hole; step four: based on the through hole, forming a capacitor structure, the capacitor structure is in contact with the second source and drain metal of the second transistor, or the capacitor structure is in contact with the second source and drain metal through the interconnection metal structure.

[0081] In step 1, based on the second active structure, a second transistor having a curved channel is formed. The present application can form the second transistor having a curved channel in two ways.

[0082] In one possible implementation, the implementation process of step one may be: etching a portion of the second active structure corresponding to the gate region of the second transistor to form a second groove; depositing semiconductor material in the gate region and the second groove to form a dummy gate structure; epitaxially growing a second source-drain structure on the second active structure; removing the dummy gate structure to expose the second groove; forming a second gate structure based on the second groove; and depositing metal material on the second source-drain structure to form a second source-drain metal.

[0083] It is understandable that after exposing the second active structure, a portion of the second active structure corresponding to the gate region of the second transistor can be etched to form a second groove. The second groove makes the channel of the second transistor a curved groove instead of a straight channel, thereby increasing the equivalent gate length of the channel to reduce leakage and improve retention time. The embodiment of the present application does not limit the shape of the second groove. For example, the second groove can be a U-shaped groove.

[0084] After the second groove is formed, the gate region of the second transistor may be opened by photolithography, and a semiconductor material (eg, Poly Si) may be deposited in the gate region of the second transistor and in the second groove to form a second dummy gate structure.

[0085] In some embodiments, after forming the second dummy gate structure, a second sidewall may be formed on both sides of the second dummy gate structure; a second source-drain structure may be formed on the second active structure on both sides of the second dummy gate structure and the second sidewall; and an interlayer dielectric may be deposited on the second source-drain structure and the second active structure to form a second interlayer dielectric layer. The second interlayer dielectric layer may cover the second source-drain structure and the second active structure. When the second source-drain structure and the first source-drain structure are subjected to epitaxial or implantation treatment, the doping ions may be the same or different, and the materials of the second interlayer dielectric layer and the first interlayer dielectric layer may also be the same or different.

[0086] It is understandable that when forming the second gate structure, the second dummy gate structure formed above can be removed by an etching process to expose the second groove and the gate groove where the gate region is located, and an insulating material is deposited at the gate groove and the second groove to form a second gate dielectric layer, and a metal material is deposited on the second gate dielectric layer to form a second gate electrode layer. The second gate dielectric layer and the second gate electrode layer together constitute the second gate structure.

[0087] After forming the second gate structure, a portion of the second interlayer dielectric layer may be etched to expose the second source-drain structure, and a metal material may be filled on the second source-drain structure to form a second source-drain metal.

[0088] In some embodiments, since the second transistor on the back side is responsible for regulating the charging and discharging of the capacitor structure, the second transistor on the back side may be an N-type transistor.

[0089] In another possible implementation, the implementation process of step one may be: depositing semiconductor material in the gate region to form a dummy gate structure; epitaxially growing a second source-drain structure on the second active structure; removing the dummy gate structure to expose the gate region and the second active structure in the channel region; etching the second active structure in the channel region to form a second groove; forming a second gate structure based on the second groove and the exposed gate region; and depositing metal material on the second source-drain structure to form a second source-drain metal.

[0090] In some embodiments, after the second dummy gate structure is formed, second spacers may be formed on both sides of the second dummy gate structure.

[0091] In some embodiments, after the second source-drain structure is formed, an interlayer dielectric may be deposited over the second source-drain structure and the second active structure, and a planarization process may be performed to form a second interlayer dielectric layer.

[0092] It can be understood that the present application can first form a second dummy gate structure, a second sidewall, a second source-drain structure, and a second interlayer dielectric layer in the gate region of the second transistor, and then remove the second dummy gate structure to expose the gate region. After removing the second dummy gate structure, the second active structure in the channel region of the second transistor will also be exposed, so after removing the second dummy gate structure, the second active structure in the channel region can be self-aligned and etched to form a second groove, and fill the second groove and the exposed gate region with metal material to form a second gate structure. Therefore, this method of etching the exposed second active structure after removing the second dummy gate structure has self-alignment.

[0093] In some embodiments, after forming the second gate structure, a portion of the second interlayer dielectric layer may be etched to expose the second source-drain structure, and a metal material may be filled on the second source-drain structure to form a second source-drain metal.

[0094] In step 2, after forming the second transistor, a back-end process may be performed to form a second metal interconnect layer. It is understandable that the second metal interconnect layer may include at least one interconnect dielectric layer and an interconnect metal structure located in the interconnect dielectric layer.

[0095] It can be understood that the capacitor structure can be a columnar or cylindrical structure, and a portion of the interconnect dielectric layer can be etched in step three to form a through hole, and then the capacitor structure is formed based on the through hole in step four.

[0096] In some embodiments, in step three, a portion of at least one interconnect dielectric layer may be etched until the interconnect metal structure is exposed to form a through hole, wherein the interconnect metal structure is in contact with the second source and drain metal.

[0097] In some embodiments, the implementation process of step four may be: forming a first electrode, a capacitor dielectric layer and a second electrode in the through hole in sequence to form a capacitor structure through the first electrode, the capacitor dielectric layer and the second electrode, wherein the first electrode is in contact with the interconnected metal structure.

[0098] After forming the through hole, a first electrode may be formed in the through hole, for example, by deposition. Here, the first electrode may be selected from but not limited to metals such as tantalum nitride, titanium nitride, tungsten, gold, aluminum, or polysilicon. It is worth noting that the first electrode covers the bottom and sidewalls of the through hole, and the first electrode contacts the interconnected metal structure.

[0099] After forming the first electrode, an oxide material may be deposited on the first electrode to cover the first electrode to form a capacitor dielectric layer. In some embodiments, the material of the dielectric layer may be a high dielectric constant (K) material. The material of the high-k dielectric layer includes hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3) or tantalum oxide (Ta2O5).

[0100] After forming the capacitor dielectric layer, a second electrode may be formed on the capacitor dielectric layer, for example, by deposition. Here, the second electrode may be selected from, but not limited to, metals such as tantalum nitride, titanium nitride, tungsten, gold, aluminum, or polysilicon. It is worth noting that the second electrode covers the capacitor dielectric layer, and the second electrode completely fills the through hole.

[0101] In the present application, a CMOS transistor is formed based on the first active structure away from the substrate by forming a first active structure and a second active structure on a substrate; then the CMOS transistor is flipped and the second active structure is exposed; based on the second active structure, a storage unit with a curved channel is formed. On the one hand, the present application can realize the homogeneous integration of a CMOS circuit with a logic function and a storage unit with a curved channel, and the storage unit to the logic circuit is monolithically integrated, and the distance between the two is shortened, which helps to reduce communication delay to improve chip performance. On the other hand, the storage unit partially applies a curved channel, which helps to increase the equivalent gate length to reduce leakage, increase retention time, and reduce power consumption. Moreover, since the CMOS transistor and the transistor in the storage unit are integrated in a "back-to-back" manner, they do not occupy additional plane size, which is conducive to further scaling of the plane size of the semiconductor device; the manufacturing process of the transistor in the logic circuit and the manufacturing process of the transistor in the storage unit can be independent of each other, and there is no need to consider the complex and cumbersome logic circuit and storage unit process compatibility issues, which is conducive to reducing the process difficulty and complexity of the semiconductor structure.

[0102] The following takes the active structure as a fin-shaped structure as an example to illustrate the first method for preparing the semiconductor structure provided by the embodiment of the present application. That is, after flipping the wafer and exposing the second active structure, etching is performed to form a curved channel. Figure 2 This is a schematic top view of the semiconductor structure in the embodiment of the present application. It should be noted that, for ease of understanding, only the active structure, gate structure and source-drain structure are shown in the top view. The AA' direction is the tangent direction of the semiconductor structure along the gate structure; the BB' direction is the tangent direction of the semiconductor structure along the source-drain structure; and the CC' direction is the tangent direction of the semiconductor structure along the active structure.

[0103] Figures 3 to 7 This is a schematic diagram of the structure of the semiconductor structure of an embodiment of the present application during the first preparation process. Figure 8 This is a schematic diagram of the first structure of the semiconductor structure of the embodiment of the present application. Figures 3 to 8 (a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., the AA' direction), Figures 3 to 8 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction), Figures 3 to 8 (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the active structure (i.e., CC' direction), Figure 8 (d) is a cross-sectional view of the capacitor structure in the semiconductor structure along the cross-sectional direction of the active structure (ie, CC' direction).

[0104] In one example, the semiconductor manufacturing process may include the following steps:

[0105] Step 1: Provide a bottom substrate 201 (such as a Si substrate); epitaxially grow a layer of SiGe material on the bottom substrate 201 as a sacrificial layer 202; and then epitaxially grow Si material on the sacrificial layer 202 to form a top substrate 203, so as to obtain Figure 3 The structure shown in FIG. 2 includes a bottom substrate 201 , a sacrificial layer 202 and a top substrate 203 together forming a substrate 20 .

[0106] Step 2: The top substrate 203, the sacrificial layer 202 and the bottom substrate 201 are sequentially etched to form a first fin structure 111, an etched sacrificial layer 21 and a second fin structure 121; then oxide is filled to form an isolation structure 22, and the structure is obtained as shown in FIG. Figure 4 The structure shown.

[0107] Step 3: Based on the first fin structure 111, a CMOS 11 is formed on the front side to obtain Figure 5 The structure shown.

[0108] It can be understood that first, a portion of the isolation structure 22 can be etched until the first fin structure 111 and the etched sacrificial layer 21 are exposed; then the gate area is opened by photolithography, and polysilicon is deposited in the gate area to form a first dummy gate structure; then the etched sacrificial layer 21 can be selectively removed to form a first groove, and a dielectric material is filled in the first groove to form an isolation layer 23; a first sidewall 24 is formed on both sides of the first dummy gate structure; a first source-drain structure 112 is formed by epitaxial growth based on the first fin structure 111 at the source-drain area, and an interlayer dielectric is deposited on the first source-drain structure 112 to form a first interlayer dielectric layer 113; then the first dummy gate structure is removed, a first gate structure 114 is formed in the gate area, and a first source-drain metal 115 is formed on the first source-drain structure 112; the back-end process of the transistor is completed to form a first metal interconnect layer 116.

[0109] It should be noted that for the convenience of presentation, Figure 5 Only one N-type transistor is shown. Actually, CMOS is a circuit having logic functions composed of N-type transistors and P-type transistors.

[0110] Step 4: Deposit oxide on the first metal interconnect layer 116 to form an insulating layer 25. Bond the carrier wafer 26 to the first insulating layer 25 above the insulating layer 25, then flip the wafer to place the substrate on top, and then thin the isolation structure 22 to expose the second fin structure 121, thereby obtaining the following: Figure 6 The structure shown.

[0111] Step 5: Etch a portion of the second fin structure 121 corresponding to the gate region to form a second groove 27, and obtain Figure 7 The structure shown.

[0112] Step 6: Based on the etched second fin structure, a storage unit 12 is formed to obtain Figure 8 The structure shown.

[0113] It can be understood that, first, the gate region can be opened by photolithography, and polysilicon can be deposited in the gate region and the second groove to form a second dummy gate structure; then, a second sidewall 28 can be formed on both sides of the second dummy gate structure; based on the second fin structure 121 at the source and drain region, a second source and drain structure 122 is formed by epitaxial growth, and an interlayer dielectric is deposited on the second source and drain structure 122 to form a second interlayer dielectric layer 123; then, the second dummy gate structure is removed to expose the gate region and the second groove; a second gate structure 124 is formed in the gate region and the second groove, and a second source and drain metal 125 is formed on the second source and drain structure 122; then, the back-end process of the transistor is completed to form a second metal interconnection layer 126; and a part of the interconnection dielectric layer in the second metal interconnection layer 126 is etched to form a through hole; and a capacitor structure 29 is formed in the through hole. Among them, the capacitor structure includes a first electrode 291, a capacitor dielectric layer 292, and a second electrode 293.

[0114] The second preparation process is described below, that is, after removing the second dummy gate structure, etching is performed to form a curved channel. Figures 9 to 11 is a schematic diagram of the structure of the semiconductor structure of an embodiment of the present application during the second preparation process, Fig.12 This is a second structural schematic diagram of the semiconductor structure of the embodiment of the present application. Figures 9 to 12 (a) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the gate structure (i.e., the AA' direction), Figures 9 to 12 (b) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the source-drain structure (i.e., BB' direction), Figures 9 to 12 (c) is a cross-sectional view of the semiconductor structure along the cross-sectional direction of the active structure (ie, CC' direction).

[0115] In one example, the semiconductor manufacturing process may include the following steps:

[0116] Step 1: Form CMOS 11 on the front side, and flip the wafer to form a second dummy gate structure 30, a second sidewall 28, a second source-drain structure 122 and a second interlayer dielectric layer 123 of the transistor on the back side, to obtain Fig. 9 The structure shown.

[0117] Here, reference may be made to the first to fourth steps in the first preparation process. Then, the gate region is opened by photolithography, and polysilicon is deposited in the gate region to form a second dummy gate structure 30; then, a second sidewall 28 may be formed on both sides of the second dummy gate structure 30; a second source-drain structure 122 is formed by epitaxial growth based on the second fin-shaped structure 121 at the source-drain region, and an interlayer dielectric is deposited on the second source-drain structure 122 to form a second interlayer dielectric layer 123.

[0118] Step 2: Remove the second dummy gate structure 30 to form a gate groove 31, and obtain Fig.10 The structure shown.

[0119] like Fig.10 As shown, after the second dummy gate structure 30 is removed, the silicon in the channel region (the second fin structure) will also be exposed.

[0120] Step 3: Etch the exposed second fin structure to form a second groove 27, and obtain Fig.11 The structure shown.

[0121] Step 4: Based on the etched second fin structure, a storage unit 12 is formed to obtain Fig.12 The structure shown.

[0122] It can be understood that a second gate structure 124 can be formed in the gate groove and the second groove, and a second source-drain metal 125 can be formed on the second source-drain structure 122; then the back-end process of the transistor is completed to form a second metal interconnection layer 126; and a portion of the interconnection dielectric layer in the second metal interconnection layer 126 is etched to form a through hole; and a capacitor structure 29 is formed in the through hole.

[0123] The third preparation process is introduced below, that is, there is no isolation layer between the first fin structure and the second fin structure. Fig.13 This is a schematic diagram of the third structure of the semiconductor structure of the embodiment of the present application. Different from the first preparation method, the first step directly provides an original silicon substrate 20, in which the top substrate and the bottom substrate are of the same height, there is no sacrificial layer, and the subsequent third step does not perform the operation of removing the sacrificial layer to form an isolation layer. Fig.13 There is no isolation layer between the first fin structure and the second fin structure.

[0124] The fourth preparation process is introduced below, that is, the case where the original substrate is an SOI substrate. Fig.14This is a schematic diagram of the fourth structure of the semiconductor structure of the embodiment of the present application. Different from the first preparation method, the middle layer between the top substrate and the bottom substrate in the substrate 20 in the first step is the BOX layer 32, so the operation of removing the sacrificial layer to form an isolation layer is not performed in the subsequent third step. After the active structure is formed, the BOX layer 32 can be directly used as an isolation layer between the first fin structure and the second fin structure.

[0125] In the present application, a CMOS transistor is formed based on the first active structure away from the substrate by forming a first active structure and a second active structure on a substrate; then the CMOS transistor is flipped and the second active structure is exposed; based on the second active structure, a storage unit with a curved channel is formed. On the one hand, the present application can realize the homogeneous integration of a CMOS circuit with a logic function and a storage unit with a curved channel, and the storage unit to the logic circuit is monolithically integrated, and the distance between the two is shortened, which helps to reduce communication delay to improve chip performance. On the other hand, the storage unit partially applies a curved channel, which helps to increase the equivalent gate length to reduce leakage, increase retention time, and reduce power consumption. Moreover, since the CMOS transistor and the transistor in the storage unit are integrated in a "back-to-back" manner, they do not occupy additional plane size, which is conducive to further scaling of the plane size of the semiconductor device; the manufacturing process of the transistor in the logic circuit and the manufacturing process of the transistor in the storage unit can be independent of each other, and there is no need to consider the complex and cumbersome logic circuit and storage unit process compatibility issues, which is conducive to reducing the process difficulty and complexity of the semiconductor structure.

[0126] Furthermore, the semiconductor structure provided in the embodiment of the present application can be detected using detection and analysis instruments, such as scanning electron microscope (SEM), transmission electron microscope (TEM), scanning transmission electron microscopy (STEM), etc. Taking TEM as an example, the embodiment of the present application can use TEM slicing to detect the circuit structure and the cross-section of the transistor in the above semiconductor structure along the active structure direction and perpendicular to the active structure direction at multiple positions, and it can be detected that: at the circuit level or chip level, the front of the semiconductor structure is a logic circuit, and the back is a DRAM cell array; at the transistor level, the active regions of the transistors on both sides are self-aligned, which is manifested as an integrated fin in the vertical channel cross section; at the transistor level, the front logic circuit has a channel morphology that is no different from that in the traditional technology, and the channel of the back DRAM cell array is U-shaped; there may be an isolation layer between the first fin structure and the second fin structure, or there may not be an isolation layer, and the edge area of ​​the U-shaped fin can be self-aligned to the edge of the spacer.

[0127] The present application provides a semiconductor device, including: a semiconductor structure as described in the above embodiment. The specific definition of the semiconductor structure can refer to the above semiconductor structure, which will not be described in detail here.

[0128] The embodiment of the present application provides an electronic device, including: a circuit board and a semiconductor device as in the above embodiment, the semiconductor device is arranged on the circuit board. The semiconductor device includes the above semiconductor structure. The specific definition of the semiconductor structure can be referred to the above memory, which is not repeated here.

[0129] In the description of the embodiments of the present application, the description with reference to the terms "one embodiment", "an embodiment", "example", "specific example", or "some examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the embodiments of the present application. In the present application, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine the different embodiments or examples described in the present application and the features of the different embodiments or examples without contradiction.

[0130] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method comprises: forming a first semiconductor structure on a substrate, wherein the first semiconductor structure comprises at least a first active structure and a second active structure, wherein the first active structure is farther away from the substrate than the second active structure; Based on the first active structure, a complementary metal oxide semiconductor (CMOS) transistor is formed; Flipping the CMOS transistor and exposing the second active structure; Based on the second active structure, a memory cell is formed, and a channel of a transistor in the memory cell is a curved channel.

2. The method according to claim 1, characterized in that The first semiconductor structure further includes an isolation layer located between the first active structure and the second active structure. The step of forming the first semiconductor structure on the substrate includes: Providing a substrate, the substrate comprising a bottom substrate, a sacrificial layer and a top substrate stacked in sequence along a first direction; Sequentially etching the top substrate, the sacrificial layer, and the bottom substrate to form the first active structure and the second active structure, wherein the first active structure is the etched top substrate, and the second active structure is the etched bottom substrate; removing the etched sacrificial layer to form a first groove; A dielectric material is filled in the first groove to form the isolation layer, and the isolation layer is used to isolate the CMOS transistor from the storage unit.

3. The method according to claim 1, characterized in that The forming of a CMOS transistor based on the first active structure comprises: epitaxially growing a first source-drain structure on the first active structure; Based on the first active structure, forming a first gate structure; A metal material is deposited on the first source-drain structure to form a first source-drain metal.

4. The method according to claim 1, characterized in that: The forming of a storage unit based on the second active structure includes: Based on the second active structure, forming the transistor; Performing a back-end process on the transistor to form an interconnection layer, wherein the interconnection layer includes: at least one interconnection dielectric layer, and an interconnection metal structure located in the interconnection dielectric layer; etching a portion of the interconnect dielectric layer to form a through hole; Based on the through hole, a capacitor structure is formed, and the capacitor structure is in contact with the second source-drain metal of the transistor, or the capacitor structure is in contact with the second source-drain metal through the interconnect metal structure.

5. The method according to claim 4, characterized in that The forming of the transistor based on the second active structure comprises: Etching a portion of the second active structure corresponding to the gate region of the transistor to form a second groove; Depositing semiconductor material in the gate region and the second groove to form a dummy gate structure; epitaxially growing a second source-drain structure on the second active structure; removing the dummy gate structure to expose the second groove; Based on the second groove, forming a second gate structure; A metal material is deposited on the second source-drain structure to form a second source-drain metal.

6. The method according to claim 4, characterized in that The forming of the transistor based on the second active structure comprises: Depositing semiconductor material in the gate region to form a dummy gate structure; epitaxially growing a second source-drain structure on the second active structure; Removing the dummy gate structure to expose the gate region and the second active structure in the channel region; Etching the second active structure in the channel region to form a second groove; Based on the second groove and the exposed gate region, forming a second gate structure; A metal material is deposited on the second source-drain structure to form a second source-drain metal.

7. The method according to claim 4, characterized in that The forming of a capacitor structure based on the through hole comprises: A first electrode, a capacitor dielectric layer and a second electrode are sequentially formed in the through hole to form the capacitor structure through the first electrode, the capacitor dielectric layer and the second electrode, wherein the first electrode is in contact with the interconnection metal structure.

8. A semiconductor structure, prepared using the preparation method according to any one of claims 1 to 7, characterized in that: include: The CMOS transistor; A memory cell is arranged opposite to the CMOS transistor, and a channel of the transistor in the memory cell is a curved channel.

9. A semiconductor device, characterized in that: include: The semiconductor structure as claimed in claim 8.

10. An electronic device, characterized in that: include: A circuit board and a semiconductor device as claimed in claim 9, wherein the semiconductor device is arranged on the circuit board.

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