Groove type MOSFET device

Abstract

The invention relates to a power semiconductor device, in particular to a groove type MOSFET device, and provides a novel shield gate groove type field effect transistor in order to reduce the cellular size of the device and achieve better compromise between breakdown voltage and on resistance. The semiconductor cell trench is composed of a plurality of deep trenches and shallow trenches which are periodically arranged at intervals in the Z direction, the deep trenches are 0.3-4 microns deeper than the shallow trenches, gate electrodes located above the trenches and shield gate electrodes located below the trenches are arranged in the shallow trenches and the deep trenches, and the gate electrodes and the shield gate electrodes are isolated from each other. The gate electrode is isolated from the corresponding side wall of the groove through a gate oxide layer, and the shield gate electrode is isolated from the corresponding side wall of the groove through a groove isolation layer; the gate electrode and the shield gate electrode are connected in the Z direction, and the shield gate electrode changes up and down along with different depths of the groove in the Z direction and is connected to the source electrode metal located on the upper surface at a proper position.

Description

Technical Field

[0001] The invention relates to a power semiconductor device, in particular to the structure of a trench field effect transistor device and a manufacturing method thereof. Background Art

[0002] A structure of an N-type shielded gate trench field effect transistor such as Figure 1 As shown, the device structure includes: an N-type semiconductor region 100; a series of cell trenches 101 located in the N-type semiconductor region 100. The cell trenches are filled with a gate electrode 110 located above and a shielding gate electrode 120 located below. The gate electrode 110 and the corresponding trench sidewall are isolated by a gate oxide layer; the shielding gate electrode 120 and the corresponding trench sidewall are isolated by a trench isolation layer 107; and the gate electrode 110 and the shielding gate electrode 120 are isolated by an inter-electrode isolation layer. The structure also includes a P-doped body region 103 and an N+ doped source region 104 located on the upper surface of the semiconductor between the cell trenches 101; in addition, a series of contact hole trenches 102 and a P+ contact doping region 105 located below the source contact hole trench 102 are included between the cell trenches 101. The source contact hole trench 102 is covered with an upper surface metal layer. A schematic diagram of the electric field strength versus trench depth of an embodiment of the structure is shown in FIG. Figure 3 As shown by the solid line in the middle, the bottom of the trench has a higher electric field, which limits the improvement of the breakdown voltage. To improve the breakdown performance, Figure 2 As shown, in Figure 1 Based on the device, the device has a trench isolation layer 107 with a variable thickness that is thin at the top and thick at the bottom. Figure 1 The schematic diagram of the electric field strength versus the groove depth is shown in the corresponding embodiment of the structure. Figure 3 As shown by the dotted line, since the trench isolation layer 107 at the bottom of the trench is thicker (d2 in the figure), the electric field strength at the bottom of the trench is reduced and the breakdown voltage is increased. Figure 2 The structure has a more optimized compromise between breakdown voltage and on-resistance. However, a thicker trench isolation layer 107 needs to be provided at the bottom of the trench in the structure, thus limiting the further reduction of the cell size. Summary of the invention

[0003] The present invention provides a novel shielded gate trench field effect transistor having a special trench structure, which is beneficial to reducing the cell size of the device and achieving a better compromise between breakdown voltage and on-resistance.

[0004] A trench MOSFET device is provided in the device, wherein a first conductive semiconductor region is provided in the first conductive semiconductor region in the X direction, wherein a series of periodically arranged and mutually parallel semiconductor cell trenches are provided, wherein the semiconductor cell trenches are composed of a plurality of deep trenches and shallow trenches periodically arranged in an interval manner in the Z direction, wherein the deep trenches are 0.3-4 μm deeper than the shallow trenches, wherein the shallow trenches and the deep trenches are provided with mutually isolated gate electrodes located above the trenches and shielding gate electrodes located below the trenches, wherein the gate electrodes are isolated from the corresponding trench sidewalls by a gate oxide layer, and the shielding gate electrodes are isolated from the corresponding trench sidewalls by a trench isolation layer; wherein the gate electrode and the shielding gate electrode are connected in the Z direction, wherein the shielding gate electrode varies in height in the Z direction with different trench depths and is connected to a source metal located on the upper surface at an appropriate position.

[0005] Furthermore, the bottoms of the shallow grooves and the deep grooves are in smooth arc shapes.

[0006] Furthermore, the trench isolation layer below the shallow trench is thicker than the trench isolation layer on the sidewall thereof.

[0007] Furthermore, the deep grooves are circular or equilateral in the XZ section, and the distances between adjacent deep grooves in any direction are equal.

[0008] Furthermore, the deep grooves are circular or equilateral in the XZ section, and the deep grooves in adjacent cell grooves are evenly staggered.

[0009] Furthermore, the deep groove is an ellipse or a long symmetrical polygon in the XZ section.

[0010] Preferably, the bottom of the shallow trench, the bottom of the deep trench and the lower sidewall are provided with a second conductive type semiconductor doping region.

[0011] Furthermore, the junction depth of the second conductive type semiconductor doping region located at the bottom of the deep trench is deeper than the junction depth of the second conductive type semiconductor doping region at the lower sidewall of the deep trench.

[0012] Furthermore, the second conductivity type semiconductor doped regions between the lower side walls of adjacent deep trenches in the Z direction are connected.

[0013] The present invention provides a novel shielded gate trench field effect transistor having a special trench structure, which is beneficial to reducing the cell size of the device and achieving a better compromise between breakdown voltage and on-resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1-3 This is a schematic diagram of an existing shielded gate trench field effect transistor structure, showing how the electric field strength of the structure varies with the trench depth.

[0015] Figure 4 A schematic diagram of a trench structure of a shielded gate trench field effect transistor device according to an embodiment of the present invention.

[0016] Figure 5 for Figure 4 A schematic cross-sectional view of the groove structure of the embodiment in FIG.

[0017] Figure 6-8 Three implementation methods of the top view of the trench structure of the shielded gate trench field effect transistor device of the present invention.

[0018] Figure 9-10 A schematic diagram of a trench cross section along the Z direction and along the X direction in one embodiment of a shielded gate trench field effect transistor device of the present invention; Figure 11-12 It is a schematic diagram of the cross-section of the trench along the Z direction and along the X direction in another embodiment of the shielded gate trench field effect transistor device of the present invention. DETAILED DESCRIPTION

[0019] The following will explain the relevant technical background of the existing shielded gate trench field effect transistor. It should be noted that the corresponding position words such as "upper", "lower", "left", "right", "front", "back", "vertical", "horizontal", and "vertical" described in this document correspond to the relative positions of the reference diagram. The specific implementation does not limit the fixed direction. It should be noted that the devices in the drawings are not necessarily drawn to a specific scale. The straight lines shown as the boundaries of the doped regions and trenches in the drawings, as well as the sharp angles formed by the boundaries, are generally not straight lines and precise angles in actual applications.

[0020] The present invention is described in detail below in conjunction with the accompanying drawings and embodiments. It should be noted that in the following description of the shielded gate trench field effect transistor device and its manufacturing method of the present invention, the semiconductor substrate of the shielded gate trench field effect transistor device is considered to be composed of silicon (Si) material. However, the substrate can also be composed of any other material suitable for the manufacture of shielded gate trench field effect transistors, such as gallium nitride (GaN), silicon carbide (SiC), etc. In the following description, the conductivity type of the semiconductor region is divided into P type (second conductivity type) and N type (first conductivity type). A semiconductor region of P type conductivity type can be formed by doping one or more impurities into the original semiconductor region. These impurities can be but are not limited to: boron (B), aluminum (Al), gallium (Ga), etc. An N type conductive semiconductor region can also be formed by doping one or more impurities into the original semiconductor region. These impurities can be but are not limited to: phosphorus (P), arsenic (As), tellurium (Sb), selenium (Se), protons (H + ) etc. In the following description, the heavily doped P-type conductive semiconductor region is marked as P + The heavily doped N-type conductive semiconductor region is marked as N+ For example, in a silicon substrate, unless otherwise specified, the impurity concentration of a heavily doped region is generally 1 × 10 19 cm -3 Up to 1 × 10 22 cm -3 Those skilled in the art should know that the P-type (second conductivity type) and the N-type (first conductivity type) described in the present invention can be interchanged.

[0021] A cell trench structure in a trench field effect transistor device of the present invention is as follows Figure 4 As shown, the structure includes an N-type semiconductor region 100, wherein a series of periodically arranged (X direction) mutually parallel semiconductor cell grooves 201 are provided above the N-type semiconductor region 100, and the series of grooves have a depth variation in the groove extension direction (Z direction), that is, a plurality of periodically arranged deep grooves 211 are formed, and shallow grooves 212 are formed between adjacent deep grooves 211, and the shallow grooves 212 and the deep grooves 211 are arranged at intervals.

[0022] Generally, the interval between the deep trenches 211 in the Z direction is equal to or slightly larger than the interval between the deep trenches 211 in the X direction (refer to Figure 6 In some embodiments, the distances between the deep trench 211 and the surrounding deep trenches 211 are the same (refer to Figure 7 In a device embodiment with a breakdown voltage of 120V, the spacing in the X direction and the Z direction is between 1.4-2.8um. ​​Generally, the spacing of the deep trench 211 in the X and Z directions is greater than 0.3um.

[0023] Generally speaking, the depth of the deep trench 211 is 0.3-4 μm deeper than the depth of the shallow trench 212. Figure 1 Based on the technical solution, the depth of some cell grooves is reduced by about 0.3-4um. In a device embodiment with a breakdown voltage of 120V, the depth of the shallow groove 212 is between 2-4um, and the depth of the deep groove 211 is 2-4um deeper than the shallow groove 212. In a device embodiment with a breakdown voltage of 165V, the depth of the shallow groove 212 is between 2-4um, and the depth of the deep groove 211 is 4-8um deeper than the shallow groove 212.

[0024] The deep groove 211 and the shallow groove 212 are usually cylindrical or elliptical, and the bottom is a smooth arc, similar to a needle.

[0025] The periodic cell trench 201 is filled with two electrodes connected to each other along the trench direction (Z direction): a gate electrode 110 located at the top and a shielding gate electrode 120 located at the bottom. The gate electrode 110 is isolated from the corresponding trench sidewall by a gate oxide layer; the shielding gate electrode 120 is isolated from the corresponding trench sidewall by a trench isolation layer 208; and the gate electrode 110 and the shielding gate electrode 120 are isolated by an inter-electrode isolation layer.

[0026] Compared with the existing device structure, the present invention adopts periodic needle-shaped deep trenches, and the shielded gate electrode in the needle-shaped deep trenches is coupled to the adjacent semiconductor in the XZ plane, and the semiconductor is depleted not only in the X direction but also in the Z direction, so the equivalent lateral electric field strength in the X direction is greater than that in the Z direction. Figure 1 The device is small, the breakdown voltage is higher, and Figure 2 Compared with the structure in the conventional structure, the structure does not need to increase the thickness of the trench isolation layer in the deep trench, so it will not limit the reduction of the cell size. At the same time, because the trench density in the deep semiconductor of the structure of the present invention is smaller than that of the existing structure, the use of a breakdown voltage of 120V Figure 2 Taking the device with a structure as an example, d1=2000-4000A, d2=5000-8000A, and the cell size is 2.2-2.6um, while the corresponding device of the present invention with a breakdown voltage of 120V, d3=4000-6000A, and the cell size is 1.8-2.4um. The cell size is reduced and the semiconductor conduction area (XZ plane) is larger. Therefore, it has a lower on-resistance during forward conduction, achieving a better compromise between breakdown voltage and on-resistance.

[0027] Figure 5 is a schematic cross-sectional view of the trench structure of the above device along the trench direction, and corresponds to Figure 4 The gate electrode 110 is connected to each other along the trench direction (Z direction) between the deep trench 211 and the shallow trench 212. The gate electrode 110 is connected to the gate metal 210 located on the upper surface through the gate contact hole 221 thereon.

[0028] The shielding gate electrode 120 is connected to each other along the trench direction (Z direction) between the deep trench 211 and the shallow trench 212 and has a height variation. In one section of the trench, the gate electrode 110 is not arranged on the upper part of the trench, and the shielding gate electrode 120 extends to the upper part of the trench and is connected to the source metal 220 located on the upper surface through the source contact 222.

[0029] In some embodiments, the trench isolation layer 218 at the bottom of the shallow trench 212 is thicker than the trench isolation layer 208 at the sidewall. This structure is beneficial for reducing the electric field strength below the shallow trench 212 and preventing the formation of a breakdown weak point.

[0030] Preferably, the deep trenches 211 are evenly arranged on the XZ plane, which is beneficial to the charge balance of the device during reverse bias to increase the breakdown voltage; Figure 6-Figure 8 FIG. 4 is a top view of an embodiment of a trench structure in which deep trenches 211 are periodically distributed in a unit cell trench 201 .

[0031] An embodiment of the present invention is Figure 6 As shown, the deep groove 211 is circular or equilateral in the XZ section, and the adjacent cellular grooves 201 in the X direction have exactly the same groove structure. The distance w1 between adjacent deep grooves 211 in the X direction and the distance w2 between adjacent deep grooves 211 in the Z direction, in one embodiment w1=w2, in another embodiment, w2 is 80-150% of w1.

[0032] Another embodiment of the present invention is Figure 7 As shown, the deep groove 211 is circular or equilateral in the XZ section, the deep grooves 211 in the adjacent cellular grooves 201 in the X direction have a difference of half a period in the Z direction (uniformly staggered), the distance between the deep grooves 211 on two adjacent cellular grooves 201 is w3, the distance between the adjacent deep grooves 211 in the Z direction is w2, in one embodiment w2=w3, in another embodiment, w2 is 80-150% of w3, and Figure 6 Compared with the structure, this structure has better charge balance ability when reverse biased.

[0033] Another embodiment of the present invention is Figure 8 As shown, the deep groove 211 is an ellipse or a symmetrical polygon that is longer in the Z direction in the XZ section, and Figure 6 , Figure 7 Compared with the structure, this structure is conducive to filling the isolation layer material and the electrode material in the deep trench 211 during the manufacturing process.

[0034] Figure 9-10 Another embodiment of the present invention is shown, wherein Fig. 9 is a schematic cross-sectional view of the embodiment along the groove direction (Z direction), Fig.10 : is a schematic cross-sectional view of the structure along the X direction, which is different from the above structure in that the bottom of the shallow trench 212 and the bottom and lower sidewall of the deep trench 211 have a P-type semiconductor doping region 230. The provision of the P-type semiconductor doping region 230 is beneficial to reducing the electric field strength near the bottom of the deep trench 211, and is also beneficial to achieving charge balance during reverse bias and improving breakdown resistance.

[0035] In some embodiments, the junction depth of the P-type semiconductor doping region 230 at the bottom of the deep trench 211 is deeper than the junction depth of the P-type semiconductor doping region 230 at the lower sidewall of the deep trench 211. In an actual embodiment, the junction depth of the P-type semiconductor doping region 230 at the bottom of the deep trench 211 is 0.2-2 um, and the junction depth of the P-type semiconductor doping region 230 at the lower sidewall of the deep trench 211 is 0.1-0.5 um.

[0036] The method for forming the P-type semiconductor doping region 230 may include multiple ion implantation steps.

[0037] Figure 11-12 Another embodiment of the present invention is shown. Fig.11 is a schematic cross-sectional view of the embodiment along the groove direction (Z direction), Fig.12 is a schematic diagram of the cross section of the structure along the X direction. and Figure 9-10 Compared to the illustrated embodiment, the P-type semiconductor doping regions 230 located on the lower side walls of adjacent deep trenches 211 are connected together in the Z direction. Since the P-type semiconductor doping regions 230 on the lower side walls of the deep trenches 211 in the Z direction are connected to each other, the depth of the P-type semiconductor doping regions 230 below the shallow trench 212 is increased. The increased P-type semiconductor doping regions 230 are beneficial to charge balance during reverse bias and can further increase the breakdown voltage.

[0038] The method for forming the P-type semiconductor doping region 230 may include at least one directional ion implantation step. The method for forming the P-type semiconductor doping region 230 may include at least one 1000-1100° C. annealing process.

[0039] In the device structure of the present invention described above, only the key trench structure is shown, and no epitaxial structure, semiconductor doping, contact hole structure, etc. are listed. Personnel in the technical field can make appropriate combinations and changes based on the structure of the existing shielded gate trench field effect transistor to realize more embodiments based on the present invention. Personnel in the technical field can also make appropriate combinations and changes based on the manufacturing process of the existing shielded gate trench field effect transistor to realize more embodiments based on the present invention with process characteristics. For example, a self-aligned contact hole structure is formed by a self-aligned process.

[0040] In addition, those skilled in the art should know that the structural features and process steps mentioned in the above-mentioned embodiments of the present invention can be combined with each other to form more embodiment device structures and implementation methods.

Claims

1. A trench MOSFET device, wherein a first conductive semiconductor region is provided in the device, characterized in that: A series of periodically arranged and mutually parallel semiconductor cell grooves are provided in the first conductive semiconductor region, each of the semiconductor cell grooves is composed of a plurality of deep grooves and shallow grooves periodically arranged in an interval manner, wherein the deep groove is 0.3-4um deeper than the shallow groove, and the shallow grooves and deep grooves are provided with mutually isolated gate electrodes located above the grooves and shielding gate electrodes located below the grooves, the gate electrodes are isolated from the corresponding groove side walls by a gate oxide layer, and the shielding gate electrodes are isolated from the corresponding groove side walls by a trench isolation layer; the gate electrode and the shielding gate electrode are connected in the Z direction, and the shielding gate electrode varies in height in the Z direction with the different groove depths and is connected to the source metal located on the upper surface at an appropriate position.

2. The trench MOSFET device according to claim 1, characterized in that: The bottoms of the shallow grooves and the deep grooves are in smooth arc shapes.

3. The trench MOSFET device according to claim 1, characterized in that: The thickness of the trench isolation layer under the shallow trench is thicker than that of the trench isolation layer on the sidewall thereof.

4. The trench MOSFET device according to claim 1, wherein: The deep grooves are circular or equilateral in the XZ section, and the distances between adjacent deep grooves in any direction are equal.

5. The trench MOSFET device according to claim 1, wherein: The deep grooves are circular or equilateral in the XZ section, and the deep grooves in adjacent cell grooves are evenly staggered.

6. The trench MOSFET device according to claim 1, wherein: The deep groove is an ellipse or a long symmetrical polygon in the XZ section.

7. The trench MOSFET device according to any one of claims 1 to 6, characterized in that: The bottom of the shallow trench, the bottom of the deep trench and the lower side wall are provided with a second conductive type semiconductor doping region.

8. The trench MOSFET device according to claim 7, characterized in that: The junction depth of the second conductive type semiconductor doping region at the bottom of the deep trench is deeper than the junction depth of the second conductive type semiconductor doping region at the lower sidewall of the deep trench.

9. The trench MOSFET device according to claim 7, characterized in that: The second conductive type semiconductor doped regions between the lower side walls of adjacent deep trenches in the Z direction are connected.

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