Integrated bidirectional switch MOSFET

Abstract

The utility model discloses an integrated bidirectional switch MOSFET which comprises a first groove group and a second groove group which are symmetrically arranged along the horizontal central axis of an N-epitaxial layer, the first groove group and the second groove group respectively comprise a plurality of same strip-shaped grooves, gate oxide layers grow in the strip-shaped grooves, gate polycrystals are deposited in the gate oxide layers, and the gate polycrystals are deposited in the strip-shaped grooves. The grid polycrystals in the strip-shaped grooves in the first groove group form a first grid of the MOSFET, and the grid polycrystals in the strip-shaped grooves in the second groove group form a second grid of the MOSFET; a first P well layer is formed at the upper part of the N-epitaxial layer outside the first groove group, and a second P well layer is formed at the upper part of the N-epitaxial layer in the second groove group; a first N + active layer is formed at the upper part of the first P well layer, and the first N + active layer is in short circuit with the grid polycrystal in the first groove group to form a first source electrode of the MOSFET; a second N + active layer is formed on the lower portion of the second P well layer, the second N + active layer and the grid polycrystal in the second groove group are in short circuit to form a second source electrode of the MOSFET, and the first source electrode and the second source electrode form a bidirectional switch of the MOSFET.

Description

Technical Field

[0001] The utility model relates to the technical field of MOSFET, in particular to an integrated bidirectional switch MOSFET. Background Art

[0002] There are some existing high current application modules, such as battery protection circuits. Because the heat dissipation capacity of a single MOS is weak, the overcurrent capacity is limited. When the current is large, the heat generated by the MOS cannot be dissipated in time, the temperature rises, and the MOS on-resistance increases with the temperature. Then the temperature rises again, increasing the conduction loss of the MOS. Therefore, in the current protection circuit, such as Figure 1 As shown, by using two MOS pairs in parallel, one discharging MOS and one charging MOS, the drains of the two MOS are connected by a wire to achieve heat dissipation and reduce the conduction loss of a single MOS. In order to increase the heat dissipation effect, several pairs of MOS pairs in parallel can be added on the basis of a pair of MOS pairs in parallel. However, in order to ensure the heat dissipation capacity of the high-current application module, it is necessary to continue to increase the number of MOS pairs in parallel, which increases the overall volume of the high-current application module, occupies too much circuit space, and makes the production process of the high-current application module complicated.

[0003] The purpose of the present invention is to design an integrated bidirectional switch MOSFET in view of the above-mentioned problems in the prior art. Utility Model Content

[0004] The purpose of the utility model is to overcome the deficiencies of the prior art and provide an integrated bidirectional switch MOSFET that can solve the above technical problems.

[0005] The utility model provides an integrated bidirectional switch MOSFET, comprising:

[0006] An N-epitaxial layer, a first trench group formed on an upper portion of the N-epitaxial layer, and a second trench group formed on a lower portion of the N-epitaxial layer;

[0007] The first trench group and the second trench group are symmetrically arranged along the horizontal center axis of the N-epitaxial layer, the first trench group and the second trench group respectively include a plurality of identical strip trenches, a gate oxide layer is grown in the strip trenches, a gate polycrystalline is deposited in the gate oxide layer, the gate polycrystalline in the strip trenches in the first trench group forms a first gate of the MOSFET, and the gate polycrystalline in the strip trenches in the second trench group forms a second gate of the MOSFET;

[0008] A first P well layer is formed on the upper part of the N-epitaxial layer outside the first trench group, and a second P well layer is formed on the upper part of the N-epitaxial layer inside the second trench group; a first N+ active layer is formed on the upper part of the first P well layer, and the first N+ active layer is short-circuited with the gate polycrystalline in the first trench group to form a first source of the MOSFET; a second N+ active layer is formed on the lower part of the second P well layer, and the second N+ active layer is short-circuited with the gate polycrystalline in the second trench group to form a second source of the MOSFET, and the first source and the second source form a bidirectional switch of the MOSFET.

[0009] Furthermore, a first ILD interlayer dielectric layer is formed above the first N+ active layer, and a second ILD interlayer dielectric layer is formed below the second N+ active layer, so as to reduce the parasitic capacitance of the MOSFET.

[0010] Furthermore, the first ILD interlayer dielectric layer and the second ILD interlayer dielectric layer have the same thickness, and the thickness of the first ILD interlayer dielectric layer and the second ILD interlayer dielectric layer is 0.3-1 um.

[0011] Furthermore, a first metal layer is formed above the first ILD interlayer dielectric layer, and a second metal layer is formed below the second ILD interlayer dielectric layer for externally connecting current.

[0012] Furthermore, the first metal layer and the second metal layer have the same thickness, and the thickness of the first metal layer and the second metal layer is 3-10 um.

[0013] Furthermore, the thickness of the N-epitaxial layer is 5-50 um; the distance between the first trench group and the second trench group in the N-epitaxial layer is 2-30 um.

[0014] Furthermore, the first P-well layer and the second P-well layer have the same thickness, and the thickness of the first P-well layer and the second P-well layer is 0.6-1.5 um.

[0015] The utility model has the following advantages:

[0016] First, by eliminating the drains of the two MOSFETs, setting the two MOSFETs symmetrically up and down to share a common epitaxial layer, retaining the source and gate of the two MOSFETs, and controlling the gates of the two symmetrical MOSFETs respectively, the two symmetrical MOSFETs are turned on at the same time. Integrating the two symmetrical MOSFETs in one device can save the circuit board space occupied by the MOSFETs.

[0017] Secondly, by arranging the two MOSFETs symmetrically up and down, the chip area utilization rate can be improved. Compared with the device in which the two MOSFETs are arranged symmetrically left and right, the cell size is smaller and a larger current density is obtained.

[0018] Third, after the first metal layer and the second metal layer obtain current from the outside at the same time, they flow to the first gate and the second gate through the first ILD interlayer dielectric layer and the second ILD interlayer dielectric layer respectively, and the first metal layer and the second metal layer are drains to each other, thereby turning on two symmetrical MOSFETs at the same time. If only one metal layer obtains current, the device cannot be turned on, ensuring the bidirectional switching function of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] In order to more clearly illustrate the embodiments of the utility model or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the utility model. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0020] Figure 1 This is the battery protection circuit diagram.

[0021] Figure 2 It is a structural diagram of an integrated bidirectional switch MOSFET. DETAILED DESCRIPTION

[0022] The present invention is further described in detail below in conjunction with the accompanying drawings and embodiments. It is particularly noted that the following embodiments are only used to illustrate the present invention, but do not limit the scope of the present invention. Similarly, the following embodiments are only partial embodiments of the present invention rather than all embodiments. All other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0023] like Figure 2 As shown, the present solution provides an integrated bidirectional switch MOSFET, including:

[0024] N-epitaxial layer 1, a first trench group 2 formed on the upper portion of the N-epitaxial layer, and a second trench group 3 formed on the lower portion of the N-epitaxial layer;

[0025] The first trench group 2 and the second trench group 3 are symmetrically arranged along the horizontal central axis of the N-epitaxial layer 1, and the first trench group 2 and the second trench group 3 respectively include a plurality of identical strip trenches 4, a gate oxide layer 5 is grown in the strip trenches 4, a gate polycrystalline 6 is deposited in the gate oxide layer 5, the gate polycrystalline 6 in the strip trenches 4 in the first trench group 2 forms a first gate of the MOSFET, and the gate polycrystalline 6 in the strip trenches 4 in the second trench group 3 forms a second gate of the MOSFET;

[0026] A first P well layer 7 is formed on the upper part of the N-epitaxial layer 1 outside the first trench group 2, and a second P well layer 8 is formed on the upper part of the N-epitaxial layer 1 in the second trench group 3; a first N+ active layer 9 is formed on the upper part of the first P well layer 7, and the first N+ active layer 9 is short-circuited with the gate polycrystalline 6 in the first trench group 2 to form a first source of the MOSFET; a second N+ active layer 10 is formed on the lower part of the second P well layer 8, and the second N+ active layer 10 is short-circuited with the gate polycrystalline 6 in the second trench group 3 to form a second source of the MOSFET, and the first source and the second source form a bidirectional switch of the MOSFET.

[0027] In this embodiment, the two MOSFETs in the prior art require a separate epitaxial layer, source, gate, and drain. In this solution, the drains of the two MOSFETs are eliminated, and the two MOSFETs are symmetrically arranged up and down to share an epitaxial layer, while the sources and gates of the two symmetrical MOSFETs are retained, and the gates of the two symmetrical MOSFETs are controlled separately, thereby turning on the two symmetrical MOSFETs at the same time.

[0028] Integrating two symmetrical MOSFETs into one device can save the circuit board space occupied by the MOSFETs. Setting the two MOSFETs symmetrically up and down can improve the chip area utilization. Compared with setting the two MOSFETs symmetrically left and right, the cell size of the device is smaller and a higher current density is obtained.

[0029] Furthermore, a first ILD interlayer dielectric layer 11 is formed above the first N+ active layer 9 , and a second ILD interlayer dielectric layer 12 is formed below the second N+ active layer 10 , for reducing the parasitic capacitance of the MOSFET.

[0030] Furthermore, the first ILD interlayer dielectric layer 11 and the second ILD interlayer dielectric layer 12 have the same thickness, and the thickness of the first ILD interlayer dielectric layer 11 and the second ILD interlayer dielectric layer 12 is 0.3-1 um.

[0031] Furthermore, a first metal layer 13 is formed above the first ILD interlayer dielectric layer 11 , and a second metal layer 14 is formed below the second ILD interlayer dielectric layer 12 for externally connecting current.

[0032] Furthermore, the first metal layer 13 and the second metal layer 14 have the same thickness, and the thickness of the first metal layer 13 and the second metal layer 14 is 3-10 um.

[0033] In this embodiment, since the substrates of the two MOSFETs are directly short-circuited together, no additional potential connection is required, and therefore no additional drain is required. The first metal layer 13 can be used as the drain corresponding to the second source and the second gate, and the second metal layer 14 can be used as the drain corresponding to the first source and the first gate. After the first metal layer and the second metal layer simultaneously obtain current from the outside, they flow to the first gate and the second gate through the first ILD interlayer dielectric layer and the second ILD interlayer dielectric layer respectively. The first metal layer and the second metal layer are drains to each other, thereby turning on two symmetrical MOSFETs at the same time. If only one metal layer obtains current, the device cannot be turned on, ensuring the bidirectional switch function of the device.

[0034] Furthermore, the thickness of the N-epitaxial layer 1 is 5-50 um; the distance between the first trench group 2 and the second trench group 3 in the N-epitaxial layer is 2-30 um.

[0035] Furthermore, the first P-well layer 7 and the second P-well layer 8 have the same thickness, and the thickness of the first P-well layer 7 and the second P-well layer 8 is 0.6-1.5 um.

[0036] In this embodiment, the distance between the two trench groups (ie, the thickness of the N-epitaxial layer) needs to be set according to the required breakdown voltage of the device. The higher the required breakdown voltage, the thicker the thickness of the N-epitaxial layer.

[0037] The above descriptions are only some embodiments of the present invention, and do not limit the protection scope of the present invention. Any equivalent device or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly used in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. An integrated bidirectional switch MOSFET, characterized in that: include: An N-epitaxial layer, a first trench group formed on an upper portion of the N-epitaxial layer, and a second trench group formed on a lower portion of the N-epitaxial layer; The first trench group and the second trench group are symmetrically arranged along the horizontal center axis of the N-epitaxial layer, the first trench group and the second trench group respectively include a plurality of identical strip trenches, a gate oxide layer is grown in the strip trenches, a gate polycrystalline is deposited in the gate oxide layer, the gate polycrystalline in the strip trenches in the first trench group forms a first gate of the MOSFET, and the gate polycrystalline in the strip trenches in the second trench group forms a second gate of the MOSFET; A first P well layer is formed on the upper part of the N-epitaxial layer outside the first trench group, and a second P well layer is formed on the upper part of the N-epitaxial layer inside the second trench group; a first N+ active layer is formed on the upper part of the first P well layer, and the first N+ active layer is short-circuited with the gate polycrystalline in the first trench group to form a first source of the MOSFET; A second N+ active layer is formed under the second P-well layer. The second N+ active layer is short-circuited with the gate polycrystalline in the second trench group to form a second source of the MOSFET. The first source and the second source form a bidirectional switch of the MOSFET.

2. An integrated bidirectional switch MOSFET according to claim 1, characterized in that: A first ILD interlayer dielectric layer is formed above the first N+ active layer, and a second ILD interlayer dielectric layer is formed below the second N+ active layer, for reducing the parasitic capacitance of the MOSFET.

3. An integrated bidirectional switch MOSFET according to claim 2, characterized in that: The first ILD interlayer dielectric layer and the second ILD interlayer dielectric layer have the same thickness, and the thickness of the first ILD interlayer dielectric layer and the second ILD interlayer dielectric layer is 0.3-1 um.

4. The integrated bidirectional switch MOSFET according to claim 2, characterized in that: A first metal layer is formed above the first ILD interlayer dielectric layer, and a second metal layer is formed below the second ILD interlayer dielectric layer for externally connecting current.

5. The integrated bidirectional switch MOSFET according to claim 4, characterized in that: The first metal layer and the second metal layer have the same thickness, and the thickness of the first metal layer and the second metal layer is 3-10 um.

6. The integrated bidirectional switch MOSFET according to claim 1, characterized in that: The thickness of the N-epitaxial layer is 5-50 um; the distance between the first trench group and the second trench group in the N-epitaxial layer is 2-30 um.

7. The integrated bidirectional switch MOSFET according to claim 1, characterized in that: The first P-well layer and the second P-well layer have the same thickness, and the thickness of the first P-well layer and the second P-well layer is 0.6-1.5 um.

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