Semiconductor device

Abstract

The invention provides a semiconductor device which comprises an N + substrate, an N-epitaxial layer and a plurality of gate trenches, the N-epitaxial layer comprises a plurality of P + buried layers and a plurality of first N + regions, the first N + regions are alternately clamped in the middle of the N-epitaxial layer, the thickness of each first N + region is larger than that of each P + buried layer, and the thickness of each first N + region is larger than that of each P + buried layer. The two sides, close to the N + substrate and away from the N + substrate, of the first N + region protrude out of the P + buried layer; the plurality of first P + regions and the plurality of second N + regions are alternately arranged on one side, far away from the N + substrate, of the P well region; an opening of each gate trench penetrates through one side, far away from the N + substrate, of the P well region and is located on the N-epitaxial layer between the P well region and the N + substrate, and each second N + region is arranged on the outer side of the corresponding gate trench in a surrounding manner. According to the invention, the gate oxide is protected, the JFET region introduced into the device by the P-type region is reduced, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices, and in particular relates to a semiconductor device. Background Art

[0002] Trench MOSFET is an improved metal oxide semiconductor field effect transistor (MOSFET), whose structure and manufacturing process are different from those of traditional planar MOSFET. Trench MOSFET forms a vertical trench in the semiconductor material (usually silicon) and embeds the gate in the trench to increase the effective gate area, thereby improving the performance of the device. At present, due to the limitation of the neck resistance of JFET (junction field effect transistor), it is difficult to reduce the unit area on-resistance to 2mΩ·cm by reducing the lithography size of planar MOSFET devices. 2 The following. Trench MOSFET transfers the conductive channel from the horizontal crystal plane to the vertical crystal plane with higher surface electron mobility, and eliminates the JFET (junction field effect transistor) area, making the device's on-resistance lower and reducing conduction losses. Therefore, trench MOSFET has a higher cell density, extremely low parasitic inductance, and faster switching speed.

[0003] However, in order to protect the gate oxide, the trench MOSFET needs to add a P-type region in the design, so as to shield the electric field away from the trench when the device is reversely withstand voltage, reducing the electric field in the gate oxide, but the P-type region will introduce a JFET region into the device, resulting in an increase in the on-resistance of the device. Summary of the invention

[0004] In view of this, the present invention provides a semiconductor device, which has a good protective effect on gate oxide, reduces the JFET region introduced by the P-type region in the device, and reduces the on-resistance of the device.

[0005] In order to achieve the above object, the present invention adopts the following technical solutions: The present invention provides a semiconductor device, comprising a drain electrode, an N+ substrate, an N-epitaxial layer and a plurality of gate trenches, wherein the N+ substrate is laid on one side of the drain electrode; the N-epitaxial layer is laid on the side of the N+ substrate away from the drain electrode, the N-epitaxial layer comprises: a plurality of P+ buried layers and a plurality of first N+ regions, a P well region, a plurality of first P+ regions and a plurality of second N+ regions, the plurality of P+ buried layers and the plurality of first N+ regions are alternately sandwiched in the middle of the N-epitaxial layer, the thickness of each first N+ region is greater than the thickness of each P+ buried layer, and the first N+ region is protruded from the P+ buried layer on both sides close to the N+ substrate and away from the N+ substrate; the P The well region is located on a side of the N-epitaxial layer away from the N+ substrate; a plurality of first P+ regions and a plurality of second N+ regions are alternately arranged on a side of the P-well region away from the N+ substrate, and the plurality of first P+ regions correspond to and are relatively arranged with the plurality of first N+ regions one by one; the plurality of gate trenches correspond to the plurality of second N+ regions one by one, the opening of each gate trench passes through the side of the P-well region away from the N+ substrate, the bottom passes through the P-well region, and is located on the N-epitaxial layer between the P-well region and the N+ substrate, each second N+ region is surrounded on the outside of the corresponding gate trench, a gate is formed in the gate trench, and a source is formed on the side of the P-well region away from the N+ substrate.

[0006] Preferably, the inner sidewall of the gate trench is provided with at least one step along the height direction.

[0007] Preferably, the bottom of the gate trench is located between the P-well region and the P+ buried layer.

[0008] Preferably, the bottom of the gate trench contacts a side of the P+ buried layer away from the N+ substrate.

[0009] Preferably, the bottom of the gate trench is located on a side of the P+ buried layer away from the N+ substrate.

[0010] Preferably, a P-type shielding layer is provided at the outer bottom of the gate trench to protect the gate oxide of the gate trench.

[0011] Preferably, a cross section of the first N+ region parallel to the N+ substrate is rectangular, rhombus, circular or polygonal.

[0012] Preferably, the length direction of each gate trench parallel to the N+ substrate is the first direction, and the direction perpendicular to the length of the gate trench is the second direction; a plurality of second P+ regions are arranged at intervals along the first direction on the side of the N-epitaxial layer away from the N+ substrate, and each second P+ region is arranged along the second direction, and the second P+ region is used to isolate each first P+ region, each second N+ region and each first N+ region, and the P+ buried layer is connected to the source through the isolation part.

[0013] Preferably, the second P+ region is connected to the P+ buried layer through two adjacent gate trenches.

[0014] Preferably, the second P+ region is connected to the P+ buried layer, the corresponding gate trench and the source in sequence.

[0015] Compared with the prior art, the present invention has the following beneficial effects: (1) The present invention uses N-type ion implantation to construct multiple first N+ regions (first N-enrich regions) to form current paths in the multiple P+ buried layers. The second N+ regions are arranged on both sides of the gate trench, and the first N+ regions are far away from the bottom and corners of the gate trench. When the device withstands reverse voltage, the strong electric field is shielded by the P+ buried layer and the P well region above the first N+ region (first N-enrich region), which plays a good protective role on the gate oxide. Therefore, the gate oxide electric field strength is insensitive to the ion doping concentration and opening size of the first N-enrich region, thereby reducing the JFET region introduced by the P-type region in the device and reducing the on-resistance of the device.

[0016] (2) The N-epitaxial layer of the present invention has an NPN structure, that is, the P+ buried layer is deeply buried in the N-epitaxial layer, achieving a good gate oxide protection effect without the need for high-energy P-type ion implantation, thereby solving the problem of limited P-type ion implantation depth in SiC.

[0017] (3) The present invention forms a gate trench structure with at least one step by etching, and at the same time, by providing multiple second P+ regions spaced apart along the first direction on the side of the N-epitaxial layer away from the N+ substrate, the P+ buried layer is connected to the source electrode, thereby avoiding high-energy ion injection and reducing damage to the material. In addition, when the device is dynamically switched, the P+ buried layer has sufficient holes for replenishment, avoiding the charge accumulation effect of the floating P region, and reducing the conduction loss of the device. Since multiple second P+ regions are spaced apart along the second direction, the second P+ region accounts for a very small proportion in a single cell of the device, thereby greatly reducing the cell size of the device and improving the overall current density.

[0018] (4) The present invention provides a plurality of second P+ regions spaced apart in a second direction on one side of the N-epitaxial layer away from the N+ substrate, so that all the second P+ regions on the entire device are interconnected to form a mesh structure. The JFET structure formed by the first N-enrich region and the P+ buried layer is grounded through the second P+ region of the gate. Under a large surge voltage, the depletion regions on both sides of the P+ buried layer can be automatically expanded to increase the on-resistance of the JFET region, which is equivalent to a buffer circuit structure that suppresses surge spikes by itself. At the same time, when the surge voltage is too large, the depletion regions on both sides of the P+ buried layer continue to expand and overlap with each other, playing a blocking effect, protecting the internal trench gate oxide, and playing a certain role in spike voltage overvoltage protection, which can increase the device's self-suppression resistance to surge voltage and overvoltage, and avoid device damage and reliability reduction caused by the actual delay of the overvoltage protection circuit and the overcurrent protection circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 A schematic diagram of the structure of a semiconductor device provided by an embodiment of the present invention; Figure 2 for Figure 1 A cross-sectional view of an embodiment in which the interior of the gate trench is stepped; Figure 3 for Figure 1 A cross-sectional view of an embodiment in which there is no step inside the gate trench; Figure 4 for Figure 1 Section B is a cross-sectional view of two embodiments; Figure 5 for Figure 1 Sectional views of three cases of section A; Figure 6 for Figure 1 A cross-sectional view of an embodiment of a gate trench bottom provided with a P-type shielding layer in section A; Figure 7 for Figure 1 Schematic diagram of TCAD simulation results of the device.

[0020] Figure numerals: semiconductor device 100, drain electrode 1, N+ substrate 2, N- epitaxial layer 3, P+ buried layer 31, first N+ region 32, P well region 33, first P+ region 34, second N+ region 35, second P+ region 36, gate trench 4, gate 5, source 6, P-type shielding layer 7. DETAILED DESCRIPTION

[0021] The present invention is further described in detail below in conjunction with specific embodiments so that those skilled in the art can understand the present invention more clearly.

[0022] Combined with Figure 1-6 As shown, the present invention provides a semiconductor device 100, including a drain electrode 1, an N+ substrate 2, an N-epitaxial layer 3 and a plurality of gate trenches 4, wherein the N+ substrate 2 is laid on one side of the drain electrode 1; the N-epitaxial layer 3 is laid on the side of the N+ substrate 2 away from the drain electrode 1, the N-epitaxial layer 3 includes: a plurality of P+ buried layers 31 and a plurality of first N+ regions 32, a P well region 33, a plurality of first P+ regions 34 and a plurality of second N+ regions 35, a plurality of P+ buried layers 31 and a plurality of first N+ regions 32 are alternately sandwiched in the middle of the N-epitaxial layer 3, a thickness of each first N+ region 32 is greater than a thickness of each P+ buried layer 31, and both sides of the first N+ region 32 close to the N+ substrate 2 and away from the N+ substrate 2 are protruded from the P+ buried layer 31; The P-well region 33 is located on the side of the N-epitaxial layer 3 away from the N+ substrate 2; a plurality of first P+ regions 34 and a plurality of second N+ regions 35 are alternately arranged on the side of the P-well region 33 away from the N+ substrate 2, and the plurality of first P+ regions 34 correspond to the plurality of first N+ regions 32 one by one and are arranged relatively; the plurality of gate trenches 4 correspond to the plurality of second N+ regions 35 one by one, and the opening of each gate trench 4 passes through the side of the P-well region 33 away from the N+ substrate 2, and the bottom passes through the P-well region 33, and is located on the N-epitaxial layer 3 between the P-well region 33 and the N+ substrate 2, and each second N+ region 35 is surrounded by the outer side of the corresponding gate trench 4, a gate 5 is formed in the gate trench 4, and a source 6 is formed on the side of the P-well region 33 away from the N+ substrate 2.

[0023] In the above technical solution, the drain electrode 1 refers to an electrode made of metal or other conductive material, which is used to contact the semiconductor material and extract current from the device. The specific function and location of the drain electrode 1 depend on the device type, but they are usually found in field effect transistors (FETs) and certain other semiconductor devices. The N+ substrate 2 refers to a semiconductor material with highly doped N-type impurities used in semiconductor devices. Here, "N" indicates that the material is an N-type semiconductor, which means that it conducts electricity mainly through electrons (negative charge carriers), while "+" indicates a high doping level, which means that the doping concentration is high. The N- epitaxial layer 3 is a layer of lightly doped N-type semiconductor material deposited on the surface of the substrate during the manufacture of semiconductor devices. The epitaxial layer is usually formed by an epitaxial growth process (such as chemical vapor deposition, CVD) and has a lower doping concentration than the substrate material. The P+ buried layer refers to a layer of highly doped P-type semiconductor region in a semiconductor device, which is usually located below or alternately formed with the N-type epitaxial layer. The doping concentration of this layer is very high, so it is represented by "P+". It has a specific and important use in the design and manufacture of semiconductor devices. N+ region (N-enrich region) refers to a highly doped N-type semiconductor region in a semiconductor device. In this type of region, the concentration of N-type dopants (such as phosphorus and arsenic) is very high, so that the concentration of free electrons (negative charge carriers) is also high.

[0024] Exemplarily, a direction parallel to the ground is regarded as the X direction, the direction vertical and perpendicular to the X direction is the Y direction, and the direction perpendicular to the X direction and the Y direction is the Z direction. The multiple P+ buried layers 31 and the multiple first N+ regions 32 are alternately arranged along the X direction and are located in the middle of the N-epitaxial layer 3. In the Y direction, the thickness of the first N+ region 32 is greater than the thickness of each P+ buried layer 31, and the first N+ region 32 protrudes from the P+ buried layer 31 on both sides. Multiple first P+ regions 34 and multiple second N+ regions 35 are alternately arranged along the X direction on the side of the P well region 33 away from the N+ substrate 2. Figure 1 As shown, each first P+ region 34 is disposed opposite to the corresponding first N+ region 32 in the Y direction, and each second N+ region 35 is disposed opposite to the corresponding P+ buried layer 31 in the Y direction. Each gate trench 4 corresponds to a second N+ region 35 .

[0025] The present invention uses N-type ion implantation to construct multiple first N+ regions 32 (first N-enrich regions) to form a current path in the multiple P+ buried layers 31, and the second N+ region 35 is surrounded on both sides of the gate trench 4, and the first N+ region 32 is far away from the bottom and corner of the gate trench 4. When the device is reversely withstand voltage, the strong electric field is shielded by the P+ buried layer 31 and the P well region 33 above the first N+ region 32 (first N-enrich region), which plays a good protective role on the gate oxide. Therefore, the gate oxide electric field strength is insensitive to the ion doping concentration and opening size of the first N-enrich region, thereby reducing the JFET region introduced by the P-type region in the device and reducing the on-resistance of the device. The N-epitaxial layer 3 of the present invention is an NPN structure, that is, the P+ buried layer 31 is deeply buried in the N-epitaxial layer 3, and a good gate oxide protection effect is achieved without the need for high-energy P-type ion implantation, which solves the problem of limited P-type ion implantation depth in the N-epitaxial layer 3.

[0026] It should be noted that if Figure 1 As shown, the width of the P+ buried layer 31 between the two first N+ regions 32 (N-enrich) is greater than the width of the gate trench 4 .

[0027] In some embodiments, the specific shape of the gate trench 4 is not limited. Figure 3 As shown, the inner sidewall of the gate trench 4 can be a smooth sidewall without steps.

[0028] like Figure 2 As shown, in some embodiments, the inner sidewall of the gate trench 4 is provided with at least one step along the height direction (Y direction in the figure), and the at least one step can be one step, two steps, three steps, etc.

[0029] like Figure 5 As shown, A, B, and C in the figure are three different states of the gate trench 4, in which A shows that the bottom of the gate trench 4 is located between the P well region 33 and the P+ buried layer 31, B shows that the bottom of the gate trench 4 is in contact with the side of the P+ buried layer 31 away from the N+ substrate 2, and C shows that the bottom of the gate trench 4 is located on the side of the P+ buried layer 31 away from the N+ substrate 2. These three shapes of the gate trench 4 are all acceptable, wherein the more the gate trench 4 contacts the P+ buried layer 31, the stronger the gate oxide protection capability of the corner of the gate trench 4 is.

[0030] like Figure 6 As shown, in some embodiments, a P-type shielding layer 7 is provided at the outer bottom of the gate trench 4 to protect the gate oxide of the gate trench 4 .

[0031] Furthermore, the cross section of the first N+ region 32 parallel to the N+ substrate 2 (the cross section along the X direction) is rectangular, rhombus, circular or polygonal. The layout of the first N+ region 32 can be of different shapes or a combination of different shapes. In a specific embodiment, the area ratio and shape of the first N+ region 32 can be designed in combination with specific needs, and the on-resistance and surge and short-circuit resistance can be adjusted to make the design of the device more flexible.

[0032] like Figure 1 As shown, further, the length direction of each gate trench 4 parallel to the N+ substrate 2 is the first direction (the above-mentioned Z direction), and the direction perpendicular to the length of the gate trench 4 is the second direction (the above-mentioned X direction); a plurality of second P+ regions 36 are arranged at intervals along the first direction (the above-mentioned Z direction) on the side of the N- epitaxial layer 3 away from the N+ substrate 2, and each second P+ region 36 is arranged along the second direction (the above-mentioned X direction), and the second P+ region 36 is used to isolate each first P+ region 34, each second N+ region 35 and each first N+ region 32, and the P+ buried layer 31 is connected to the source 6 through the isolation part.

[0033] Further, in some embodiments, the present invention forms a gate trench 4 structure with at least one step by etching, and at the same time, by providing multiple second P+ regions 36 at intervals along the first direction on the side of the N-epitaxial layer 3 away from the N+ substrate 2, the P+ buried layer 31 is connected to the source 6, thereby avoiding high-energy ion injection and reducing damage to the material. In addition, when the device is dynamically switched, the P+ buried layer 31 has sufficient holes to be supplemented, avoiding the charge accumulation effect of the floating P region, and reducing the conduction loss of the device. Since the second P+ regions 36 are multiple and arranged at intervals along the second direction, the second P+ regions 36 account for a very small proportion in a single cell of the device, thereby greatly reducing the cell size of the device and improving the overall current density. The present invention provides multiple second P+ regions 36 at intervals along the second direction on the side of the N-epitaxial layer 3 away from the N+ substrate 2, so that all the second P+ regions 36 on the entire device are interconnected to form a mesh structure. The JFET structure formed by the first N-enrich region and the P+ buried layer 31 is grounded through the second P+ region 36 of the gate 5. Under a large surge voltage, the depletion regions on both sides of the first N+ region 32 can be automatically expanded to increase the on-resistance of the JFET region, which is equivalent to a buffer circuit structure that suppresses surge spikes by itself. At the same time, when the surge voltage is too large, the depletion regions on both sides of the first N+ region 32 continue to expand and overlap each other, playing a blocking effect, protecting the internal trench gate oxide, and playing a certain role in spike voltage overvoltage protection, which can increase the device's self-suppression resistance to surge voltage and overvoltage, and avoid device damage and reliability reduction caused by the actual delay of the overvoltage protection circuit and the overcurrent protection circuit.

[0034] Furthermore, if Figure 4 As shown, there are two different schematic diagrams of cross section B, one of which is that the second P+ region 36 is connected to the P+ buried layer 31 through two adjacent gate trenches 4, and the other is that the entire P+ buried layer 31 is connected to the source 6. In some embodiments, the second P+ region 36 is connected to the P+ buried layer 31, the corresponding gate trench 4 and the source 6 in sequence. Among them, the whole piece is grounded for a better effect.

[0035] Exemplarily, the present invention provides a method for manufacturing a semiconductor device 100, comprising the following steps: S1, growing an NPN epitaxial layer on an N+ substrate 2; S2, forming a first N+ region 32 by photolithography and ion implantation; S3, retaining the hard mask of the ion implantation of the first N+ region 32, and forming the first P+ region 34 by ion implantation; S4, removing the hard mask, and forming the second N+ region 35 and the P well region 33 by photolithography and ion implantation; S5, dry etching to form gate trenches 4 (wherein each trench has at least one step inside); S6. On the cross section B, a second P+ region 36 is formed by ion implantation, so that the P+ buried layer 31 is connected to the source 6; S7, gate dielectric and gate polysilicon growth and etching; S8, source electrode 6 deposition and etching, drain electrode 1 deposition.

[0036] The device prepared by this method was subjected to TCAD simulation experiment, and the obtained TCAD simulation schematic diagram is shown as follows: Figure 7 As shown in the figure, when the device is subjected to a high voltage of 1200V, the maximum electric field strength in the gate oxide is less than 2.2MV / cm, and most of the electric field is shielded by the P+ buried layer 31 and the P well region 33 above the first N-enrich region. When the device is forward-conducted, due to the large ion doping concentration and opening size design values ​​of the first N-enrich region, the current can be well conducted through the first N-enrich region, and the device specific on-resistance obtained by simulation is less than 2mΩ•cm 2 , which is much lower than the existing trench MOSFET in the industry.

[0037] The specific raw materials not described in the present invention are all existing materials and can be directly purchased from the market.

[0038] The above are only preferred embodiments of the present invention and are not intended to limit the protection scope of the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

Claims

1. A semiconductor device, characterized in that: include: Drain electrode; An N+ substrate is disposed on one side of the drain electrode; An N-epitaxial layer is disposed on a side of the N+ substrate away from the drain electrode, and the N-epitaxial layer includes: A plurality of P+ buried layers and a plurality of first N+ regions are alternately sandwiched in the middle of the N-epitaxial layer, the thickness of each first N+ region is greater than the thickness of each P+ buried layer, and the first N+ region is protruded from the P+ buried layer on both sides close to the N+ substrate and away from the N+ substrate; A P-well region, located on a side of the N- epitaxial layer away from the N+ substrate; A plurality of first P+ regions and a plurality of second N+ regions are alternately arranged on a side of the P-well region away from the N+ substrate, and the plurality of first P+ regions correspond to the plurality of first N+ regions one by one and are arranged relatively; A plurality of gate trenches are arranged one by one corresponding to the plurality of second N+ regions, the opening of each gate trench passes through the side of the P-well region away from the N+ substrate, the bottom passes through the P-well region, and is located on the N-epitaxial layer between the P-well region and the N+ substrate, each second N+ region is surrounded by the outer side of the corresponding gate trench, a gate is formed in the gate trench, and a source is formed on the side of the P-well region away from the N+ substrate.

2. A semiconductor device according to claim 1, characterized in that: The inner sidewall of the gate trench is provided with at least one step along the height direction.

3. A semiconductor device according to claim 1, characterized in that: The bottom of the gate trench is located between the P well region and the P+ buried layer.

4. A semiconductor device according to claim 1, characterized in that: The bottom of the gate trench contacts a side of the P+ buried layer away from the N+ substrate.

5. A semiconductor device according to claim 1, characterized in that: The bottom of the gate trench is located at a side of the P+ buried layer away from the N+ substrate.

6. A semiconductor device according to claim 1, characterized in that: A P-type shielding layer is provided at the outer bottom of the gate trench to protect the gate oxide of the gate trench.

7. A semiconductor device according to claim 1, characterized in that: A cross section of the first N+ region parallel to the N+ substrate is rectangular, diamond, circular or polygonal.

8. A semiconductor device according to claim 1, characterized in that: The length direction of each gate trench parallel to the N+ substrate is a first direction, and the direction perpendicular to the length of the gate trench is a second direction; A plurality of second P+ regions are arranged at intervals along the first direction on one side of the N-epitaxial layer away from the N+ substrate, and each second P+ region is arranged along the second direction. The second P+ region is used to isolate each first P+ region, each second N+ region and each first N+ region, and the P+ buried layer is connected to the source through the isolation part.

9. A semiconductor device according to claim 8, characterized in that: The second P+ region is connected to the P+ buried layer through two adjacent gate trenches.

10. A semiconductor device according to claim 8, characterized in that: The second P+ region is connected to the P+ buried layer, the corresponding gate trench and the source in sequence.

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