Low-on-resistance discrete device and preparation method thereof

Abstract

The invention discloses a low-on-resistance discrete device and a preparation method thereof, which are applied to the field of semiconductor manufacturing, and the device comprises an epitaxial function layer, one side of which is provided with an interlayer dielectric layer; a groove structure functional area is arranged in the epitaxial functional layer and is positioned on one side, close to the epitaxial functional layer, of the interlayer dielectric layer; a through hole for exposing the epitaxial function layer is formed in the interlayer dielectric layer, and the conductive contact structure passes through the through hole and extends into the epitaxial function layer; the conductive contact structures are located on the two sides in the epitaxial function layer and the outer sides of the ends, doped regions making contact with the conductive contact structures are formed on the conductive contact structures, at least part of the surfaces of the doped regions are exposed out of the through holes, and the exposed surfaces of the doped regions form step structures; the top mesa of the step structure is in contact with the conductive contact structure. According to the invention, at least part of the surface of the doped region is exposed by arranging the through hole, so that the contact area of the conductive contact structure and the doped region is increased, and the on-resistance of the device is reduced.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor manufacturing, and in particular to a low on-resistance discrete device and a method for preparing the low on-resistance discrete device. Background Art

[0002] Existing discrete devices are faced with the problem that on-resistance affects the overall efficiency of the device and limits the application scope of the device. In order to pursue higher device performance and reliability and reduce the on-resistance of the device during operation, the on-resistance of discrete devices has been improved by thinning the thickness of the wafer and adjusting the doping concentration of ion implantation. However, the methods of thinning the thickness of the wafer or adjusting the ion doping concentration in the device are limited.

[0003] Therefore, how to provide a structure that can further reduce the on-resistance when the original method of thinning the wafer thickness and the method of adjusting the ion doping concentration in the device are limited is a technical problem that technical personnel in this field urgently need to solve. Summary of the invention

[0004] In view of this, the purpose of the present invention is to provide a low on-resistance discrete device and a method for preparing a low on-resistance discrete device, which solves the problem of improving the on-resistance limitation of discrete devices by thinning the thickness of the wafer and adjusting the doping concentration of ion implantation in the prior art.

[0005] In order to solve the above technical problems, the present invention provides a low on-resistance discrete device, comprising:

[0006] An epitaxial functional layer, wherein an interlayer dielectric layer is disposed on one side of the epitaxial functional layer;

[0007] A groove structure functional area is arranged in the epitaxial functional layer and located on a side of the interlayer dielectric layer close to the epitaxial functional layer;

[0008] The interlayer dielectric layer is formed with a through hole exposing the epitaxial functional layer, and the conductive contact structure passes through the through hole and extends into the epitaxial functional layer;

[0009] The conductive contact structure is located on both sides of the epitaxial functional layer, and the outer side of the end portion located in the epitaxial functional layer is formed with a doped region in contact with the conductive contact structure, the through hole exposes at least part of the surface of the doped region, and the exposed surface of the doped region forms a step structure;

[0010] A top terrace of the step structure contacts the conductive contact structure.

[0011] Optionally, the through hole exposes the entire surface of the doped region, and the exposed surface of the doped region forms a step structure.

[0012] Optionally, an isolation layer is provided on a side of the interlayer dielectric layer close to the epitaxial functional layer.

[0013] Optionally, the trench structure functional region includes a source functional region and a gate functional region.

[0014] Optionally, the doped region includes an N-type sub-doped region and a P-type sub-doped region.

[0015] The present invention also provides a method for preparing a low on-resistance discrete device, comprising:

[0016] A discrete device preform is provided; the discrete device preform comprises an epitaxial functional layer, an interlayer dielectric layer is arranged on one side of the epitaxial functional layer, a groove structure functional region is arranged in the epitaxial functional layer and on a side of the interlayer dielectric layer close to the epitaxial functional layer, and a first sub-doping region is arranged next to the groove structure functional region;

[0017] preparing a through hole in the interlayer dielectric layer to expose the first sub-doped region;

[0018] A sidewall protection layer is prepared on the sidewall of the through hole as a temporary through hole; the temporary through hole exposes a portion of the first sub-doped region;

[0019] Etching the exposed first sub-doped region along the temporary through hole to expose an undoped region in the epitaxial functional layer as a region to be doped;

[0020] Removing the sidewall protection layer, and performing doping treatment on the area to be doped to form a second sub-doping area, thereby obtaining a discrete device to be filled;

[0021] In the discrete device to be filled, a conductive contact structure is prepared that contacts both the exposed surface of the first sub-doping region and the exposed surface of the second sub-doping region; at least a portion of the surface of the top of the first sub-doping region is exposed, and the exposed surface of the first sub-doping region forms a step structure with the exposed surface of the second sub-doping region, and the top table of the step structure contacts the conductive contact structure.

[0022] Optionally, preparing a through hole in the interlayer dielectric layer to expose the first sub-doped region includes:

[0023] The through hole is prepared in the interlayer dielectric layer to expose the entire first sub-doping region.

[0024] Optionally, a sidewall protection layer is prepared on the sidewall of the through hole as a temporary through hole, comprising:

[0025] Preparing a protective layer on the surface of the discrete device preform having the through hole prepared in the interlayer dielectric layer;

[0026] The protective layer is etched by a sidewall etching process, and only the protective layer remains on the sidewall of the through hole as the sidewall protective layer, thereby obtaining the temporary through hole.

[0027] Optionally, the sidewall protection layer is a tetraethoxysilane protection layer.

[0028] Optionally, removing the sidewall protection layer includes:

[0029] The sidewall protection layer is removed, and an arc-shaped chamfered structure is fabricated at the top corner of the interlayer dielectric layer.

[0030] It can be seen that the low on-resistance discrete device provided by the present invention includes an epitaxial functional layer, an interlayer dielectric layer is arranged on one side of the epitaxial functional layer; a groove structure functional area is arranged in the epitaxial functional layer and located on the side of the interlayer dielectric layer close to the epitaxial functional layer; a through hole is formed in the interlayer dielectric layer to expose the epitaxial functional layer, and the conductive contact structure passes through the through hole and extends into the epitaxial functional layer; the conductive contact structure is located on both sides of the epitaxial functional layer and the outer side of the end portion located in the epitaxial functional layer, and both are formed with a doped region in contact with the conductive contact structure, the through hole exposes at least part of the surface of the doped region, and the exposed surface of the doped region forms a step structure; the top table of the step structure is in contact with the conductive contact structure. The present invention exposes at least part of the surface of the doped region by setting a through hole, and the exposed surface of the doped region forms a step structure, that is, the through hole exposes at least part of the top surface of the doped region, and the top surface forms the top table of the step structure, and by increasing the contact between the top table and the conductive contact structure, the contact area between the conductive contact structure and the doped region is increased, thereby reducing the on-resistance of the device.

[0031] In addition, the present invention also provides a method for preparing a low on-resistance discrete device, which also has the above-mentioned beneficial effects. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying creative work.

[0033] Figure 1 It is a structural schematic diagram of an existing low on-resistance discrete device;

[0034] Figure 2A schematic structural diagram of a low on-resistance discrete device provided by an embodiment of the present invention;

[0035] Figure 3 A flow chart of a method for preparing a low on-resistance discrete device provided by an embodiment of the present invention;

[0036] Figures 4 to 10 An example flow chart of a method for preparing a low on-resistance discrete device provided by an embodiment of the present invention;

[0037] Figure 1 to Figure 2 ,as well as Figures 4 to 10 In the figure, the reference numerals are described as follows:

[0038] 1-top table of the step structure, 10-epitaxial functional layer, 11-groove structure functional area, 12-doping area, 121-first sub-doping area, 122-second sub-doping area, 20-interlayer dielectric layer, 21-isolation layer, 30-conductive contact structure, 31-existing conductive contact structure, 40-through hole, 41-temporary through hole, 50-protective layer, 51-sidewall protection layer. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0040] Existing discrete devices face the problem that on-resistance affects the overall efficiency of the device and limits the application scope of the device. In order to pursue higher device performance and reliability, it is necessary to reduce the on-resistance of the device during operation. There are two main ways to reduce the on-resistance of the device during operation:

[0041] 1. Reduce the thickness of the wafer;

[0042] 2. Adjust the doping concentration of ion implantation;

[0043] However, no matter whether the above-mentioned method of thinning the wafer thickness or adjusting the ion doping concentration in the device is adopted, there is a limit to the continuous improvement. Therefore, it is necessary to implement a method other than the above-mentioned method 1 and method 2 to reduce the on-resistance of the device during operation in order to meet the needs of the continuous development of discrete device performance. Please refer to Figure 1 , Figure 1 The figure is a schematic diagram of the structure of an existing low on-resistance discrete device.

[0044] The present invention exposes at least part of the surface of the doped region by setting a through hole, and the exposed surface of the doped region forms a step structure, that is, the through hole exposes at least part of the top surface of the doped region, and the top surface forms the top table of the step structure. By increasing the contact between the top table and the conductive contact structure, the contact area between the conductive contact structure and the doped region is increased, thereby reducing the on-resistance of the device. Please refer to the following embodiments for details:

[0045] Please refer to Figure 2 , Figure 2 A schematic diagram of a low on-resistance discrete device provided by an embodiment of the present invention. The device may include:

[0046] An epitaxial functional layer 10, with an interlayer dielectric layer 20 disposed on one side of the epitaxial functional layer 10;

[0047] A groove structure functional area 11 is arranged in the epitaxial functional layer 10 and located on a side of the interlayer dielectric layer 20 close to the epitaxial functional layer 10;

[0048] The interlayer dielectric layer 20 is formed with a through hole exposing the epitaxial functional layer 10 , and the conductive contact structure 30 passes through the through hole and extends into the epitaxial functional layer 10 ;

[0049] The conductive contact structure 30 is located on both sides of the epitaxial functional layer 10, and the outer side of the end portion of the epitaxial functional layer 10 is formed with a doped region 12 in contact with the conductive contact structure 30, and the through hole exposes at least part of the surface of the doped region 12, and the exposed surface of the doped region 12 forms a step structure;

[0050] The top mesa 1 of the step structure is in contact with the conductive contact structure 30 .

[0051] In this embodiment, the epitaxial functional layer 10 is generally formed by growth on the substrate surface, and the interlayer electrolyte layer provided on one side of the epitaxial functional layer 10 is used to protect the epitaxial functional layer 10, prevent the external conductive contact structure 30 from being in full contact with the epitaxial functional layer 10, and ensure the functionality of the device. In this embodiment, the groove structure functional area 11 located in the epitaxial functional layer 10 is a side of the epitaxial functional layer 10 close to the interlayer dielectric layer 20, and a groove structure is opened inward along the side facing away from the interlayer dielectric layer 20, and the functional area material is deposited in the groove structure to form the groove structure functional area 11. In this embodiment, the region between the groove structure functional regions 11 is generally provided with a doping region 12 conductively connected to the conductive contact structure 30. It should be specifically explained that in this embodiment, a through hole is provided in the interlayer dielectric layer 20, and a conductive contact structure 30 is provided through the through hole and partially extends to the inside of the epitaxial functional layer 10. At this time, both sides of the conductive contact structure 30 extending into the epitaxial functional layer 10 and the end of the conductive contact structure 30 extending into the epitaxial functional layer 10 are provided with a doping region 12 in contact with the conductive contact structure 30. In a general preparation scenario, the interlayer dielectric layer 20 is generally prepared on the upper side of the epitaxial functional layer 10, and the groove structure functional region 11 is prepared downward along the upper surface of the epitaxial functional layer 10. Further, both sides and the lower part of the conductive contact structure 30 extending into the epitaxial functional layer 10 are provided with a doping region 12 in contact with the conductive contact structure 30 extending into the epitaxial functional layer 10.

[0052] In the present embodiment, the through hole prepared in the interlayer dielectric layer 20 exposes at least part of the surface of the doped region 12, so that the exposed doped region 12 forms a step structure. Since the doped region 12 is located on both sides and outside the end of the conductive contact structure 30 extending to the epitaxial functional layer 10, the step structure formed by the exposed doped region 12 should be that the surface of the middle doped region 12 is lower as the bottom table, and the surface of the edge doped region 12 is higher as the top table, and the top table and the bottom table are connected by the step sidewall. Compared with the through hole in the existing interlayer dielectric layer 20 that only exposes the inner surface of a recessed area of ​​the doped region 12, in the present embodiment, the doped region 12 at the top table connected to the recessed area is additionally exposed, and the top table in the formed step structure is arranged to contact the conductive contact structure 30, which can increase the contact area between the conductive contact structure 30 and the doped region 12, thereby reducing the on-resistance of the device during operation. In the present embodiment, the specific material of the conductive contact structure 30 is not limited, as long as it can achieve conductive connection, and the above conductive contact structure 30 can be specifically set as a metal structure. Accordingly, the present embodiment does not limit the specific material of the interlayer dielectric layer 20, as long as it can achieve electrical isolation, for example, it can be set to silicon oxide, benzocyclobutene (BCB), polyimide (PI), undoped silicon dioxide (USG), borophosphosilicate glass (BPSG) and titanium nitride (TiN). In the present embodiment, the epitaxial functional layer 10 can be set to a silicon epitaxial functional layer grown on a silicon substrate, and the corresponding interlayer dielectric layer 20 can be set to a silicon oxide interlayer dielectric layer. In the present embodiment, by preparing the above-mentioned low on-resistance discrete device, the on-resistance in the prior art is at least 6 milliohms, which is improved to the on-resistance of 3.85 milliohms in the present embodiment, thereby improving the performance of the device.

[0053] Furthermore, in order to reduce the on-resistance of the device to the greatest extent, the through hole may be arranged to expose the entire surface of the doped region 12 , and the exposed surface of the doped region 12 forms a step structure.

[0054] It should be noted that in this embodiment, a through hole is provided to expose the entire surface of the doped region 12, and the exposed surface of the doped region 12 forms a step structure. At this time, the through hole exposes the entire top table of the step structure formed by the doped region 12, which can maximize the contact area between the doped region 12 and the conductive contact structure 30, thereby improving the operating efficiency of the device.

[0055] Furthermore, to further ensure the electrical isolation of the epitaxial functional layer 10 , an isolation layer 21 may be provided on a side of the interlayer dielectric layer 20 close to the epitaxial functional layer 10 .

[0056] It should be noted that, in this embodiment, an isolation layer 21 is additionally provided between the interlayer dielectric layer 20 and the epitaxial functional layer 10 , which can further improve the electrical isolation effect on the epitaxial functional layer 10 .

[0057] Furthermore, in a feasible embodiment, the trench structure functional region 11 may include a source functional region and a gate functional region.

[0058] It should be noted that in this embodiment, the trench structure functional area 11 includes a source functional area and a gate functional area to achieve the functionality of a discrete device.

[0059] Furthermore, in a feasible embodiment, the doping region 12 may include an N-type sub-doping region and a P-type sub-doping region.

[0060] It should be noted that in this embodiment, the N-type sub-doping region and the P-type sub-doping region together form the doping region 12 to achieve device functionality.

[0061] A low on-resistance discrete device provided by an embodiment of the present invention includes an epitaxial functional layer 10, an interlayer dielectric layer 20 is arranged on one side of the epitaxial functional layer 10; a groove structure functional area 11 is arranged in the epitaxial functional layer 10 and located on the side of the interlayer dielectric layer 20 close to the epitaxial functional layer 10; the interlayer dielectric layer 20 is formed with a through hole exposing the epitaxial functional layer 10, and a conductive contact structure 30 passes through the through hole and extends into the epitaxial functional layer 10; the conductive contact structure 30 is located in the epitaxial functional layer 10. Both sides of the epitaxial functional layer 10 and the outer side of the end of the epitaxial functional layer 10 are formed with doped regions 12 in contact with the conductive contact structure 30, the through hole exposes at least part of the surface of the doped region 12, and the exposed surface of the doped region 12 forms a step structure; the top table 1 of the step structure is in contact with the conductive contact structure 30. The present invention exposes at least a portion of the surface of the doped region 12 by setting a through hole, and the exposed surface of the doped region 12 forms a step structure, that is, the through hole exposes at least a portion of the top surface of the doped region 12, and the top surface forms a top table 1 of the step structure. By increasing the contact between the top table and the conductive contact structure 30, the contact area between the conductive contact structure 30 and the doped region 12 is increased, thereby reducing the on-resistance of the device.

[0062] In addition, the embodiment of the present invention exposes the entire surface of the doped region 12 by setting a through hole, and the exposed surface of the doped region 12 forms a step structure. At this time, the through hole exposes the entire top table of the step structure formed by the doped region 12, which can maximize the contact area between the doped region 12 and the conductive contact structure 30 and improve the operating efficiency of the device; by additionally setting an isolation layer 21 between the interlayer dielectric layer 20 and the epitaxial functional layer 10, the electrical isolation effect of the epitaxial functional layer 10 can be further improved; the groove structure functional area 11 includes a source functional area and a gate functional area, and the doped region 12 is composed of an N-type sub-doped area and a P-type sub-doped area, which can realize the functionality of a discrete device.

[0063] A method for preparing a low on-resistance discrete device provided by an embodiment of the present invention is introduced below. The method for preparing a low on-resistance discrete device described below and the low on-resistance discrete device described above can be referred to each other.

[0064] Please refer to Figure 3 , Figure 3 A flowchart of a method for preparing a low on-resistance discrete device provided by an embodiment of the present invention, the method may include:

[0065] S101: providing a discrete device preform; the discrete device preform comprises an epitaxial functional layer 10, an interlayer dielectric layer 20 is arranged on one side of the epitaxial functional layer 10, a groove structure functional region 11 is arranged in the epitaxial functional layer 10 and located on the side of the interlayer dielectric layer 20 close to the epitaxial functional layer 10, and a first sub-doping region 121 is arranged next to the trench structure functional region 11.

[0066] It should be noted that this embodiment can refer to Figures 4 to 10 , Figures 4 to 10 This is a flowchart of a method for preparing a low on-resistance discrete device provided by an embodiment of the present invention. Figure 4The discrete device preform provided in this embodiment includes an epitaxial functional layer 10 and is located on one side of the epitaxial functional layer 10. A groove structure functional area 11 and a first sub-doping area 121 are prepared in the epitaxial functional layer 10, and an interlayer dielectric layer 20 is prepared outside the same side of the epitaxial functional layer 10. It should be noted that in this embodiment, the epitaxial functional layer 10 is generally an epitaxial layer grown and prepared on a substrate, and the groove structure functional area 11 is generally prepared along the upper surface of the epitaxial functional layer 10, and a groove structure is prepared downward, and a functional area structure is prepared in the groove structure to form a groove structure functional area 11. The above-mentioned interlayer dielectric layer 20 is used for electrical isolation and protection of the epitaxial functional layer 10, and can be arranged on the surface of the epitaxial functional layer 10 on the side where the groove structure functional area 11 is prepared. In this embodiment, the first sub-doping region 121 can be a part of the doping region finally formed by the discrete device. For example, the doping region finally formed by the discrete device includes an N-type sub-doping region and a P-type sub-doping region. In this embodiment, the first sub-doping region 121 can be an N-type sub-doping region, and the N-type sub-doping region can be located on the side of the entire doping region close to the interlayer dielectric layer 20.

[0067] S102 : preparing a through hole 40 in the interlayer dielectric layer 20 to expose the first sub-doped region 121 .

[0068] This step S102 can refer to Figure 5. In the present embodiment, a through hole 40 is prepared in the interlayer dielectric layer 20, and the through hole 40 needs to expose the first sub-doping region 121, so as to facilitate the subsequent preparation of the conductive contact structure 30 and the surface contact of the first sub-doping region 121. It should be further explained that, in the present embodiment, in order to ensure the contact area between the first sub-doping region 121 and the conductive contact structure 30 prepared subsequently, the first sub-doping region 121 and the conductive contact structure 30 are generally extended to the side of the epitaxial functional layer 10 to form contact, that is, the conductive contact structure 30 extends into the position in the epitaxial functional layer 10, and is located inside the first sub-doping region 121. In order to ensure the convenience of preparation, the first sub-doping region 121 in the provided discrete device preform can be set as an integrally connected sub-doping region to ensure the convenience of preparation, and then when the conductive contact structure 30 is prepared subsequently, the first sub-doping region 121 is etched to allow the conductive contact structure 30 to pass through the first sub-doping region 121. Correspondingly, in this embodiment, the discrete device preform can also be set as a first sub-doping region 121 to form a patterned first sub-doping region 121 with a through hole 40 structure, but the preparation process is complicated. In this embodiment, a patterned photoresist can be prepared on the surface of the interlayer dielectric layer 20, and then the through hole 40 is prepared in the interlayer dielectric layer 20 by the patterned photoresist, and then the patterned photoresist is removed. It should be noted that after removing the patterned photoresist, SPM and SC-1 can also be used for wet cleaning, wherein SPM is a solution formed by mixing concentrated sulfuric acid and hydrogen peroxide in a certain proportion, and this mixed solution has strong acidity and oxidizing properties, and can effectively remove organic pollutants and some inorganic pollutants on the surface of the wafer, and SC-1 is a surface treatment liquid No. 1, which is also a solution formed by mixing concentrated sulfuric acid and hydrogen peroxide in a certain proportion, and its composition ratio is similar to SPM, but the specific concentration may be different.

[0069] Furthermore, in order to minimize the on-resistance in the discrete device, the above-mentioned preparation of the through hole 40 in the interlayer dielectric layer 20 to expose the first sub-doped region 121 may include:

[0070] A through hole 40 is formed in the interlayer dielectric layer 20 to expose the entire first sub-doping region 121 .

[0071] The through hole 40 prepared in this embodiment exposes the entire first sub-doping region 121 , so that the entire remaining surface of the first sub-doping region 121 facing the interlayer dielectric layer 20 is in contact with the conductive contact structure 30 , thereby increasing the contact area between the doping region and the conductive contact structure 30 .

[0072] S103 : preparing a sidewall protection layer 51 on the sidewall of the through hole 40 to serve as a temporary through hole 41 ; the temporary through hole 41 exposes a portion of the first sub-doping region 121 .

[0073] In this embodiment, after the through hole 40 exposes the first sub-doped region 121, a sidewall protection layer 51 is prepared on the sidewall of the prepared through hole 40 to form a temporary through hole 41. It should be noted that, since the sidewall protection layer 51 is located at the sidewall position in the through hole 40, the temporary through hole 41 reduces the diameter of the original through hole 40 on the basis of the original through hole 40, and at this time, the temporary through hole 41 exposes part of the first sub-doped region 121. It can be understood that if the through hole 40 in the original interlayer dielectric layer 20 exposes the entire first sub-doping region 121, the temporary through hole 41 formed at this time only exposes a portion of the first sub-doping region 121, and it can be seen that the sidewall protection layer 51 covers a portion of the first sub-doping region 121 located at the edge; and if the through hole 40 in the original interlayer dielectric layer 20 exposes a portion of the first sub-doping region 121, and the first sub-doping region 121 is a complete area, the area exposed by the above-mentioned through hole 40 is all within the first sub-doping region 121, and the sidewall protection layer 51 further covers a portion of the first sub-doping region 121 on the original basis.

[0074] Further, in order to ensure that the sidewall protection layer 51 is successfully prepared, the above-mentioned preparation of the sidewall protection layer 51 on the sidewall of the through hole 40 as a temporary through hole 41 may include the following steps:

[0075] Step S11 : preparing a protection layer 50 on the surface of the discrete device preform having a through hole 40 prepared in the interlayer dielectric layer 20 .

[0076] This step S11 can refer to Figure 6 .

[0077] Step S12 : etching the protection layer 50 by a sidewall etching process, leaving only the protection layer 50 on the sidewall of the through hole 40 as a sidewall protection layer 51 , thereby obtaining a temporary through hole 41 .

[0078] This step S12 can refer to Figure 7 It should be noted that, in this embodiment, the surface of the discrete device preform having the through hole 40 is first prepared in the interlayer dielectric layer 20, a complete protective layer 50 is prepared, and the protective layer 50 is etched by using the sidewall etching process, so that the protective layer 50 on the surface of the interlayer dielectric layer 20 facing away from the epitaxial functional layer 10 and the protective layer 50 on the surface of the first sub-doped region 121 exposed by the through hole 40 can be removed, and the protective layer 50 on the side wall of the through hole 40 is retained, thereby completing the preparation of the sidewall protective layer 51.

[0079] Furthermore, in order to ensure that the sidewall protection layer 51 covers and protects a portion of the first sub-doping region 121 , the sidewall protection layer 51 may be a tetraethoxysilane protection layer 50 .

[0080] In this embodiment, the tetraethoxysilane (TEOS) protection layer 50 can protect the covered first sub-doping region 121 from being etched, thereby achieving patterned etching of the first sub-doping region 121 and facilitating subsequent removal.

[0081] S104: etching the exposed first sub-doped region 121 along the temporary through hole 41 to expose the undoped region in the epitaxial functional layer 10 as the region to be doped.

[0082] This step S104 can refer to Figure 8 In this embodiment, the first sub-doped region 121 exposed by the temporary through hole 41 is etched along the temporary through hole 41. Since the temporary through hole 41 only exposes a portion of the first sub-doped region 121, a doped region through hole 40 having a diameter smaller than that of the through hole 40 in the interlayer dielectric layer 20 is formed in the etched first sub-doped region 121. When the sidewall protection layer 51 is prepared on the sidewall of the through hole 40 in the above step S103, it can be ensured that the thickness of the sidewall protection layer 51 is uniform at all sides of the through hole 40. At this time, the center of the doped region through hole 40 should coincide with the center of the through hole 40 in the interlayer dielectric layer 20. In addition, the present embodiment does not limit the stop position of etching the exposed first sub-doped region 121 along the temporary through hole 41. For example, the exposed first sub-doped region 121 can be etched along the temporary through hole 41, and the etching can be stopped when the undoped region in the epitaxial functional layer 10 is exposed. However, this method has high requirements on the accuracy of the etching process and increases the complexity of the preparation. Therefore, it can also be set that the exposed first sub-doped region 121 is etched along the temporary through hole 41, and when the undoped region in the epitaxial functional layer 10 is exposed, the epitaxial functional layer 10 at the undoped region of a certain thickness is continued to be etched to ensure that the first sub-doped region 121 is completely etched and removed, thereby improving the device quality and preparation convenience.

[0083] S105: removing the sidewall protection layer 51 and performing doping treatment on the area to be doped to form a second sub-doping area 122 to obtain a discrete device to be filled.

[0084] The step S105 can refer to Fig. 9 . This step removes the above-mentioned sidewall protection layer 51, and performs doping treatment on the area to be doped, so as to perform doping treatment on the exposed area to be doped in the epitaxial functional layer 10, and form a second sub-doping area 122. The second sub-doping area 122 can be a sub-doping area opposite to the above-mentioned first sub-doping area 121. When the above-mentioned first sub-doping area 121 is an N-type sub-doping area, the second sub-doping area 122 can be set as a P-type sub-doping area. It should be further explained that, in this embodiment, since the sidewall protection layer 51 is removed, the surface of the first sub-doping area 121 originally covered by the sidewall protection layer 51 is exposed, thereby increasing the contact area with the conductive contact structure 30.

[0085] Furthermore, in order to facilitate the subsequent preparation of the conductive contact structure 30, the above-mentioned removal of the sidewall protection layer 51 may include:

[0086] The sidewall protection layer 51 is removed, and an arc-shaped chamfered structure is fabricated at the top corner of the interlayer dielectric layer 20 .

[0087] It should be noted that, in this embodiment, after removing the sidewall protection layer 51, the top corner of the interlayer dielectric layer 20, that is, the top corner of the through hole 40, is processed to prepare an arc chamfered structure, which can facilitate the subsequent preparation of the conductive contact structure 30. In particular, when the conductive contact structure 30 is prepared by a deposition process, the uniformity of the conductive contact structure 30 prepared by deposition can be improved, and the top of the through hole 40 in the interlayer dielectric layer 20 can be avoided to close, thereby avoiding the appearance of gaps inside the conductive contact structure 30 prepared by deposition. In this embodiment, the top corner of the interlayer dielectric layer 20 is processed to prepare an arc chamfered structure, and a hydrofluoric acid etching solution can be used for back etching to adjust the inclination of the hole wall. This back etching step helps to improve the quality of the contact hole, reduce defects, and ensure that the metal in the subsequent metallization step can better fill the contact hole. In this embodiment, a wet etching process can be specifically used to etch and remove the sidewall protection layer 51.

[0088] S106: In the discrete device to be filled, prepare a conductive contact structure 30 that contacts the surface of the exposed first sub-doping region 121 and the surface of the exposed second sub-doping region 122; at least a portion of the surface of the top of the first sub-doping region 121 is exposed, and the exposed surface of the first sub-doping region 121 forms a step structure with the exposed surface of the second sub-doping region 122, and the top table 1 of the step structure contacts the conductive contact structure 30.

[0089] This step S106 can refer to Fig.10 In this embodiment, the exposed upper surface of the first sub-doping region 121, which was originally covered by the sidewall protection layer 51, forms a step structure with the exposed surface of the second sub-doping region 122. At this time, the top table 1 of the step structure, that is, the exposed upper surface of the first sub-doping region 121, which was originally covered by the sidewall protection layer 51, is an area that contacts the conductive contact structure 30 and is increased relative to the existing structure, thereby reducing the on-resistance of the discrete device.

[0090] The method for preparing a low on-resistance discrete device provided by an embodiment of the present invention comprises S101: providing a discrete device preform; the discrete device preform comprises an epitaxial functional layer 10, an interlayer dielectric layer 20 is arranged on one side of the epitaxial functional layer 10, a groove structure functional region 11 is arranged in the epitaxial functional layer 10 and located on the side of the interlayer dielectric layer 20 close to the epitaxial functional layer 10, and a first sub-doping region 121 is arranged next to the groove structure functional region 11; S102: preparing a through hole 40 in the interlayer dielectric layer 20 to expose the first sub-doping region 121; S103: preparing a sidewall protection layer 51 on the sidewall of the through hole 40 as a temporary through hole 41; the temporary through hole 41 exposes part of the first sub-doping region 121; S104: The temporary through hole 41 etches the exposed first sub-doping region 121 to expose the undoped region in the epitaxial functional layer 10 as the region to be doped; S105: remove the sidewall protection layer 51, and dope the region to be doped to form the second sub-doping region 122, and obtain a discrete device to be filled; S106: in the discrete device to be filled, prepare a conductive contact structure 30 that contacts the surface of the exposed first sub-doping region 121 and the surface of the exposed second sub-doping region 122; the top of the first sub-doping region 121 at least partially exposes the surface, and the exposed surface of the first sub-doping region 121 forms a step structure with the exposed surface of the second sub-doping region 122, and the top table 1 of the step structure contacts the conductive contact structure 30. The present invention exposes at least a portion of the surface of the doped region by setting a through hole 40, and the exposed surface of the doped region forms a step structure, that is, the through hole 40 exposes at least a portion of the top surface of the doped region, and the top surface forms a top table 1 of the step structure. By increasing the contact between the top table and the conductive contact structure 30, the contact area between the conductive contact structure 30 and the doped region is increased, thereby reducing the on-resistance of the device.

[0091] In addition, the embodiment of the present invention exposes the entire first sub-doping region 121 by setting the prepared through hole 40, so that the entire remaining surface of the first sub-doping region 121 close to the interlayer dielectric layer 20 can be in contact with the conductive contact structure 30, thereby increasing the contact area between the doping region and the conductive contact structure 30; first, a surface of a discrete device preform having a through hole 40 is prepared in the interlayer dielectric layer 20, a complete protective layer 50 is prepared, and the protective layer 50 is etched using a sidewall etching process, which can ensure that the sidewall protective layer 51 is successfully prepared; by setting a tetraethoxysilane protective layer 50 covers and protects part of the first sub-doped region 121, realizes the graphical etching of the first sub-doped region 121, and is convenient for subsequent removal; by preparing an arc chamfer structure at the top corner of the interlayer dielectric layer 20 after removing the sidewall protection layer 51, it is convenient for the subsequent preparation of the conductive contact structure 30, especially when the conductive contact structure 30 is prepared by a deposition process, the uniformity of the conductive contact structure 30 prepared by deposition can be improved, and the top of the through hole 40 in the interlayer dielectric layer 20 can be avoided to close, thereby avoiding the formation of voids inside the conductive contact structure 30 prepared by deposition.

[0092] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0093] In addition, it should be noted that, in this article, relationships such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprises" or any other variants are intended to cover non-exclusive inclusions.

[0094] The above is a detailed introduction to a low on-resistance discrete device and a method for preparing a low on-resistance discrete device provided by the present invention. Specific examples are used in this article to illustrate the principles and implementation methods of the present invention. The description of the above embodiments is only used to help understand the method of the present invention and its core idea; at the same time, for general technical personnel in this field, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A low on-resistance discrete device, characterized in that: include: An epitaxial functional layer, wherein an interlayer dielectric layer is disposed on one side of the epitaxial functional layer; A groove structure functional area is arranged in the epitaxial functional layer and located on a side of the interlayer dielectric layer close to the epitaxial functional layer; The interlayer dielectric layer is formed with a through hole exposing the epitaxial functional layer, and the conductive contact structure passes through the through hole and extends into the epitaxial functional layer; The conductive contact structure is located on both sides of the epitaxial functional layer, and the outer side of the end portion located in the epitaxial functional layer is formed with a doped region in contact with the conductive contact structure, the through hole exposes at least part of the surface of the doped region, and the exposed surface of the doped region forms a step structure; A top terrace of the step structure contacts the conductive contact structure.

2. The low on-resistance discrete device according to claim 1, characterized in that: The through hole exposes the entire surface of the doped region, and the exposed surface of the doped region forms a step structure.

3. The low on-resistance discrete device according to claim 1, characterized in that: An isolation layer is disposed on a side of the interlayer dielectric layer close to the epitaxial functional layer.

4. The low on-resistance discrete device according to claim 1, characterized in that: The trench structure functional area includes a source functional area and a gate functional area.

5. The low on-resistance discrete device according to claim 1, characterized in that: The doping region includes an N-type sub-doping region and a P-type sub-doping region.

6. A method for preparing a low on-resistance discrete device, characterized in that: include: A discrete device preform is provided; the discrete device preform comprises an epitaxial functional layer, an interlayer dielectric layer is arranged on one side of the epitaxial functional layer, a groove structure functional region is arranged in the epitaxial functional layer and on a side of the interlayer dielectric layer close to the epitaxial functional layer, and a first sub-doping region is arranged next to the groove structure functional region; preparing a through hole in the interlayer dielectric layer to expose the first sub-doped region; A sidewall protection layer is prepared on the sidewall of the through hole as a temporary through hole; the temporary through hole exposes a portion of the first sub-doped region; Etching the exposed first sub-doped region along the temporary through hole to expose an undoped region in the epitaxial functional layer as a region to be doped; Removing the sidewall protection layer, and performing doping treatment on the area to be doped to form a second sub-doping area, thereby obtaining a discrete device to be filled; In the discrete device to be filled, a conductive contact structure is prepared that contacts both the exposed surface of the first sub-doping region and the exposed surface of the second sub-doping region; at least a portion of the surface of the top of the first sub-doping region is exposed, and the exposed surface of the first sub-doping region forms a step structure with the exposed surface of the second sub-doping region, and the top table of the step structure contacts the conductive contact structure.

7. The method for preparing a low on-resistance discrete device according to claim 6, characterized in that: Preparing a through hole in the interlayer dielectric layer to expose the first sub-doped region includes: The through hole is prepared in the interlayer dielectric layer to expose the entire first sub-doping region.

8. The method for preparing a low on-resistance discrete device according to claim 6, characterized in that: A sidewall protection layer is prepared on the sidewall of the through hole as a temporary through hole, comprising: Preparing a protective layer on the surface of the discrete device preform having the through hole prepared in the interlayer dielectric layer; The protective layer is etched by a sidewall etching process, and only the protective layer remains on the sidewall of the through hole as the sidewall protective layer, thereby obtaining the temporary through hole.

9. The method for preparing a low on-resistance discrete device according to claim 8, characterized in that: The side wall protection layer is a tetraethoxysilane protection layer.

10. The method for preparing a low on-resistance discrete device according to claim 6, characterized in that: Removing the sidewall protection layer comprises: The sidewall protection layer is removed, and an arc-shaped chamfered structure is fabricated at the top corner of the interlayer dielectric layer.

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