Super-junction MOSFET structure and preparation method thereof

Abstract

The invention provides a super-junction MOSFET structure and a preparation method thereof, and relates to the technical field of semiconductor devices. Comprising a first conductive type epitaxial layer formed on a first conductive type substrate layer; the second conduction type doped columns are formed in the middle area of the first conduction type epitaxial layer, the second conduction type doped columns comprise second preset conduction type doped columns and a plurality of second target conduction type doped columns located on the two sides of the lower surfaces of the second preset conduction type doped columns, and the second target conduction type doped columns are arranged at intervals; the second conduction type body region is formed on the second preset conduction type doped column; the plurality of first conductive type source regions are formed in the second conductive type body region and are arranged at intervals; gate oxide layers are formed in edge regions on two sides of the first conductive type epitaxial layer; the polycrystalline silicon layer is formed on the gate oxide layer; and sequentially forming a plurality of interlayer dielectric layers and metal layers on the polycrystalline silicon layer. And the failure risk caused by starting of an in-vivo parasitic NPN triode is reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor devices, and in particular to a super junction MOSFET structure and a preparation method thereof. Background Art

[0002] In the field of power device technology, industry insiders have proposed relevant improvement methods for the "silicon limit" problem. Among them, the superjunction metal oxide semiconductor field effect transistor (Metal Oxide SemiconductorField Effect Transistor, MOSFET) structure that uses charge balance to change the internal electric field distribution has become one of the main methods. Compared with the traditional vertical double-diffused metal-oxide-semiconductor (Vertical Double-diffused Metal-Oxide-Semiconductor, VDMOS) structure, the superjunction MOSFET introduces P-type doped columns in the N-type epitaxial region to form alternating PNPN columns, and its internal electric field distribution also changes from the original longitudinal electric field to the joint action of the horizontal and vertical electric fields. Due to the introduction of the lateral electric field, the electric field in the device body changes from a triangular distribution to an approximately rectangular distribution, reducing the specific on-resistance (Rsp) at the same breakdown voltage level, which to a certain extent breaks the "silicon limit".

[0003] At present, the conventional multi-epitaxial super junction MOSFET structure includes: a heavily doped first conductivity type substrate, a first conductivity type epitaxial, a P column, a P-type body region and a heavily doped first conductivity type source region on the P column, a gate oxide layer, a gate polysilicon, an interlayer dielectric layer and a metal layer on the silicon surface, and the metal layer contacts the silicon surface through a contact hole to form an electrode. However, the current distribution of the conventional multi-epitaxial super junction MOSFET structure under the withstand voltage state flows from the drain to the source contact hole, passing through the P-type body region under the heavily doped first conductivity type source region, which easily causes the parasitic NPN transistor in the body to turn on, resulting in device failure, especially under the condition of charge imbalance (biased in the N direction), the situation is more serious. Summary of the invention

[0004] The purpose of the embodiments of the present invention is to provide a super junction MOSFET structure and a preparation method thereof, so as to solve the problem that the existing super junction MOSFET structure easily causes the internal parasitic NPN transistor to turn on, resulting in device failure.

[0005] To solve the above technical problems, the embodiments of the present invention provide the following technical solutions:

[0006] The present invention provides a super junction MOSFET structure, the super junction MOSFET structure comprising:

[0007] a first conductive type substrate layer;

[0008] A first conductive type epitaxial layer formed on the first conductive type substrate layer;

[0009] A second conductive type doped column is formed in the middle region of the first conductive type epitaxial layer, the second conductive type doped column comprises a second preset conductive type doped column and a plurality of second target conductive type doped columns, the plurality of second target conductive type doped columns are located on both sides of the lower surface of the second preset conductive type doped column, and the plurality of second target conductive type doped columns are arranged at intervals;

[0010] A second conductive type body region is formed on a second preset conductive type doped column, wherein an upper surface of the second conductive type body region and an upper surface of the first conductive type epitaxial layer are located at the same level;

[0011] A plurality of first conductivity type source regions are formed inside the second conductivity type body region and are arranged at intervals;

[0012] A gate oxide layer is formed on both side edge regions of the first conductivity type epitaxial layer, a portion of the second conductivity type body region, and a portion of the plurality of first conductivity type source regions;

[0013] a polysilicon layer formed on the gate oxide layer;

[0014] A plurality of interlayer dielectric layers are formed on the polysilicon layer and a portion of the plurality of first conductivity type source regions, and the plurality of interlayer dielectric layers wrap the polysilicon layer and the gate oxide layer;

[0015] The metal layer is formed on the plurality of interlayer dielectric layers, a portion of the second conductive type body region and a portion of the plurality of first conductive type source regions.

[0016] In some modified implementations of the first aspect of the present invention, upper surfaces of the plurality of first conductivity type source regions, upper surfaces of the second conductivity type body regions, and upper surfaces of the first conductivity type epitaxial layer are located on the same horizontal plane.

[0017] In some modified embodiments of the first aspect of the present invention, the material of the plurality of interlayer dielectric layers includes SiN.

[0018] In some modified embodiments of the first aspect of the present invention, the number of multiple second target conductivity type doped columns includes a first number and a second number, the first number of second target conductivity type doped columns are located on one side of the lower surface of the second preset conductivity type doped column, and the second number of second target conductivity type doped columns are located on the other side of the lower surface of the second preset conductivity type doped column.

[0019] In some modified implementations of the first aspect of the present invention, a first number of second target conductivity type doped columns are arranged at intervals along the vertical direction, and a second number of second target conductivity type doped columns are arranged at intervals along the vertical direction.

[0020] In some modified embodiments of the first aspect of the present invention, the implanted impurities of the second conductive type doped column include second conductive type impurities, the implanted impurities of the second conductive type body region are second conductive type impurities, and the implantation dose of the second conductive type impurities of the second conductive type doped column is less than the implantation dose of the second conductive type impurities of the second conductive type body region.

[0021] A second aspect of the present invention provides a method for preparing a super junction MOSFET structure, the method comprising:

[0022] Growing a first conductivity type epitaxial layer on a first conductivity type substrate layer, wherein the first conductivity type substrate layer is a heavily doped substrate layer;

[0023] Using a preset resistivity, sequentially injecting a first conductive type impurity and an initial second conductive impurity according to a preset number of times to form a conductive type doped column to be excited, the preset number of times includes a first preset number of times and a second preset number of times, and the injection position of the initial second conductive impurity in the first preset number of times is different from the injection position of the initial second conductive impurity in the second preset number of times;

[0024] Growing a doped first conductivity type epitaxial layer using a target resistivity;

[0025] Implanting an intermediate second conductive type impurity on the upper surface of the doped first conductive type epitaxial layer, wherein the implantation dose of the intermediate second conductive type impurity is less than the implantation dose of the initial second conductive impurity;

[0026] Exciting the first conductive type impurities, the initial second conductive type impurities and the intermediate second conductive type impurities through a thermal process to form second conductive type doped columns, wherein the second conductive type doped columns are arranged at intervals;

[0027] forming a thick oxide layer on the upper surface of the first conductive type epitaxial layer by a thermal oxidation process, and etching the thick oxide layer by a photolithography process;

[0028] Forming a gate oxide layer on the upper surface of the first conductive type epitaxial layer by a thermal oxidation process, depositing a polysilicon layer on the upper surface of the gate oxide layer, and etching the polysilicon layer and the gate oxide layer in sequence;

[0029] Implanting target second conductivity type impurities by a self-aligned process, and stimulating the target second conductivity type impurities by a thermal process to form a second conductivity type body region;

[0030] Implanting first conductivity type impurities to form a plurality of first conductivity type source regions;

[0031] Depositing an interlayer dielectric to form an interlayer dielectric layer, etching the interlayer dielectric layer to form a contact hole, and finally injecting second conductive type impurities;

[0032] Depositing a metal layer and patterning the metal layer to form a gate and a source;

[0033] Depositing a passivation layer and patterning the passivation layer to form an electrode wiring area;

[0034] The structure after the passivation layer is deposited is subjected to substrate thinning and back-gold processing to obtain a super junction MOSFET structure.

[0035] In some modified embodiments of the second aspect of the present invention, the implantation dose of the intermediate second conductivity type impurity is smaller than the implantation dose of the target second conductivity type impurity.

[0036] In some modified embodiments of the second aspect of the present invention, the target resistivity is greater than the preset resistivity.

[0037] Compared with the prior art, the present invention provides a super junction MOSFET structure and a preparation method thereof, wherein the super junction MOSFET structure comprises a first conductive type substrate layer; a first conductive type epitaxial layer, formed on the first conductive type substrate layer; a second conductive type doped column, formed in the middle region of the first conductive type epitaxial layer, the second conductive type doped column comprising a second preset conductive type doped column and a plurality of second target conductive type doped columns, the plurality of second target conductive type doped columns are located on both sides of the lower surface of the second preset conductive type doped column, and the plurality of second target conductive type doped columns are arranged at intervals; a second conductive type body region, formed in the second preset conductive type doped column, On the impurity column, the upper surface of the second conductive type body region and the upper surface of the first conductive type epitaxial layer are located at the same horizontal plane; multiple first conductive type source regions are formed inside the second conductive type body region and are arranged at intervals; a gate oxide layer is formed on both side edge regions of the first conductive type epitaxial layer, part of the second conductive type body region and part of the multiple first conductive type source regions; a polysilicon layer is formed on the gate oxide layer; multiple interlayer dielectric layers are formed on the polysilicon layer and part of the multiple, and the multiple interlayer dielectric layers wrap the polysilicon layer and the gate oxide layer; a metal layer is formed on the multiple interlayer dielectric layers, part of the second conductive type body region and part of the multiple first conductive type source regions. In this way, by setting two different second conductive type doped columns, the overall second conductive type doped column, i.e., the P column, can be split, and the morphology of the lower part of the second conductive type doped column, i.e., the P column, can be changed to form more subdivided staggered PN columns. Without affecting the withstand voltage, the current path of the super junction MOSFET structure in the withstand voltage state can be changed to avoid current flowing through the parasitic NPN transistor in the body, thereby reducing the risk of failure caused by the turning on of the parasitic NPN transistor in the body. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] By reading the detailed description below with reference to the accompanying drawings, the above and other objects, features and advantages of the exemplary embodiments of the present invention will become readily understood. In the accompanying drawings, several embodiments of the present invention are shown in an exemplary and non-limiting manner, and the same or corresponding reference numerals represent the same or corresponding parts, wherein:

[0039] Figure 1 A schematic diagram of a superjunction MOSFET structure is schematically shown;

[0040] Figure 2 A flow chart of a method for preparing a super junction MOSFET structure is schematically shown;

[0041] Figure 3 The schematic diagram of preparing the first conductivity type epitaxial layer is schematically shown;

[0042] Figure 4 The schematic diagram of preparing the conductive type doped column to be excited is schematically shown;

[0043] Figure 5 The schematic diagram of preparing a doped first conductivity type epitaxial layer is schematically shown;

[0044] Figure 6 The schematic diagram of injecting the middle second conductivity type impurity is schematically shown;

[0045] Figure 7 The schematic diagram of forming the second conductivity type doped column is schematically shown;

[0046] Figure 8 The schematic diagram of preparing the gate oxide layer and the polysilicon layer is schematically shown;

[0047] Fig. 9 The schematic diagram of preparing the second conductivity type body region is schematically shown;

[0048] Fig.10 The schematic diagram of preparing a plurality of first conductivity type source regions is schematically shown;

[0049] Fig.11 The schematic diagram of preparing the interlayer dielectric layer and the contact hole is schematically shown;

[0050] Fig.12 schematically shows a schematic diagram of depositing a metal layer;

[0051] Fig.13 The current distribution diagram of a conventional super junction MOSFET structure under a withstand voltage state is schematically shown;

[0052] Fig.14 The current distribution diagram of the super junction MOSFET structure of the present invention in the withstand voltage state is schematically shown.

[0053] Description of reference numerals:

[0054] 1. First conductive type substrate layer; 2. First conductive type epitaxial layer; 3. Second conductive type doped column; 31. Second preset conductive type doped column; 32. Multiple second target conductive type doped columns; 4. Second conductive type body region; 5. Multiple first conductive type source regions; 6. Gate oxide layer; 7. Polysilicon layer; 8. Multiple interlayer dielectric layers; 9. Metal layer. DETAILED DESCRIPTION

[0055] The following is a further detailed description of the embodiments of the present invention in conjunction with the accompanying drawings and examples. The detailed description of the following embodiments and the accompanying drawings are used to exemplarily illustrate the principles of the present invention, but cannot be used to limit the scope of the present invention. The present invention can be implemented in many different forms and is not limited to the specific embodiments disclosed herein, but includes all technical solutions falling within the scope of the claims.

[0056] A super junction MOSFET structure in an embodiment of the present invention is described in detail below.

[0057] See also Figure 1 As shown, Figure 1 The structure diagram of the super junction MOSFET structure is schematically shown. The embodiment of the present invention proposes a super junction MOSFET structure including:

[0058] A first conductive type substrate layer 1;

[0059] A first conductive type epitaxial layer 2, formed on the first conductive type substrate layer 1;

[0060] A second conductive type doped column 3 is formed in the middle region of the first conductive type epitaxial layer 2, the second conductive type doped column 3 comprises a second preset conductive type doped column 31 and a plurality of second target conductive type doped columns 32, the plurality of second target conductive type doped columns 32 are located on both sides of the lower surface of the second preset conductive type doped column 31, and the plurality of second target conductive type doped columns 32 are arranged at intervals;

[0061] A second conductive type body region 4 is formed on the second preset conductive type doped column 31, and the upper surface of the second conductive type body region 4 and the upper surface of the first conductive type epitaxial layer 2 are located at the same level;

[0062] A plurality of first conductivity type source regions 5 are formed inside the second conductivity type body region 4 and are arranged at intervals;

[0063] A gate oxide layer 6 is formed on both side edge regions of the first conductivity type epitaxial layer 2, a portion of the second conductivity type body region 4 and a portion of the plurality of first conductivity type source regions 5;

[0064] A polysilicon layer 7 formed on the gate oxide layer 6;

[0065] A plurality of interlayer dielectric layers 8 are formed on the polysilicon layer 7 and a portion of the plurality of first conductivity type source regions 5, and the plurality of interlayer dielectric layers 8 wrap the polysilicon layer 7 and the gate oxide layer 6;

[0066] The metal layer 9 is formed on the plurality of interlayer dielectric layers 8 , a portion of the second conductivity type body region 4 and a portion of the plurality of first conductivity type source regions 5 .

[0067] Exemplarily, the number of the plurality of second target conductivity type doped columns 32 may be 8 or 9, and the number of the plurality of second target conductivity type doped columns 32 is not specifically limited herein.

[0068] The first conductivity type is N type, and the second conductivity type is P type.

[0069] In this embodiment, the upper surfaces of the plurality of first conductivity type source regions 5 , the upper surfaces of the second conductivity type body regions 4 , and the upper surface of the first conductivity type epitaxial layer 2 are located at the same level.

[0070] In this embodiment, the material of the plurality of interlayer dielectric layers 8 includes SiN.

[0071] Specifically, the plurality of interlayer dielectric layers 8 comprising SiN material can block the influence of foreign impurities and water vapor.

[0072] In this embodiment, the number of multiple second target conductive type doped columns 32 includes a first number and a second number, the first number of second target conductive type doped columns are located on one side of the lower surface of the second preset conductive type doped column 31, and the second number of second target conductive type doped columns are located on the other side of the lower surface of the second preset conductive type doped column 31.

[0073] Specifically, the first number of second target conductivity type doped columns and the second number of second target conductivity type doped columns may be symmetrical structures or may not be symmetrical structures. The first number and the second number may be the same or different. Exemplarily, the first number may be 4, and the second number may also be 4, 4 second target conductivity type doped columns are located on one side of the lower surface of the second preset conductivity type doped column 31, and the other 4 second target conductivity type doped columns are located on the other side of the lower surface of the second preset conductivity type doped column 31.

[0074] In this embodiment, a first number of second target conductivity type doped columns are arranged at intervals along the vertical direction, and a second number of second target conductivity type doped columns are arranged at intervals along the vertical direction.

[0075] In this embodiment, the implanted impurities of the second conductive type doped column 3 include second conductive type impurities, the implanted impurities of the second conductive type body region 4 are second conductive type impurities, and the implantation dose of the second conductive type impurities of the second conductive type doped column 3 is less than the implantation dose of the second conductive type impurities of the second conductive type body region 4.

[0076] Specifically, the implanted impurities of the second conductive type doped column 3 also include the first conductive type impurities. The total number of times the second conductive type impurities are implanted is 7 times. The 1st to 6th times and the 7th time are implanted separately. The implantation positions of the second conductive type impurities of the 1st to 4th times are different from the implantation positions of the second conductive type impurities of the 5th to 6th times. The implantation positions of the second conductive type impurities of the 1st to 4th times are the same, and the implantation positions of the second conductive type impurities of the 5th and 6th times are the same.

[0077] The first conductive type impurity may be P (phosphorus), and the second conductive type impurity may be B (boron). The first conductive type impurity and the second conductive type impurity are not specifically limited herein.

[0078] Based on the above Figure 1It can be seen from the implementation method that the super junction MOSFET structure of the embodiment of the present invention includes a first conductive type substrate layer 1; a first conductive type epitaxial layer 2, formed on the first conductive type substrate layer 1; a second conductive type doped column 3, formed in the middle area of ​​the first conductive type epitaxial layer 2, the second conductive type doped column 3 includes a second preset conductive type doped column 31 and a plurality of second target conductive type doped columns 32, the plurality of second target conductive type doped columns 32 are located on both sides of the lower surface of the second preset conductive type doped column 31, and the plurality of second target conductive type doped columns 32 are arranged at intervals; a second conductive type body region 4, formed on the second preset conductive type doped column 31, the second conductive type body region 4 and the upper surface of the first conductive type epitaxial layer 2 are located at the same horizontal plane; multiple first conductive type source regions 5 are formed inside the second conductive type body region 4 and are arranged at intervals; a gate oxide layer 6 is formed on both side edge regions of the first conductive type epitaxial layer 2, part of the second conductive type body region 4 and part of the multiple first conductive type source regions 5; a polysilicon layer 7 is formed on the gate oxide layer 6; multiple interlayer dielectric layers 8 are formed on the polysilicon layer 7 and part of the multiple first conductive type source regions 5, and the multiple interlayer dielectric layers 8 wrap the polysilicon layer 7 and the gate oxide layer 6; a metal layer 9 is formed on the multiple interlayer dielectric layers 8, part of the second conductive type body region 4 and part of the multiple first conductive type source regions 5. In this way, by setting two different second conductive type doped columns 3, the overall second conductive type doped column 3, i.e., the P column, can be split, and the morphology of the lower part of the second conductive type doped column 3, i.e., the P column, can be changed to form more subdivided staggered PN columns. Without affecting the withstand voltage, the current path of the super junction MOSFET structure in the withstand voltage state can be changed to avoid current flowing through the parasitic NPN transistor in the body, thereby reducing the failure risk caused by the turning on of the parasitic NPN transistor in the body.

[0079] Figure 2 The flowchart of the method for preparing the super junction MOSFET structure is schematically shown, see Figure 2 As shown, a method for preparing a super junction MOSFET structure may include:

[0080] S201 , growing a first conductivity type epitaxial layer 2 on a first conductivity type substrate layer 1 .

[0081] The first conductive type substrate layer 1 is a heavily doped substrate layer.

[0082] Figure 3 The schematic diagram of preparing the first conductivity type epitaxial layer 2 is schematically shown. The first conductivity type epitaxial layer 2 is grown on a heavily doped first conductivity type substrate.

[0083] S202 , using a preset resistivity, sequentially injecting first conductive type impurities and initial second conductive impurities according to a preset number of times to form conductive type doped columns to be excited.

[0084] The preset number of times includes a first preset number of times and a second preset number of times, and the initial injection position of the second conductive impurities in the first preset number of times is different from the initial injection position of the second conductive impurities in the second preset number of times.

[0085] Specifically, the preset resistivity ranges from 0.8 to 300 Ω·cm. The preset number of times may be 6 times, and the preset number of times is not specifically limited. The initial second conductive impurities are second conductive type impurities injected 1 to 6 times.

[0086] Figure 4 The schematic diagram of preparing the conductive type doped column to be excited is schematically shown. It is necessary to sequentially inject the first conductive type impurity and the initial second conductive impurity into the first conductive type epitaxial layer 2, and it is necessary to perform the operation of sequentially injecting the first conductive type impurity and the initial second conductive impurity 6 times. The initial second conductive impurity injection can be performed using a photomask, wherein the photomask used for the 1st to 4th injection of the initial second conductive type impurity is different from the photomask used for the 5th to 6th injection of the initial second conductive type impurity.

[0087] S203 , growing a doped first conductivity type epitaxial layer 2 using a target resistivity.

[0088] The target resistivity ranges from 8 to 300 Ω·cm.

[0089] In this embodiment, the target resistivity is greater than the preset resistivity.

[0090] Seven epitaxial growths are required, but not limited to seven epitaxial growths. The first conductive type epitaxial layer 2 is formed by resistivity plus implantation of first conductive type impurities.

[0091] Figure 5 The schematic diagram of preparing the doped first conductivity type epitaxial layer 2 is schematically shown. The doped first conductivity type epitaxial layer 2 is grown on the structure after the conductive type doping column to be activated is formed, using the target resistivity.

[0092] S204 , implanting intermediate second conductivity type impurities into the upper surface of the doped first conductivity type epitaxial layer 2 .

[0093] The implantation dosage of the intermediate second conductive type impurities is smaller than the implantation dosage of the initial second conductive impurities.

[0094] Specifically, the implantation dose of the middle second conductive type impurity is of the order of magnitude of e12. The middle second conductive impurity is the second conductive type impurity implanted for the seventh time.

[0095] Figure 6 The schematic diagram of implanting the intermediate second conductive type impurities is schematically shown, where the upper surface of the doped first conductive type epitaxial layer 2 is implanted with the intermediate second conductive type impurities at a dosage smaller than the initial second conductive impurities.

[0096] S205 , exciting the first conductive type impurities, the initial second conductive type impurities and the intermediate second conductive type impurities through a thermal process to form a second conductive type doped column 3 .

[0097] The second conductive type doped columns 3 are arranged at intervals.

[0098] Figure 7 The schematic diagram of forming the second conductive type doped column 3 is schematically shown. The second conductive type doped column 3 is formed by exciting the internal impurities through a thermal process. The internal impurities include the first conductive type impurities, the initial second conductive type impurities and the intermediate second conductive type impurities.

[0099] S206 , forming a thick oxide layer on the upper surface of the first conductive type epitaxial layer 2 by a thermal oxidation process, and etching the thick oxide layer by a photolithography process.

[0100] The growth method of the thick oxide layer is not limited to the thermal oxidation process, and a thermal oxidation plus deposition method can also be used.

[0101] S207 , forming a gate oxide layer 6 on the upper surface of the first conductive type epitaxial layer 2 by a thermal oxidation process, depositing a polysilicon layer 7 on the upper surface of the gate oxide layer 6 , and etching the polysilicon layer 7 and the gate oxide layer 6 in sequence.

[0102] Figure 8 The schematic diagram of preparing the gate oxide layer 6 and the polysilicon layer 7 is schematically shown. Through a thermal oxidation process, a gate oxide layer is formed on the upper surface of the first conductive type epitaxial layer 2, and a polysilicon layer 7 is deposited thereon. The polysilicon layer 7 and the gate oxide layer 6 are etched in sequence using a photolithography process.

[0103] S208 , implanting target second conductivity type impurities by a self-aligned process, and stimulating the target second conductivity type impurities by a thermal process to form a second conductivity type body region 4 .

[0104] In the present embodiment, the implantation dose of the intermediate second conductivity type impurity is smaller than the implantation dose of the target second conductivity type impurity.

[0105] Fig. 9The schematic diagram of preparing the second conductivity type body region 4 is schematically shown, the target second conductivity type impurities are implanted by a self-alignment process, and the target second conductivity type impurities are stimulated by a thermal process to form the second conductivity type body region 4.

[0106] S209 , injecting first conductivity type impurities to form a plurality of first conductivity type source regions 5 .

[0107] The implantation dose of the first conductive type impurity is on the order of e15.

[0108] Fig.10 The schematic diagram of preparing a plurality of first conductivity type source regions 5 is schematically shown, and the first conductivity type impurities with an implantation dose of the order of e15 are implanted to form a plurality of first conductivity type source regions 5 .

[0109] S210, depositing an interlayer dielectric to form an interlayer dielectric layer, etching the interlayer dielectric layer to form a contact hole, and finally injecting second conductive type impurities.

[0110] The material of the interlayer dielectric layer contains SiN.

[0111] Fig.11 The schematic diagram of preparing the interlayer dielectric layer and the contact hole is schematically shown, the interlayer dielectric is deposited to form the interlayer dielectric layer, the interlayer dielectric layer is etched by an etching process to form the contact hole, and the final second conductive type impurities are injected under the contact hole.

[0112] S211, depositing a metal layer 9, and patterning the metal layer 9 to form a gate and a source.

[0113] Fig.12 The schematic diagram of depositing a metal layer 9 is schematically shown. The metal layer 9 is deposited and patterned to form a gate and a source. The metal layer 9 is a front metal layer 9 .

[0114] S212, depositing a passivation layer, and patterning the passivation layer to form an electrode wiring area.

[0115] S213, performing substrate thinning and back-gold process on the structure after the passivation layer is deposited to obtain a super junction MOSFET structure.

[0116] The super junction MOSFET structure prepared by the present invention splits the P column through different lithography areas, changes the morphology of the lower part of the P column, and forms more subdivided staggered PN columns. Without affecting the withstand voltage, the current path of the device in the withstand voltage state is changed to avoid current flowing through the parasitic NPN transistor in the body, which can reduce the failure risk caused by the turning on of the parasitic NPN transistor in the body to a certain extent.

[0117] Fig.13The current distribution diagram of a conventional super junction MOSFET structure under a withstand voltage state is schematically shown. The current of the conventional super junction MOSFET structure is distributed on both sides of the second conductive type doped column 3, flowing from the drain at the bottom to the contact hole of the source. The current usually passes through the parasitic NPN transistor in the body, especially in the N-rich state (N-rich) condition, causing the parasitic NPN transistor to turn on and the conventional super junction MOSFET structure to fail. Fig.14 The current distribution diagram of the super junction MOSFET structure of the present invention under the withstand voltage state is schematically shown. The current direction of the super junction MOSFET structure of the present invention under the withstand voltage state is from bottom to top, and the current is distributed in the second conductive type doped column 3, flowing from the bottom drain to the source contact hole, which to a certain extent avoids the current flowing through the parasitic NPN transistor in the body and reduces the risk of failure of the super junction MOSFET structure.

[0118] Although some specific embodiments of the present invention have been described in detail by way of examples, it should be understood by those skilled in the art that the above examples are for illustration only and are not intended to limit the scope of the present invention. It should be understood by those skilled in the art that the above embodiments may be modified or some technical features may be replaced by equivalents without departing from the scope and spirit of the present invention. In particular, the various technical features mentioned in the various embodiments may be combined in any manner as long as there is no structural conflict.

[0119] The above are only specific embodiments of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A super junction MOSFET structure, characterized in that: The super junction MOSFET structure comprises: a first conductive type substrate layer; A first conductive type epitaxial layer, formed on the first conductive type substrate layer; A second conductive type doped column is formed in the middle region of the first conductive type epitaxial layer, the second conductive type doped column comprises a second preset conductive type doped column and a plurality of second target conductive type doped columns, the plurality of second target conductive type doped columns are located on both sides of the lower surface of the second preset conductive type doped column, and the plurality of second target conductive type doped columns are arranged at intervals; A second conductive type body region is formed on the second preset conductive type doped column, wherein an upper surface of the second conductive type body region and an upper surface of the first conductive type epitaxial layer are located at the same level; A plurality of first conductivity type source regions are formed inside the second conductivity type body region and are arranged at intervals; A gate oxide layer is formed on both side edge regions of the first conductive type epitaxial layer, a portion of the second conductive type body region, and a portion of the plurality of first conductive type source regions; a polysilicon layer formed on the gate oxide layer; A plurality of interlayer dielectric layers are formed on the polysilicon layer and a portion of the plurality of first conductivity type source regions, and the plurality of interlayer dielectric layers wrap the polysilicon layer and the gate oxide layer; A metal layer is formed on the plurality of interlayer dielectric layers, a portion of the second conductive type body regions and a portion of the plurality of first conductive type source regions.

2. The super junction MOSFET structure according to claim 1, characterized in that: The upper surfaces of the plurality of first conductivity type source regions, the upper surface of the second conductivity type body region, and the upper surface of the first conductivity type epitaxial layer are located at the same level.

3. The super junction MOSFET structure according to claim 1, characterized in that: The material of the plurality of interlayer dielectric layers includes SiN.

4. The super junction MOSFET structure according to claim 1, characterized in that: The number of the multiple second target conductivity type doped columns includes a first number and a second number, the first number of second target conductivity type doped columns are located on one side of the lower surface of the second preset conductivity type doped column, and the second number of second target conductivity type doped columns are located on the other side of the lower surface of the second preset conductivity type doped column.

5. The super junction MOSFET structure according to claim 4, characterized in that: The first number of second target conductivity type doped columns are arranged at intervals along the vertical direction, and the second number of second target conductivity type doped columns are arranged at intervals along the vertical direction.

6. The super junction MOSFET structure according to claim 1, characterized in that: The implanted impurities of the second conductive type doped column include second conductive type impurities, the implanted impurities of the second conductive type body region are second conductive type impurities, and the implantation dose of the second conductive type impurities of the second conductive type doped column is less than the implantation dose of the second conductive type impurities of the second conductive type body region.

7. A method for preparing a super junction MOSFET structure, characterized in that: The super junction MOSFET structure according to any one of claims 1 to 6 comprises: Growing a first conductivity type epitaxial layer on a first conductivity type substrate layer, wherein the first conductivity type substrate layer is a heavily doped substrate layer; Using a preset resistivity, sequentially injecting a first conductive type impurity and an initial second conductive impurity according to a preset number of times to form a conductive type doped column to be excited, wherein the preset number of times includes a first preset number of times and a second preset number of times, and the injection position of the initial second conductive impurity in the first preset number of times is different from the injection position of the initial second conductive impurity in the second preset number of times; Growing a doped first conductivity type epitaxial layer using a target resistivity; Implanting intermediate second conductive type impurities on the upper surface of the doped first conductive type epitaxial layer, wherein the implantation dose of the intermediate second conductive type impurities is less than the implantation dose of the initial second conductive impurities; Exciting the first conductive type impurities, the initial second conductive type impurities and the intermediate second conductive type impurities through a thermal process to form second conductive type doped columns, wherein the second conductive type doped columns are arranged at intervals; Forming a thick oxide layer on the upper surface of the first conductive type epitaxial layer by a thermal oxidation process, and etching the thick oxide layer by a photolithography process; Forming a gate oxide layer on the upper surface of the first conductive type epitaxial layer by a thermal oxidation process, depositing a polysilicon layer on the upper surface of the gate oxide layer, and etching the polysilicon layer and the gate oxide layer in sequence; Implanting target second conductivity type impurities by a self-aligned process, and stimulating the target second conductivity type impurities by the thermal process to form a second conductivity type body region; Implanting the first conductive type impurities to form a plurality of first conductive type source regions; Depositing an interlayer dielectric to form an interlayer dielectric layer, etching the interlayer dielectric layer to form a contact hole, and finally injecting second conductive type impurities; Depositing a metal layer and patterning the metal layer to form a gate and a source; Depositing a passivation layer, and patterning the passivation layer to form an electrode wiring area; The structure after the passivation layer is deposited is subjected to substrate thinning and back-gold processing to obtain the super junction MOSFET structure.

8. The method for preparing a super junction MOSFET structure according to claim 7, characterized in that: An implantation dose of the intermediate second conductive type impurity is smaller than an implantation dose of the target second conductive type impurity.

9. The method for preparing a super junction MOSFET structure according to claim 7, characterized in that: The target resistivity is greater than the preset resistivity.

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