Groove power device and preparation method thereof

Abstract

The invention discloses a trench power device and a preparation method thereof, the trench power device comprises a substrate and an epitaxial layer, and further comprises at least one trench gate structure located in the epitaxial layer, the trench gate structure comprises a gate electrode and a gate oxide layer, the gate electrode has a first side surface and a second side surface which are oppositely arranged in a second direction, and the first side surface and the second side surface are opposite to each other in the second direction. The gate oxide layers are respectively located on the first side surface of the gate and on one side, close to the substrate, of the gate, and the second direction is parallel to the first surface; the Schottky diode structure at least makes contact with the second side face and the first epitaxial layer, the Schottky diode structure is located on the second side face of the grid electrode, the Schottky diode structure comprises a plurality of doped regions, and the multiple doped regions comprise first doped regions and second doped regions which are alternately arranged in the second direction; the first doped region and the second doped region have different doping types. The problems that in the prior art, a grid electrode of a groove power device is resistant to static breakdown, and the device is high in switching loss under the high-frequency working condition are solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductors, and in particular, to a trench power device and a method for preparing the trench power device. Background Art

[0002] Power MOSFET has the characteristics of low forward voltage drop, high switching speed, and easy gate control, and has become an important semiconductor device in power electronic applications. The gate antistatic ability of power MOSFET is directly related to the chip area and gate oxide thickness. Compared with Si MOS devices, SiC MOS devices are limited by material and process characteristics, with small chip area, thin gate oxide thickness, and poor gate antistatic breakdown ability. As SiC MOS devices are increasingly widely used, new SiC MOS with high antistatic ability continue to emerge. However, new SiC MOS devices have higher switching losses under high-frequency working conditions. Summary of the invention

[0003] The present application provides a trench power device and a method for preparing the trench power device, so as to solve the problems in the related art of poor anti-static breakdown capability of the gate of the trench power device and high switching loss of the device under high-frequency working conditions.

[0004] According to one aspect of the present application, a trench power device is provided, comprising: a substrate; an epitaxial layer, the epitaxial layer is located on one side of the substrate, the epitaxial layer comprises a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer has a first doping type, the second epitaxial layer has a second doping type, the epitaxial layer has a first surface away from the substrate, the first direction is perpendicular to the first surface; at least one trench gate structure, the trench gate structure is located in the epitaxial layer, the surface of the trench gate structure away from the substrate is located in the first surface, the trench gate structure is close to the surface of the substrate and contacts the first epitaxial layer, the trench gate structure comprises A gate and a gate oxide layer, wherein the gate has a first side surface and a second side surface arranged opposite to each other in a second direction, the gate oxide layer is respectively located on the first side surface of the gate and the gate oxide layer is located on a side of the gate close to the substrate, and the second direction is parallel to the first surface; a Schottky diode structure, wherein the Schottky diode structure is in contact with at least the second side surface and the first epitaxial layer, the Schottky diode structure is located on the second side surface of the gate, and the Schottky diode structure includes a plurality of doped regions, the plurality of doped regions include a first doped region and a second doped region alternately arranged along the second direction, and the first doped region and the second doped region have different doping types.

[0005] Optionally, the gate contacts any one of the first doping region or the second doping region, and a doping type of the doping region contacting the gate is different from a doping type of the gate.

[0006] Optionally, in the Schottky diode structure, the doping region in contact with the gate is a first sub-doping region, and the remaining doping region is a second sub-doping region, the second sub-doping region includes a third doping region, and the trench power device also includes: multiple conductive parts, and the conductive parts and the gate are respectively in contact with different doping regions.

[0007] Optionally, the doping concentration of the doping region in contact with the conductive portion is greater than the doping concentration of the remaining doping regions.

[0008] Optionally, the doping type of the doping region in contact with the conductive portion is P type.

[0009] Optionally, the Schottky diode structure and the trench gate structure have the same depth in the first direction.

[0010] Optionally, the width of the first doping region in the second direction is the same as the width of the first doping region.

[0011] According to another aspect of the present application, a method for preparing a trench power device is provided, which is used to prepare any one of the trench power devices, and the method comprises: providing a substrate; forming an epitaxial layer on one side of the substrate, the epitaxial layer comprising a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, the epitaxial layer having a first surface away from the substrate, and the first direction being perpendicular to the first surface; forming at least one trench gate structure in the epitaxial layer, the surface of the trench gate structure away from the substrate being located in the first surface, the surface of the trench gate structure close to the substrate being in contact with the first epitaxial layer, The trench gate structure includes a gate and a gate oxide layer, the gate has a first side surface and a second side surface arranged opposite to each other in a second direction, the gate oxide layer is respectively located on the first side surface of the gate and the gate oxide layer is located on a side of the gate close to the substrate, and the second direction is parallel to the first surface; a Schottky diode structure is formed, the Schottky diode structure is in contact with at least the second side surface and the first epitaxial layer, the Schottky diode structure is located on the second side surface of the gate, the Schottky diode structure includes a plurality of doped regions, the plurality of doped regions include a first doped region and a second doped region alternately arranged along the second direction, and the first doped region and the second doped region have different doping types.

[0012] Optionally, the steps of forming the trench gate structure and the Schottky diode structure include: forming a first trench in the epitaxial layer by an etching process, wherein the bottom surface of the first trench exposes the first epitaxial layer; forming the trench gate structure on the sidewall of the first trench, and the remaining area in the first trench is the second trench; forming an insulating region on the sidewall of the second trench, and the remaining area in the second trench is the third trench; removing the second insulating layer located on the sidewall of the third trench and the first insulating layer located on the side of the second insulating layer close to the substrate, and the remaining area in the third trench is the fourth trench; and forming a plurality of doped regions in the fourth trench by an epitaxial growth process, wherein the plurality of doped regions include the first doped region and the second doped region having different doping types.

[0013] Optionally, the step of forming a plurality of the doped regions in the fourth trench using an epitaxial growth process includes: forming a first type of doped region in the fourth trench using an epitaxial growth process; forming at least one fifth trench in the first type of doped region using an etching process; forming the second doped region in the fourth trench using an epitaxial growth process, and the remaining first type of doped regions constitute the first doped region.

[0014] By applying the technical solution of the present application, a trench power device is provided, in which a Schottky diode structure is located on one side of the trench gate structure in the second direction, so that a Schottky barrier diode (SBD) is integrated in the trench power device, and the gate can be protected. Specifically, the Schottky diode structure includes a plurality of doping regions, and the doping regions include a first doping region and a second doping region with different doping types, and the first doping region and the second doping region have different doping types, so that at least one PN junction is included in the Schottky diode structure, and the gate is in direct contact with the doping region. After the gate is applied with a voltage, a conduction circuit can be formed in the Schottky diode structure. When the gate voltage exceeds the safety range, the integrated Schottky diode structure will be turned on, and the current will be released through the PN junction in the Schottky diode structure, which can protect the gate oxide layer from being broken down, and improve the antistatic ability of the trench gate structure. In addition, one side of the gate is in contact with the doping region, and has a large contact area, which reduces the contact resistance between the gate and the doping region, so that the gate has a smaller switching energy consumption in high resistance or high frequency operation. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] The drawings constituting a part of the present application are used to provide a further understanding of the present application. The illustrative embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0016] Figure 1is a schematic cross-sectional structure diagram of a trench power device according to an embodiment of the present application;

[0017] Figure 2 is a schematic cross-sectional structure diagram of another trench power device according to an embodiment of the present application;

[0018] Figure 3 is a flow chart of a method for preparing a trench power device provided in an embodiment of the present application;

[0019] Figure 4 It is a schematic diagram of a cross-sectional structure of a substrate provided in a method for preparing a trench MOS device provided in an embodiment of the present application;

[0020] Figure 5 is Figure 4 A schematic diagram of the cross-sectional structure of the substrate after the epitaxial layer is shown;

[0021] Figure 6 is Figure 5 A schematic diagram of the cross-sectional structure of the substrate after the first trench is formed in the epitaxial layer shown;

[0022] Figure 7 is Figure 6 A schematic diagram of the cross-sectional structure of the substrate after a trench gate structure and a second trench are formed in the first trench;

[0023] Figure 8 A schematic diagram of a basic structure obtained in each step of a preparation method for forming a trench gate structure provided in an embodiment of the present application is shown;

[0024] Fig. 9 is Figure 7 A schematic cross-sectional structure diagram of the substrate after the insulating region and the third trench are formed in the second trench;

[0025] Fig.10 is Fig. 9 The schematic cross-sectional structure diagram of the substrate after the insulating region in the third trench and the insulating layer in the third trench are removed to form a fourth trench;

[0026] Fig.11 is Fig.10 A schematic diagram of the cross-sectional structure of the substrate after the first type doping region is formed in the fourth trench shown;

[0027] Fig.12 is Fig.11 A schematic diagram of the cross-sectional structure of the substrate after the fifth trench is formed in the first type doping region;

[0028] Fig.13 is Fig.12 A schematic cross-sectional structure diagram of the substrate after the second doping region is formed in the fifth trench shown;

[0029] Fig.14 is Fig.13 A schematic diagram of the cross-sectional structure of the substrate after the implantation region is formed in the substrate shown;

[0030] Fig.15 is Fig.14 A schematic diagram of the cross-sectional structure of the substrate after a dielectric material layer is formed on the substrate shown;

[0031] Fig.16 is Fig.15 The cross-sectional structure diagram of the substrate after a plurality of through holes are formed in the dielectric material layer is shown.

[0032] The above drawings include the following reference numerals:

[0033] 10. substrate; 20. epitaxial layer; 201. first surface; 21. first epitaxial layer; 22. second epitaxial layer; 30. trench gate structure; 31. gate; 3101. first side; 3102. second side; 311. gate material region; 32. gate oxide layer; 321. first region; 322. second region; 40. Schottky diode structure; 41. doped region; 411. first doped region; 4111. first type type doping region; 412, second doping region; 50, injection region; 60, conductive portion; 61, first conductive portion; 611, first through hole; 62, second conductive portion; 621, second through hole; 63, third conductive portion; 631, third through hole; 64, conductive layer; 70, insulating portion; 71, dielectric material layer; 81, first trench; 811, first sub-trench; 82, second trench; 83, third trench; 84, fourth trench; 85, fifth trench; 90, insulating region; 91, first insulating layer; 911, first insulating region. DETAILED DESCRIPTION

[0034] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0035] In order to enable those skilled in the art to better understand the solution of the present application, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present application.

[0036] It should be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequential order. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present application described here. In addition, the terms "including" and "having" and any of their variations are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device comprising a series of steps or units is not necessarily limited to those steps or units clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0037] As described in the background technology, in the prior art, SiC MOS devices have a thin gate oxide layer, a poor anti-static breakdown capability of the device gate, and a high switching loss under high-frequency working conditions. In order to solve the above problems, the present application provides a trench power device and a method for preparing the trench power device.

[0038] According to one aspect of the present application, a trench power device is provided, such as Figure 1 to Figure 2 As shown, it includes: a substrate 10; an epitaxial layer 20, the epitaxial layer 20 is located on one side of the substrate 10, the epitaxial layer 20 includes a first epitaxial layer 21 and a second epitaxial layer 22 stacked along a first direction A, the first epitaxial layer 21 has a first doping type, the second epitaxial layer 22 has a second doping type, the epitaxial layer 20 has a first surface 201 away from the substrate 10, and the first direction A is perpendicular to the first surface 201; at least one trench gate structure 30, the trench gate structure 30 is located in the epitaxial layer 20, the surface of the trench gate structure 30 away from the substrate 10 is located in the first surface 201, the surface of the trench gate structure 30 close to the substrate 10 is in contact with the first epitaxial layer 21, the trench gate structure 30 includes a gate 31 and a gate oxide layer 32, the gate 31 is in the second A first side surface 3101 and a second side surface 3102 are arranged opposite to each other in direction B, the gate oxide layer 32 is respectively located on the first side surface 3101 of the gate electrode 31 and the gate oxide layer 32 is located on the side of the gate electrode 31 close to the substrate 10, and the second direction B is parallel to the first surface 201; a Schottky diode structure 40, the Schottky diode structure 40 is in contact with at least the second side surface 3102 and the first epitaxial layer 21, the Schottky diode structure 40 is located on the second side surface 3102 of the gate electrode 31, and the Schottky diode structure 40 includes a plurality of doping regions 41, and the plurality of doping regions 41 include a first doping region 411 and a second doping region 412 alternately arranged along the second direction B, and the first doping region 411 and the second doping region 412 have different doping types.

[0039] In the above trench power device, the Schottky diode structure is located on the second side of the gate, and the doped region is in contact with the gate, so that the Schottky barrier diode (SBD) is integrated into the trench power device, and the gate can be protected. Specifically, the Schottky diode structure includes multiple doped regions, and the doped regions include a first doped region and a second doped region with different doping types, and the first doped region and the second doped region have different doping types, so that at least one PN junction is included in the Schottky diode structure, and the gate is in direct contact with the doped region. After the gate is applied with a voltage, a conduction circuit can be formed in the Schottky diode structure. When the gate voltage exceeds the safe range, the integrated Schottky diode structure will be turned on, and the current will be released through the PN junction in the Schottky diode structure, which can protect the gate oxide layer from being broken down, and improve the antistatic ability of the trench gate structure. In addition, one side of the gate is in contact with the doped region, and has a large contact area, which reduces the contact resistance between the gate and the doped region, so that the gate has a smaller switching energy consumption in high resistance or high frequency rental.

[0040] Specifically, the breakdown voltage of the Schottky diode structure is greater than the gate turn-on voltage and less than the gate oxide layer breakdown voltage. Under normal working conditions, the on and off of the trench power device will not be affected by the Schottky diode structure; if the gate voltage exceeds the safe range, the integrated Schottky diode structure will turn on, and the current will be released through the PN junction in the Schottky diode structure, protecting the gate oxide layer from breakdown.

[0041] The thickness of the second epitaxial layer is 0.5 μm to 1.5 μm, and the depth of the trench gate structure in the first direction is less than 2 μm, wherein the depth of the trench gate structure in the first direction is greater than the thickness of the second epitaxial layer, so as to form a MOS structure.

[0042] In some optional embodiments, such as Figure 1 to Figure 2 As shown, the device further includes an implantation region 50 , which is located in the second epitaxial layer 22 and contacts a surface of the trench gate structure 30 away from the Schottky diode structure 40 , and has a first doping type.

[0043] Specifically, the injection region and the second epitaxial layer have different doping types, and both the injection region and the second epitaxial layer are in contact with the gate oxide of the trench gate structure, that is, the injection region, the second epitaxial layer and the trench gate structure constitute a MOS structure, wherein, by controlling the magnitude of the gate voltage, a channel is formed in the region where the second epitaxial layer contacts the gate oxide layer, thereby controlling the flow of electrons (or holes).

[0044] The doping concentration of the implanted region is 1.0×10 20 cm -3 ~1.0×1021 cm -3 The specific concentration is not limited in this application.

[0045] In some optional embodiments, such as Figure 1 to Figure 2 As shown, the gate oxide layer 32 includes a first region 321 and a second region 322. The first region 321 is located on the side of the gate 31 away from the Schottky diode structure 40, and the second region 322 is located on the side of the gate 31 close to the substrate 10. The first region 321 has a first thickness in the second direction B, and the second region 322 has a second thickness in the first direction A, and the first thickness is greater than the second thickness.

[0046] Specifically, in the trench MOS device, electric field concentration is likely to occur at the bottom of the trench gate due to the gate oxide quality and the trench corner, resulting in deterioration of the breakdown characteristics of the gate oxide layer at the bottom of the trench. In the above embodiment, by increasing the thickness of the first region of the gate oxide layer located at the bottom of the gate, the voltage resistance performance of the bottom of the trench is increased, which not only realizes the protection of the gate, but also avoids the voltage resistance failure of the gate oxide at the bottom of the trench, thereby improving the reliability of the trench gate structure, and further increasing the reliability of the trench MOS device.

[0047] The first thickness is 0.3 μm to 2 μm, which is not specifically limited in this application.

[0048] In some optional embodiments, the gate contacts any one of the first doping region or the second doping region, and the doping type of the doping region contacting the gate is different from the doping type of the gate.

[0049] Specifically, the contact between the gate and doping region of different doping types accelerates the speed of carriers and effectively improves the conductivity. In addition, the gate material has a high carrier affinity and has a strong attraction to carriers, which can generate carrier transport characteristics at the contact interface, thereby improving the performance of the device.

[0050] In some optional embodiments, the material of the gate may include doped polysilicon material, wherein the doping type includes P-type doping and N-type doping.

[0051] Exemplarily, the gate material is N-type polysilicon, and the doping region material in contact with the gate is P-type silicon carbide. Among them, N-type polysilicon has a higher electron mobility, and can improve the conductivity of the contact surface with P-type silicon carbide. N-type polysilicon has a higher hole affinity and a lower electron affinity, which can make the holes in P-type silicon carbide have a stronger attraction, produce a stronger transmission characteristic at the contact surface, and improve the performance of the device.

[0052] Among them, the work function of polysilicon can be accurately adjusted by adjusting the type and concentration of doping elements, thereby achieving precise control of the threshold voltage; polysilicon is process compatible with silicon and can be annealed at high temperatures, which helps to reduce defects at the contact surface between the gate and the trench and improve the reliability and stability of the device; during the high-temperature process, polysilicon can maintain stable performance and machinability, is not prone to melting or deformation, and will not have problems such as wafer breakage, thereby ensuring the preparation quality of the device.

[0053] In some optional embodiments, such as Figure 1 to Figure 2 As shown, the trench power device further includes: a plurality of conductive parts 60 , and the conductive parts 60 and the gate 31 are in contact with different doping regions 41 respectively.

[0054] In the above embodiments, there are isolation regions between the conductive parts.

[0055] Specifically, the multiple conductive parts are source electrodes of the trench power device, wherein the multiple conductive parts may include a first conductive part 61 and a second conductive part 62, wherein the first conductive part 61 contacts the doped region 41, and when the voltage of the gate 31 exceeds the safe range, the integrated Schottky diode structure 40 will be turned on, and the current will flow into the Schottky diode structure 40 through the doped region 41 in contact with the gate 31, and flow out through the first conductive part 61, so that the current is released; the second conductive part 62 contacts the gate 31 to provide the device with a gate voltage. The gate is connected in series to the source metal through an integrated SBD, which can ensure the normal operation of the device. In the case of high static electricity, the SBD is turned on, and the current is released through the source level, and static electricity will not break through the gate oxide.

[0056] Specifically, in the Schottky diode structure, the first doped region is in contact with the second doped region, and the contact surface of the two can form a PN junction, which has a unidirectional conduction effect. The conductive part and the gate are in contact with different doped regions respectively. The current can flow through the PN junction, so that the gate voltage is released, protecting the gate oxide layer from breakdown, and improving the anti-static ability of the trench gate structure.

[0057] Among them, in the Schottky diode structure, there can be multiple doped regions between the doped region in contact with the conductive part and the doped region in contact with the gate, that is, at least one PN junction is formed between the conductive part and the gate. In the case of one PN junction, a PN junction is formed between the doped region in contact with the conductive part and the doped region in contact with the gate; in the case of multiple PN junctions, multiple PN junctions form a series relationship, and current can flow through multiple series-connected PN junctions, thereby making full use of the series relationship of multiple PN junctions, reducing cost waste, and at the same time, saving chip area.

[0058] In some embodiments, the breakdown voltage of the Schottky diode structure can be adjusted by setting the number of doped regions between the conductive portion and the gate to protect the trench gate structure in different applications. This is because any two adjacent doped regions have different doping types, so that multiple groups of PN junctions in series can be formed in the Schottky diode structure. For example, there are 4 doped regions, the first doped region and the second doped region form a first group of PN junctions, the third doped region and the fourth doped region form a second group of PN junctions, and the first group of PN junctions and the second group of PN junctions form a series relationship. Trench power devices have different requirements for the breakdown voltage of Schottky diodes in different applications. For example, the application requires the Schottky diode structure to have a breakdown voltage of 36V. If the breakdown voltage of each group of PN junctions is the same and is 12V, a Schottky diode structure with 3 groups of PN junctions in series is required to protect the gate oxide layer from breakdown.

[0059] In some other embodiments, the conductive portion further includes a third conductive portion 63 , and the third conductive portion 63 is in contact with the implantation region 50 .

[0060] Specifically, the third conductive portion serves as a source and can provide current for the MOS structure.

[0061] In some specific embodiments, Figure 1 to Figure 2 As shown, the trench power device further includes a conductive layer 64 . The conductive layer 64 is located on a side of the substrate 10 away from the epitaxial layer 20 , and can serve as a drain electrode of the trench power device.

[0062] Specifically, the conductive part and the conductive layer both include conductive materials, and the conductive materials include but are not limited to any one of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals or alloy materials. The conductive part includes a layer of conductive material or multiple layers of conductive materials. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made in the application. In addition, the conductive layer and the conductive part of the present application may also include a multi-layer conductive structure, which is not specifically limited in the present application.

[0063] Furthermore, by selecting the material of the conductive part and the material of the conductive layer, the conductive part and the conductive layer can form an ohmic contact with the semiconductor material in contact to reduce the on-resistance of the device. Exemplarily, the material of the conductive part is a Ni / Ti / TiN / Al structure, wherein the thickness of each layer is 0.1μm~0.2μm / 0.1μm~0.2μm / 0.1μm~0.2μm / 3μm~6μm, respectively, the first conductive part contacts the first doped region to form an ohmic contact, the second conductive part contacts the gate to form an ohmic contact, the third conductive part contacts the injection region to form an ohmic contact, and the conductive layer contacts the substrate to form an ohmic contact.

[0064] In some specific embodiments, Figure 1 to Figure 2As shown, the device further includes an insulating portion 70, which is located in an isolation region between the plurality of conductive portions 60. The insulating portion 70 prevents the conductive portions from being short-circuited, thereby forming a protection circuit.

[0065] Specifically, the material of the insulating part includes but is not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide, and indium tin oxide. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0066] In some optional embodiments, the doping concentration of the doping region in contact with the conductive portion is greater than the doping concentration of the remaining doping regions.

[0067] Specifically, increasing the doping concentration of the doped region in contact with the conductive part can improve the conductivity between the metal and the semiconductor. In the doped region in contact with the conductive part, the higher the doping concentration, the higher the concentration of carriers therein, and the increase in carrier concentration will reduce the resistivity of the semiconductor, thereby improving its conductivity, that is, the higher the semiconductor doping concentration, the easier it is for the semiconductor material to conduct electricity.

[0068] In some optional embodiments, the doping type of the doping region in contact with the conductive portion is P type.

[0069] Specifically, the contact between the P-type doped region and the conductive part can improve the conductivity between the conductive part and the Schottky diode structure. When the P-type semiconductor contacts the metal, the free electrons in the metal will diffuse into the semiconductor and form a charge balance with the holes in the P-type doped region, so that the contact between the P-type doped region and the conductive part has a very small contact resistance, thus providing a good conductive channel and improving the conductive performance.

[0070] In some optional embodiments, the Schottky diode structure and the trench gate structure have the same depth in the first direction.

[0071] Specifically, in the first direction, the Schottky diode structure and the trench gate structure have the same depth, so that the bottom surface of the Schottky diode structure and the trench gate structure have the same bottom surface, and the trench gate structure and the Schottky diode structure can be formed in the same trench in terms of process, and the insulating region and the gate oxide layer are formed in the same process, which simplifies the preparation process and reduces the preparation cost. At the same time, the trench gate structure and the Schottky diode structure are formed in the same trench, so that the Schottky diode structure is integrated in the trench cell structure, which reduces the chip area and further reduces the manufacturing cost.

[0072] In some optional embodiments, the first doping regions have the same first width in the second direction, and / or the second doping regions have the same width in the second direction.

[0073] Specifically, the widths of the first doped regions are the same, and the widths of the second doped regions are the same. In the process of designing and adjusting the breakdown voltage of the PN junction formed by the first doped regions and the second doped regions, the design of the doped regions can be simplified; and the preparation process can be simplified.

[0074] In some optional embodiments, the doping concentration of the doping region having the same doping type as the first epitaxial layer is greater than the doping concentration of the first epitaxial layer, and the doping concentration of the doping region having the same doping type as the second epitaxial layer is greater than the doping concentration of the second epitaxial layer.

[0075] Specifically, in trench power devices, the epitaxial layer, as the voltage-resistant layer of the MOS structure, should have a lower doping concentration to ensure the voltage-resistant performance of the epitaxial layer, so the epitaxial layer has a smaller doping concentration. The doping concentration of the doping concentration cannot be lower than the doping concentration of the epitaxial layer to ensure that the Schottky diode structure can be normally turned on when the gate voltage exceeds the safe range, so as to protect the trench gate structure.

[0076] The doping concentration range of the first type doping region and the second type doping region is 1.0×10 17 cm -3 ~1.0×10 19 cm -3 .

[0077] In an embodiment of the present application, if the first doping region is P-type, the second doping region is N-type, or the first doping region is N-type, the second doping region is P-type, wherein N-type doping is the addition of pentavalent elements into the semiconductor material, and the pentavalent elements include but are not limited to phosphorus, arsenic and antimony; P-type doping is the addition of trivalent elements into the semiconductor material, and the trivalent elements include but are not limited to boron, aluminum and gallium. The specific doping elements are not specifically limited in this application.

[0078] Specifically, the doping concentration of the first doping region and the second doping region and the breakdown voltage of the PN formed by the two satisfy the formula: , where k is a constant, is the breakdown voltage of the PN junction, is the doping concentration of the first doping region, The above formula shows that the breakdown voltage of the PN junction is inversely proportional to the product of the doping concentrations of the first doping region and the second doping region, that is, when the doping concentrations of the first doping region and the second doping region increase, the breakdown voltage of the PN junction decreases.

[0079] In addition, the doping concentration of the first doping region and the doping concentration of the second doping region can also be adjusted by the above formula, so that the Schottky diode structure has different breakdown voltages to meet the gate protection requirements of different products. It should be noted that the above formula is a simplified formula, and the breakdown voltage of the PN junction is also affected by factors such as the properties, temperature and structure of the semiconductor material. Those skilled in the art will make adjustments according to the specific circumstances of the actual application.

[0080] In some optional embodiments, such as Figure 2 As shown, the surface of the doping region 41 close to the gate 31 has a plurality of first depths S in the second direction B, and the plurality of first depths S decreases along the direction from the gate 31 to the doping region 41 of the conductive portion 60 .

[0081] Specifically, in the above embodiment, the multiple first depths of the multiple doping regions decrease along the direction from the gate to the conductive portion, which can reduce the leakage current of the Schottky diode. When the PN junction is reverse biased, minority carriers will generate a reverse leakage current due to diffusion and drift. The leakage current of the PN junction is proportional to the contact area between the P region and the N region. Therefore, the multiple first depths decrease along the direction from the gate to the conductive portion, and the leakage current of the multiple groups of PN junctions decreases along the direction from the gate to the conductive portion, thereby reducing the leakage current of the Schottky diode structure.

[0082] According to another aspect of the present application, a method for preparing a trench power device is provided, which is used to prepare any trench power device, such as Figure 3 As shown, the preparation method comprises:

[0083] Step S101: providing a substrate;

[0084] Step S102: forming an epitaxial layer on one side of the substrate, the epitaxial layer comprising a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, the epitaxial layer having a first surface facing away from the substrate, and the first direction being perpendicular to the first surface;

[0085] Step S103: forming at least one trench gate structure in the epitaxial layer, wherein a surface of the trench gate structure facing away from the substrate is located in the first surface, and a surface of the trench gate structure close to the substrate is in contact with the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate has a first side surface and a second side surface arranged oppositely in a second direction, the gate oxide layer is respectively located on the first side surface of the gate and the gate oxide layer is located on a side of the gate close to the substrate, and the second direction is parallel to the first surface;

[0086] Step S104: forming a Schottky diode structure, the Schottky diode structure being in contact with at least the second side and the first epitaxial layer, the Schottky diode structure being located on the second side of the gate, the Schottky diode structure comprising a plurality of doping regions, the plurality of doping regions comprising a first doping region and a second doping region alternately arranged along a second direction, the first doping region and the second doping region having different doping types.

[0087] The above-mentioned preparation method of the embodiment of the present application is adopted, on the basis of the traditional trench power device, multiple epitaxial processes are adopted to realize the integration of Schottky diode structure on one side of the gate level, and the antistatic ability of the gate level is improved. Among them, a trench gate structure and a Schottky diode structure are formed in the trench, and the Schottky diode structure includes multiple doping regions, and the doping regions include a first doping region and a second doping region with different doping types, and the first doping region and the second doping region have different doping types, so that at least one PN junction is included in the Schottky diode structure, and the gate is in direct contact with the doping region. After the gate is applied with a voltage, a conduction circuit can be formed in the Schottky diode structure. When the gate voltage exceeds the safe range, the integrated Schottky diode structure will be turned on, and the current will be released through the PN junction in the Schottky diode structure, which can protect the gate oxide layer from being broken down, and improve the antistatic ability of the trench gate structure. In addition, one side of the gate is in contact with the doping region, and has a large contact area, which reduces the contact resistance between the gate and the doping region, so that the gate has a small switching energy consumption in high resistance or high frequency rental.

[0088] The following will describe in more detail the exemplary embodiments of the method for preparing the trench power device provided by the present application in conjunction with the accompanying drawings. However, these exemplary embodiments can be implemented in a variety of different forms and should be interpreted as being limited to the embodiments described herein. It should be understood that these embodiments are provided to make the disclosure of the present application thorough and complete, and to fully convey the concepts of these exemplary embodiments to those of ordinary skill in the art.

[0089] First, if Figure 4 As shown, step S101 is performed: providing a substrate 10 .

[0090] Specifically, the materials of the substrate 10 include silicon carbide, silicon, gallium nitride, gallium oxide, gallium arsenide, aluminum nitride and the like, and those skilled in the art can reasonably select them according to actual needs, and no specific limitation is made without application. The substrate has a first doping type.

[0091] Exemplarily, the substrate includes a doped SiC substrate to form an ohmic contact at the source, which can reduce the forward voltage drop of the diode structure and increase the breakdown voltage.

[0092] After providing the substrate, as Figure 5As shown, step S102 is performed: an epitaxial layer 20 is formed on one side of the substrate 10 .

[0093] Specifically, the epitaxial layer 20 includes a first epitaxial layer 21 and a second epitaxial layer 22 which are stacked, the first epitaxial layer 21 has a first doping type, and the second epitaxial layer 22 has a second doping type. The thickness of the second epitaxial layer is 0.5 μm to 1.5 μm.

[0094] In other optional embodiments, the process of forming the first epitaxial layer 21 and the second epitaxial layer 22 includes but is not limited to a deposition process and an epitaxial growth process. In the epitaxial growth process, the doping concentration of impurities is relatively easy to control and the activation rate is relatively fixed, so it is easy to achieve the target doping distribution. It is not only suitable for silicon-based power devices, but also can avoid the difficulty of injection doping of silicon carbide power devices and improve the efficiency of its terminal structure. The deposition process is relatively mature, simple to operate and has low cost. The deposition process includes but is not limited to physical vapor deposition (PVD), chemical vapor deposition (CVD) and atomic layer deposition (ALD). Physical vapor deposition (PVD) includes but is not limited to magnetron sputtering process, reactive sputtering process, DC sputtering process, AC sputtering process, vacuum coating process, arc evaporation process, and chemical vapor deposition (CVD) includes but is not limited to plasma enhanced chemical vapor deposition (PECVD), metal-organic chemical vapor deposition (MOCVD), and laser-induced chemical vapor deposition (LCVD). Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0095] After the epitaxial layer is formed, step S103 is performed: forming a trench gate structure.

[0096] Specifically, the steps of forming the trench gate structure may include: first, Figure 6 As shown, a first trench 81 is formed in the epitaxial layer 20 by an etching process, and the bottom surface of the first trench 81 exposes the first epitaxial layer 21; then, as shown in Figure 7 As shown, a trench gate structure 30 is formed on the sidewall of the first trench 81 , and the remaining area in the first trench 81 is a second trench 82 , wherein the trench gate structure 30 includes a gate 31 and a gate oxide layer 32 .

[0097] In some specific embodiments, Figure 8 As shown, the steps of forming the trench gate structure may include:

[0098] Step S1031: Figure 8 As shown in (a), a first trench 81 is formed in the epitaxial layer 20 by an etching process, and the bottom surface of the first trench 81 exposes the first epitaxial layer 21, wherein: Figure 8 (a) with Figure 6 The same preparation steps;

[0099] Step S1032: Figure 8 As shown in (b), an insulating material is filled in the first trench 81 by a deposition process to form a first insulating region 911;

[0100] Step S1033: Figure 8 As shown in (c), a first sub-trench 811 is formed in the first insulating region 911 by an etching process, and the remaining first insulating region constitutes a first insulating layer 91;

[0101] Step S1034: Figure 8 As shown in (d), a deposition process is used to fill the first sub-trench 811 with a gate material to form a gate material region 311;

[0102] Step S1035: Figure 8 As shown in (e), a second trench 82 is formed in the gate material region 311 by an etching process, and the second trench 82 exposes the bottom insulating layer, wherein: Figure 8 (e) with Figure 7 The preparation steps are the same.

[0103] In the above Figure 7 or Figure 8 After step (e), if Fig. 9 As shown in FIG. 1 , an insulating region 90 is formed on the sidewall of the second trench 82, and the remaining area in the second trench 82 is the third trench 83; then, as shown in FIG. Fig.10 As shown, the insulating region 90 on the sidewall of the third trench 83 and the insulating layer at the bottom of the third trench 83 are removed, and the remaining area in the third trench 83 is the fourth trench 84. The insulating region 90 serves as a sacrificial layer to protect the gate when the bottom insulating layer is removed.

[0104] The depth of the first trench is less than 2 μm, and the bottom surface of the first trench exposes the first epitaxial layer. In addition, the thickness of the first insulating layer located at the bottom surface of the first trench in the first direction is greater than the thickness of the first insulating layer located at the side wall of the first trench in the second direction, so as to ensure the anti-puncture capability of the bottom of the trench, and the thickness of the first insulating layer located at the side wall of the first trench in the second direction is 50 nm to 100 nm.

[0105] Specifically, the above-mentioned etching process includes but is not limited to dry etching and wet etching, wherein dry etching includes physical etching, chemical etching and chemical-physical etching, and physical etching includes ion beam etching, plasma etching, reactive ion etching, etc. Technical personnel in this field can make reasonable selections according to actual needs, and no specific limitation is made without application.

[0106] After the trench gate structure is formed, step S104 is performed: forming a Schottky diode structure.

[0107] Specifically, the steps of forming the Schottky diode structure include: using an epitaxial growth process in the following manner: Fig.10 A plurality of doping regions are formed in the fourth trench 84 shown in the figure, wherein the plurality of doping regions include a first doping region and a second doping region having different doping types. More specifically, the steps of forming the plurality of doping regions include: first, Fig.11 As shown in FIG. 12 , a first type doping region 4111 is formed in the fourth trench 84 by an epitaxial growth process; then, as shown in FIG. 12 , at least one fifth trench 85 is formed in the first type doping region 4111 by an etching process; then, as shown in FIG. Fig.13 As shown, the second doping region 412 is formed in the fifth trench 85 by using an epitaxial growth process, and the remaining first type doping region constitutes the first doping region 411 .

[0108] In some optional embodiments, such as Fig.14 As shown, the preparation method further includes step S105: forming an implantation region 50.

[0109] Specifically, the process of forming the second implantation region includes an ion implantation process. The implantation region and the second epitaxial layer have different doping types, and both the implantation region and the second epitaxial layer are in contact with the gate oxide of the trench gate structure, that is, the implantation region, the second epitaxial layer and the trench gate structure constitute a MOS structure, wherein, by controlling the magnitude of the gate voltage, a channel is formed in the region where the second epitaxial layer contacts the gate oxide layer, thereby controlling the flow of electrons (or holes). The doping concentration of the implantation region is 1.0×10 20 cm -3 ~1.0×10 21 cm -3 The specific concentration is not limited in this application.

[0110] In some optional implementations, the preparation method further includes step S106: forming a conductive portion.

[0111] Specifically, the steps of forming the conductive part include: first, Fig.15 As shown, in Fig.14 A dielectric material layer 71 is formed on the substrate as shown; then, Fig.16As shown, a plurality of through holes penetrating the dielectric material layer 71 are formed in the dielectric material layer 71 by an etching process, wherein the plurality of through holes include a first through hole 611, a second through hole 621 and a third through hole 631, the first through hole 611 exposes the doped region 41, the second through hole 621 exposes the gate 31, the third through hole 631 exposes the implanted region 50, and the remaining dielectric material layer 71 constitutes the insulating portion 70; then, as shown Figure 1 As shown, a plurality of conductive parts 60 are formed in a plurality of through holes by a deposition process, a first conductive part 61 is formed in the first through hole 611 , a second conductive part 62 is formed in the second through hole 621 , and a third conductive part 63 is formed in the third through hole 631 .

[0112] In the above embodiment, Figure 1 As shown, the preparation method further includes step S107: forming a conductive layer 64.

[0113] Specifically, a deposition process is used to deposit a conductive material on a side of the substrate 10 facing away from the epitaxial layer 20 to form a conductive layer 64 .

[0114] Specifically, the conductive part and the conductive layer both include conductive materials, and the conductive materials include but are not limited to any one of silver, copper, aluminum, gold, titanium, nickel, platinum and palladium metals or alloy materials. The conductive part includes a layer of conductive material or multiple layers of conductive materials. Those skilled in the art can make reasonable selections according to actual needs, and no specific limitation is made in the application. In addition, the conductive layer and the conductive part of the present application may also include a multi-layer conductive structure, which is not specifically limited in the present application.

[0115] Furthermore, by selecting the material of the conductive part and the material of the conductive layer, the conductive part and the conductive layer can form an ohmic contact with the semiconductor material in contact to reduce the on-resistance of the device. Exemplarily, the material of the conductive part is a Ni / Ti / TiN / Al structure, wherein the thickness of each layer is 0.1μm~0.2μm / 0.1μm~0.2μm / 0.1μm~0.2μm / 3μm~6μm, respectively, the first conductive part contacts the doped region to form an ohmic contact, the second conductive part contacts the gate to form an ohmic contact, the third conductive part contacts the injection region to form an ohmic contact, and the conductive layer contacts the substrate to form an ohmic contact.

[0116] Specifically, the material of the dielectric material or the insulating part includes but is not limited to any one or more of aluminum oxide, silicon oxide, aluminum nitride, titanium oxide, germanium oxide, gallium oxide, and indium tin oxide. Those skilled in the art can make reasonable selections based on actual needs, and no specific limitation is made without application.

[0117] The following will further illustrate a trench power device formed by the method for preparing a trench power device of the present application in conjunction with an embodiment.

[0118] The method for preparing a trench power device provided in this embodiment comprises the following steps:

[0119] Provide an N-type SiC substrate 10, such as Figure 4 As shown;

[0120] A first N-type epitaxial layer 21 and a second P-type epitaxial layer 22 are formed on an N-type SiC substrate 10 by using a double epitaxial growth process. The first N-type epitaxial layer 21 and the second P-type epitaxial layer 22 constitute an epitaxial layer 20. Figure 5 As shown;

[0121] A first trench 81 is formed in the epitaxial layer 20 by an etching process. Figure 8 (a) as shown;

[0122] The first trench 81 is filled with silicon oxide by a deposition process to form a first insulating region 911. Figure 8 (b) as shown;

[0123] The first sub-groove 811 is formed in the first insulating region 911 by an etching process, and the remaining first insulating region constitutes the first insulating layer 91. Figure 8 (c) as shown;

[0124] The first sub-trench 811 is filled with N-type polysilicon by a deposition process to form a gate material region 311, such as Figure 8 (d) as shown;

[0125] The second trench 82 is formed in the gate material region 311 by an etching process. The second trench 82 exposes the first insulating layer 91 at the bottom. The remaining gate material constitutes the gate 31. Figure 8 (e) as shown;

[0126] Silicon oxide is deposited on the sidewall of the second trench 82 to form an insulating region 90. The remaining area in the second trench 82 is the third trench 83. Fig. 9 As shown;

[0127] The insulating region 90 located on the sidewall of the third trench 83 and the first insulating region 911 located at the bottom of the third trench 83 are removed, and the remaining area in the third trench 83 is the fourth trench 84. Fig.10 As shown;

[0128] An epitaxial growth process is used to form P-type silicon carbide in the fourth trench 84 to form a first type doped region 4111, such as Fig.11 As shown;

[0129] Two fifth trenches 85 are formed in the first type doping region 4111 by etching process. Fig.12 As shown;

[0130] The fifth trench 85 is filled with N-type silicon carbide by an epitaxial growth process to form a second doping region 412, and the remaining first-type doping region constitutes a first doping region 411. Fig.13 As shown;

[0131] An N-type implantation region 50 is formed in the second epitaxial layer 22 near the trench gate structure 30 by an ion implantation process. Fig.14 As shown;

[0132] The deposition process is used in Fig.14 A silicon oxide layer is formed on the substrate as shown to form a dielectric material layer 71, as shown in FIG. Fig.15 As shown;

[0133] A plurality of through holes penetrating the dielectric material layer 71 are formed in the dielectric material layer 71 by etching process, wherein the plurality of through holes include a first through hole 611, a second through hole 621 and a third through hole 631, wherein the first through hole 611 exposes the first doped region 411, the second through hole 621 exposes the gate 31, and the third through hole 631 exposes the implantation region 50. Fig.16 As shown;

[0134] A deposition process is used to fill a plurality of through holes with Ni / Ti / TiN / Al material layers to form a plurality of conductive portions, wherein a first conductive portion 61 is formed in the first through hole 611, a second conductive portion 62 is formed in the second through hole 621, and a third conductive portion 63 is formed in the third through hole 631. Figure 1 As shown;

[0135] A conductive layer 64 of a Ni / Ti / Ni / Ag structure is formed on the side of the substrate 10 away from the epitaxial layer 20 by a deposition process. Figure 1 shown.

[0136] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0137] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A trench power device, characterized in that: include: substrate; An epitaxial layer, the epitaxial layer is located on one side of the substrate, the epitaxial layer includes a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer has a first doping type, the second epitaxial layer has a second doping type, the epitaxial layer has a first surface away from the substrate, and the first direction is perpendicular to the first surface; at least one trench gate structure, wherein the trench gate structure is located in the epitaxial layer, a surface of the trench gate structure facing away from the substrate is located in the first surface, a surface of the trench gate structure close to the substrate is in contact with the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate has a first side surface and a second side surface arranged oppositely in a second direction, the gate oxide layer is respectively located on the first side surface of the gate and the gate oxide layer is located on a side of the gate close to the substrate, and the second direction is parallel to the first surface; A Schottky diode structure, wherein the Schottky diode structure is in contact with at least the second side and the first epitaxial layer, the Schottky diode structure is located on the second side of the gate, the Schottky diode structure includes a plurality of doped regions, the plurality of doped regions include a first doped region and a second doped region alternately arranged along the second direction, the first doped region and the second doped region have different doping types.

2. The trench power device according to claim 1, characterized in that: The gate contacts any one of the first doping region or the second doping region, and a doping type of the doping region contacting the gate is different from a doping type of the gate.

3. The trench power device according to claim 1, characterized in that: The trench power device further comprises: A plurality of conductive parts, wherein the conductive parts and the gate are in contact with different doping regions respectively.

4. The trench power device according to claim 3, characterized in that: The doping concentration of the doping region in contact with the conductive portion is greater than the doping concentration of the remaining doping regions.

5. The trench power device according to claim 3, characterized in that: The doping type of the doping region contacting the conductive portion is P type.

6. The trench power device according to claim 1, characterized in that: The Schottky diode structure and the trench gate structure have the same depth in the first direction.

7. The trench power device according to claim 1, characterized in that: The width of the first doping region in the second direction is the same as the width of the first doping region.

8. A method for preparing a trench power device, characterized in that: Used to prepare the trench power device according to any one of claims 1 to 7, the preparation method comprising: providing a substrate; Forming an epitaxial layer on one side of the substrate, the epitaxial layer comprising a first epitaxial layer and a second epitaxial layer stacked along a first direction, the first epitaxial layer having a first doping type, the second epitaxial layer having a second doping type, the epitaxial layer having a first surface away from the substrate, and the first direction being perpendicular to the first surface; At least one trench gate structure is formed in the epitaxial layer, wherein a surface of the trench gate structure facing away from the substrate is located in the first surface, and a surface of the trench gate structure close to the substrate is in contact with the first epitaxial layer, the trench gate structure comprises a gate and a gate oxide layer, the gate has a first side surface and a second side surface that are oppositely arranged in a second direction, the gate oxide layer is respectively located on the first side surface of the gate and the gate oxide layer is located on a side of the gate close to the substrate, and the second direction is parallel to the first surface; A Schottky diode structure is formed, wherein the Schottky diode structure is in contact with at least the second side surface and the first epitaxial layer, and the Schottky diode structure is located on the second side surface of the gate. The Schottky diode structure includes a plurality of doped regions, and the plurality of doped regions include a first doped region and a second doped region alternately arranged along the second direction, and the first doped region and the second doped region have different doping types.

9. The preparation method according to claim 8, characterized in that: The steps of forming the trench gate structure and the Schottky diode structure include: Forming a first trench in the epitaxial layer by an etching process, wherein a bottom surface of the first trench exposes the first epitaxial layer; forming the trench gate structure on the sidewall of the first trench, and the remaining area in the first trench is the second trench; forming an insulating region on the sidewall of the second trench, and the remaining area in the second trench is a third trench; The second insulating layer located on the sidewall of the third trench and the first insulating layer located on the side of the second insulating layer close to the substrate are removed, and the remaining area in the third trench is the fourth trench; An epitaxial growth process is used to form a plurality of doping regions in the fourth trench, wherein the plurality of doping regions include the first doping region and the second doping region having different doping types.

10. The preparation method according to claim 9, characterized in that: The step of forming a plurality of the doped regions in the fourth trench by using an epitaxial growth process comprises: forming a first type doped region in the fourth trench by using an epitaxial growth process; forming at least one fifth trench in the first type doping region by an etching process; The second doping region is formed in the fourth trench by using an epitaxial growth process, and the remaining first type doping region constitutes the first doping region.

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