Display device and method of manufacturing same

Abstract

A display device and a method of manufacturing the same are provided. The display device includes a substrate including an emission area and a non-emission area, a pixel electrode positioned on the emission area of the substrate, a pixel defining layer positioned on the pixel electrode, overlapping the non-emission area, and having a first opening defined therein, a bank structure positioned on the pixel defining layer, an auxiliary electrode positioned on the non-emission area, and a common electrode positioned on the non-emission area and having a second opening defined therein, a bank structure positioned on the pixel defining layer and having a second opening defined therein, an auxiliary electrode positioned on the bank structure and including a conductive material, a common electrode positioned on the pixel electrode and contacting the auxiliary electrode in the second opening, and wherein the bank structure includes a first bank layer and a second bank layer including conductive materials different from each other, the second bank layer includes a tip protruding from a side surface of the first bank layer toward the first opening, and the auxiliary electrode completely covers the tip of the second bank layer.

Description

[0001] This application claims priority to and all benefits derived from Korean Patent Application No. 10-2023-0099641, filed on Jul. 31, 2023, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0002] The present disclosure relates to a display device and a method of manufacturing the display device. Background Art

[0003] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. For example, display devices are applied to various electronic devices, such as smart phones, digital cameras, notebook computers, navigation devices, and smart TVs. The display device may be a flat panel display device, such as a liquid crystal display device, a field emission display device, and an organic light emitting display device. Among these flat panel display devices, the light emitting display device includes a light emitting element that enables each pixel of the display panel to emit light by itself. Therefore, the light emitting display device can display an image without a backlight unit that provides light to the display panel. Summary of the invention

[0004] Aspects of the present disclosure provide a display device that physically protects a bank structure during a manufacturing process.

[0005] Aspects of the present disclosure also provide a display device having reduced driving resistance.

[0006] However, aspects of the present disclosure are not limited to the aspects described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art by referring to the detailed description of the present disclosure given below.

[0007] In an embodiment of the present disclosure, a display device includes a substrate, a pixel electrode, a pixel defining layer, a dam structure, an auxiliary electrode and a common electrode, the substrate including an emission area and a non-emission area, the pixel electrode is positioned on the emission area of ​​the substrate, the pixel defining layer is positioned on the pixel electrode, overlaps with the non-emission area and defines a first opening therein, the dam structure is positioned on the pixel defining layer and defines a second opening therein, the auxiliary electrode is positioned on the dam structure and includes a conductive material, the common electrode is positioned on the pixel electrode and contacts the auxiliary electrode in the second opening, wherein the dam structure may include a first dam layer and a second dam layer including conductive materials different from each other, the second dam layer includes a tip protruding from a side surface of the first dam layer toward the first opening, and the auxiliary electrode completely covers the tip of the second dam layer.

[0008] In an embodiment, the second embankment layer may include a first surface facing the substrate, a second surface facing the first surface, and a side surface opposite to the first opening and connecting the first surface and the second surface, and the auxiliary electrode overlaps with the tip of the second embankment layer to contact the first surface, the side surface and the second surface of the second embankment layer.

[0009] In embodiments, the auxiliary electrode may contact and completely cover the second surface of the second bank layer.

[0010] In embodiments, the auxiliary electrode may contact and completely cover a side surface of the first bank layer.

[0011] In an embodiment, the bank structure may be completely surrounded by the pixel defining layer and the auxiliary electrode.

[0012] In an embodiment, the auxiliary electrode may be a crystalline transparent oxide.

[0013] In an embodiment, the first bank layer may include aluminum (Al), and the second bank layer may include titanium (Ti).

[0014] In an embodiment, the display device may further include a light emitting layer positioned between the pixel electrode and the common electrode, wherein the light emitting layer contacts the auxiliary electrode in the second opening.

[0015] In an embodiment, the auxiliary electrode may include a first portion contacting the light emitting layer and a second portion contacting the common electrode, and a width of the second portion is greater than a width of the first portion in a direction perpendicular to a main surface of the substrate.

[0016] In an embodiment, the display device may further include an organic pattern and an electrode pattern, the organic pattern overlapping with the tip of the second bank layer, positioned on the auxiliary electrode and containing the same material as the light-emitting layer, the electrode pattern positioned on the organic pattern and containing the same material as the common electrode, wherein the organic pattern is separated from the light-emitting layer, and the electrode pattern is separated from the common electrode.

[0017] In an embodiment, the display device may further include an encapsulation layer positioned on the common electrode and the electrode pattern, wherein the encapsulation layer contacts the auxiliary electrode on a side surface of the first bank layer.

[0018] In an embodiment, the display device may further include a pattern positioned between the pixel defining layer and the pixel electrode and overlapping with the tip of the second embankment layer in a direction perpendicular to the main surface of the substrate, wherein the pattern overlaps with the auxiliary electrode in a direction perpendicular to the main surface of the substrate.

[0019] In an embodiment of the present disclosure, a display device includes a substrate, a first pixel electrode, a pixel defining layer, a second pixel electrode, a dam structure and an auxiliary electrode, the substrate including a first emission region, a second emission region and a non-emission region positioned between the first emission region and the second emission region, the first pixel electrode overlaps with the first emission region and is positioned on the substrate, the pixel defining layer overlaps with the non-emission region and is positioned on the first pixel electrode, the second pixel electrode overlaps with the second emission region and is separated from the first pixel electrode by the pixel defining layer, the dam structure is positioned on the pixel defining layer, and the auxiliary electrode is positioned on the pixel defining layer and the dam structure, wherein the auxiliary electrode includes a first portion overlapping with the first emission region, a second portion overlapping with the second emission region and a third portion overlapping with the non-emission region, and the first and second portions of the auxiliary electrode extend from the third portion, and the third portion of the auxiliary electrode completely covers the upper surface of the dam structure.

[0020] In an embodiment, the embankment structure may include a first embankment layer and a second embankment layer, the second embankment layer may include a tip protruding from a side surface of the first embankment layer toward the first emission region and the second emission region, respectively, and the first and second portions of the auxiliary electrode completely cover the tip of the second embankment layer, respectively.

[0021] In an embodiment, the display device may further include a first common electrode positioned on the first pixel electrode and a second common electrode positioned on the second pixel electrode, wherein the first common electrode and the second common electrode may be separated from each other by a dam structure, the first common electrode may contact a first portion of the auxiliary electrode, and the second common electrode may contact a second portion of the auxiliary electrode.

[0022] In an embodiment, the display device may further include a first inorganic layer covering the first common electrode and a second inorganic layer covering the second common electrode, wherein the first inorganic layer and the second inorganic layer overlap the third portion of the auxiliary electrode and are spaced apart from each other.

[0023] In an embodiment, the display device may further include an organic encapsulation layer positioned on the first inorganic layer and the second inorganic layer, wherein the third portion of the auxiliary electrode may contact the organic encapsulation layer.

[0024] In an embodiment of the present disclosure, a method for manufacturing a display device includes: forming a plurality of pixel electrodes spaced apart from each other on a substrate, a sacrificial layer arranged on the pixel electrodes, a pixel defining layer arranged on the sacrificial layer, and a first embankment material layer and a second embankment material layer arranged on the pixel defining layer; forming a first hole overlapping the pixel electrode and passing through the first embankment material layer and the second embankment material layer to expose the pixel defining layer arranged on the pixel electrode; forming a tip of the second embankment material layer protruding from the sidewall of the first embankment material layer by wet etching the sidewall of the first hole; forming an auxiliary electrode material layer covering the pixel defining layer, the first embankment material layer, and the second embankment material layer; and An opening is formed by removing a portion of the auxiliary electrode material layer overlapping with the pixel electrode, removing a portion of the pixel defining layer overlapping with the pixel electrode by dry etching, and removing a portion of the sacrificial layer overlapping with the pixel electrode by wet etching, and exposing the pixel electrode overlapping with the opening; performing high-temperature heat treatment on the auxiliary electrode material layer covering the first embankment material layer and the second embankment material layer; forming a light-emitting layer and a common electrode on each of the pixel electrodes in the opening, and forming an inorganic layer on the common electrode and the auxiliary electrode material layer; and partially removing a portion of the inorganic layer arranged on the auxiliary electrode material layer, wherein the auxiliary electrode material layer completely covers the tip of the second embankment material layer.

[0025] In an embodiment, the auxiliary electrode material layer may be transformed into a crystalline transparent oxide by a high temperature heat treatment.

[0026] In an embodiment, the first bank material layer and the second bank material layer may be completely surrounded by the pixel defining layer and the auxiliary electrode material layer.

[0027] The display device according to the embodiment may include an auxiliary electrode covering the bank structure. Etching of the bank structure can be prevented during a process of manufacturing the display device, and a driving resistance of the display device can be reduced.

[0028] It should be noted that the effects of the present disclosure are not limited to the above-mentioned effects, and other effects of the present disclosure will be apparent to those skilled in the art through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] These and / or other aspects will become apparent and more readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, in which:

[0030] Figure 1 is a perspective view of a display device according to an embodiment;

[0031] Figure 2 is a plan view of a display panel and a display driver according to an embodiment;

[0032] Figure 3 is a perspective view of a display device according to an embodiment;

[0033] Figure 4 is along Figure 1 A cross-sectional view of the display device taken along line Y1-Y1';

[0034] Figure 5 yes Figure 4 A cross-sectional view of a display device in which a bending area is bent;

[0035] Figure 6 is a plan view showing the arrangement of emission areas in a display area;

[0036] Figure 7 is along Figure 6 A cross-sectional view of the display device taken along line X1-X1';

[0037] Figure 8 yes Figure 7 an enlarged cross-sectional view of a first emission region;

[0038] Fig. 9 yes Figure 7 an enlarged cross-sectional view of area "A";

[0039] Fig.10 yes Fig. 9 An enlarged cross-sectional view of a first portion of an auxiliary electrode;

[0040] Fig.11 yes Fig. 9 An enlarged cross-sectional view of a second portion of the auxiliary electrode;

[0041] Fig.12 yes Figure 2 An enlarged plan view of area "Q";

[0042] Fig.13 is along Fig.12 A cross-sectional view of the display device taken along line Q1-Q1'; and

[0043] Figures 14 to 24 are cross-sectional views sequentially illustrating a portion of a display region during a process of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0044] The terms used herein are only for the purpose of describing a particular embodiment and are not intended to be limiting. Unless the context clearly indicates otherwise, "one", "the", "at least one" as used herein do not represent the limitation of quantity, and are intended to include both the singular and the plural. For example, unless the context clearly indicates otherwise, "element" has the same meaning as "at least one element". "At least one" will not be interpreted as being limited to "one" or "one". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. It should also be understood that the terms "include" and / or "include" or "include" and / or "include" when used in this specification specify the existence of stated features, regions, entireties, steps, operations, elements and / or parts, but do not exclude the existence or addition of one or more other features, regions, entireties, steps, operations, elements, parts and / or their groups.

[0045] Now the present invention will be described more fully below with reference to the accompanying drawings in which preferred embodiments of the present invention are shown. However, the present invention can be implemented in different forms and should not be construed as being limited to the embodiments set forth herein. On the contrary, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. Throughout the specification, the same reference numerals indicate the same components. In the accompanying drawings, for clarity, the thickness of the layers and zones is magnified.

[0046] It should also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on another layer or substrate, or there may also be an intervening layer. On the contrary, when an element is referred to as being "directly" "on" another element, there is no intervening element. In addition, relative terms such as "lower" or "bottom" and "upper" or "top" may be used herein to describe the relationship between an element and another element as shown in the figure. It should be understood that, in addition to the orientations depicted in the figure, relative terms are also intended to cover different orientations of the device. For example, if the device in one of the figures is turned over, the element described as being located on the "lower" side of the other elements will then be oriented to be located on the "upper" side of the other elements. Therefore, the term "lower" can cover both the "lower" and "upper" orientations depending on the specific orientation of the figure. Similarly, if the device in one of the figures is turned over, the element described as being "below" or "below" the other elements will then be oriented to be "above" the other elements. Therefore, the term "lower" or "under" can cover both the orientations above and below.

[0047] It should be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element, or to facilitate its description and explanation. For example, when discussing a "first element" in the description, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner without departing from the teachings herein.

[0048] Each of the various embodiments of the present invention may be partially or fully combinable or combined with each other, various interlocks and drives are technically possible, and each embodiment may be able to be performed independently relative to each other or may be implemented together in a linked relationship.

[0049] As used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation range for a particular value as determined by one of ordinary skill in the art, taking into account the errors associated with the measurements and the measurements of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, or ±5% of the stated value. Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings.

[0050] Figure 1 is a perspective view of a display device 10 according to the embodiment. Figure 2 1 is a plan view of the display panel 100 and the display driver 200 according to the embodiment. As used herein, a “plan view” is a view in the thickness direction (Z-axis direction) of the substrate 110 .

[0051] Reference Figure 1 and Figure 2 The display device 10 according to the embodiment is a device for displaying a moving image or a still image. The display device 10 can be used as a display screen in portable electronic devices such as mobile phones, smart phones, tablet personal computers ("PCs"), smart watches, watch phones, mobile communication terminals, electronic notepads, electronic books, portable multimedia players ("PMPs"), navigation devices, and ultra mobile PCs ("UMPCs"), as well as in various products such as televisions, notebook computers, monitors, billboards, and Internet of Things ("IoT") devices.

[0052] The display device 10 according to the embodiment may be a light-emitting display device, such as an organic light-emitting display device using an organic light-emitting diode, a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, or a micro or nano light-emitting display device using a micro or nano light-emitting diode. The following will mainly describe the case where the display device 10 is an organic light-emitting display device, but the present disclosure is not limited thereto.

[0053] The display device 10 according to the embodiment may include a display panel 100 , a display driver 200 , and a circuit board 300 .

[0054] The display panel 100 may be shaped like a rectangular plane having a long side in a first direction (X-axis direction) and a short side in a second direction (Y-axis direction) intersecting the first direction (X-axis direction). Each corner where the long side extending in the first direction (X-axis direction) intersects the short side extending in the second direction (Y-axis direction) may be a right angle or may be rounded with a curvature. The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may also be other polygonal shapes, circular shapes, or elliptical shapes. In the accompanying drawings, the first direction (X-axis direction) and the second direction (Y-axis direction) are horizontal directions intersecting each other. For example, the first direction (X-axis direction) and the second direction (Y-axis direction) may be orthogonal to each other. In addition, the third direction (Z-axis direction) may intersect with the first direction (X-axis direction) and the second direction (Y-axis direction), for example, it may be a vertical direction orthogonal to the first direction (X-axis direction) and the second direction (Y-axis direction). In this specification, a direction indicated by an arrow from each of the first direction to the third direction (X-axis direction, Y-axis direction, and Z-axis direction) may be referred to as one side, and the opposite direction may be referred to as the other side.

[0055] The display panel 100 may be formed to be flat, but the present disclosure is not limited thereto. For another example, the display panel 100 may include a bent portion formed at the left and right ends and having a constant or varying curvature. In addition, the display panel 100 may be formed to be flexible so that it can be bent, curved, folded, or rolled.

[0056] The display panel 100 may include a main area MA, a bending area BA, and a pad area PDA. The main area MA may include a display area DA displaying an image and a non-display area NDA disposed around the display area DA.

[0057] The display area DA may occupy most of the area of ​​the display panel 100. The display area DA may be disposed at the center of the display panel 100. Pixels including emission areas may be respectively disposed in the display area DA to display an image.

[0058] The non-display area NDA may be adjacent to the display area DA. The non-display area NDA may be an area outside the display area DA. The non-display area NDA may surround the display area DA. The non-display area NDA may be an edge area of ​​the display panel 100.

[0059] The bending area BA may be arranged between the display area DA and the pad area PDA in the second direction (Y-axis direction). The bending area BA may extend in the first direction (X-axis direction). The bending area BA is an area bent toward the bottom of the display panel 100. When the bending area BA is bent toward the bottom of the display panel 100, the display driver 200 and the circuit board 300 may be arranged under the display panel 100.

[0060] The pad area PDA may be a lower edge area of ​​the display panel 100. The pad area PDA may include a display driver 200, a display pad PD, and a circuit board 300.

[0061] The display driver 200 may be arranged in the pad area PDA. The display driver 200 may be arranged in the non-display area NDA located between the display pad PD and the display area DA. Each of the display drivers 200 may be attached to the non-display area NDA of the display panel 100 using a chip on glass (“COG”) method. In an embodiment, each of the display drivers 200 may also be attached to the circuit board 300 using a chip on plastic (“COP”) method.

[0062] The circuit board 300 may be arranged on the display pad PD arranged on the edge of the display panel 100. The circuit board 300 may be attached to the display pad PD using a conductive adhesive member such as an anisotropic conductive film or an anisotropic conductive adhesive. Thus, the circuit board 300 may be electrically connected to the signal line of the display panel 100. Each of the circuit boards 300 may be a flexible printed circuit board or a flexible film such as a chip on film.

[0063] Figure 3 is a perspective view of a display device 30 according to the embodiment.

[0064] Reference Figure 3 , the shape of the display panel 100 included in the display device 30 may be different from the shape of the display panel 100 included in the display device 10. In an embodiment, for example, in the display panel 100 included in the display device 30, the length of the main area MA in the first direction (X-axis direction) may be greater than the length of the bending area BA and the pad area PDA in the first direction (X-axis direction). The bending area BA and the pad area PDA may protrude from a portion of one side of the main area MA. The shape of the display panel 100 is not limited to Figures 1 to 3 The shape shown in , and may vary according to the type of the display device 10 .

[0065] Figure 4 is along Figure 1 A cross-sectional view of the side of the display device 10 taken along line Y1-Y1'.

[0066] Reference Figure 4The display device 10 may include a display panel 100, a color filter layer 190, a display driver 200, and a circuit board 300. The display panel 100 may include a substrate 110, a thin film transistor layer 130, a light emitting element layer 150, a thin film encapsulation layer 170, and a touch sensor layer 180.

[0067] The substrate 110 may be a base substrate or a base member. The substrate 110 may be a flexible substrate that can be bent, folded, curled, etc. In an embodiment, for example, the substrate 110 may include a polymer resin such as polyimide ("PI"), but the present disclosure is not limited thereto. For another example, the substrate 110 may include a glass material or a metal material.

[0068] The thin film transistor layer 130 may be arranged on the substrate 110. The thin film transistor layer 130 may include a plurality of thin film transistors. Each of the thin film transistors may include a semiconductor region, a source electrode, a drain electrode, and a gate electrode. In addition, the thin film transistor layer 130 may further include a gate line, a data line, a power line, a gate control line, a fan-out line connecting the display driver 200 and the data line, and a lead connecting the display driver 200 and the pad unit. In an embodiment, for example, when the gate driver is arranged on one side of the non-display area NDA of the display panel 100, it may include a thin film transistor.

[0069] The thin film transistor layer 130 may be arranged in the main area MA, the bending area BA, and the pad area PDA. The thin film transistors, gate lines, data lines, and power lines of the thin film transistor layer 130 may be arranged in the display area DA of the main area MA. The gate control lines and fan-out lines of the thin film transistor layer 130 may be arranged in the non-display area NDA of the main area MA. In addition, the leads of the thin film transistor layer 130 may be arranged in the bending area BA and the pad area PDA.

[0070] The light emitting element layer 150 may be disposed on the thin film transistor layer 130. The light emitting element layer 150 may include a plurality of light emitting elements each including a pixel electrode, a light emitting layer, and a common electrode to emit light, a pixel defining layer, and a bank structure.

[0071] In an embodiment, the light-emitting layer may include an organic light-emitting layer including an organic material. The light-emitting layer may include a hole transport layer, an organic light-emitting layer, and an electron transport layer. When the pixel electrode receives a voltage through the thin film transistor of the thin film transistor layer 130 and the common electrode receives a cathode voltage, holes and electrons may move to the organic light-emitting layer through the hole transport layer and the electron transport layer, respectively. Then, the holes and electrons may combine with each other in the organic light-emitting layer to emit light. In an embodiment, each of the light-emitting elements may include a quantum dot light-emitting diode including a quantum dot light-emitting layer, an inorganic light-emitting diode including an inorganic semiconductor, or a micro light-emitting diode.

[0072] The thin film encapsulation layer 170 may cover the upper surface and the side surface of the light emitting element layer 150 and may protect the light emitting element layer 150. The thin film encapsulation layer 170 may include at least one inorganic layer and at least one organic layer to encapsulate the light emitting element layer 150.

[0073] The touch sensor layer 180 may be arranged on the thin film encapsulation layer 170. The touch sensor layer 180 may include a plurality of touch electrodes and a plurality of touch lines for sensing the touch of a user in a capacitive manner. In an embodiment, for example, the touch sensor layer 180 may sense the touch of a user in a mutual capacitance manner or a self-capacitance manner. The touch electrodes of the touch sensor layer 180 may be arranged in a touch sensor area overlapping the display area DA. The touch lines of the touch sensor layer 180 may be arranged in a touch peripheral area overlapping the non-display area NDA.

[0074] The color filter layer 190 may be arranged on the touch sensor layer 180. The color filter layer 190 may include a plurality of color filters corresponding to the plurality of emission regions, respectively. Each of the color filters may selectively transmit light of a specific wavelength and block or absorb light of other wavelengths. The color filter layer 190 may absorb a portion of the light from outside the display device 10, thereby reducing reflected light caused by external light. Therefore, the color filter layer 190 can prevent color distortion caused by reflection of external light.

[0075] Since the color filter layer 190 is directly disposed on the touch sensor layer 180 , the display device 10 may not require a separate substrate for the color filter layer 190 .

[0076] Reference Figure 5 , the pad area PDA of the display device 10 may be bent by the bending area BA. When the pad area PDA is bent by the bending area BA, the display driver 200 and the circuit board 300 positioned in the pad area PDA may overlap the main area MA in the third direction (Z-axis direction).

[0077] Figure 6 is a plan view showing the arrangement of the emission areas EA1 to EA3 in the display area DA.

[0078] Reference Figure 6 , the display device 10 may include a plurality of emission areas EA1 to EA3 and a non-emission area NLA arranged in the display area DA.

[0079] The emission areas EA1 to EA3 may include a first emission area EA1, a second emission area EA2, and a third emission area EA3 that emit light of different colors. Each of the emission areas EA1 to EA3 may emit red light, green light, or blue light, and the color of the light emitted from each of the emission areas EA1 to EA3 may be determined according to the light emitting element ED1, ED2, or ED3 (see FIG. 1 ) to be described later. Figure 7 ). In an embodiment, the first emission area EA1 may emit a red first light, the second emission area EA2 may emit a green second light, and the third emission area EA3 may emit a blue third light. However, the present disclosure is not limited thereto.

[0080] The emission areas EA1 to EA3 can be arranged as Type, for example, diamond Type. In an embodiment, for example, the first emission area EA1 and the third emission area EA3 may be spaced apart from each other in the first direction (X-axis direction) and the second direction (Y-axis direction) and may be alternately arranged in the first direction (X-axis direction) and the second direction (Y-axis direction). In the arrangement of the emission areas EA1 to EA3, the first emission area EA1 and the third emission area EA3 may be alternately arranged in the first direction (X-axis direction) in the first row R1 and the third row R3. The first emission area EA1 and the third emission area EA3 may be alternately arranged in the second direction (Y-axis direction) in the first column C1 and the third column C3.

[0081] Each of the second emission areas EA2 may be spaced apart from other adjacent second emission areas EA2 in the first direction (X-axis direction) and the second direction (Y-axis direction), and may be spaced apart from the adjacent first emission areas EA1 and the third emission areas EA3 in the fourth direction DR4 or the fifth direction DR5. The second emission areas EA2 may be repeatedly arranged along the first direction (X-axis direction) and the second direction (Y-axis direction). The second emission areas EA2 and the first emission areas EA1 or the second emission areas EA2 and the third emission areas EA3 may be alternately arranged along the fourth direction DR4 or the fifth direction DR5. In the arrangement of the emission areas EA1 to EA3, the second emission areas EA2 may be repeatedly arranged in the first direction (X-axis direction) in the second row R2 and the fourth row R4, and may be repeatedly arranged in the second direction (Y-axis direction) in the second column C2 and the fourth column C4.

[0082] Each of the first to third emission areas EA1 to EA3 may be formed by an inorganic pixel defining layer 151 (see FIG. 1 ) to be described later. Figure 7 ) and dike structure 160 (see Figure 7 ) is defined by a first opening OP1 and a second opening OP2 formed.

[0083] The non-emission area NLA may surround the emission areas EA1 to EA3. The non-emission area NLA may be an area from which light is not emitted. The inorganic pixel defining layer 151 and the light blocking layer BM (see Figure 7 ) can be positioned in the non-emitting area NLA.

[0084] Figure 7 is along Figure 6 1 is a cross-sectional view of the display device 10 taken along line X1 - X1 ′.

[0085] Reference Figure 7 , the display panel 100 may include a substrate 110 , a thin film transistor layer 130 , a light emitting element layer 150 , a thin film encapsulation layer 170 , and a touch sensor layer 180 .

[0086] Since the substrate 110 has been mentioned, a description thereof will be omitted.

[0087] The thin film transistor layer 130 may include a first buffer layer 111, a bottom metal layer BML, a second buffer layer 113, a thin film transistor TFT, a gate insulating layer 131, a first interlayer insulating layer 133, a capacitor electrode CPE, a second interlayer insulating layer 135, a first connection electrode CNE1, a first passivation layer 137, a second connection electrode CNE2 and a second passivation layer 139.

[0088] The first buffer layer 111 may be disposed on the substrate 110. The first buffer layer 111 may include an inorganic layer capable of preventing penetration of air or moisture. In an embodiment, for example, the first buffer layer 111 may include a plurality of inorganic layers alternately stacked.

[0089] The bottom metal layer BML may be disposed on the first buffer layer 111. In an embodiment, for example, each of the bottom metal layers BML may be a single layer or a multilayer made of any one or more of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), copper (Cu), and alloys thereof.

[0090] The second buffer layer 113 may cover the first buffer layer 111 and the bottom metal layer BML. The second buffer layer 113 may include an inorganic layer capable of preventing penetration of air or moisture. In an embodiment, for example, the second buffer layer 113 may include a plurality of inorganic layers alternately stacked.

[0091] The thin film transistor TFT may be arranged on the second buffer layer 113. The thin film transistor TFT may constitute a corresponding pixel circuit of a plurality of pixels. In an embodiment, for example, each of the thin film transistors TFT may be a driving transistor or a switching transistor of a pixel circuit. Each of the thin film transistors TFT may include a semiconductor layer ACT, a source electrode SE, a drain electrode DE, and a gate electrode GE.

[0092] The semiconductor layer ACT may be disposed on the second buffer layer 113. The semiconductor layer ACT may overlap the bottom metal layer BML and the gate electrode GE in the third direction (Z-axis direction), and may be insulated from the gate electrode GE by the gate insulating layer 131. In a portion of the semiconductor layer ACT, the material of the semiconductor layer ACT may be made conductive to form the source electrode SE and the drain electrode DE.

[0093] The gate electrode GE may be disposed on the gate insulating layer 131. In a cross-sectional view, the gate electrode GE may overlap the semiconductor layer ACT with the gate insulating layer 131 interposed therebetween.

[0094] The gate insulating layer 131 may be disposed on the semiconductor layer ACT. In an embodiment, for example, the gate insulating layer 131 may cover the semiconductor layer ACT and the second buffer layer 113 and may insulate the semiconductor layer ACT from the gate electrode GE. The gate insulating layer 131 may include a contact hole through which the first connection electrode CNE1 passes.

[0095] The first interlayer insulating layer 133 may cover the gate electrode GE and the gate insulating layer 131. The first interlayer insulating layer 133 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the first interlayer insulating layer 133 may be connected to the contact hole of the gate insulating layer 131 and the contact hole of the second interlayer insulating layer 135.

[0096] The capacitor electrode CPE may be disposed on the first interlayer insulating layer 133. The capacitor electrode CPE may overlap the gate electrode GE in the thickness direction (Z-axis direction) of the substrate 110. The capacitor electrode CPE and the gate electrode GE may form a capacitance.

[0097] The second interlayer insulating layer 135 may cover the capacitor electrode CPE and the first interlayer insulating layer 133. The second interlayer insulating layer 135 may include a contact hole through which the first connection electrode CNE1 passes. The contact hole of the second interlayer insulating layer 135 may be connected to the contact hole of the first interlayer insulating layer 133 and the contact hole of the gate insulating layer 131.

[0098] The first connection electrode CNE1 may be disposed on the second interlayer insulating layer 135. The first connection electrode CNE1 may electrically connect the drain electrode DE of the thin film transistor TFT to the second connection electrode CNE2. The first connection electrode CNE1 may be inserted into a contact hole defined in the second interlayer insulating layer 135, the first interlayer insulating layer 133, and the gate insulating layer 131 to contact the drain electrode DE of the thin film transistor TFT.

[0099] The first passivation layer 137 may cover the first connection electrode CNE1 and the second interlayer insulating layer 135. The first passivation layer 137 may protect the thin film transistor TFT. The first passivation layer 137 may include a contact hole through which the second connection electrode CNE2 passes.

[0100] The second connection electrode CNE2 may be disposed on the first passivation layer 137. The second connection electrode CNE2 may electrically connect the first connection electrode CNE1 to the pixel electrodes AE1 to AE3 of the light emitting elements ED1 to ED3. The second connection electrode CNE2 may be inserted into a contact hole defined in the first passivation layer 137 to contact the first connection electrode CNE1.

[0101] The second passivation layer 139 may cover the second connection electrode CNE2 and the first passivation layer 137. The second passivation layer 139 may include contact holes through which the pixel electrodes AE1 to AE3 of the light emitting elements ED1 to ED3 pass.

[0102] The light emitting element layer 150 may be disposed on the thin film transistor layer 130. The light emitting element layer 150 may include light emitting elements ED1 to ED3, an inorganic pixel defining layer 151, a bank structure 160, and an auxiliary electrode AXE.

[0103] The light emitting elements ED1 to ED3 may be disposed on the second passivation layer 139. The light emitting elements ED1 to ED3 may include pixel electrodes AE1 to AE3, light emitting layers EL1 to EL3, and common electrodes CE1 to CE3.

[0104] The pixel electrodes AE1 to AE3 may be arranged in the emission areas EA1 to EA3, respectively. The pixel electrodes AE1 to AE3 may include a first pixel electrode AE1 arranged in the first emission area EA1, a second pixel electrode AE2 arranged in the second emission area EA2, and a third pixel electrode AE3 arranged in the third emission area EA3. The pixel electrodes AE1 to AE3 may be spaced apart from each other on the second passivation layer 139. The pixel electrodes AE1 to AE3 may be arranged in different emission areas EA1 to EA3 to respectively form light emitting elements ED1 to ED3 for emitting light of different colors.

[0105] The pixel electrodes AE1 to AE3 may be electrically connected to the drain electrode DE of the thin film transistor TFT through the first connection electrode CNE1 and the second connection electrode CNE2. In an embodiment, the pixel electrodes AE1 to AE3 may include a material such as indium tin oxide ("ITO"), indium zinc oxide ("IZO"), zinc oxide (ZnO), or indium oxide (In 2 O 3 ) and a stacked structure of a reflective material layer such as silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), lead (Pb), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), lithium (Li), calcium (Ca) or a mixture thereof. The material layer with a high work function may be arranged on the reflective material layer so that it is positioned close to the light-emitting layers EL1 to EL3. In an embodiment, for example, the pixel electrodes AE1 to AE3 may have ITO / Mg, ITO / MgF 2 , ITO / Ag or ITO / Ag / ITO multilayer structure, but not limited thereto.

[0106] The inorganic pixel defining layer 151 may be positioned on the second passivation layer 139 and the pixel electrodes AE1 to AE3. The inorganic pixel defining layer 151 may define therein a plurality of first openings OP1 respectively overlapping the emission areas EA1 to EA3 in a plan view. The inorganic pixel defining layer 151 may be arranged on the entire second passivation layer 139 to overlap the non-emission area NLA, but may overlap the emission areas EA1 to EA3 to partially overlap the pixel electrodes AE1 to AE3. In a plan view, the inorganic pixel defining layer 151 may partially expose the upper surfaces of the pixel electrodes AE1 to AE3 overlapping the first openings OP1.

[0107] The inorganic pixel defining layer 151 may include an inorganic insulating material. In an embodiment, for example, the inorganic pixel defining layer 151 may include aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxycarbide (SiOC).

[0108] The bank structure 160 may be positioned in the non-emission area NLA and may be positioned on the inorganic pixel defining layer 151. The bank structure 160 may define a plurality of second openings OP2 forming emission areas EA1 to EA3. The bank structure 160 may include a first bank layer 161 and a second bank layer 163 including different conductive materials and structures and playing different roles.

[0109] The first bank layer 161 may be positioned on the inorganic pixel defining layer 151. In the display device 10 according to the embodiment, the common electrodes CE1 to CE3 arranged in different emission areas EA1 to EA3 may not be directly connected to each other, but may be electrically connected through the first bank layer 161 of the bank structure 160. Therefore, the common electrodes CE1 to CE3 arranged in different emission areas EA1 to EA3 may be spaced apart from each other across the bank structure 160. The common electrodes CE1 to CE3 arranged in different emission areas EA1 to EA3 may contact the bank structure 160. The first bank layer 161 may include a metal having high electrical conductivity. In an embodiment, for example, the first bank layer 161 may include aluminum (Al).

[0110] The second bank layer 163 may be positioned on the first bank layer 161. The second bank layer 163 may include a material having an etching rate lower than that of the material of the first bank layer 161. In an embodiment, for example, the second bank layer 163 may include titanium (Ti). The second bank layer 163 may include a side surface 161c (see Figure 8 ) The tip TIP protrudes toward the first opening OP1 (see Figure 8 ). The tip TIP of the second bank layer 163 may protrude toward the emission areas EA1 to EA3 in a direction parallel to the main surface of the substrate 110 than the side surface 161c of the first bank layer 161. Therefore, an undercut may be formed between each tip TIP of the second bank layer 163 and the side surface 161c of the first bank layer 161. Here, the main surface (e.g., the upper surface) of the substrate 110 may be parallel to a plane defined by the first direction (X-axis direction) and the second direction (Y-axis direction).

[0111] In some embodiments, the auxiliary electrode AXE may be positioned on the inorganic pixel defining layer 151 and the embankment structure 160. The auxiliary electrode AXE may cover a portion of the inorganic pixel defining layer 151 and the entire embankment structure 160, but may not overlap with the first opening OP1 to expose the light emitting elements ED1 to ED3 in a plan view. In other words, a plurality of auxiliary electrodes AXE may be spaced apart from each other across the first opening OP1, and may overlap with the non-emission area NLA. Specifically, the auxiliary electrode AXE may overlap with the second opening OP2 to cover the inorganic pixel defining layer 151 and the embankment structure 160 in a plan view, and may overlap with the non-emission area NLA to cover the second embankment layer 163.

[0112] The auxiliary electrode AXE may help the common electrodes CE1 to CE3 to be electrically connected to the embankment structure 160. As mentioned above, in the display device 10, the common electrodes CE1 to CE3 arranged in the different emission areas EA1 to EA3 are not directly connected to each other, but may be electrically connected through the first embankment layer 161 of the embankment structure 160. Therefore, as the contact area between the common electrodes CE1 to CE3 and the first embankment layer 161 increases, the driving resistance of the display device 10 may be reduced, and the display device 10 may be electrically stable. In the display device 10 included in the current embodiment, the auxiliary electrode AXE positioned between the common electrodes CE1 to CE3 and the first embankment layer 161 may help the common electrodes CE1 to CE3 to be easily electrically connected to the first embankment layer 161.

[0113] The auxiliary electrode AXE may include a conductive metal. In the current embodiment, a case where each of the auxiliary electrodes AXE is indium tin oxide (ITO) will be described later as an example, but the present disclosure is not limited to this case. The auxiliary electrode AXE may also include any metal oxide containing a conductive material, such as indium zinc oxide (IZO), zinc oxide (ZnO), indium gallium zinc oxide (IGZO), or indium zinc tin oxide.

[0114] In some embodiments, a high temperature heat treatment process may be included in the process of manufacturing the auxiliary electrode AXE. The auxiliary electrode AXE may include a crystalline transparent oxide. In an embodiment, for example, the auxiliary electrode AXE may include polymerized indium tin oxide (ITO). The auxiliary electrode AXE may ensure improved conductivity and stability through a high temperature heat treatment process. Therefore, the display device 10 including the auxiliary electrode AXE located between the common electrodes CE1 to CE3 and the first bank layer 161 can reduce its driving resistance and have electrical stability.

[0115] The light-emitting layers EL1 to EL3 may be arranged on the pixel electrodes AE1 to AE3, respectively. The light-emitting layers EL1 to EL3 may include organic light-emitting layers made of organic materials and may be formed on the pixel electrodes AE1 to AE3 by a deposition process. When the thin film transistors TFT apply a predetermined voltage to the pixel electrodes AE1 to AE3 and when the common electrodes CE1 to CE3 receive a common voltage or a cathode voltage, holes and electrons may move to the organic light-emitting layers in the light-emitting layers EL1 to EL3 through the hole transport layer and the electron transport layer, respectively. Then, the holes and electrons may be combined with each other in the organic light-emitting layers in the light-emitting layers EL1 to EL3 to emit light.

[0116] The light-emitting layers EL1 to EL3 may include a first light-emitting layer EL1, a second light-emitting layer EL2, and a third light-emitting layer EL3, which are respectively arranged in different emission areas EA1 to EA3. The first light-emitting layer EL1 may be arranged on the first pixel electrode AE1 in the first emission area EA1, the second light-emitting layer EL2 may be arranged on the second pixel electrode AE2 in the second emission area EA2, and the third light-emitting layer EL3 may be arranged on the third pixel electrode AE3 in the third emission area EA3. In an embodiment, for example, the first light-emitting layer EL1 may be a light-emitting layer that emits light of a first color (i.e., red light), the second light-emitting layer EL2 may be a light-emitting layer that emits light of a second color (i.e., green light), and the third light-emitting layer EL3 may be a light-emitting layer that emits light of a third color (i.e., blue light).

[0117] The common electrodes CE1 to CE3 may be arranged on the light emitting layers EL1 to EL3, respectively. The common electrodes CE1 to CE3 may include a transparent conductive material to allow light generated by the light emitting layers EL1 to EL3 to pass through the common electrodes CE1 to CE3. The common electrodes CE1 to CE3 may receive a common voltage or a low potential voltage. When the pixel electrodes AE1 to AE3 receive a voltage corresponding to the data voltage and the common electrodes CE1 to CE3 receive a low potential voltage, a potential difference may be formed between the pixel electrodes AE1 to AE3 and the common electrodes CE1 to CE3. Accordingly, the light emitting layers EL1 to EL3 may emit light.

[0118] In an embodiment, for example, the common electrodes CE1 to CE3 may include silver (Ag). However, the present disclosure is not limited thereto. In another embodiment, the common electrodes CE1 to CE3 may include a material layer having a small work function, such as Li, Ca, LiF, Al, Mg, Pt, Pd, Ni, Au, Nd, Ir, Cr, BaF 2 , Ba or a compound or mixture thereof (eg, a mixture of Ag and Mg), or a material having a multilayer structure such as LiF / Ca or LiF / Al. The common electrodes CE1 to CE3 may further include a transparent metal oxide layer disposed on the material layer having a small work function.

[0119] In the display device 10, even in a deposition process without using a mask, the common electrodes CE1 to CE3 can be individually arranged in different regions by the tip TIP of the embankment structure 160. The common electrodes CE1 to CE3 may include a first common electrode CE1, a second common electrode CE2, and a third common electrode CE3 respectively arranged in different emission regions EA1 to EA3. The first common electrode CE1 may be arranged on the first light emitting layer EL1 in the first emission region EA1, the second common electrode CE2 may be arranged on the second light emitting layer EL2 in the second emission region EA2, and the third common electrode CE3 may be arranged on the third light emitting layer EL3 in the third emission region EA3. The separately formed common electrodes CE1 to CE3 may be electrically connected to each other through the auxiliary electrode AXE and the first embankment layer 161.

[0120] A portion of each of the common electrodes CE1 to CE3 may contact the auxiliary electrode AXE. As mentioned above, the auxiliary electrode AXE may help the first bank layer 161 and the common electrodes CE1 to CE3 to be electrically connected to each other. As the contact area between the common electrodes CE1 to CE3 and the auxiliary electrode AXE increases, the driving resistance of the display device 10 may be reduced.

[0121] The cover layers CPL1 to CPL3 may be disposed on the common electrodes CE1 to CE3, respectively. The cover layers CPL1 to CPL3 may include an inorganic insulating material to cover the light emitting elements ED1 to ED3. The cover layers CPL1 to CPL3 may prevent the light emitting elements ED1 to ED3 from being damaged by external air. The cover layers CPL1 to CPL3 may include a first cover layer CPL1 overlapping the first emission area EA1, a second cover layer CPL2 overlapping the second emission area EA2, and a third cover layer CPL3 overlapping the third emission area EA3.

[0122] The cover layers CPL1 to CPL3 respectively overlapping the emission areas EA1 to EA3 may overlap the first opening OP1 to completely cover the common electrodes CE1 to CE3. However, the cover layers CPL1 to CPL3 respectively overlapping the emission areas EA1 to EA3 may overlap the second opening OP2 to partially expose the common electrodes CE1 to CE3 in a plan view. The cover layers CPL1 to CPL3 may protect the common electrodes CE1 to CE3 to prevent them from peeling off.

[0123] The cover layers CPL1 to CPL3 may include aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 )、zinc oxide (ZnO), silicon oxide (SiO 2 ), silicon nitride (Si 3 N 4 ) or silicon oxycarbide (SiOC).

[0124] Reference Figure 7 , a plurality of organic patterns ELP1 to ELP3, a plurality of electrode patterns CEP1 to CEP3, and a plurality of cover patterns CLP1 to CLP3 may be arranged on the auxiliary electrode AXE to surround the first opening OP1. The organic patterns ELP1 to ELP3, the electrode patterns CEP1 to CEP3, and the cover patterns CLP1 to CLP3 may be partially etched during a process of manufacturing the display device 10. Accordingly, the organic patterns ELP1 to ELP3, the electrode patterns CEP1 to CEP3, and the cover patterns CLP1 to CLP3 may define a trench TP overlapping the non-emission area NLA (see Figure 8 ).

[0125] The organic patterns ELP1 to ELP3 may be positioned on the auxiliary electrode AXE. The organic patterns ELP1 to ELP3 may include the same material as that of the light-emitting layers EL1 to EL3, respectively. The first organic pattern ELP1 may include the same material as that of the first light-emitting layer EL1 of the first light-emitting element ED1, the second organic pattern ELP2 may include the same material as that of the second light-emitting layer EL2 of the second light-emitting element ED2, and the third organic pattern ELP3 may include the same material as that of the third light-emitting layer EL3 of the third light-emitting element ED3. Since the embankment structure 160 includes the tip TIP, the organic patterns ELP1 to ELP3 may be traces formed by being separated from the light-emitting layers EL1 to EL3.

[0126] The electrode patterns CEP1 to CEP3 may be arranged on the organic patterns ELP1 to ELP3, respectively. In an embodiment, for example, the first electrode pattern CEP1, the second electrode pattern CEP2, and the third electrode pattern CEP3 may be directly arranged on the first organic pattern ELP1, the second organic pattern ELP2, and the third organic pattern ELP3, respectively. The arrangement relationship between the electrode patterns CEP1 to CEP3 and the organic patterns ELP1 to ELP3 may be the same as the arrangement relationship between the common electrodes CE1 to CE3 and the light-emitting layers EL1 to EL3. The electrode patterns CEP1 to CEP3 may include the same material as that of the common electrodes CE1 to CE3, respectively. Since the embankment structure 160 includes a tip TIP, the electrode patterns CEP1 to CEP3 may be traces formed when the deposited material is separated from the common electrodes CE1 to CE3.

[0127] The covering patterns CLP1 to CLP3 may be positioned on the electrode patterns CEP1 to CEP3, respectively. The covering patterns CLP1 to CLP3 may include the same material as that of the covering layers CPL1 to CPL3. The arrangement relationship between the covering patterns CLP1 to CLP3 and the electrode patterns CEP1 to CEP3 may be the same as the arrangement relationship between the covering layers CPL1 to CPL3 and the common electrodes CE1 to CE3. The covering patterns CLP1 to CLP3 may be traces formed when the covering layers CPL1 to CPL3 are damaged by the tip TIP included in the embankment structure 160. The covering patterns CLP1 to CLP3 may prevent the pattern thereunder from being peeled off during the manufacturing process.

[0128] The thin film encapsulation layer 170 may be arranged on the light emitting elements ED1 to ED3, the auxiliary electrode AXE, and the cover patterns CLP1 to CLP3, and may cover the light emitting elements ED1 to ED3, the auxiliary electrode AXE, and the cover patterns CLP1 to CLP3. The thin film encapsulation layer 170 may include at least one inorganic layer to prevent oxygen or moisture from penetrating into the light emitting element layer 150. The thin film encapsulation layer 170 may include at least one organic layer to protect the light emitting element layer 150 from foreign matter such as dust. In an embodiment, the thin film encapsulation layer 170 may include a first encapsulation layer 171, a second encapsulation layer 173, and a third encapsulation layer 175 stacked sequentially. The first encapsulation layer 171 and the third encapsulation layer 175 may be inorganic encapsulation layers, and the second encapsulation layer 173 arranged therebetween may be an organic encapsulation layer.

[0129] Each of the first encapsulation layer 171 and the third encapsulation layer 175 may include one or more inorganic insulating materials. The inorganic insulating material may include aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride.

[0130] The second encapsulation layer 173 may include a polymer-based material. Examples of polymer-based materials may include acrylic resins, epoxy resins, polyimide, and polyethylene. In an embodiment, for example, the second encapsulation layer 173 may include an acrylic resin such as polymethyl methacrylate or polyacrylic acid. The second encapsulation layer 173 may be formed by curing a monomer or applying a polymer.

[0131] The first encapsulation layer 171 may include first to third inorganic layers 171 - 1 to 171 - 3 arranged to correspond to different emission areas EA1 to EA3 , respectively.

[0132] The first to third inorganic layers 171-1 to 171-3 may cover the light emitting elements ED1 to ED3, the auxiliary electrodes AXE, and the cover patterns CLP1 to CLP3. Since the first to third inorganic layers 171-1 to 171-3 can be formed by chemical vapor deposition (CVD), they can be formed to a uniform thickness along the steps on which their layers are deposited. In an embodiment, for example, each of the first to third inorganic layers 171-1 to 171-3 may form a thin layer even under an undercut formed by the tip TIP of the embankment structure 160.

[0133] Despite Figure 7 The first to third inorganic layers 171-1 to 171-3 are arranged at the same layer, but they may also be formed in different processes. In an embodiment, for example, the first inorganic layer 171-1 may be formed after forming the first common electrode CE1, the second inorganic layer 171-2 may be formed after forming the second common electrode CE2, and the third inorganic layer 171-3 may be formed after forming the third common electrode CE3.

[0134] The first to third inorganic layers 171 - 1 to 171 - 3 may overlap the non-emission area NLA, but may be spaced apart from each other. Accordingly, the auxiliary electrode AXE may be partially exposed. A portion of the upper surface of each of the exposed auxiliary electrodes AXE may contact the second encapsulation layer 173 .

[0135] The touch sensor layer 180 may be disposed on the thin film encapsulation layer 170. The touch sensor layer 180 may include a touch buffer layer 181, a touch insulating layer 183, touch electrodes TE, and a touch protection layer 185.

[0136] The touch buffer layer 181 may be arranged on the thin film encapsulation layer 170. The touch buffer layer 181 may have insulating and optical functions. The touch buffer layer 181 may include at least one inorganic layer. Optionally, the touch buffer layer 181 may be omitted. Although not shown in the drawings, a connection electrode electrically connecting the touch electrode TE may be arranged on the touch buffer layer 181. The connection electrode may be a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and indium tin oxide (ITO / APC / ITO).

[0137] The touch insulating layer 183 may cover the touch buffer layer 181. The touch insulating layer 183 may have an insulating function. In an embodiment, for example, the touch insulating layer 183 may be an inorganic layer including at least one of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and an aluminum oxide layer.

[0138] The touch electrodes TE may be arranged on the touch insulating layer 183 to overlap the non-emission area NLA. Each of the touch electrodes TE may not overlap the first to third emission areas EA1 to EA3. Each of the touch electrodes TE may be a single layer of molybdenum (Mo), titanium (Ti), copper (Cu), aluminum (Al), or indium tin oxide (ITO), or may be a stacked structure of aluminum and titanium (Ti / Al / Ti), a stacked structure of aluminum and indium tin oxide (ITO / Al / ITO), an APC alloy, or a stacked structure of an APC alloy and indium tin oxide (ITO / APC / ITO).

[0139] The touch protection layer 185 may cover the touch electrode TE and the touch insulating layer 183 . The touch protection layer 185 may have insulating and optical functions. The touch protection layer 185 may be made of at least one of the example materials of the touch insulating layer 183 .

[0140] The light blocking layer BM may be positioned in the non-emission area NLA and arranged on the touch sensor layer 180. The light blocking layer BM may overlap with the inorganic pixel defining layer 151, the embankment structure 160, and the touch electrode TE in a plan view. The light blocking layer BM may include a light absorbing material. In an embodiment, for example, the light blocking layer BM may include an inorganic black pigment or an organic black pigment. The inorganic black pigment may be carbon black, and the organic black pigment may include at least one of lactam black, perylene black, and aniline black. However, the present disclosure is not limited thereto. The light blocking layer BM may prevent color mixing by preventing the intrusion of visible light between the first emission area EA1 to the third emission area EA3, thereby improving the color gamut of the display device 10.

[0141] The color filter layer 190 may be disposed on the touch protection layer 185 and the light blocking layer BM to overlap the emission areas EA1 to EA3 .

[0142] The color filter layer 190 may include a first color filter 191, a second color filter 193, and a third color filter 195, which are respectively arranged to correspond to different emission areas EA1 to EA3. Each of the color filters 191, 193, and 195 may include a colorant such as a dye or a pigment that absorbs light in a wavelength band other than light in a specific wavelength band, and may be arranged to correspond to the color of light emitted from one of the emission areas EA1 to EA3. In an embodiment, for example, the first color filter 191 may be a red color filter that overlaps with the first emission area EA1 and transmits only red first light. The second color filter 193 may be a green color filter that overlaps with the second emission area EA2 and transmits only green second light, and the third color filter 195 may be a blue color filter that overlaps with the third emission area EA3 and transmits only blue third light.

[0143] exist Figure 7 In the embodiment of the present invention, each of the color filters 191, 193, and 195 is spaced apart from other adjacent color filters 191, 193, and 195 on the light blocking layer BM. However, the present disclosure is not limited thereto. In other words, each of the color filters 191, 193, and 195 may also partially overlap with other adjacent color filters 191, 193, and 195. That is, different color filters 191, 193, and 195 may overlap with the non-emission area NLA and may overlap with each other on the light blocking layer BM.

[0144] An overcoat layer OC may be disposed on the color filter layer 190 and the light blocking layer BM to planarize the upper ends of the color filters 191, 193, and 195. The overcoat layer OC may be a colorless light-transmitting layer having no color in the visible light band. In an embodiment, for example, the overcoat layer OC may include a colorless light-transmitting organic material such as an acrylic resin.

[0145] Figure 8 yes Figure 7An enlarged cross-sectional view of the first emission area EA1.

[0146] Reference Figure 8 , the inorganic pixel defining layer 151 may be positioned on the second passivation layer 139 and the first pixel electrode AE1. The inorganic pixel defining layer 151 may overlap the second opening OP2, and may be spaced apart from the first pixel electrode AE1 in the third direction (Z-axis direction) via a space. The space between the inorganic pixel defining layer 151 and the first pixel electrode AE1 may be formed by a sacrificial layer to be described later.

[0147] During the manufacturing process, the display device 10 may include a sacrificial layer positioned between the inorganic pixel defining layer 151 and the first pixel electrode AE1. The sacrificial layer may be disposed between the inorganic pixel defining layer 151 and the first pixel electrode AE1, and may then be removed by a subsequent etching process. An unremoved portion of the sacrificial layer may remain between the inorganic pixel defining layer 151 and the first pixel electrode AE1 as a residual pattern 157. This will be described in detail later in the manufacturing process.

[0148] In some embodiments, the first light emitting layer EL1 may be arranged in a portion between the inorganic pixel defining layer 151 and the first pixel electrode AE1. In the process of manufacturing the first light emitting layer EL1 included in the current embodiment, the material of the first light emitting layer EL1 may be deposited at an angle in a direction between the first direction (X-axis direction) and the third direction (Z-axis direction). Accordingly, the first light emitting layer EL1 may be deposited while partially filling the portion between the first pixel electrode AE1 and the inorganic pixel defining layer 151. Therefore, the residual pattern 157 and the first light emitting layer EL1 may be positioned to contact each other in the portion between the first pixel electrode AE1 and the inorganic pixel defining layer 151.

[0149] The bank structure 160 may be positioned on the inorganic pixel defining layer 151. The bank structure 160 may include a first bank layer 161 and a second bank layer 163 including different conductive materials.

[0150] The first bank layer 161 may include a side surface 161c facing the first opening OP1. The side surface 161c of the first bank layer 161 may be positioned in an inclined shape in a direction between the first direction (X-axis direction) and the third direction (Z-axis direction). The side surface 161c of the first bank layer 161 may be recessed toward one side in the first direction (X-axis direction) than the side surface of the inorganic pixel defining layer 151. Therefore, the side surface 161c of the first bank layer 161 may overlap with the second opening OP2 to partially expose the inorganic pixel defining layer 151.

[0151] The second bank layer 163 may be positioned on the first bank layer 161. The second bank layer 163 may include an upper surface 163e, a lower surface 163a, and a side surface 163c.

[0152] The lower surface 163a of the second bank layer 163 may be a surface in contact with the first bank layer 161. The first bank layer 161 and the second bank layer 163 may cover along the step of the inorganic pixel defining layer 151. Accordingly, the lower surface 163a of the second bank layer 163 may include a step.

[0153] The side surface 163c of the second bank layer 163 may protrude from the side surface 161c of the first bank layer 161 toward the first opening OP1. Specifically, the first bank layer 161 and the second bank layer 163 may be formed by a wet etching process during a manufacturing process. The second bank layer 163 may include a material that is relatively stable in a wet etching process compared to a material of the first bank layer 161. Therefore, the side surface 163c of the second bank layer 163 may protrude toward the first opening OP1 more than the side surface 161c of the first bank layer 161. In other words, the side surface 161c of the first bank layer 161 may be recessed toward one side in the first direction (X-axis direction) more than the side surface 163c of the second bank layer 163.

[0154] like Figure 8 As shown in FIG. 1 , the side surface 163c of the second bank layer 163 of the bank structure 160 may include a tip TIP protruding toward the first opening OP1 more than the side surface 161c of the first bank layer 161. Accordingly, an undercut may be formed between the bottom of each tip TIP of the second bank layer 163 and the side surface 161c of the first bank layer 161.

[0155] The upper surface 163e of the second bank layer 163 may be a surface facing the lower surface 163a of the second bank layer 163. Similar to the lower surface 163a of the second bank layer 163, the upper surface 163e of the second bank layer 163 may cover along the step of the inorganic pixel defining layer 151.

[0156] The auxiliary electrode AXE may be positioned on the inorganic pixel defining layer 151 and the bank structure 160. The auxiliary electrode AXE may contact the upper surface of the inorganic pixel defining layer 151 exposed by the side surface 161c of the first bank layer 161. In addition, the auxiliary electrode AXE may contact the side surface 161c of the first bank layer 161 and the lower surface 163a, the side surface 163c, and the upper surface 163e of the second bank layer 163.

[0157] Fig. 9 yes Figure 7 An enlarged cross-sectional view of area "A" of FIG. Fig.10 yes Fig. 9 An enlarged cross-sectional view of a first portion AXE-1 of the auxiliary electrode AXE. Fig.11 yes Fig. 9 An enlarged cross-sectional view of a second portion AXE-2 of the auxiliary electrode AXE.

[0158] Reference Fig. 9, the auxiliary electrode AXE may completely cover the bank structure 160. In other words, the bank structure 160 may be completely surrounded by the inorganic pixel defining layer 151 and the auxiliary electrode AXE.

[0159] In some embodiments, the auxiliary electrode AXE may include a first portion AXE-1 overlapping the first emission area EA1, a second portion AXE-2 overlapping the second emission area EA2, and a third portion AXE-3 overlapping the non-emission area NLA. The first portion AXE-1 overlapping the first emission area EA1 and the second portion AXE-2 overlapping the second emission area EA2 may extend from the third portion AXE-3 overlapping the non-emission area NLA.

[0160] In some embodiments, the first portion AXE-1 of the auxiliary electrode AXE may contact the upper surface of the inorganic pixel defining layer 151 and may cover the upper surface of the inorganic pixel defining layer 151. The first portion AXE-1 of the auxiliary electrode AXE may overlap the inorganic pixel defining layer 151 and the first light emitting layer EL1 in the third direction (Z-axis direction). In addition, the first portion AXE-1 of the auxiliary electrode AXE may overlap the second opening OP2, may be positioned on the side surface 161c of the first bank layer 161 to contact the side surface 161c of the first bank layer 161, and may completely cover the side surface 161c of the first bank layer 161. In addition, the first portion AXE-1 of the auxiliary electrode AXE may contact the tip TIP of the second bank layer 163 and may completely cover the tip TIP of the second bank layer 163. Specifically, the first portion AXE-1 of the auxiliary electrode AXE may contact the lower surface 163a, the side surface 163c, and the upper surface 163e of the second bank layer 163 to completely cover the tip TIP of the second bank layer 163. The first portion AXE- 1 of the auxiliary electrode AXE may overlap the first emission area EA1 to cover the bank structure 160 , thereby protecting the side surface 161 c of the first bank layer 161 and the tip TIP of the second bank layer 163 from repeated etching processes.

[0161] Reference Fig.10 The first portion AXE-1 of the auxiliary electrode AXE may include a side surface AXE-1c positioned on the side surface 161c of the first bank 161. The side surface AXE-1c of the first portion AXE-1 may overlap the first emission region EA1 and the tip TIP of the second bank 163.

[0162] The first light emitting layer EL1, the first common electrode CE1, and the first inorganic layer 171-1 may partially contact the side surface AXE-1c of the first portion AXE-1. Therefore, the side surface AXE-1c of the first portion AXE-1 may be divided into a first sub-portion c1 in contact with the first light emitting layer EL1, a second sub-portion c2 in contact with the first common electrode CE1, and a third sub-portion c3 in contact with the first inorganic layer 171-1. The width W1 of the first sub-portion c1 in contact with the first light emitting layer EL1 may be smaller than the width W2 of the second sub-portion c2 in contact with the first common electrode CE1. This is because during the process of manufacturing the light emitting elements ED1 to ED3, the deposition process for forming the common electrodes CE1 to CE3 is performed at a larger angle than the angle of the deposition process for forming the light emitting layers EL1 to EL3, relative to the main surface of the substrate 110.

[0163] In an embodiment, when the angle of the deposition process for forming the light emitting layers EL1 to EL3 is defined as the first angle, the deposition process for forming the light emitting layers EL1 to EL3 may be performed at an angle of 45 to 50 degrees relative to the upper surface of the pixel electrodes AE1 to AE3. That is, the first angle may be 45 to 50 degrees. Therefore, the light emitting layers EL1 to EL3 may be formed to fill the space between the pixel electrodes AE1 to AE3 and the inorganic pixel defining layer 151, and may also be arranged on the sidewall of the second opening OP2 in the area covered by the tip TIP of the bank structure 160.

[0164] In addition, when the angle of the deposition process for forming the common electrodes CE1 to CE3 is defined as the second angle, the deposition process for forming the common electrodes CE1 to CE3 may be performed at an angle of 30 degrees or less relative to the upper surfaces of the pixel electrodes AE1 to AE3. Therefore, in the side surface AXE-1c of the first portion AXE-1, the width W1 of the first sub-portion c1 contacting the first light emitting layer EL1 may be smaller than the second width W2 of the second sub-portion c2 contacting the first common electrode CE1. The “width” may be as follows: Fig.10 Measured in the third direction (Z-axis direction) or the surface direction of the side surface AXE-1c as shown in FIG.

[0165] As described above, as the width W2 of the first common electrode CE1 contacting the auxiliary electrode AXE increases, the total area of ​​each emission region where the first common electrode CE1 contacts the auxiliary electrode AXE increases, and the driving resistance of the display device 10 can be reduced. Therefore, the electrical characteristics of the display device 10 can be effectively stabilized.

[0166] Reference Fig. 9, the second portion AXE-2 of the auxiliary electrode AXE may contact the inorganic pixel defining layer 151 overlapping with the second pixel electrode AE2 in a plan view, and may cover the upper surface of the inorganic pixel defining layer 151. In addition, the second portion AXE-2 of the auxiliary electrode AXE may be positioned on the side surface 161c of the first bank layer 161 to contact the side surface 161c of the first bank layer 161 and may completely cover the side surface 161c of the first bank layer 161. In addition, the second portion AXE-2 of the auxiliary electrode AXE may overlap with the tip TIP of the second bank layer 163, and may completely cover the tip TIP of the second bank layer 163. Specifically, the second portion AXE-2 of the auxiliary electrode AXE may contact the lower surface 163a, the side surface 163c, and the upper surface 163e of the second bank layer 163 to completely cover the tip TIP of the second bank layer 163. The second portion AXE-2 of the auxiliary electrode AXE may overlap the second emission area EA2 to cover the bank structure 160, thereby protecting the side surface 161c of the first bank layer 161 and the tip TIP of the second bank layer 163 from repeated etching processes.

[0167] Reference Fig.11 The second portion AXE-2 of the auxiliary electrode AXE may include a side surface AXE-2c positioned on the side surface 161c of the first bank layer 161. The side surface AXE-2c of the second portion AXE-2 may overlap the second emission region EA2 and the tip end TIP of the bank structure 160.

[0168] The second light emitting layer EL2, the second common electrode CE2, and the second inorganic layer 171-2 may contact the side surface AXE-2c of the second portion AXE-2. Therefore, the side surface AXE-2c of the second portion AXE-2 may be divided into a first sub-portion c4 in contact with the second light emitting layer EL2, a second sub-portion c5 in contact with the second common electrode CE2, and a third sub-portion c6 in contact with the second inorganic layer 171-2. A width W4 of the first sub-portion c4 in contact with the second light emitting layer EL2 may be smaller than a width W5 of the second sub-portion c5 in contact with the second common electrode CE2. Since other details have been mentioned, their description will be omitted.

[0169] Reference Fig. 9 , the third portion AXE-3 of the auxiliary electrode AXE may overlap the non-emission area NLA and may extend to the first portion AXE-1 and the second portion AXE-2 of the auxiliary electrode AXE. That is, the first portion AXE-1, the second portion AXE-2, and the third portion AXE-3 of the auxiliary electrode AXE may extend as a single portion. The third portion AXE-3 of the auxiliary electrode AXE may contact the upper surface 163e of the second bank layer 163 and may cover the upper surface 163e of the second bank layer 163.

[0170] The organic patterns ELP1 and ELP2 , the electrode patterns CEP1 and CEP2 , the capping patterns CLP1 and CLP2 , and the first and second inorganic layers 171 - 1 and 171 - 2 may be positioned on the auxiliary electrode AXE to overlap the third portion AXE- 3 of the auxiliary electrode AXE in a plan view.

[0171] The first organic pattern ELP1, the first electrode pattern CEP1, and the first covering pattern CLP1 overlapping the third portion AXE-3 of the auxiliary electrode AXE may be separated from the second organic pattern ELP2, the second electrode pattern CEP2, and the second covering pattern CLP2 overlapping the third portion AXE-3 of the auxiliary electrode AXE in a plan view. In addition, the first inorganic layer 171-1 and the second inorganic layer 171-2 overlapping the third portion AXE-3 of the auxiliary electrode AXE may be spaced apart from each other in a plan view. This may be caused by an etching process included in the manufacturing process of the display device 10. Specifically, the first organic pattern ELP1, the first electrode pattern CEP1, the first covering pattern CLP1, and the first inorganic layer 171-1 may be deposited not only in the first emission area EA1 but also in the second emission area EA2 and the third emission area EA3 during the manufacturing process, and may then be formed into the shape of the pattern shown by a subsequent etching process. In addition, the second organic pattern ELP2, the second electrode pattern CEP2, the second cover pattern CLP2, and the second inorganic layer 171-2 may be deposited not only in the second emission area EA2 but also in the first emission area EA1 and the third emission area EA3 during the manufacturing process, and may then be formed into the shape of the pattern shown by a subsequent etching process. Therefore, the third portion AXE-3 of the auxiliary electrode AXE may be partially exposed by a plurality of patterns spaced apart from each other and the first inorganic layer 171-1 and the second inorganic layer 171-2. The third portion AXE-3 of the auxiliary electrode AXE may protect the second bank layer 163 from repeated etching processes.

[0172] The second encapsulation layer 173 may be positioned on the first inorganic layer 171-1 and the second inorganic layer 171-2. The third portion AXE-3 of the auxiliary electrode AXE partially exposed by the pattern and the first inorganic layer 171-1 and the second inorganic layer 171-2 spaced apart from each other may contact the second encapsulation layer 173. For the convenience of description, the structure overlapping the first emission area EA1 and the second emission area EA2 has been shown and described. However, the structure included in the emission areas EA1 to EA3 and the non-emission area NLA positioned in the display area DA of the display device 10 may include the same features as the above-mentioned structure.

[0173] Fig.12 yes Figure 2 An enlarged plan view of area "Q". Fig.13 is along Fig.121 is a cross-sectional view of an example of the display device 10 taken along line Q1 - Q1 ′.

[0174] Reference Fig.12 , the emission areas EA1 to EA3 may be positioned in the display area DA, and the embankment structure 160 may surround the emission areas EA1 to EA3 . The emission areas EA1 to EA3 may be formed by the second openings OP2 defined by the embankment structure 160 .

[0175] Reference Fig.12 and Fig.13 , the dam structure DM1 surrounding the display area DA may be positioned in the non-display area NDA. The dam structure DM1 may be positioned between the end EG of the substrate 110 and the levee structure 160 of the display area DA. The dam structure DM1 may be formed to prevent the organic material applied to the display area DA from overflowing into the non-display area NDA. In an embodiment, for example, the second encapsulation layer 173 applied to the display area DA may not flow to the non-display area NDA due to the dam structure DM1.

[0176] The dam structure DM1 may be positioned on the second passivation layer 139 to overlap the non-display area NDA. The dam structure DM1 may include a first dam layer DM11 and a second dam layer DM12. The first dam layer DM11 may include the same material as the first dam layer 161 of the dam structure 160, and the second dam layer DM12 may include the same material as the second dam layer 163 of the dam structure 160. The dam structure DM1 may be formed to extend from the dam structure 160 during the manufacturing process, and may then be formed into the shape of the dam structure DM1 shown by a subsequent etching process. That is, the dam structure DM1 may be formed integrally with the dam structure 160 during the manufacturing process, and may then be separated from the dam structure 160 by a subsequent process.

[0177] The side surface DM12c of the second dam layer DM12 may protrude in the first direction (X-axis direction) more than the side surface DM11c of the first dam layer DM11. Therefore, an undercut may be formed between the second dam layer DM12 and the first dam layer DM11. The first dam layer DM11 and the second dam layer DM12 may have the same shape as the first bank layer 161 and the second bank layer 163.

[0178] The auxiliary electrode AXE may be positioned on the dam structure DM1. The auxiliary electrode AXE may extend from the display area DA to the non-display area NDA. The auxiliary electrode AXE may completely cover the dam structure DM1 in the non-display area NDA. The auxiliary electrode AXE may also cover the undercut portion between the first dam layer DM11 and the second dam layer DM12 included in the dam structure DM1. Specifically, the auxiliary electrode AXE may be positioned on the opposite side surfaces DM11c of the first dam layer DM11 to contact them, and may completely cover the opposite side surfaces DM11c of the first dam layer DM11. In addition, the auxiliary electrode AXE may contact the opposite protruding portion of the second dam layer DM12 and completely cover the opposite protruding portion of the second dam layer DM12. In addition, the auxiliary electrode AXE may contact the upper surface of the second dam layer DM12 and completely cover the upper surface of the second dam layer DM12. The auxiliary electrode AXE covering the first dam layer DM11 and the second dam layer DM12 may extend as a single electrode.

[0179] The first encapsulation layer 171 may be positioned on the auxiliary electrode AXE to overlap the dam structure DM1 positioned in the non-display area NDA. The first encapsulation layer 171 may extend along the auxiliary electrode AXE to cover the auxiliary electrode AXE. The first encapsulation layer 171 may extend to the end EG of the substrate 110 to prevent moisture and oxygen from penetrating from the non-display area NDA into the display area DA.

[0180] The third encapsulation layer 175 may be positioned on the first encapsulation layer 171 to overlap the dam structure DM1 positioned in the non-display area NDA. Since the second encapsulation layer 173 does not flow to the non-display area NDA due to the dam structure DM1 as described above, the second encapsulation layer 173 may not overlap with the upper surface of the dam structure DM1 in a plan view. Therefore, the first encapsulation layer 171 and the third encapsulation layer 175 overlapping the non-display area NDA may contact each other. The third encapsulation layer 175 may extend to the end EG of the substrate 110 to prevent moisture and oxygen from penetrating from the non-display area NDA into the display area DA.

[0181] Figures 14 to 24 1 is a cross-sectional view sequentially showing a display area DA during a process of manufacturing a display device according to an embodiment. Specifically, Figures 14 to 24 The display device 10 (see Figure 7 ) of the bank structure 160 and the light emitting element ED. In the following description of the process of manufacturing the display device 10, the formation process of each layer will not be described, and the formation order of each layer will be described.

[0182] Reference Fig.14 , a plurality of pixel electrodes AE1 to AE3 , a sacrificial layer SFL, an inorganic pixel defining layer 151 , and a plurality of bank material layers 161L and 163L are formed on the thin film transistor layer 130 .

[0183] Although not shown in the drawings, the thin film transistor layer 130 may be disposed on the substrate 110 (see Figure 7 The structure of the thin film transistor layer 130 is similar to that of the thin film transistor layer 130. Figure 7 The structures described are the same, and thus a detailed description thereof will be omitted.

[0184] The pixel electrodes AE1 to AE3 may be spaced apart from each other on the thin film transistor layer 130. The pixel electrodes AE1 to AE3 may include first, second, and third pixel electrodes AE1, AE2, and AE3 of different light emitting elements ED1 to ED3. The first to third pixel electrodes AE1 to AE3 may be spaced apart from each other on the thin film transistor layer 130.

[0185] The sacrificial layer SFL may be disposed on the pixel electrodes AE1 to AE3. The sacrificial layer SFL disposed on the pixel electrodes AE1 to AE3 may be partially removed in a subsequent process to form a space in which the light emitting layers EL1 to EL3 will be disposed. The sacrificial layer SFL may prevent the upper surfaces of the pixel electrodes AE1 to AE3 from contacting the inorganic pixel defining layer 151. The sacrificial layer SFL may be removed in a subsequent process to form a space between the pixel electrodes AE1 to AE3 and the inorganic pixel defining layer 151. In an embodiment, the sacrificial layer SFL may include an oxide semiconductor. In an embodiment, for example, the sacrificial layer SFL may include at least one of indium gallium zinc oxide ("IGZO"), zinc tin oxide ("ZTO"), and indium tin oxide (ITO).

[0186] The inorganic pixel defining layer 151 and the embankment material layers 161L and 163L may be arranged on the sacrificial layer SFL. The inorganic pixel defining layer 151 may be arranged to cover the entire sacrificial layer SFL and the thin film transistor layer 130, and the embankment material layers 161L and 163L may be arranged to cover the entire inorganic pixel defining layer 151. The embankment material layers 161L and 163L may include a first embankment material layer 161L and a second embankment material layer 163L. The first embankment material layer 161L may be directly arranged on the inorganic pixel defining layer 151, and the second embankment material layer 163L may be arranged on the first embankment material layer 161L. The embankment material layers 161L and 163L may be partially etched in a subsequent process to form Figure 7 1 and 163 of the bank structure 160 shown in FIG. The bank material layers 161L and 163L are substantially the same as the bank layers 161 and 163 described above, and thus a detailed description thereof will be omitted and may be used interchangeably in some cases.

[0187] Next, refer to Fig.15A photoresist PR is formed on the bank material layers 161L and 163L, and a first etching process for partially etching the bank material layers 161L and 163L is performed using the photoresist PR as a mask. In the current process, the first holes HOL1 may be formed to overlap the pixel electrodes AE1 to AE3, respectively, in a plan view.

[0188] The photoresists PR may be spaced apart from each other on the bank material layers 161L and 163L. The photoresists PR may be arranged on the second bank material layer 163L to be exposed at portions respectively overlapping the pixel electrodes AE1 to AE3 in a plan view.

[0189] In an embodiment, the first etching process may be performed as dry etching. Since the first etching process is performed as a dry etching process, the bank material layers 161L and 163L including different materials may be etched. Therefore, the inorganic pixel defining layer 151 overlapping each of the pixel electrodes AE1 to AE3 may be exposed. The first hole HOL1 may be defined in a region overlapping the pixel electrodes AE1 to AE3 in a plan view. The first hole HOL1 may form an opening of the bank structure 160.

[0190] Next, refer to Fig.16 , a second etching process for forming a tip TIP of the embankment structure 160 is performed. In an embodiment, the second etching process may be performed as a wet etching process. In the current process, the first embankment material layer 161L of the embankment material layers 161L and 163L may be etched at a faster rate than the second embankment material layer 163L. Accordingly, a tip TIP protruding from the side surface of the first embankment material layer 161L may be formed on the side surface of the second embankment material layer 163L. Therefore, an undercut may be formed on the side surface of the first embankment material layer 161L and under the tip TIP of the second embankment material layer 163L.

[0191] Next, refer to Fig.17 , an auxiliary electrode material layer AXEL may be formed on the side surfaces of the second bank material layer 163L, the first bank material layer 161L, and the upper surface of the inorganic pixel defining layer 151. In an embodiment, for example, the auxiliary electrode material layer AXEL may be formed by a sputtering process. As described above, the auxiliary electrode material layer AXEL may help to electrically connect the formed common electrodes CE1 to CE3 to the bank structure 160 in a subsequent process. Fig.18 In a subsequent process, the auxiliary electrode material layer AXEL may be formed into the auxiliary electrode AXE described above. The auxiliary electrode material layer AXEL is substantially the same as the auxiliary electrode AXE described above, and thus a detailed description thereof will be omitted.

[0192] Next, refer to Fig.18, a third etching process for removing the auxiliary electrode material layer AXEL, the inorganic pixel defining layer 151, and the sacrificial layer SFL overlapping with the pixel electrodes AE1 to AE3 in a plan view is performed. Specifically, in the third etching process, a dry etching process and a wet etching process may be performed alternately. Specifically, first, the auxiliary electrode material layer AXEL including a conductive metal may be removed by a wet etching process. Accordingly, a portion of the auxiliary electrode material layer AXEL overlapping with each of the pixel electrodes AE1 to AE3 in a plan view may be removed, and the inorganic pixel defining layer 151 overlapping with each of the pixel electrodes AE1 to AE3 in a plan view may be exposed.

[0193] Next, the inorganic pixel defining layer 151 including the inorganic layer may be removed by a dry etching process. Accordingly, a portion of the inorganic pixel defining layer 151 overlapping each of the pixel electrodes AE1 to AE3 in a plan view may be removed, and the sacrificial layer SFL respectively overlapping the pixel electrodes AE1 to AE3 may be exposed.

[0194] Third, the sacrificial layer SFL including the oxide semiconductor may be removed by a wet etching process. In the current process, the sacrificial layer SFL between the inorganic pixel defining layer 151 and the pixel electrodes AE1 to AE3 may be removed. However, the sacrificial layer SFL may not be completely removed, but may remain as a residual pattern 157 between the inorganic pixel defining layer 151 and the pixel electrodes AE1 to AE3. As a portion formed by removing the sacrificial layer SFL, a space may be formed between the pixel electrodes AE1 to AE3 and the inorganic pixel defining layer 151 disposed on the pixel electrodes AE1 to AE3. In a subsequent process, the light emitting layers EL1 to EL3 may be formed on the pixel electrodes AE1 to AE3 to fill the space.

[0195] Next, refer to Fig.19 , a high temperature heat treatment may be performed on the auxiliary electrode AXE positioned on the bank structure 160. Therefore, the auxiliary electrode AXE may include a crystalline transparent oxide. In an embodiment, for example, the auxiliary electrode AXE may include polymerized indium tin oxide (ITO).

[0196] Next, refer to Fig. 20 , a first light emitting layer EL1, a first common electrode CE1, and a first cover layer CPL1 may be deposited on each of the pixel electrodes AE1 to AE3. The first light emitting layer EL1, the first common electrode CE1, and the first cover layer CPL1 may be formed not only on the first pixel electrode AE1, but also on the second pixel electrode AE2 and the third pixel electrode AE3.

[0197] In addition, in the deposition process, materials forming the first light emitting layer EL1, the first common electrode CE1, and the first cover layer CPL1 may also be deposited on the second bank material layer 163L to form a plurality of patterns. In an embodiment, for example, some of the materials may be deposited on the second bank material layer 163L to form the first organic pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CLP1. The structures and relationships of the first light emitting layer EL1, the first common electrode CE1, and the first cover layer CPL1 and the first organic pattern ELP1, the first electrode pattern CEP1, and the first cover pattern CLP1 are the same as those described above, and thus a description thereof will be omitted.

[0198] As mentioned above Fig.10 As described above, the light emitting layers EL1 to EL3 may be deposited at a first angle relative to the upper surface of the pixel electrodes AE1 to AE3, and the common electrodes CE1 to CE3 may be deposited at a second angle relative to the upper surface of the pixel electrodes AE1 to AE3. Therefore, they may be deposited even smoothly below the tip TIP of the second bank material layer 163L. As described above, since the second angle includes a value smaller than the value of the first angle, the deposition process for forming the common electrodes CE1 to CE3 may be performed at an angle relatively closer to the horizontal direction (e.g., the X-axis direction or the Y-axis direction) than the angle of the deposition process for forming the light emitting layers EL1 to EL3. Accordingly, the common electrodes CE1 to CE3 may contact the first bank material layer 161L over a larger area than the light emitting layers EL1 to EL3. In other words, the common electrodes CE1 to CE3 may be deposited at a higher position on the side surface of the first bank material layer 161L than the light emitting layers EL1 to EL3. The common electrodes CE1 to CE3 formed at different positions may contact the first bank material layer 161L of high conductivity, and thus may be electrically connected to each other.

[0199] Next, refer to Fig.21 , a first inorganic layer 171-1 is formed to cover the first cover layer CPL1 and the first cover pattern CLP1. The first inorganic layer 171-1 may be formed to overlap each of the pixel electrodes AE1 to AE3 in a plan view. Unlike the light emitting layers EL1 to EL3 and the common electrodes CE1 to CE3, the first inorganic layer 171-1 may be formed by a CVD process. The first inorganic layer 171-1 may form a uniform layer regardless of the step of the portion where it is deposited. That is, the first inorganic layer 171-1 may cover the structure thereunder with a uniform thickness along the contour of the structure.

[0200] The first inorganic layer 171-1 may completely cover the first capping layer CPL1, the side surface of the first bank material layer 161L, and the first capping pattern CLP1. Specifically, the first inorganic layer 171-1 may also be deposited under the tip TIP of the second bank material layer 163L.

[0201] Next, refer to Fig. 22 , a photoresist PR is formed on the bank material layers 161L and 163L positioned on the first pixel electrode AE1 and the opposite sides of the first pixel electrode AE1, and then a fourth etching process is performed.

[0202] In the current process, except for the portion around the first pixel electrode AE1, the first light emitting layer EL1, the first common electrode CE1, the first cover layer CPL1, the patterns ELP1, CEP1 and CLP1, and the first inorganic layer 171-1 in the portion where the photoresist PR is not formed may all be removed. In an embodiment, the process of removing all portions except for the portion around the first pixel electrode AE1 may be performed as a dry etching process using a fluorine (F)-based etchant. Through the above process, a structure such as Figure 7 The first inorganic layer 171 - 1 shown in FIG. 1 covers the first light emitting element ED1 , the first capping layer CPL1 , the first organic pattern ELP1 , the first electrode pattern CEP1 , and the first capping pattern CLP1 .

[0203] Reference Fig.23 and Fig.24 , a process similar to the above process may be repeated to form a second light emitting element ED2, a third light emitting element ED3, a second inorganic layer 171-2, and a third inorganic layer 171-3. Although not shown in the drawings, a thin film encapsulation layer 170 may be formed by forming a second encapsulation layer 173 and a third encapsulation layer 175 on the first encapsulation layer 171 and the embankment structure 160 (see Figure 7 Then, the touch sensor layer 180, the light blocking layer BM, the color filter layer 190, and the overcoat layer OC may be formed to produce the display device 10 (see Figure 7 ).

[0204] At the end of the detailed description, those skilled in the art will recognize that many changes and modifications can be made to the preferred embodiment without departing substantially from the principles of the present invention. Therefore, the preferred embodiments of the present invention disclosed are used only in a general and descriptive sense and not for the purpose of limitation.

[0205] However, the effects of the present disclosure are not limited to the effects set forth herein. The above and other effects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure belongs by referring to the claims.

Claims

1. A display device, comprising: A substrate, the substrate comprising an emitting region and a non-emitting region; a pixel electrode, the pixel electrode being positioned on the emission region of the substrate; a pixel defining layer, the pixel defining layer being positioned on the pixel electrode, overlapping the non-emitting region, and having a first opening defined therein; a dam structure positioned on the pixel defining layer and having a second opening defined therein; an auxiliary electrode positioned on the bank structure and comprising a conductive material; as well as a common electrode positioned on the pixel electrode and contacting the auxiliary electrode in the second opening, The bank structure includes a first bank layer and a second bank layer including conductive materials different from each other, the second bank layer includes a tip protruding from a side surface of the first bank layer toward the first opening, and the auxiliary electrode completely covers the tip of the second bank layer.

2. The display device according to claim 1, wherein: The second bank layer includes a first surface facing the substrate, a second surface opposite to the first surface, and a side surface facing the first opening and connecting the first surface and the second surface, and The auxiliary electrode overlaps with the tip of the second bank layer to contact the first surface, the side surface, and the second surface of the second bank layer.

3. The display device according to claim 2, wherein: The auxiliary electrode contacts and completely covers the second surface of the second bank layer.

4. The display device according to claim 3, wherein: The auxiliary electrode contacts and completely covers the side surface of the first bank layer.

5. The display device according to claim 4, wherein: The bank structure is completely surrounded by the pixel defining layer and the auxiliary electrode.

6. The display device according to claim 3, wherein: The auxiliary electrode is a crystalline transparent oxide.

7. The display device according to claim 6, wherein: The first bank layer includes aluminum, and the second bank layer includes titanium.

8. The display device according to claim 1, further comprising: A light emitting layer is positioned between the pixel electrode and the common electrode, wherein the light emitting layer contacts the auxiliary electrode in the second opening.

9. The display device according to claim 8, wherein: The auxiliary electrode includes a first portion contacting the light emitting layer and a second portion contacting the common electrode, and a width of the second portion is greater than a width of the first portion in a direction perpendicular to a main surface of the substrate.

10. The display device according to claim 8, further comprising: an organic pattern, the organic pattern overlapping the tip of the second bank layer, being positioned on the auxiliary electrode, and comprising the same material as the light emitting layer; as well as an electrode pattern positioned on the organic pattern and comprising the same material as the common electrode, The organic pattern is spaced apart from the light emitting layer, and the electrode pattern is spaced apart from the common electrode.

11. The display device according to claim 10, further comprising: An encapsulation layer is positioned on the common electrode and the electrode pattern, wherein the encapsulation layer contacts the auxiliary electrode on the side surface of the first bank layer.

12. The display device according to claim 11, further comprising: A pattern, the pattern is positioned between the pixel defining layer and the pixel electrode and overlaps with the tip of the second embankment layer in a direction perpendicular to the main surface of the substrate, wherein the pattern overlaps with the auxiliary electrode in the direction perpendicular to the main surface of the substrate.

13. A display device, comprising: a substrate comprising a first emission region, a second emission region, and a non-emitting region positioned between the first emission region and the second emission region; a first pixel electrode, the first pixel electrode overlapping the first emission region and positioned on the substrate; a pixel defining layer overlapping the non-emitting region and positioned on the first pixel electrode; a second pixel electrode, the second pixel electrode overlapping the second emission region and spaced apart from the first pixel electrode via the pixel defining layer; a levee structure, the levee structure being positioned on the pixel defining layer; as well as an auxiliary electrode, the auxiliary electrode being positioned on the pixel defining layer and the bank structure, Wherein, the auxiliary electrode comprises: a first portion overlapping the first emission region; a second portion overlapping the second emission region; and a third portion overlapping the non-emitting region, The first portion and the second portion of the auxiliary electrode extend from the third portion, and the third portion of the auxiliary electrode completely covers an upper surface of the embankment structure.

14. The display device according to claim 13, wherein: The embankment structure includes a first embankment layer and a second embankment layer, the second embankment layer includes tips protruding from side surfaces of the first embankment layer toward the first emission region and the second emission region, respectively, and the first and second portions of the auxiliary electrode completely cover the tips of the second embankment layer, respectively.

15. The display device according to claim 14, further comprising: a first common electrode, the first common electrode being positioned on the first pixel electrode; as well as a second common electrode, the second common electrode being positioned on the second pixel electrode, The first common electrode and the second common electrode are spaced apart from each other via the dam structure, the first common electrode contacts the first portion of the auxiliary electrode, and the second common electrode contacts the second portion of the auxiliary electrode.

16. The display device according to claim 15, further comprising: a first inorganic layer, wherein the first inorganic layer covers the first common electrode; as well as a second inorganic layer, the second inorganic layer covering the second common electrode, The first inorganic layer and the second inorganic layer overlap the third portion of the auxiliary electrode and are spaced apart from each other.

17. The display device according to claim 16, further comprising: An organic encapsulation layer is positioned on the first inorganic layer and the second inorganic layer, wherein the third portion of the auxiliary electrode contacts the organic encapsulation layer.

18. A method for manufacturing a display device, the method comprising: forming a plurality of pixel electrodes spaced apart from each other, a sacrificial layer disposed on the pixel electrodes, a pixel defining layer disposed on the sacrificial layer, and a first bank material layer and a second bank material layer disposed on the pixel defining layer on a substrate; forming a first hole overlapping the pixel electrode and passing through the first bank material layer and the second bank material layer to expose the pixel defining layer disposed on the pixel electrode; forming a tip of the second bank material layer protruding from a sidewall of the first bank material layer by wet etching a sidewall of the first hole; forming an auxiliary electrode material layer covering the pixel defining layer, the first bank material layer and the second bank material layer; Forming an opening by removing a portion of the auxiliary electrode material layer overlapping the pixel electrode by wet etching, removing a portion of the pixel defining layer overlapping the pixel electrode by dry etching, and removing a portion of the sacrificial layer overlapping the pixel electrode by wet etching, and exposing the pixel electrode overlapping the opening; performing a heat treatment on the auxiliary electrode material layer covering the first bank material layer and the second bank material layer; forming a light emitting layer and a common electrode on each of the pixel electrodes in the opening, and forming an inorganic layer on the common electrode and the auxiliary electrode material layer; as well as partially removing a portion of the inorganic layer disposed on the auxiliary electrode material layer, Wherein, the auxiliary electrode material layer completely covers the tip of the second bank material layer.

19. The method of claim 18, wherein: The auxiliary electrode material layer becomes a crystalline transparent oxide through the heat treatment.

20. The method of claim 19, wherein: The first bank material layer and the second bank material layer are completely surrounded by the pixel defining layer and the auxiliary electrode material layer.

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