PIN amplitude limiter

Abstract

The invention discloses a PIN (Personal Identification Number) amplitude limiter, which adopts a three-stage amplitude limiting structure, and the first-stage amplitude limiting structure, the second-stage amplitude limiting structure and the third-stage amplitude limiting structure respectively adopt N1, N2 and N3 pairs of diode strings which are reversely connected in parallel, so that the amplitude limiter has higher bandwidth while resisting high power; in addition, T-shaped microstrip lines are arranged between the first-stage amplitude limiting structure and the input end and between the third-stage amplitude limiting structure and the output end, microstrip lines are arranged between the adjacent amplitude limiting structures, and microstrip lines are arranged in the first-stage amplitude limiting structure, so that the amplitude limiter can meet insertion loss which is low enough.

Description

Technical Field

[0001] The invention relates to a PIN limiter, belonging to the technical field of radio frequency microwaves. Background Art

[0002] With the rapid development of microwave technology, electronic systems such as radar, television broadcasting and communications have higher and higher requirements for high-power microwave devices, and the electromagnetic protection issues of electronic equipment cannot be ignored. The PIN limiter is one of the most important devices for electromagnetic protection. It is mainly used to prevent high-power microwave signals from damaging the receiver. When the input signal is small, the signal can pass through the limiter almost without attenuation, but as the power of the signal increases, the limiter will have a large attenuation on the signal, limiting the output signal amplitude to a certain range so that it does not change with the input signal.

[0003] PIN limiters are widely used in the front end of radar receivers. As a protection device for wireless communication systems, they are usually used between the receiving link antenna and other devices to protect the subsequent low-noise amplifiers, mixers and other sensitive devices from being damaged by high-power microwave signals. In addition, they must have good impedance matching to ensure low insertion loss and low noise, so as to avoid affecting the RF front end's reception performance for small signals.

[0004] The PIN passive limiter mainly limits the amplitude through the conductivity modulation effect of the PIN diode. The impedance value of the limiter can change with the input signal. When the input signal power level is lower than the limiting threshold level, the microwave signal passes through the transmission line with low loss to reach the load; when the input signal power level is higher than this threshold, the PIN limiting diode begins to conduct, the impedance value decreases, resulting in circuit mismatch, causing most of the input signal to be reflected back to the source, thereby achieving the limiting effect.

[0005] The traditional basic limiting circuit of the PIN passive limiter adopts a single-tube cascade circuit, with a quarter wavelength between the two stages. The front stage uses a PIN diode with a thicker intrinsic I layer to increase the power capacity, and the back stage uses a PIN diode with a thinner intrinsic I layer to speed up the conduction speed and improve the sensitivity. The circuit has a simple structure, small size, fast response time and no external power supply. However, the traditional passive limiting circuit has obvious defects. The inherent parasitic capacitance of the PIN diode will seriously affect the working bandwidth of the limiter. The traditional cascade method is difficult to simultaneously meet other performance requirements such as high power resistance, ultra-wideband, and low insertion loss. Summary of the invention

[0006] The present invention provides a PIN limiter, which solves the problem disclosed in the background technology.

[0007] According to one aspect of the present disclosure, there is provided a PIN limiter, comprising a first T-type microstrip line, a second microstrip line, a third microstrip line and a fourth T-type microstrip line; The main microstrip line in the first T-type microstrip line, the second microstrip line, the third microstrip line and the main microstrip line in the fourth T-type microstrip line are connected in series in sequence, N1 pairs of first diode strings and N1 fifth microstrip lines are connected in parallel between the first line and the ground, each pair of first diode strings includes two first diode strings connected in reverse parallel, N2 pairs of second diode strings are connected in parallel between the second line and the ground, each pair of second diode strings includes two second diode strings connected in reverse parallel, N3 pairs of two third diodes are connected in parallel between the third line and the ground, each pair of third diode strings includes two third diode strings connected in reverse parallel; wherein, the first line is a line between the main microstrip line and the second microstrip line in the first T-type microstrip line, the second line is a line between the second microstrip line and the third microstrip line, the third line is a line between the third microstrip line and the main microstrip line in the fourth T-type microstrip line, the number of diodes in the N2 pair of second diode strings is not less than the number of diodes in the N3 pair of two third diodes, and the number of diodes in the N1 pair of first diode strings is not less than the number of diodes in the N2 pair of second diode strings.

[0008] In some embodiments of the present disclosure, the thickness of the I-region of the first diode is greater than the thickness of the I-region of the second diode and the third diode.

[0009] In some embodiments of the present disclosure, the first diode is a circular junction PIN transistor, and the second diode and the third diode are elliptical junction PIN transistors.

[0010] In some embodiments of the present disclosure, the die size of the second diode is consistent with the die size of the third diode, and both are smaller than the die size of the first diode.

[0011] In some embodiments of the present disclosure, the lengths of the second microstrip line and the third microstrip line are consistent and both are shorter than the length of the fifth microstrip line.

[0012] In some embodiments of the present disclosure, two pairs of first diode strings and two fifth microstrip lines are connected in parallel between the first line and the ground.

[0013] In some embodiments of the present disclosure, the first diode string includes three diodes connected in series.

[0014] In some embodiments of the present disclosure, the second diode string and the third diode string each include one diode.

[0015] The beneficial effects achieved by the present invention are as follows: the present invention adopts a three-stage limiting structure, and the first-stage, second-stage and third-stage limiting structures respectively adopt N1, N2 and N3 pairs of reverse-parallel diode strings, which can make the limiter withstand high power while having a higher bandwidth, and the present invention arranges a T-shaped microstrip line between the first-stage limiting structure and the input end, and between the third-stage limiting and the output end, arranges a microstrip line between adjacent limiting structures, and arranges a microstrip line in the first-stage limiting structure, which can make the limiter meet a sufficiently low insertion loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is the structural diagram of PIN limiter; Figure 2 It is the simulation schematic diagram of PIN limiter; Figure 3 It is the limiting characteristic curve diagram of the PIN limiter; Figure 4 This is a diagram of small signal simulation results; Figure 5 This is the transient simulation result diagram of the PIN limiter; Figure 6 This is the result diagram of the junction capacitance of the first diode of the PIN limiter in the zero-bias state; Figure 7 is the IV curve of the first diode of the PIN limiter; Figure 8 This is the result diagram of junction capacitance of the second diode and the third diode of the PIN limiter in the zero bias state; Fig. 9 This is the IV curve diagram of the second diode and the third diode of the PIN limiter. DETAILED DESCRIPTION

[0017] The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is obvious that the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. The following description of at least one exemplary embodiment is actually only illustrative and is by no means intended to limit the present disclosure and its application or use. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present disclosure.

[0018] Unless otherwise specified, the relative arrangement of components and steps, the numerical expressions and numerical values ​​set forth in these embodiments do not limit the scope of the present disclosure.

[0019] At the same time, it should be understood that for the convenience of description, the sizes of the various parts shown in the drawings are not drawn according to the actual proportional relationship.

[0020] Technologies, methods, and equipment known to ordinary technicians in the relevant art may not be discussed in detail, but where appropriate, the technologies, methods, and equipment should be considered part of the specification.

[0021] In all examples shown and discussed herein, any specific values ​​should be interpreted as merely exemplary and not as limiting. Therefore, other examples of the exemplary embodiments may have different values.

[0022] It should be noted that similar symbols and letters refer to similar items in the following figures, and therefore, once an item is defined in one figure, it does not require further discussion in subsequent figures.

[0023] In order to solve the problem that the existing limiter is difficult to simultaneously meet the requirements of high power resistance, ultra-wide bandwidth and low insertion loss, the present disclosure proposes a PIN limiter.

[0024] Figure 1 The schematic diagram of an embodiment of the PIN limiter disclosed in the present invention includes a first T-type microstrip line TL1, a second microstrip line TL2, a third microstrip line TL3, a fourth T-type microstrip line TL4, a primary limiting structure, a secondary limiting structure, and a tertiary limiting structure. The main microstrip line in the first T-type microstrip line TL1, the second microstrip line TL2, the third microstrip line TL3, and the main microstrip line in the fourth T-type microstrip line TL4 are connected in series in sequence, and the primary limiting structure, the secondary limiting structure, and the tertiary limiting structure are connected to the first line, the second line, and the third line respectively; wherein the first line is the line between the main microstrip line in the first T-type microstrip line TL1 and the second microstrip line TL2, the second line is the line between the second microstrip line TL2 and the third microstrip line TL3, and the third line is the line between the third microstrip line TL3 and the main microstrip line in the fourth T-type microstrip line TL4.

[0025] It should be noted that all T-type microstrip lines mainly include a main microstrip line (i.e., the vertical microstrip line in the figure) and an open microstrip line connected to the main microstrip line (i.e., the vertical microstrip line in the figure). This structure can more flexibly adjust the impedance matching at the port by changing the microstrip lines of different lengths, thereby replacing the traditional λ / 4 transmission line and reducing the return loss at the input and output ends at high frequencies. Specifically, the loss at high frequencies can be reduced to below -20dB.

[0026] In an embodiment, the first-level limiting structure includes N1 pairs of first diode D1 strings and N1 fifth microstrip lines TL5, and the N1 pairs of first diode D1 strings and N1 fifth microstrip lines TL5 are all connected in parallel between the first line and the ground, and each pair of first diode D1 strings includes two reverse-parallel first diode D1 strings; wherein, the number of diodes in the first-level limiting structure is not less than the number of diodes in the second-level limiting structure, and the specific number N1 depends on the limiting index required by the limiter and the limiting capacity of a single diode, and is generally not less than 2.

[0027] Taking the figure as an example, two pairs of first diode strings D1 and two fifth microstrip lines TL5 are connected in parallel between the first line and the ground, and the first diode string D1 includes three diodes connected in series.

[0028] The first-stage limiting structure is formed by a power-splitting structure in which two pairs of first diodes D1 are connected in reverse parallel. The first diode D1 string of this structure has a sufficiently wide I zone thickness and can withstand large continuous wave power, thereby protecting the subsequent circuit, dispersing the incident current, improving the voltage handling capability, and increasing the heat dissipation area, thereby improving the overall power resistance performance of the circuit without increasing additional insertion loss.

[0029] In an embodiment, the secondary limiting structure includes N2 pairs of second diode D2 strings, each pair of second diode D2 strings includes two reverse-parallel second diode D2 strings; wherein the number of diodes in the secondary limiting structure is not less than the number of diodes in the tertiary limiting structure.

[0030] Taking the figure as an example, the secondary limiting structure is two second diodes D2, and the two second diodes D2 are connected in reverse parallel between the second line and the ground.

[0031] In the embodiment, the three-stage limiting structure includes N3 pairs of third diode D3 strings, each pair of third diode D3 strings includes two third diode D3 strings connected in reverse parallel; specifically, it may include two third diodes D3, and the two third diodes D3 are connected in reverse parallel between the third line and the ground.

[0032] It should be noted that the size of the second diode D2 is smaller than that of the first diode D1, and the two-stage limiting structure further limits the power leakage of the previous stage, and the second diode D2 of this stage is turned on before the first-stage diode.

[0033] It should be noted that the three-stage clipping structure can improve the overall bandwidth of the circuit, and the chip of this stage directly affects the value of the clipping level and can directly determine the turn-on response time. In order to minimize the impact on the turn-on response time, the size of the third diode D3 is consistent with the size of the second diode D2.

[0034] It should be noted that, since the primary limiting structure needs to have a sufficiently wide I region thickness, in some embodiments, the I region thickness of the first diode D1 is greater than the I region thickness of the second diode D2 and the third diode D3. Specifically, the first diode D1 adopts the circular junction PIN tube (PINC tube, i.e., Circle PIN tube) of Sanan PINAB11, and the second diode D2 and the third diode D3 adopt the elliptical junction PIN tube (PINO tube, i.e., Oval PIN tube) of Sanan PINAB11.

[0035] The PINC tube has a wider I zone thickness than the PINO. As a key component of the first-stage limiting structure, it can withstand sufficiently large continuous wave power, ensuring the high-power resistance of the limiter. The second and third stages use thinner PINO tubes to improve the limiting effect of the limiter and speed up the turn-on response time of the limiter when a large signal passes through.

[0036] It should be noted that the larger the size of the diode, the greater the current per unit area, the more fully it is turned on, and the more obvious the limiting characteristics, but it will also bring new insertion loss problems. In order to balance the relationship between insertion loss and conduction, after multiple simulation optimizations, the size of the PINC tube is determined to be 20μm×20μm, and the size of the PINO tube is 20μm×10μm.

[0037] Figure 6 and Figure 8 The following are the junction capacitance results of PINC and PINO tubes in zero bias state under the above specific dimensions. In the frequency range of 2-18GHz, the junction capacitance of PINC and PINO tubes in zero bias state is less than 100fF, showing high impedance under small signals, and their signals are almost completely reflected back to the main circuit, so the leakage signal is small, resulting in smaller insertion loss.

[0038] Figure 7 and Fig. 9 The IV curves of PINC and PINO tubes are respectively determined under certain dimensions. It can be calculated that the on-resistance of PINC tube is much greater than that of PINO tube, so the high power resistance of PINC tube is higher than that of PINO tube, and it is more suitable for the first-level limiting structure. The theoretical high power resistance of a single PINC tube can reach 27dBm.

[0039] The limiter threshold is related to the conduction voltage, operating frequency band and intrinsic layer width of the PIN diode. The limiter level of a single diode is usually around 10dBm. Here, two pairs of diode strings are used to control the limiter level to around 16dBm, limiting the large signal without affecting the small signal loss.

[0040] It should be noted that the diode used here is in a zero-bias state, and the I region forms a thin space charge layer at the junction boundary. The diode has a very small junction capacitance and appears as a high impedance to the outside. When a small signal is input, the impedance matching of the main circuit makes the signal attenuation smaller, and the output shows a small insertion loss state. When a high-power input signal passes through, the diode is in a forward-biased conduction state, and the external electric field causes the carriers of the P layer and the N layer to be continuously injected into the I region and recombined in the I region. Dynamic equilibrium is reached when the number of injected electron-hole pairs is equal to the number of recombined electron-hole pairs. At this time, a large number of carriers are stored in the I region, the conductivity is very large, and it is conductive to the outside. At this time, the diode is in a state of RF conductivity modulation, which is equivalent to a small resistor, causing a serious mismatch in the impedance of the RF circuit and producing a reflection limiting effect.

[0041] Therefore, in the forward bias state, the equivalent resistance R of region I can be obtained by the following calculation formula: f , let W be the thickness of zone I, A be the area of ​​zone I, μ p and μ n are the mobilities of holes and electrons respectively, and N is the total concentration of carrier injection at forward bias. The conductivity of region I can be expressed as: σ = μN × e; Where σ is the conductivity of zone I, μ=2μ p μ n / (μ p +μ n ) is the average mobility of holes and electrons, and e is the charge of the electron; Then the equivalent resistance of region I in the forward bias state can be expressed as: R f =W / eA(μ p p+μ n n); In the formula, the hole concentration p and the electron concentration n are generally considered to be the same, that is, p=n=N / 2, so the junction capacitance C of the I region is j In the reverse bias state, it can be estimated as: C j =ε0ε r πD 2 / 4W; In the formula, ε0 and ε r represent the vacuum dielectric constant and relative dielectric constant respectively, and D is the diameter of zone I.

[0042] Figure 6 This is the junction capacitance result diagram of the PINC tube in zero bias state. Figure 8 This is the result of the junction capacitance of the PINO tube in the zero-bias state. In the frequency range of 2-18GHz, the junction capacitance of the PINC tube and the PINO tube in the zero-bias state is less than 100fF, and the impedance under small signals is very large, so the leakage signal is small.

[0043] It should be noted that the lengths of the second microstrip line TL2, the third microstrip line TL3 and the fifth microstrip line TL5 are different. The limiting circuit is optimized by using microstrip lines with different impedances to reduce the insertion loss of the circuit. The inductor coil in the traditional microstrip line limiting circuit is used to improve the isolation of the circuit and expand the operating frequency band of the circuit. At the same time, the setting of the fifth microstrip line TL5 can reduce the insertion loss of the limiter while optimizing the standing wave.

[0044] In order to satisfy the requirement of lower insertion loss of the limiter, after multiple simulation optimizations, the lengths of the second microstrip line TL2 and the third microstrip line TL3 are consistent and both are shorter than the length of the fifth microstrip line TL5.

[0045] In the embodiment, a DC blocking capacitor is provided between the main microstrip line in the first T-type microstrip line TL1 and the input end of the PIN limiter, and between the main microstrip line in the fourth T-type microstrip line TL4 and the output end of the PIN limiter. In order to verify the above limiter, it is simulated. The simulation structure is as follows Figure 2 As shown, it is necessary to add DC blocking capacitors (i.e., DC Block) at both the input and output ends of the limiter to eliminate the influence of large DC signals on the circuit simulation results, and connect a 100nH large inductor L1 in parallel at the input end of the limiter as electrostatic protection to eliminate the electrostatic effect. Specifically, a 0.1nH metal wire is used to connect the port to the external dielectric substrate.

[0046] In the ADS2021 simulation software Figure 2 The limiter is used for small signal, harmonic balance and transient simulation. The results are as follows Figure 3 , 4 , as shown in Figure 5.

[0047] The simulation results show that within the 2~18GHz frequency band, it can be used as the front-end protection circuit of the RF receiver that fully covers the S, C, X, and Ku bands. The small signal insertion loss is less than -0.2dB, the return loss is below -20dB, the power withstand reaches 46dBm, the limiting level is less than 18dBm, and the input and output voltage standing wave ratio is less than 1.2. Due to the thinner size of the final PIN tube and the number of multi-stage parallel PIN tubes, the peak leakage time of the signal of the limiter is only 5ns under the condition of pulse signal excitation, and the peak voltage of the peak leakage is not obvious.

[0048] The overall final size of the above limiter is about 1.4mm×0.6mm, and it adopts a three-stage limiting structure. The first-stage limiting structure adopts two pairs of reverse-parallel diode strings, and the second-stage and third-stage limiting structures adopt reverse-parallel diodes, which can make the limiter withstand high power and have higher bandwidth. In addition, the above limiter sets a T-shaped microstrip line between the first-stage limiting structure and the input end, and between the third-stage limiting and the output end, sets a microstrip line between adjacent limiting structures, and sets a microstrip line in the first-stage limiting structure, so that the limiter can meet sufficiently low insertion loss. The limiter can withstand high power, has higher bandwidth, lower insertion loss, and a small area, and has broad application prospects.

[0049] The above is only a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the technical principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims

1. A PIN limiter, characterized in that: It includes a first T-type microstrip line, a second microstrip line, a third microstrip line and a fourth T-type microstrip line; The main microstrip line in the first T-type microstrip line, the second microstrip line, the third microstrip line and the main microstrip line in the fourth T-type microstrip line are connected in series in sequence, N1 pairs of first diode strings and N1 fifth microstrip lines are connected in parallel between the first line and the ground, each pair of first diode strings includes two reverse-parallel first diode strings, N2 pairs of second diode strings are connected in parallel between the second line and the ground, each pair of second diode strings includes two reverse-parallel second diode strings, N3 pairs of two third diodes are connected in parallel between the third line and the ground, each pair of third diode strings includes two reverse-parallel third diode strings; wherein the first line is a line between the main microstrip line and the second microstrip line in the first T-type microstrip line, the second line is a line between the second microstrip line and the third microstrip line, the third line is a line between the third microstrip line and the main microstrip line in the fourth T-type microstrip line, the number of diodes in the N2 pair of second diode strings is not less than the number of diodes in the N3 pair of two third diodes, and the number of diodes in the N1 pair of first diode strings is not less than the number of diodes in the N2 pair of second diode strings.

2. The PIN limiter according to claim 1, characterized in that: The thickness of the I region of the first diode is greater than the thickness of the I region of the second diode and the third diode.

3. The PIN limiter according to claim 2, characterized in that: The first diode is a circular junction PIN tube, and the second diode and the third diode are elliptical junction PIN tubes.

4. The PIN limiter according to any one of claims 1 to 3, characterized in that: The die size of the second diode is consistent with the die size of the third diode, and both are smaller than the die size of the first diode.

5. The PIN limiter according to claim 1, characterized in that: The lengths of the second microstrip line and the third microstrip line are consistent, and are both shorter than the length of the fifth microstrip line.

6. The PIN limiter according to claim 1, characterized in that: Two pairs of first diode strings and two fifth microstrip lines are connected in parallel between the first line and the ground.

7. The PIN limiter according to claim 1 or 6, characterized in that: The first diode string includes three diodes connected in series.

8. The PIN limiter according to claim 1, characterized in that: The second diode string and the third diode string each include one diode.

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