Software phase-locked loop algorithm with notch filter

Abstract

The invention provides a software phase-locked loop algorithm with a notch filter, and belongs to the field of power converters. The method comprises the following implementation steps: step 1, adopting a multiplication phase discriminator as a PD link, and carrying out operation on an input signal and a feedback signal; step 2, adding a notch filter to filter out a double frequency component; 3, controlling the phase difference to be zero through a PI control link; 4, converting the voltage signal passing through the PI (LPF) link into a frequency signal through a voltage-controlled oscillator (VCO); and step 5, after the frequency signal is obtained, inputting the frequency signal back to the phase discriminator through a feedback link as a feedback signal for operation with the input signal.

Description

Technical Field

[0001] The invention belongs to the field of power converters, and in particular relates to a software phase-locked loop algorithm with a notch filter. Background Art

[0002] Software PLL (SPLL) is a phase-locked loop algorithm implemented in a digital signal processor (DSP) or microcontroller, which is used to synchronize and track the frequency and phase of the input signal. Software PLL is widely used in power electronics and communication systems, especially in power converter design, where SPLL is used to accurately estimate the grid phase angle to synchronize power with the grid.

[0003] In the software phase-locked loop scenario, the loop filter has a low-pass characteristic that can filter out the high-frequency components output by the phase detector. When the frequency of the locked signal is high, the low-pass characteristic of the PI controller can filter out the existing double-frequency components. However, the frequency of the power grid is very low (50Hz), and the PI controller cannot achieve the ideal filtering effect. The high-frequency components output by the loop filter will affect the performance of the final PLL.

[0004] The low-pass characteristic of the PI controller cannot completely meet the requirement of filtering out the component of twice the grid frequency in the phase detector output. Therefore, a method must be found to linearize the output of the phase detector. Summary of the invention

[0005] In view of this, the object of the present invention is to provide a software phase-locked loop algorithm with a notch filter, which can be used to attenuate the twice frequency component of the grid voltage output by the phase detector. An adjustable notch filter can also accurately remove the component of the corresponding frequency when the voltage frequency fluctuates within a small range.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] The software phase-locked loop algorithm with notch filter includes the following steps:

[0008] Step 1: Use a multiplication phase detector as the PD link to calculate the input signal and the feedback signal;

[0009] Step 2: Add a notch filter to filter out the double frequency component;

[0010] Step 3: Control the phase difference to zero through the PI control link;

[0011] Step 4: Convert the voltage signal passing through the PI (LPF) link into a frequency signal through a voltage controlled oscillator (VCO);

[0012] Step 5: After the frequency signal is obtained, it is input back to the phase detector through the feedback link as a feedback signal to be operated with the input signal;

[0013] Assume the input signal is , the VCO output signal is The multiplier input and output can be expressed as:

[0014] .

[0015] .

[0016] In the dynamic case, the two signals have different frequencies and the instantaneous phase is:

[0017] Input signal: .

[0018] Output signal: .

[0019] So, the PD output is: ,in: is the signal amplitude, Angular frequency, ; Output signal amplitude, VCO natural frequency .

[0020] The transfer function of the notch filter structure is expressed in the s domain as:

[0021]

[0022] in, is the damping ratio of the system, is the natural frequency of the system. To make the system stable, C2<< C1 is required.

[0023] After discretizing the s-domain equation into the z-domain using the zero-order hold method:

[0024]

[0025] T is the sampling period, and the coefficient of the notch filter can be adjusted according to the swing of the grid frequency. The corresponding transmission energy consumption can be expressed as:

[0026] The PI transfer function is expressed in the s domain as:

[0027]

[0028] Where Kp is the proportional gain, Ki is the integral gain, and T is the sampling period.

[0029] After discretizing the s-domain equation into the z-domain using the zero-order hold method:

[0030]

[0031] The VCO transfer function is expressed in the s domain as:

[0032]

[0033] in is the LPF output, is the reference frequency.

[0034] After discretizing the s-domain equation into the z-domain using the zero-order hold method:

[0035]

[0036] After the above steps, the phase information is:

[0037]

[0038] in is the phase locked by the VCO output, mod is the modulo operation, is the phase information.

[0039] In order to improve the operation speed, the integral method is used to calculate the sine / cosine value, and the definition formula is:

[0040]

[0041] For a sine or cosine signal, this expression translates to:

[0042]

[0043]

[0044] Compared with the prior art, the advantages and beneficial effects of the present invention are as follows: the present invention effectively attenuates the double frequency interference problem at low frequencies, effectively reduces the amount of calculation, effectively improves the calculation speed, and effectively accelerates the phase-locking speed. Compared with the traditional phase-locked loop algorithm, the method of the present invention can well adapt to the phase-locking task at low frequencies.

[0045] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0046] In order to make the purpose, technical solutions and advantages of the present invention clearer, the present invention will be described in detail below in conjunction with the accompanying drawings, in which:

[0047] Figure 1 It is a block diagram of the software phase-locked loop system of the present invention.

[0048] Figure 2 It is the work flow chart of the present invention. DETAILED DESCRIPTION

[0049] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0050] The accompanying drawings are only for illustrative purposes and are schematic diagrams rather than physical drawings. They cannot be construed as limiting the present invention. In order to better illustrate the embodiments of the present invention, some parts of the accompanying drawings may be omitted, enlarged, or reduced, and do not represent the size of the actual product. It is understandable to those skilled in the art that some well-known structures and their descriptions may be omitted in the accompanying drawings. The same or similar reference numerals in the accompanying drawings of the embodiments of the present invention correspond to the same or similar parts.

[0051] The present invention provides a software phase-locked loop algorithm with a notch filter, which takes the minimum calculation task and accurate phase locking and filtering out double frequency interference as the optimization goal, realizes filtering out double frequency interference through the notch filter, increases the operation speed and phase locking accuracy, and includes the following steps:

[0052] Step 1: Use a multiplication phase detector as the PD link to calculate the input signal and the feedback signal;

[0053] Step 2: Add a notch filter to filter out the double frequency component;

[0054] Step 3: Control the phase difference to zero through the PI control link;

[0055] Step 4: Convert the voltage signal passing through the PI (LPF) link into a frequency signal through a voltage controlled oscillator (VCO);

[0056] Step 5: After the frequency signal is obtained, it is input back to the phase detector through the feedback link as a feedback signal to be operated with the input signal;

[0057] Furthermore, the present invention uses matlab simulink to simulate the algorithm.

[0058] The system generates a frequency , a sine wave with an initial phase of zero is used as the test signal, and the MatlabFunction module is called to implement the phase-locked algorithm.

[0059] Define two input signals u1, u2; output signal y.

[0060] Defines the PD storage multiplier phase detector output.

[0061] Define Notch to store the notch filter output.

[0062] Defines LPF to store loop filter output.

[0063] Define theta to store vector information, cos_out to store cosine, and sin_out to store sine.

[0064] In the multiplication phase-detection link, PD=u1*u2.

[0065] In the notch filter link, the discretized z-domain transfer function is solved:

[0066]

[0067] .

[0068] Among them, Notch* is the information at different times, Notch1 is the current information, Notch2 is the Notch* information of the next cycle, and the initial value is 0.

[0069] Similarly, in the LPF link, according to the discretized z-domain equation:

[0070]

[0071] .

[0072] Among them, LPF* is the information at different times, LPF1 is the current information, LPF2 is the LPF* information of the next cycle, and the initial value is 0.

[0073] In the VCO stage, the phase information is the sum of the reference signal W0 and the LPF output signal and then integrated:

[0074]

[0075] Among them, theta* is the information at different times, theta1 is the current information, theta2 is the theta* information of the next cycle, and the initial value is 0.

[0076] Use integration to solve for sine and cosine:

[0077]

[0078] Among them, cos_out* is the information at different times, cos_out1 is the current information, cos_out2 is the cos_out* information of the next cycle, and the initial value is 1.

[0079] Use in loop Parameters are updated and cos_out1 is fed back to the multiplication phase detector as feedback input.

[0080] Furthermore, a modular operation is performed outside the loop so that the phase θ∈[0, 2π].

[0081] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. Digital phase-locked loop algorithm with notch filter, characterized by: The following steps are involved: Step 1: Use a multiplication phase detector as the PD link to calculate the input signal and the feedback signal; Step 2: Add a notch filter to filter out the double frequency component; Step 3: Control the phase difference to zero through the PI control link; Step 4: Convert the voltage signal passing through the PI (LPF) link into a frequency signal through a voltage controlled oscillator (VCO); Step 5: After the frequency signal is obtained, it is input back to the phase detector through the feedback link as a feedback signal to be operated with the input signal.

2. The digital phase-locked loop algorithm with notch filter according to claim 1, characterized in that: The phase detector structure can be expressed as: Assume the input signal is v i , the VCO output signal is v o ; Therefore, the multiplier input and output can be expressed as v i (t)=V i sin[ω i t+θ i (t)] v o (t)=V o cos[ω o t+θ o (t)] PD=v i *v o Where: V i is the signal amplitude, ω i Angular frequency, θ i (t) instantaneous phase angle; V o Output signal amplitude, ω o VCO natural frequency θ o (t) instantaneous phase angle; In the dynamic case, the two signals have different frequencies and the instantaneous phase is: Input signal: [ω i t+θ i (t)]=[ω o t+θ1(t)] Output signal: [ω o t+θ o (t)]=[ω o t+θ2(t)] So, the PD output is: v PD (t)=K m v i (t)v o (t)。 3. The digital phase-locked loop algorithm with notch filter according to claim 1, characterized in that: The notch filter structure transfer function is expressed in the s domain as: where, C1 and C2 are the damping ratios of the system, and ω n is the natural frequency of the system. To ensure the stable operation of the system, it is necessary to make C2 << C1. After discretizing the s-domain equation to the z-domain using the zero-order hold method: T is the sampling period, and the coefficient of the notch filter can be adjusted according to the swing of the grid frequency; the corresponding transmission energy consumption can be expressed as.

4. The digital phase-locked loop algorithm with notch filter according to claim 1, characterized in that: The PI transfer function is expressed in the s domain as: Where Kp is the proportional gain, Ki is the integral gain, and T is the sampling period; after discretizing the s-domain equation to the z-domain using the zero-order hold method:

5. The digital phase-locked loop algorithm with notch filter according to claim 1, characterized in that: The VCO transfer function is expressed in the s domain as: where ω n is the LPF output, ω o is the reference frequency; after discretizing the s-domain equation to the z-domain using the zero-order hold method: The phase information is θ out mod 2π=θ where θ out is the phase locked by the VCO output, mod is the modulo operation, and θ is the phase information; The integral method is used to find the sine / cosine value, and the definition is: For a sine or cosine signal, this expression translates to: sin(t+Δt)=sin(t)+cos(t)*Δt cos(t+Δt)=cos(t)-sin(t)*Δt.

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