Semiconductor device and memory device

Abstract

Provided is a semiconductor device capable of achieving miniaturization or high integration. The semiconductor device includes a first conductor and a second conductor spaced apart from each other on an oxide, a third conductor in contact with a portion of a top surface of the first conductor, and a fourth conductor in contact with a portion of a top surface of the second conductor, the first insulator is arranged on the third conductor and the fourth conductor and is provided with an opening between the third conductor and the fourth conductor; the first insulator is arranged in the opening of the first insulator and is connected with the other part of the top surface of the first conductor and the other part of the top surface of the second conductor; a second insulator in contact with a side surface of the third conductor and a side surface of the fourth conductor; a third insulator in contact with a top surface of the oxide and side surfaces of the first conductor, the second conductor, and the second insulator; and a fifth conductor disposed on the third insulator. A distance between the first conductor and the second conductor is smaller than a distance between the third conductor and the fourth conductor, the second insulator includes a first layer and a second layer on the first layer, the first layer includes a nitride insulator, and the second layer includes an oxide insulator.

Description

Technical Field

[0001] One embodiment of the present invention relates to a semiconductor device, a storage device, and an electronic device using an oxide semiconductor. Another embodiment of the present invention relates to a method for manufacturing the semiconductor device.

[0002] Note that one embodiment of the present invention is not limited to the above-mentioned technical field. As an example of the technical field of one embodiment of the present invention, a semiconductor device, a display device, a light-emitting device, a power storage device, a storage device, an electronic device, a lighting device, an input device (e.g., a touch sensor), an input-output device (e.g., a touch panel), a driving method of the above-mentioned device, or a manufacturing method of the above-mentioned device can be cited.

[0003] Note that in this specification, etc., semiconductor devices refer to all devices that can work by utilizing semiconductor characteristics. In addition to semiconductor elements such as transistors, semiconductor circuits, computing devices, or storage devices are also a form of semiconductor devices. Sometimes it can be said that display devices (liquid crystal display devices, light-emitting display devices, etc.), projection devices, lighting devices, electro-optical devices, power storage devices, storage devices, semiconductor circuits, camera devices, electronic devices, etc. include semiconductor devices. Background Art

[0004] In recent years, semiconductor devices have been developed, and LSI, CPU, memory, etc. are mainly used for semiconductor devices. CPU is a collection of semiconductor elements including a semiconductor integrated circuit (including at least transistors and memory) formed by processing a semiconductor wafer into a chip and having electrodes as connection terminals.

[0005] Semiconductor circuits (IC chips) such as LSIs, CPUs, and memories are mounted on circuit boards (eg, printed wiring boards) and are used as one of the components of various electronic devices.

[0006] In addition, the technology of forming a transistor using a semiconductor thin film formed on a substrate having an insulating surface has attracted attention. The transistor is widely used in electronic devices such as integrated circuits (ICs) and image display devices (simply recorded as display devices). As a semiconductor thin film that can be applied to transistors, silicon-based semiconductor materials are widely known. As other materials, oxide semiconductors have attracted attention.

[0007] In addition, it is known that a transistor using an oxide semiconductor has extremely low leakage current in a non-conducting state. For example, Patent Document 1 has disclosed a low-power CPU that utilizes the low leakage current characteristic of a transistor using an oxide semiconductor. In addition, for example, Patent Document 2 has disclosed a storage device that can retain stored content for a long time by utilizing the low leakage current characteristic of a transistor using an oxide semiconductor.

[0008] Patent Document 3 discloses a transistor having a microstructure in which a source electrode layer and a drain electrode layer are provided in contact with the top surface of an oxide semiconductor.

[0009] [Prior technical literature]

[0010] [Patent Document]

[0011] [Patent Document 1] Japanese Patent Application Publication No. 2012-257187

[0012] [Patent Document 2] Japanese Patent Application Publication No. 2011-151383

[0013] [Patent Document 3] International Patent Application Publication No. 2016-125052 Summary of the invention

[0014] Technical problem to be solved by the invention

[0015] One of the purposes of one embodiment of the present invention is to provide a semiconductor device that can achieve miniaturization or high integration. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with a high operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with good electrical characteristics. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with small unevenness in the electrical characteristics of transistors. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with high reliability. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with a large on-state current. In addition, one of the purposes of one embodiment of the present invention is to provide a semiconductor device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a novel semiconductor device. In addition, one of the purposes of one embodiment of the present invention is to provide a method for manufacturing a semiconductor device with high productivity. In addition, one of the purposes of one embodiment of the present invention is to provide a novel method for manufacturing a semiconductor device.

[0016] In addition, one of the purposes of one embodiment of the present invention is to provide a storage device with a large storage capacity. In addition, one of the purposes of one embodiment of the present invention is to provide a storage device with a fast operating speed. In addition, one of the purposes of one embodiment of the present invention is to provide a storage device with low power consumption. In addition, one of the purposes of one embodiment of the present invention is to provide a novel storage device.

[0017] Note that the description of these purposes does not prevent the existence of other purposes. One embodiment of the present invention does not need to achieve all of the above purposes. Purposes other than the above can be extracted from the description of the specification, drawings, and claims.

[0018] Solutions to technical problems

[0019] One embodiment of the present invention is a semiconductor device, comprising: an oxide on a substrate; a first conductor and a second conductor separated from each other on the oxide; a third conductor in contact with a portion of a top surface of the first conductor; a fourth conductor in contact with a portion of a top surface of the second conductor; a first insulator arranged on the third and fourth conductors and having an opening overlapping a region between the third and fourth conductors; a second insulator arranged in the opening of the first insulator and in contact with another portion of the top surface of the first conductor, another portion of the top surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator arranged in the opening of the first insulator and in contact with the top surface of the oxide, the side surface of the first conductor, the side surface of the second conductor, and the side surface of the second insulator; and a fifth conductor arranged on the third insulator in the opening of the first insulator and having a region overlapping with the oxide via the third insulator, wherein a distance between the first and second conductors is smaller than a distance between the third and fourth conductors, and the second insulator comprises a first layer and a second layer on the first layer, the first layer comprises a nitride insulator, and the second layer comprises an oxide insulator.

[0020] In the semiconductor device, preferably, the first layer is in contact with the first conductor, the second conductor, the third conductor, the fourth conductor and the first insulator, and the second layer is not in contact with the first conductor, the second conductor, the third conductor, the fourth conductor and the first insulator.

[0021] In the above semiconductor device, the first layer preferably includes silicon nitride.

[0022] In the above semiconductor device, the second layer preferably includes silicon oxide.

[0023] In the above semiconductor device, the second layer preferably includes aluminum oxide.

[0024] In the above semiconductor device, the second layer preferably includes hafnium oxide.

[0025] In the above semiconductor device, the first conductor and the second conductor preferably include metal nitride.

[0026] In the above semiconductor device, the first conductor and the second conductor preferably include tantalum nitride.

[0027] In the above semiconductor device, preferably, the first conductor and the second conductor include tantalum nitride, and the third conductor and the fourth conductor include tungsten.

[0028] In the above semiconductor device, the difference between the distance between the third conductor and the fourth conductor and the distance between the first conductor and the second conductor is preferably equal to or substantially equal to twice the thickness of the second insulator.

[0029] Furthermore, in the above semiconductor device, it is preferred that the side surface of the opening of the first insulator is aligned or substantially aligned with the side surface of the third conductor and the side surface of the fourth conductor in a plan view.

[0030] Another embodiment of the present invention is a memory device including the semiconductor device and a capacitor, wherein one electrode of the capacitor is electrically connected to a third conductor of the semiconductor device.

[0031] Effects of the Invention

[0032] According to one embodiment of the present invention, a semiconductor device capable of miniaturization or high integration can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a high operating speed can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with good electrical characteristics can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with small unevenness in the electrical characteristics of transistors can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with high reliability can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with a large on-state current can be provided. In addition, according to one embodiment of the present invention, a semiconductor device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a novel semiconductor device can be provided. In addition, according to one embodiment of the present invention, a method for manufacturing a semiconductor device with high productivity can be provided. In addition, according to one embodiment of the present invention, a novel method for manufacturing a semiconductor device can be provided.

[0033] According to one embodiment of the present invention, a storage device with large storage capacity can be provided. In addition, according to one embodiment of the present invention, a storage device with high operating speed can be provided. In addition, according to one embodiment of the present invention, a storage device with low power consumption can be provided. In addition, according to one embodiment of the present invention, a novel storage device can be provided.

[0034] Note that the description of these effects does not prevent the existence of other effects. One embodiment of the present invention does not necessarily have all of the above effects. Effects other than the above can be extracted from the description of the specification, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1A is a plan view showing an example of a semiconductor device. Figures 1B to 1D is a cross-sectional view showing an example of a semiconductor device.

[0036] Figure 2A and Figure 2B is a cross-sectional view showing an example of a semiconductor device.

[0037] FIG. 3A to FIG. 3C is a cross-sectional view showing an example of a semiconductor device.

[0038] FIG. 4A to FIG. 4C is a cross-sectional view showing an example of a semiconductor device.

[0039] Figure 5A and Figure 5B is a cross-sectional view showing an example of a semiconductor device.

[0040] Fig. 6A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 6B to FIG. 6D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0041] Fig. 7A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 7B to FIG. 7D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0042] Fig. 8A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 8B to FIG. 8D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0043] Fig. 9A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 9B to FIG. 9D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0044] Fig. 10A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 10B to FIG. 10D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0045] Fig.11A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 11B to FIG. 11D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0046] Fig. 12A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 12B to FIG. 12D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0047] Fig.13A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 13B to FIG. 13Dis a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0048] Fig.14A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 14B to FIG. 14D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0049] FIG. 15A to FIG. 15C is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0050] Fig.16A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 16B to FIG. 16D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0051] Fig.17A It is a plan view showing an example of a method for manufacturing a semiconductor device. FIG. 17B to FIG. 17D is a cross-sectional view showing an example of a method for manufacturing a semiconductor device.

[0052] Fig.18 is a block diagram showing an example of a storage device.

[0053] Fig.19A and Fig.19B 1 is a schematic diagram and a circuit diagram showing an example of a storage device.

[0054] Fig. 20A and Fig. 20B is a schematic diagram showing an example of a storage device.

[0055] Fig.21 is a circuit diagram showing an example of a storage device.

[0056] Fig. 22 is a cross-sectional view showing an example of a storage device.

[0057] Fig.23 is a cross-sectional view showing an example of a storage device.

[0058] Fig.24 is a cross-sectional view showing an example of a storage device.

[0059] Fig.25 is a cross-sectional view showing an example of a storage device.

[0060] Fig.26 is a cross-sectional view showing an example of a storage device.

[0061] Fig. 27 is a cross-sectional view showing an example of a storage device.

[0062] FIG. 28A to FIG. 28C is a circuit diagram showing an example of a storage device.

[0063] Fig.29A and Fig.29B is a diagram showing an example of a semiconductor device.

[0064] Fig. 30A and Fig. 30B is a diagram showing an example of an electronic component;

[0065] Fig.31A and Fig.31B is a diagram showing an example of an electronic device, FIG. 31C to FIG. 31E This is a diagram showing an example of a large computer.

[0066] Fig.32 is a diagram showing an example of space equipment.

[0067] Fig.33 is a diagram showing an example of a storage system that can be used in a data center. DETAILED DESCRIPTION

[0068] The embodiments are described in detail with reference to the accompanying drawings. Note that the present invention is not limited to the following description, and a person skilled in the art can easily understand that the mode and details can be transformed into various forms without departing from the purpose and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the contents described in the embodiments shown below.

[0069] Note that in the invention structure described below, the same reference numerals are used in common in different drawings to represent the same parts or parts with the same function, and repeated description is omitted. In addition, when representing parts with the same function, the same hatching is sometimes used without adding a reference numeral.

[0070] In addition, for ease of understanding, the positions, sizes, and ranges of various components shown in the drawings may not represent their actual positions, sizes, and ranges. Therefore, the disclosed invention is not necessarily limited to the positions, sizes, and ranges disclosed in the drawings.

[0071] Note that in this specification, etc., ordinal numbers such as "first" and "second" are added for convenience, but they do not limit the number of components or the order of components (for example, the order of processes or the order of stacking). In addition, the ordinal numbers added to components in one part of this specification may not be consistent with the ordinal numbers added to the components in other parts of this specification or claims.

[0072] In addition, depending on the situation or condition, "film" and "layer" may be interchanged. For example, "conductive layer" may be interchanged with "conductive film". In addition, "insulating film" may be interchanged with "insulating layer". In addition, depending on the situation or condition, "conductive body" may be interchanged with "conductive layer" or "conductive film". In addition, depending on the situation or condition, "insulator" may be interchanged with "insulating layer" or "insulating film".

[0073] The opening includes, for example, a groove, a slit, etc. In addition, a region where the opening is formed may be referred to as an opening portion.

[0074] In addition, the drawings used in this embodiment mode illustrate the case where the side wall of the opening portion of the insulator is perpendicular or substantially perpendicular to the substrate surface or the formed surface, but the side wall may also have a tapered shape.

[0075] Note that in this specification, etc., a tapered shape refers to a shape in which at least a portion of the side surface of a constituent element is inclined relative to a substrate surface or a formed surface. For example, it is preferable to have a region in which the angle formed by the inclined side surface and the substrate surface or the formed surface (hereinafter, sometimes referred to as a taper angle) is less than 90°. Note that the side surface and the substrate surface of a constituent element do not necessarily have to be completely flat, and may be a substantially planar shape with a slight curvature or a substantially planar shape with fine concave-convex shapes.

[0076] (Implementation Method 1)

[0077] In this embodiment, a semiconductor device including an oxide semiconductor and a method for manufacturing the semiconductor device are described with reference to FIGS. 1 to 17 .

[0078] <Structural Example of Semiconductor Device>

[0079] An example of the structure of a semiconductor device will be described using FIGS. 1 to 5 . Figures 1A to 1D 1 and 2 are a plan view and a cross-sectional view of a semiconductor device (transistor 200 ). Figure 1A is a plan view of the semiconductor device. Figures 1B to 1D is a cross-sectional view of the semiconductor device. Figure 1B It is along Figure 1A The cross-sectional view of the portion along the dot-dash line A1-A2 in FIG. 1 is also a cross-sectional view along the channel length direction of the transistor 200. Figure 1C It is along Figure 1A The cross-sectional view of the portion along the dashed line A3-A4 in FIG. 1 is also a cross-sectional view along the channel width direction of the transistor 200. Figure 1D It is along Figure 1A The cross-sectional view of the portion along the dashed line A5-A6 in FIG. 1 is also a cross-sectional view in the channel width direction of the transistor 200. Note that Figure 1A In the plan view, some components are omitted for clarity. FIG. 2A to FIG. 5BAn enlarged cross-sectional view of the transistor 200 in the channel length direction is shown.

[0080] Transistor 200 includes a conductor 205 (conductor 205a and conductor 205b) arranged in a manner embedded in an insulator 216, an insulator 221 on the insulator 216 and the conductor 205, an insulator 222 on the insulator 221, an insulator 224 on the insulator 222, an oxide 230 (oxide 230a and oxide 230b) on the insulator 224, a conductor 242a (conductor 242a1 and conductor 242a2) and a conductor 242b (conductor 242b1 and conductor 242b2) on the oxide 230, an insulator 271a on the conductor 242a, an insulator 271b on the conductor 242b, an insulator 250 on the oxide 230, and a conductor 260 (conductor 260a and conductor 260b) on the insulator 250.

[0081] An insulator 275 is provided on the insulators 271a and 271b, and an insulator 280 is provided on the insulator 275. The insulator 250 and the conductor 260 are arranged inside the openings provided in the insulator 280 and the insulator 275. In addition, an insulator 255a and an insulator 255b (hereinafter, sometimes collectively referred to as the insulator 255) are arranged inside the openings. The insulator 255 is provided between the conductor 242a2, the conductor 242b2, the insulator 271a, the insulator 271b, the insulator 275, the insulator 280 and the insulator 250. In addition, an insulator 282 is provided on the insulator 280 and the conductor 260. In addition, an insulator 283 is provided on the insulator 282. In addition, an insulator 215 is provided under the insulator 216 and the conductor 205.

[0082] The oxide 230 has a region used as a channel formation region of the transistor 200. In addition, the conductor 260 has a region used as a first gate electrode (upper gate electrode) of the transistor 200. The insulator 250 has a region used as a first gate insulator of the transistor 200. In addition, the conductor 205 has a region used as a second gate electrode (lower gate electrode) of the transistor 200. The insulator 224, the insulator 222, and the insulator 221 all have a region used as a second gate insulator of the transistor 200.

[0083] The conductor 242a has a region that functions as one of a source electrode and a drain electrode of the transistor 200. The conductor 242b has a region that functions as the other of a source electrode and a drain electrode of the transistor 200.

[0084] The conductor 242a has a laminated structure of a conductor 242a1 and a conductor 242a2 on the conductor 242a1, and the conductor 242b has a laminated structure of a conductor 242b1 and a conductor 242b2 on the conductor 242b1. The conductors 242a1 and 242b1 in contact with the oxide 230b are preferably conductors that are not easily oxidized, such as metal nitrides. Thus, the conductors 242a and 242b can be prevented from being excessively oxidized due to oxygen in the oxide 230b. In addition, the conductors 242a2 and 242b2 are preferably conductors such as metal layers having higher conductivity than the conductors 242a1 and 242b1. Thus, the conductors 242a and 242b can be used as wiring or electrodes with high conductivity. In this way, a semiconductor device can be provided in which the conductors 242 a and 242 b serving as wirings or electrodes are provided in contact with the top surface of the oxide 230 serving as an active layer.

[0085] like Figure 2B As shown, when the transistor 200 is cross-sectionally viewed in the channel length direction, the distance L2 between the conductor 242a1 and the conductor 242b1 is smaller than the distance L1 between the conductor 242a2 and the conductor 242b2. Note that the distance L2 refers to the shortest distance between the conductor 242a1 and the conductor 242b1, and the distance L1 refers to the shortest distance between the conductor 242a2 and the conductor 242b2. Specifically, the difference between L1 and L2 is consistent or approximately consistent with twice the thickness of the insulator 255. Here, the thickness of the insulator 255 refers to the thickness in the A1-A2 direction of at least a portion of the insulator 255. By adopting this structure, the distance between the source and the drain can be further shortened and the channel length can be correspondingly reduced. Therefore, the frequency characteristics of the transistor 200 can be improved. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0086] The openings provided in the insulator 280 and the insulator 275 overlap with the area between the conductor 242a2 and the conductor 242b2. When viewed from above, the side surface of the insulator 280 in the opening is aligned or substantially aligned with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. In addition, a portion of the conductor 242a1 and the conductor 242b1 are formed in a manner protruding into the above-mentioned opening. Here, a portion of the top surface of the conductor 242a1 contacts the conductor 242a2, and a portion of the top surface of the conductor 242b1 contacts the conductor 242b2. Therefore, the insulator 255 contacts the other portion of the top surface of the conductor 242a1, the other portion of the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2 in the above-mentioned opening. In addition, the insulator 250 is in contact with the top surface of the oxide 230 , the side surface of the conductor 242 a 1 , the side surface of the conductor 242 b 1 , and the side surface of the insulator 255 .

[0087] The insulator 255 is formed into a side wall shape by anisotropic etching in a manner of contacting the side wall of the opening provided in the insulator 280 or the like (here, the side wall of the opening corresponds to, for example, the side of the insulator 280 or the like in the opening). The insulator 255 includes an insulator 255a and an insulator 255b. The insulator 255a is formed in a manner of contacting the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2. The insulator 255b is formed on the side closer to the conductor 260 than the insulator 255a, so it does not contact the top surface of the conductor 242a1, the top surface of the conductor 242b1, the side surface of the conductor 242a2, and the side surface of the conductor 242b2.

[0088] The insulator 255a preferably uses a nitride insulator. For example, silicon nitride can be used as the insulator 255a. The insulator 255a has a function of protecting the conductor 242a2 and the conductor 242b2. After the conductor 242a1 and the conductor 242b1 are separated and before the insulator 250 is deposited, it is preferable to perform heat treatment in an oxygen-containing atmosphere. At this time, since the insulator 255a is formed in a manner that contacts the side surface of the conductor 242a2 and the side surface of the conductor 242b2, the conductor 242a2 and the conductor 242b2 can be prevented from being excessively oxidized.

[0089] An oxide insulator is preferably used as the insulator 255b. For example, silicon oxide can be used as the insulator 255b. By using silicon oxide with a low dielectric constant for the insulator 255b, the distance between the conductor 260 and the conductor 242a or the conductor 242b can be increased to reduce parasitic capacitance. In addition, as the insulator 255b, for example, aluminum oxide or hafnium oxide can be used. Aluminum oxide and hafnium oxide have the function of capturing or fixing hydrogen that becomes an impurity in an oxide semiconductor. As a result, the electrical characteristics and reliability of a transistor using an oxide semiconductor can be improved.

[0090] The oxide 230 preferably includes an oxide 230a on the insulator 224 and an oxide 230b on the oxide 230a. By providing the oxide 230a below the oxide 230b, it is possible to suppress diffusion of impurities from a structure formed below the oxide 230a to the oxide 230b.

[0091] This embodiment shows an example in which the oxide 230 has a two-layer structure of the oxide 230 a and the oxide 230 b , but the present invention is not limited thereto. The oxide 230 may have a single-layer structure of the oxide 230 b or a stacked-layer structure of three or more layers.

[0092] The oxide 230b has a channel formation region of the transistor 200 and a source region and a drain region disposed so as to sandwich the channel formation region. At least a portion of the channel formation region overlaps with the conductor 260. The source region overlaps with the conductor 242a, and the drain region overlaps with the conductor 242b. Note that the source region and the drain region may be swapped.

[0093] Since the channel formation region has fewer oxygen vacancies or lower impurity concentration than the source region and the drain region, the channel formation region is a high resistance region with low carrier concentration. Therefore, the channel formation region can be said to be an i-type (intrinsic) or substantially i-type region.

[0094] In addition, the source region and the drain region have many oxygen vacancies or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, and are therefore low-resistance regions with high carrier concentrations. That is, the source region and the drain region are n-type regions (low-resistance regions) with higher carrier concentrations than the channel formation region.

[0095] The carrier concentration in the channel formation region is preferably 1×10 18 cm -3 Below, less than 1×10 17 cm -3 , less than 1×10 16 cm -3 , less than 1×10 15 cm -3 , less than 1×10 14 cm-3 , less than 1×10 13 cm -3 , less than 1×10 12 cm -3 , less than 1×10 11 cm -3 or less than 1×10 10 cm -3 Note that there is no particular restriction on the lower limit of the carrier concentration in the channel formation region, and it can be, for example, 1×10 -9 cm -3 .

[0096] In the case where the purpose is to reduce the carrier concentration of the oxide 230b, the impurity concentration in the oxide 230b can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor (or metal oxide) with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor (or metal oxide).

[0097] Therefore, in order to stabilize the electrical characteristics of the transistor 200, it is effective to reduce the impurity concentration in the oxide 230b. In order to reduce the impurity concentration in the oxide 230b, it is preferable to also reduce the impurity concentration in the nearby film. Impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, silicon, etc. Note that the impurities in the oxide 230b refer to, for example, elements other than the main component constituting the oxide 230b. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0098] In addition, the channel formation region, the source region, and the drain region may be formed not only in the oxide 230 b but also in the oxide 230 a .

[0099] In the oxide 230, it is sometimes difficult to clearly observe the boundaries between the regions. The concentrations of the metal elements and impurity elements such as hydrogen and nitrogen detected in each region do not need to change in stages for each region, but may change continuously in each region. That is, the closer to the channel formation region, the lower the concentrations of the metal elements and impurity elements such as hydrogen and nitrogen may be.

[0100] Note that a metal oxide serving as a semiconductor (hereinafter also referred to as an oxide semiconductor) is preferably used for the oxide 230 (the oxide 230 a and the oxide 230 b ).

[0101] The band gap of the metal oxide used as a semiconductor is preferably 2 eV or more, more preferably 2.5 eV or more. By using a metal oxide with a wider band gap, the off-state current of the transistor can be reduced. Therefore, a transistor containing a metal oxide in the channel formation region is called an OS transistor. The off-state current of the OS transistor is small, so the power consumption of the semiconductor device can be fully reduced. In addition, the frequency characteristics of the OS transistor are high, so the semiconductor device can be operated at high speed.

[0102] The oxide 230 preferably includes a metal oxide (oxide semiconductor). As metal oxides that can be used for the oxide 230, for example, indium oxide, gallium oxide and zinc oxide can be cited. The metal oxide preferably includes at least indium (In) or zinc (Zn). The metal oxide preferably includes two or three selected from indium, element M and zinc. In addition, the element M is a metal element or a metalloid element with a high bond energy with oxygen, for example, a metal element or a metalloid element with a bond energy with oxygen higher than that of indium. Specifically, as the element M, aluminum, gallium, tin, yttrium, titanium, vanadium, chromium, manganese, iron, cobalt, nickel, zirconium, molybdenum, hafnium, tantalum, tungsten, lanthanum, cerium, neodymium, magnesium, calcium, strontium, barium, boron, silicon, germanium and antimony can be cited. The element M contained in the metal oxide is preferably any one or more of the above elements, more preferably one or more selected from aluminum, gallium, tin and yttrium, and further preferably gallium. In addition, in this specification and the like, metal elements and metalloid elements may be collectively referred to as "metal elements", and the "metal elements" described in this specification and the like may include metalloid elements.

[0103] The oxide 230 can use, for example, indium zinc oxide (In-Zn oxide), indium tin oxide (In-Sn oxide), indium titanium oxide (In-Ti oxide), indium gallium oxide (In-Ga oxide), indium gallium aluminum oxide (In-Ga-Al oxide), indium gallium tin oxide (In-Ga-Sn oxide), gallium zinc oxide (Ga-Zn oxide, also referred to as GZO), aluminum zinc oxide (Al-Zn oxide, also referred to as AZO), indium aluminum zinc oxide (In-Al-Zn oxide, also referred to as IAZO), indium tin zinc oxide (In-Sn-Zn oxide), indium titanium zinc oxide (In-Ti-Zn oxide), indium gallium zinc oxide (In-Ga-Zn oxide, also referred to as IGZO), indium gallium tin zinc oxide (In-Ga-Sn-Zn oxide, also referred to as IGZTO), indium gallium aluminum zinc oxide (In-Ga-Al-Zn oxide, also referred to as IGAZO or IAGZO), etc. Alternatively, indium tin oxide, gallium tin oxide (Ga—Sn oxide), aluminum tin oxide (Al—Sn oxide), or the like containing silicon may be used.

[0104] At this time, by increasing the atomic number ratio of indium contained in the metal oxide relative to the total atomic number of all metal elements, the field effect mobility of the transistor can be increased.

[0105] In addition, the metal oxide may also replace indium or contain one or more metal elements with a large period number in addition to indium. The greater the orbital overlap of the metal element, the greater the carrier conduction in the metal oxide tends to be. Therefore, by including a metal element with a large period number, the field effect mobility of the transistor can sometimes be improved. As a metal element with a large period number, metal elements belonging to the 5th period and metal elements belonging to the 6th period can be cited. As the metal element, specifically, yttrium, zirconium, silver, cadmium, tin, antimony, barium, lead, bismuth, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium can be cited. In addition, lanthanum, cerium, praseodymium, neodymium, promethium, samarium and europium are called light rare earth elements.

[0106] In addition, the metal oxide may also contain one or more non-metallic elements. When the metal oxide contains non-metallic elements, the field effect mobility of the transistor may sometimes be improved. Examples of the non-metallic elements include carbon, nitrogen, phosphorus, sulfur, selenium, fluorine, chlorine, bromine, and hydrogen.

[0107] In addition, by increasing the ratio of the number of zinc atoms contained in the metal oxide to the total number of atoms of all metal elements, the crystallinity of the metal oxide is improved, thereby suppressing the diffusion of impurities in the metal oxide. Therefore, the variation of the electrical characteristics of the transistor is suppressed, thereby improving the reliability.

[0108] In addition, by increasing the atomic number ratio of the element M contained in the metal oxide relative to the sum of the atomic numbers of all metal elements, the formation of oxygen vacancies in the metal oxide can be suppressed. Therefore, the generation of carriers caused by oxygen vacancies is suppressed, thereby realizing a transistor with a small off-state current. In addition, the change of the electrical characteristics of the transistor is suppressed, thereby improving reliability.

[0109] As described above, the electrical characteristics and reliability of the transistor vary depending on the composition of the metal oxide used for the oxide 230. Therefore, by varying the composition of the metal oxide according to the electrical characteristics and reliability required of the transistor, a semiconductor device having both excellent electrical characteristics and high reliability can be realized.

[0110] The oxide 230 preferably has a stacked structure of a plurality of oxide layers having different chemical compositions. For example, the atomic number ratio of the element M in the metal oxide used for the oxide 230a to the metal element of the main component is preferably greater than the atomic number ratio of the element M in the metal oxide used for the oxide 230b to the metal element of the main component. In addition, the atomic number ratio of the element M in the metal oxide used for the oxide 230a to In is preferably greater than the atomic number ratio of the element M in the metal oxide used for the oxide 230b to In. By adopting this structure, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 230a to the oxide 230b.

[0111] In addition, the atomic number ratio of In in the metal oxide used for oxide 230b to element M is preferably greater than the atomic number ratio of In in the metal oxide used for oxide 230a to element M. With this structure, transistor 200 can obtain large on-state current and high frequency characteristics.

[0112] In addition, since oxide 230a and oxide 230b contain a common element as a main component in addition to oxygen, the defect state density at the interface between oxide 230a and oxide 230b can be reduced. As a result, the influence of interface scattering on carrier conduction is reduced, and transistor 200 can obtain a large on-state current and high frequency characteristics.

[0113] Specifically, as the oxide 230a, a metal oxide having a composition of In:M:Zn=1:3:2 [atomic ratio] or a composition close thereto, In:M:Zn=1:3:4 [atomic ratio] or a composition close thereto, or In:M:Zn=1:1:0.5 [atomic ratio] or a composition close thereto can be used. In addition, as the oxide 230b, a metal oxide having a composition of In:M:Zn=1:1:1 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:1.2 [atomic ratio] or a composition close thereto, In:M:Zn=1:1:2 [atomic ratio] or a composition close thereto, or In:M:Zn=4:2:3 [atomic ratio] or a composition close thereto can be used. Note that the nearby composition includes a range of ±30% of the desired atomic ratio. In addition, gallium is preferably used as the element M. In addition, when a single layer of the oxide 230b is provided as the oxide 230, the metal oxide that can be used for the oxide 230a can also be used as the oxide 230b. In addition, the composition of the metal oxide that can be used for the oxide 230a and the oxide 230b is not limited thereto. For example, the composition of the metal oxide that can be used for the oxide 230a can also be applied to the oxide 230b. Similarly, the composition of the metal oxide that can be used for the oxide 230b can also be applied to the oxide 230a.

[0114] Furthermore, when the metal oxide is deposited by sputtering, the above-mentioned atomic number ratio is not limited to the atomic number ratio of the deposited metal oxide, but may also be the atomic number ratio of the sputtering target used for the deposition of the metal oxide.

[0115] The oxide 230 b preferably has crystallinity. In particular, CAAC-OS (c-axis aligned crystalline oxide semiconductor) is preferably used as the oxide 230 b.

[0116] CAAC-OS has a dense structure with high crystallinity and is a metal oxide with few impurities and defects (e.g., oxygen vacancies). In particular, by heat treating the metal oxide at a temperature at which the metal oxide is not polycrystallized (e.g., above 400°C and below 600°C) after forming the metal oxide, the CAAC-OS can have a dense structure with higher crystallinity. In this way, by further increasing the density of CAAC-OS, the diffusion of impurities or oxygen in the CAAC-OS can be further reduced.

[0117] In addition, it is not easy to observe clear grain boundaries in CAAC-OS, so it is not easy to cause a decrease in electron mobility due to grain boundaries. Therefore, the physical properties of the metal oxide containing CAAC-OS are stable. Therefore, the metal oxide with CAAC-OS has heat resistance and high reliability.

[0118] In addition, by using a crystalline oxide such as CAAC-OS as the oxide 230 b, the source electrode or the drain electrode can suppress the extraction of oxygen from the oxide 230 b. Therefore, even if heat treatment is performed, the extraction of oxygen from the oxide 230 b can be reduced, so that the transistor 200 is also stable to the high temperature (so-called thermal budget) in the manufacturing process.

[0119] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in the region where the oxide semiconductor forms a channel, the electrical characteristics are easily changed, and reliability is sometimes reduced. In addition, hydrogen near the oxygen vacancy forms a defect in which hydrogen enters the oxygen vacancy (hereinafter sometimes referred to as V O H) and may generate electrons that become carriers. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor will have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V O H. In other words, it is preferable that the carrier concentration of the channel formation region in the oxide semiconductor is reduced and the oxide semiconductor is made i-type (intrinsic) or substantially i-type.

[0120] In contrast, by providing an insulator containing oxygen that is released by heating (hereinafter sometimes referred to as excess oxygen) near the oxide semiconductor and performing heat treatment, oxygen can be supplied from the insulator to the oxide semiconductor to reduce oxygen vacancies and V O H. Note that when too much oxygen is supplied to the source region or the drain region, the on-state current of the transistor 200 may decrease or the field effect mobility may decrease. Furthermore, when the amount of oxygen supplied to the source region or the drain region is uneven within the substrate surface, the characteristics of the semiconductor device including the transistor become uneven. In addition, when the oxygen supplied from the insulator to the oxide semiconductor diffuses to the conductor such as the gate electrode, the source electrode and the drain electrode, the conductor is sometimes oxidized, which leads to a loss of conductivity, thereby having a negative impact on the electrical characteristics and reliability of the transistor.

[0121] Therefore, in the oxide semiconductor, it is preferred that the carrier concentration of the channel formation region is reduced and the region is i-type or substantially i-type, while it is preferred that the carrier concentration of the source region and the drain region is high and the region is n-type. In other words, it is preferred to reduce oxygen vacancies and V O H. In addition, it is preferable that the source region and the drain region are not supplied with excessive oxygen and the V of the source region and the drain region are not excessively reduced. O H content. In addition, it is preferable to have a structure that suppresses a decrease in the conductivity of the conductor 260, the conductor 242a, the conductor 242b, and the like. For example, it is preferable to have a structure that suppresses oxidation of the conductor 260, the conductor 242a, the conductor 242b, and the like. Note that hydrogen in the oxide semiconductor may form V O H, so in order to reduce V O H amount, it is necessary to reduce the hydrogen concentration.

[0122] Therefore, the semiconductor device in this embodiment has a structure in which the hydrogen concentration in the channel formation region is reduced, oxidation of the conductors 242a, 242b, and 260 is suppressed, and reduction in the hydrogen concentration in the source region and the drain region is suppressed.

[0123] The insulator 250 in contact with the channel formation region in the oxide 230b preferably has a function of trapping or fixing hydrogen. Thus, the hydrogen concentration in the channel formation region of the oxide 230b can be reduced. Therefore, the V O H makes the channel formation region i-type or substantially i-type.

[0124] Here, if Figure 2AAs shown, the insulator 250 preferably has a stacked structure of an insulator 250a in contact with the oxide 230, an insulator 250b on the insulator 250a, and an insulator 250c on the insulator 250b. In this case, the insulator 250a preferably has a function of capturing or fixing hydrogen.

[0125] As an insulator having the function of capturing or fixing hydrogen, a metal oxide having an amorphous structure can be cited. As the insulator 250a, for example, a metal oxide such as magnesium oxide or an oxide containing one or both of aluminum and hafnium is preferably used. The above-mentioned metal oxide having an amorphous structure sometimes has the following property: the oxygen atom has a dangling bond and hydrogen is captured or fixed by the dangling bond. That is, it can be said that the metal oxide having an amorphous structure has a high ability to capture or fix hydrogen.

[0126] In addition, the insulator 250a preferably uses a high dielectric constant (high-k) material. As an example of a high-k material, there is an oxide containing one or both of aluminum and hafnium. When a high-k material is used as the insulator 250a, the gate potential applied when the transistor is operating can be reduced while maintaining the physical thickness of the gate insulator. In addition, the equivalent oxide thickness (EOT) of the insulator used as the gate insulator can be reduced.

[0127] Therefore, as the insulator 250a, it is preferred to use an oxide containing one or both of aluminum and hafnium, and it is more preferred to use an oxide having an amorphous structure and containing one or both of aluminum and hafnium. Since aluminum oxide can be used and an amorphous film can be easily deposited using the ALD method, it is further preferred to use aluminum oxide having an amorphous structure. In this embodiment, an aluminum oxide film is used as the insulator 250a. In this case, the insulator 250a is an insulator containing at least oxygen and aluminum. In addition, the aluminum oxide has an amorphous structure. In this case, the insulator 250a has an amorphous structure.

[0128] Next, as the insulator 250b, an insulator having thermal stability, such as silicon oxide or silicon oxynitride, is preferably used. Note that in this specification, etc., "oxynitride" refers to a material whose oxygen content is higher than the nitrogen content, and "nitride oxide" refers to a material whose nitrogen content is higher than the oxygen content. For example, "silicon oxynitride" refers to a material whose oxygen content is higher than the nitrogen content, and "silicon nitride oxide" refers to a material whose nitrogen content is higher than the oxygen content.

[0129] In addition, if Figure 3BAs shown in FIG. 1 , a structure in which an insulator 250d is provided on the insulator 250b may also be adopted. In this case, an insulator that can be used as the insulator 250a may be provided as the insulator 250d. For example, hafnium oxide may be used as the insulator 250d. Here, by providing the insulator 250d between the insulator 250c and the insulator 250b, hydrogen contained in the insulator 250b and the like may be more effectively captured and fixed.

[0130] In order to suppress oxidation of the conductors 242a, 242b, and 260, an oxygen blocking insulator is preferably provided near each of the conductors 242a, 242b, and 260. In the semiconductor device described in this embodiment, the insulators are, for example, the insulators 250a, 250c, 250d, 255a, and 275.

[0131] Note that in this specification, etc., a blocking insulator refers to an insulator having a barrier property. In this specification, etc., having a barrier property means having a property of hindering the penetration of a corresponding substance (also referred to as low permeability). For example, an insulator having a barrier property has a property that a corresponding substance does not easily diffuse into the inside of the insulator. For example, an insulator having a barrier property has a function of capturing or fixing (also referred to as gettering) a corresponding substance inside the insulator.

[0132] Examples of oxygen blocking insulators include oxides containing one or both of aluminum and hafnium, magnesium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon oxynitride. In addition, examples of oxides containing one or both of aluminum and hafnium include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). For example, the insulators 250a, 250c, 250d, 255a, and 275 preferably have a single-layer structure or a stacked-layer structure of the above-mentioned oxygen blocking insulators.

[0133] Insulator 250a and insulator 255a preferably have oxygen barrier properties. Insulator 250a and insulator 255a are preferably less likely to allow oxygen to penetrate than insulator 280. Insulator 250a has a region in contact with the side surface of conductor 242a1 and the side surface of conductor 242b1. Insulator 255a has a region in contact with the top surface of conductor 242a1, the top surface of conductor 242b1, the top surface of conductor 242a2, and the top surface of conductor 242b2. Insulator 250a is in contact with the side surface of insulator 255a. When insulator 250a and insulator 255a have oxygen barrier properties, it is possible to suppress the side surfaces of conductor 242a and conductor 242b from being oxidized and forming an oxide film on the side surfaces. Therefore, it is possible to suppress the decrease in the on-state current of transistor 200 or the decrease in field effect mobility.

[0134] The insulator 250a is provided in contact with the top surface and side surfaces of the oxide 230b, the side surfaces of the oxide 230a, the side surfaces of the insulator 224, and the top surface of the insulator 222. When the insulator 250a has oxygen barrier properties, it is possible to suppress the detachment of oxygen from the channel formation region of the oxide 230b during heat treatment, etc. Therefore, the formation of oxygen vacancies in the oxides 230a and 230b can be reduced.

[0135] In addition, by providing the insulator 250a and the insulator 255a, even if the insulator 280 contains too much oxygen, the excessive supply of oxygen to the oxide 230a and the oxide 230b can be suppressed, and an appropriate amount of oxygen can be supplied to the oxide 230a and the oxide 230b. Therefore, the source region and the drain region can be prevented from being excessively oxidized, and the decrease in the on-state current of the transistor 200 or the decrease in the field effect mobility can be suppressed.

[0136] Since an oxide containing one or both of aluminum and hafnium has an oxygen barrier property, it can be suitably used as the insulator 250 a .

[0137] In addition, silicon nitride has oxygen barrier properties, so it can be appropriately used as the insulator 255a. In this case, the insulator 255a is an insulator containing at least nitrogen and silicon as main components. In addition, the insulator 255a preferably has hydrogen barrier properties. Thus, impurities such as hydrogen in the conductors 242a2 and 242b2 can be prevented from diffusing into the oxide 230b.

[0138] The insulator 250c preferably has oxygen barrier properties. The insulator 250c is provided between the channel formation region of the oxide 230 and the conductor 260 and between the insulator 280 and the conductor 260. By adopting this structure, it is possible to suppress the diffusion of oxygen in the channel formation region of the oxide 230 into the conductor 260 and the formation of oxygen vacancies in the channel formation region of the oxide 230. In addition, it is possible to suppress the diffusion of oxygen in the oxide 230 and oxygen in the insulator 280 into the conductor 260 and the oxidation of the conductor 260. The insulator 250c is preferably at least less likely to allow oxygen to permeate than the insulator 280. For example, a silicon nitride film is preferably used as the insulator 250c. In this case, the insulator 250c is an insulator containing at least nitrogen and silicon.

[0139] In addition, the insulator 250c preferably has a hydrogen barrier property, so that impurities such as hydrogen contained in the conductor 260 can be prevented from diffusing into the oxide 230b.

[0140] Insulator 275 preferably has oxygen barrier properties. Insulator 275 is provided between insulator 280 and conductor 242a and between insulator 280 and conductor 242b. By adopting this structure, it is possible to suppress the diffusion of oxygen contained in insulator 280 into conductor 242a and conductor 242b. Therefore, it is possible to suppress the oxidation of conductor 242a and conductor 242b caused by oxygen contained in insulator 280, thereby increasing resistivity and reducing on-state current. Insulator 275 is preferably at least less likely to allow oxygen to penetrate than insulator 280. For example, silicon nitride is preferably used as insulator 275. At this time, insulator 275 is an insulator containing at least nitrogen and silicon.

[0141] In order to suppress a decrease in the hydrogen concentration in the source region and the drain region in the oxide 230 , a hydrogen blocking insulator is preferably provided near the source region and near the drain region. In the semiconductor device described in this embodiment, the hydrogen blocking insulator is, for example, the insulator 275 .

[0142] Examples of the hydrogen barrier insulator include oxides such as aluminum oxide, hafnium oxide, and tantalum oxide, and nitrides such as silicon nitride. For example, the insulator 275 preferably has a single-layer structure or a stacked-layer structure of the above hydrogen barrier insulators.

[0143] By providing the insulator 275, the diffusion of hydrogen from the source region and the drain region to the outside can be reduced, thereby suppressing the reduction of the hydrogen concentration in the source region and the drain region. Therefore, the source region and the drain region can be made n-type.

[0144] By adopting the above structure, the channel forming region can be i-type or substantially i-type and the source region and the drain region can be n-type, and a semiconductor device with good electrical characteristics can be provided. By adopting the above structure, even if the semiconductor device is miniaturized or highly integrated, it can have good electrical characteristics. In addition, by miniaturizing the transistor 200, the high-frequency characteristics can be improved. Specifically, the cut-off frequency can be increased.

[0145] Insulators 250a to 250d are used as part of the first gate insulator. Insulators 250a to 250d are arranged in an opening formed in insulator 280 together with insulator 255 and conductor 260. In order to achieve miniaturization of transistor 200, the thickness of insulators 250a to 250d is preferably thin. The thickness of insulators 250a to 250d is preferably 0.1nm or more and 10nm or less, more preferably 0.1nm or more and 5.0nm or less, further preferably 0.5nm or more and 5.0nm or less, further preferably 1.0nm or more and less than 5.0nm, and further preferably 1.0nm or more and 3.0nm or less. In addition, at least a portion of insulators 250a to 250d includes an area of ​​the above-mentioned thickness.

[0146] In order to reduce the thickness of the insulators 250a to 250d as described above, it is preferred to use an atomic layer deposition (ALD) method for deposition. In addition, in order to set the insulators 250a to 250d, the insulator 255a and the insulator 255b in the openings of the insulator 280, etc., it is preferred to use an ALD method for deposition. The ALD method includes a thermal ALD method that uses only thermal energy to react precursors and reactants, and a PEALD (Plasma Enhanced ALD) method that uses reactants excited by plasma. In the PEALD method, deposition can be performed at a lower temperature by using plasma, so it is sometimes preferred.

[0147] The ALD method can deposit atoms in layers, and thus has the advantages of being able to deposit extremely thin films, being able to deposit structures with high aspect ratios, being able to deposit with fewer defects such as pinholes, being able to deposit with high coverage, and being able to deposit at low temperatures. Therefore, the insulators 250 and 255 can be deposited with the aforementioned small thickness and high coverage on the side surfaces of the opening formed in the insulator 280 and the side ends of the conductors 242a and 242b.

[0148] The precursor used in the ALD method sometimes contains carbon, etc. Therefore, the film formed by the ALD method sometimes contains more impurities such as carbon than the film formed by other deposition methods. In addition, the quantitative analysis of impurities can be performed by secondary ion mass spectrometry (SIMS: Secondary Ion Mass Spectrometry), X-ray photoelectron spectroscopy (XPS: X-ray Photoelectron Spectroscopy) or Auger electron spectroscopy (AES: Auger Electron Spectroscopy).

[0149] Note that in the above description, the insulator 250 has a three-layer structure of the insulators 250a to 250c or a four-layer structure of the insulators 250a to 250d, but the present invention is not limited thereto. The insulator 250 may have a structure including at least one of the insulators 250a to 250d. By forming the insulator 250 with one, two, or three layers of the insulators 250a to 250d, the manufacturing process of the semiconductor device can be simplified, thereby improving productivity.

[0150] For example, Figure 3A As shown, the insulator 250 may also have a two-layer structure. In this case, the insulator 250 preferably has a stacked structure of an insulator 250a and an insulator 250c on the insulator 250a. A high-k material may be used for at least one of the insulator 250a and the insulator 250c. Thus, the equivalent oxide thickness (EOT) can be reduced while the thickness of the insulator 250a and the insulator 250c is maintained to a degree that suppresses leakage current.

[0151] In this embodiment, it is preferred that the semiconductor device has a structure for suppressing the mixing of hydrogen into the transistor 200, etc. in addition to the above-mentioned structure. For example, it is preferred that an insulator having a function of suppressing the diffusion of hydrogen is provided in a manner covering one or both of the upper and lower parts of the transistor 200, etc. In the semiconductor device described in this embodiment, the insulator is, for example, an insulator 283, an insulator 282, an insulator 222, and an insulator 221, etc. In addition, the insulator 215 under the transistor 200 may also have the same structure as either or both of the insulator 282 and the insulator 283. In this case, the insulator 215 may have a stacked structure of the insulator 282 and the insulator 283, and may adopt a structure in which the insulator 282 is located at the bottom and the insulator 283 is located at the top, or may adopt a structure in which the insulator 282 is located at the top and the insulator 283 is located at the bottom.

[0152] One or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 are preferably used as a blocking insulator to inhibit impurities such as water and hydrogen from diffusing from the substrate side or above the transistor 200 to the transistor 200. Therefore, one or more of the insulator 283, the insulator 282, the insulator 222, and the insulator 221 preferably contain an insulating material that does not easily diffuse (does not easily allow the above impurities to pass through) impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), and copper atoms. In addition, it is preferred to contain an insulating material that does not easily diffuse (does not easily allow the above oxygen to pass through) oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0153] Insulator 283, insulator 282, insulator 222, and insulator 221 preferably all include an insulator having a function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen, and for example, aluminum oxide, magnesium oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), an oxide containing hafnium and zirconium (hafnium zirconium oxide), gallium oxide, indium gallium zinc oxide, silicon nitride, or silicon oxynitride, etc., can be used. For example, silicon nitride with higher hydrogen barrier properties is preferably used for insulator 283 and insulator 221. In addition, for example, aluminum oxide with high ability to capture or fix hydrogen is preferably used for insulator 282. In addition, for example, hafnium oxide with high ability to capture or fix hydrogen and a high dielectric constant (high-k) material is preferably used for insulator 222.

[0154] By adopting such a structure, it is possible to suppress impurities such as water and hydrogen from diffusing from an interlayer insulating film or the like disposed above the insulator 283 to the transistor 200 or the like. In addition, it is possible to suppress impurities such as water and hydrogen from diffusing from an interlayer insulating film or the like disposed below the insulator 221 to the transistor 200 or the like. In addition, hydrogen in the insulators 280, 224, and 250 or the like can be captured or fixed to the insulator 282 or the insulator 222. In addition, by providing the insulators 282 and 283, it is possible to suppress oxygen in the insulators 280 or the like from diffusing to the top of the transistor 200 or the like. In addition, by providing the insulators 222 and 221, it is possible to suppress oxygen in the insulators 224 or the like from diffusing to the bottom of the transistor 200 or the like. In this way, by adopting a structure in which the upper and lower parts of the transistor 200 are surrounded by an insulator having a function of suppressing the diffusion of impurities such as water and hydrogen and oxygen, it is possible to reduce the diffusion of excess oxygen and hydrogen to the oxide semiconductor. Thus, it is possible to achieve improvement in the electrical characteristics and reliability of the semiconductor device.

[0155] In addition, the insulator 255a, the insulator 275, and the insulator 250c are preferably made of silicon nitride or the like having a higher hydrogen barrier property. In addition, for example, the insulator 250a is preferably made of aluminum oxide or the like having a high ability to capture or fix hydrogen.

[0156] Here, it is preferable that the region of the insulator 275 that does not overlap with the oxide 230 is in contact with the insulator 222, the side end of the insulator 275 is in contact with the insulator 255a, and the upper end of the insulator 255a and the upper ends of the insulators 250a to 250c are in contact with the insulator 282. With the above structure, in the region sandwiched between the insulator 283 and the insulator 221, the insulator 275 separates the insulator 280 from the oxide 230, the insulator 255a and the insulator 250a separate the insulator 280 from the insulator 250b, the insulator 250c separates the conductor 260 from the insulator 250b, and the insulator 255a and the insulator 250a separate the conductor 242a2 and the conductor 242b2 from the insulator 250b.

[0157] Thus, it is possible to suppress the diffusion of impurities such as water and hydrogen in the insulator 280 to the oxide 230 and the insulator 250b. In addition, it is possible to suppress the diffusion of impurities such as water and hydrogen in the conductor 260 to the oxide 230 through the insulator 250b. In addition, it is possible to suppress the diffusion of impurities such as water and hydrogen in the conductor 242a2 and the conductor 242b2 to the oxide 230 through the insulator 250b. For example, even if a contact plug is formed in contact with the top surface of the conductor 242a2 and the conductor 242b2 and impurities such as water and hydrogen diffuse to the conductor 242a2 and the conductor 242b2 through the contact plug, the diffusion of impurities such as water and hydrogen to the oxide 230 can be reduced. In addition, hydrogen in the insulator 250a and the insulator 250b can be captured and fixed to the insulator 282. By adopting such a structure, the diffusion of hydrogen to the oxide semiconductor can be further reduced. Thus, the electrical characteristics and reliability of the semiconductor device can be improved.

[0158] In the transistor 200, the conductor 205 is arranged so as to overlap with the oxide 230 and the conductor 260. Here, the conductor 205 is preferably provided so as to be embedded in the opening formed in the insulator 216. Figure 1A and Figure 1C As shown in FIG. 1 , the conductor 205 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 205 can be used as wiring when a plurality of transistors are arranged.

[0159] like Figure 1B and Figure 1C As shown, the conductor 205 preferably includes a conductor 205a and a conductor 205b. The conductor 205a is provided in a manner of contacting the bottom surface and the side wall of the above-mentioned opening. The conductor 205b is provided in a manner of being embedded in the concave portion of the conductor 205a formed along the above-mentioned opening. Here, the height of the top surface of the conductor 205 is consistent or substantially consistent with the height of the top surface of the insulator 216.

[0160] Here, as the conductor 205a, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (N2O, NO, NO2, etc.), copper atoms, etc. Alternatively, it is preferred that the conductor 205a includes a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0161] By using a conductive material having a function of reducing hydrogen diffusion as the conductor 205a, impurities such as hydrogen contained in the conductor 205b can be prevented from diffusing to the oxide 230 through the insulator 216 and the like. In addition, by using a conductive material having a function of inhibiting oxygen diffusion as the conductor 205a, it is possible to inhibit the conductor 205b from being oxidized and the conductivity from being reduced. As the conductive material having a function of inhibiting oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide can be cited. The conductor 205a can have a single-layer structure or a laminated structure of the above-mentioned conductive material. For example, the conductor 205a preferably contains titanium nitride.

[0162] In addition, the conductor 205b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. For example, the conductor 205b preferably contains tungsten.

[0163] The conductor 205 can be used as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 200 can be controlled by independently changing the potential applied to the conductor 205 without linking it with the potential applied to the conductor 260. In particular, by applying a negative potential to the conductor 205, the Vth of the transistor 200 can be further increased and the off-state current can be reduced. Thus, compared with the case where the negative potential is not applied to the conductor 205, when the negative potential is applied to the conductor 205, the drain current when the potential applied to the conductor 260 is 0V can be reduced.

[0164] In addition, the resistivity of the conductor 205 is designed in consideration of the potential applied to the conductor 205, and the thickness of the conductor 205 is set according to the resistivity. In addition, the thickness of the insulator 216 is substantially the same as that of the conductor 205. Here, it is preferred to reduce the thickness of the conductor 205 and the insulator 216 within the range allowed by the design of the conductor 205. By reducing the thickness of the insulator 216, the absolute amount of impurities such as hydrogen contained in the insulator 216 can be reduced, so the diffusion of the impurities into the oxide 230 can be suppressed.

[0165] Note that in the above structure, a stacked structure of the conductor 205a and the conductor 205b is shown, but the present invention is not limited thereto, and the conductor 205 may have a single-layer structure or a stacked structure of three or more layers. For example, when the conductor 205 has a three-layer stacked structure, the stacked structure of the conductor 205a and the conductor 205b described above may be adopted, and a conductor made of the same material as the conductor 205a may be provided on the conductor 205b. In this case, the conductor may be formed in a manner embedded in a recess formed by the conductor 205a and the conductor 205b, and the recess is formed in a manner such that the top surface of the conductor 205b is lower than the uppermost portion of the conductor 205a.

[0166] The insulator 224 , the insulator 221 , and the insulator 222 are used as a second gate insulator.

[0167] The insulator 224 in contact with the oxide 230 preferably includes, for example, silicon oxide or silicon oxynitride. Thus, oxygen can be supplied from the insulator 224 to the oxide 230 to reduce oxygen vacancies.

[0168] In addition, the insulator 224 is preferably processed into an island shape in the same manner as the oxide 230. Thus, when a plurality of transistors 200 are provided, an insulator 224 of substantially the same size is provided in each transistor 200. Therefore, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 is substantially equal. Thus, the non-uniformity of the electrical characteristics of the transistor 200 within the substrate surface can be suppressed. Note that this is not limiting, and a structure in which the pattern of the insulator 224 is not formed in the same manner as the insulator 222 may be adopted.

[0169] In addition, the insulator 224 may have a stacked structure of two or more layers. In this case, the insulator 224 is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials.

[0170] As the conductor 242a, the conductor 242b, and the conductor 260, it is preferable to use a conductive material that is not easily oxidized or a conductive material having a function of inhibiting oxygen diffusion. As the conductive material, for example, a conductive material containing nitrogen and a conductive material containing oxygen can be cited. Thus, the conductivity of the conductor 242a, the conductor 242b, and the conductor 260 can be suppressed from decreasing. When a conductive material containing metal and nitrogen is used as the conductor 242a, the conductor 242b, and the conductor 260, the conductor 242a, the conductor 242b, and the conductor 260 are conductors containing at least metal and nitrogen.

[0171] exist Figure 1B In the embodiment, the conductors 242a and 242b have a two-layer structure. The conductor 242a is a laminated film of the conductor 242a1 and the conductor 242a2 on the conductor 242a1, and the conductor 242b is a laminated film of the conductor 242b1 and the conductor 242b2 on the conductor 242b1. At this time, as the layer in contact with the oxide 230b (conductor 242a1 and conductor 242b1), it is preferred to use the above-mentioned conductive material that is not easily oxidized or a conductive material having the function of inhibiting oxygen diffusion. This can inhibit the conductivity of the conductors 242a and 242b from being reduced. In addition, it can inhibit oxygen from being extracted from the oxide 230b to form excessive oxygen vacancies. In addition, by using a material that easily absorbs (extracts) hydrogen as the layer in contact with the oxide 230b (conductor 242a1 and conductor 242b1), the hydrogen concentration of the oxide 230 can be reduced, so it is preferred.

[0172] As the conductors 242a1 and 242b1, metal nitrides are preferably used, for example, nitrides containing tantalum, nitrides containing titanium, nitrides containing molybdenum, nitrides containing tungsten, nitrides containing tantalum and aluminum, nitrides containing titanium and aluminum, etc. are preferably used. In one embodiment of the present invention, nitrides containing tantalum are particularly preferably used. In addition, for example, ruthenium, ruthenium oxide, ruthenium nitride, oxides containing strontium and ruthenium, oxides containing lanthanum and nickel, etc. can also be used. These materials are conductive materials that are not easily oxidized or materials that maintain conductivity even if they absorb oxygen, so they are preferred.

[0173] Note that hydrogen contained in the oxide 230b or the like may diffuse into the conductor 242a1 or the conductor 242b1. In particular, when a nitride containing tantalum is used as the conductor 242a1 or the conductor 242b1, hydrogen contained in the oxide 230b or the like may easily diffuse into the conductor 242a1 or the conductor 242b1, and the diffused hydrogen may bond with nitrogen contained in the conductor 242a1 or the conductor 242b1. In other words, hydrogen contained in the oxide 230b or the like may be absorbed by the conductor 242a1 or the conductor 242b1.

[0174] The electrical conductivity of the conductor 242a2 and the conductor 242b2 is preferably higher than that of the conductor 242a1 and the conductor 242b1. For example, the thickness of the conductor 242a2 and the conductor 242b2 is preferably greater than that of the conductor 242a1 and the conductor 242b1. As the conductor 242a2 and the conductor 242b2, a conductor that can be used for the conductor 205b described above can be used. By adopting the above structure, the resistance of the conductor 242a2 and the conductor 242b2 can be reduced. As a result, the operating speed of the semiconductor device according to this embodiment can be improved.

[0175] For example, tantalum nitride or titanium nitride can be used as the conductor 242 a 1 and the conductor 242 b 1 , and tungsten can be used as the conductor 242 a 2 and the conductor 242 b 2 .

[0176] In addition, in order to suppress the decrease in the conductivity of the conductors 242a and 242b, a crystalline oxide such as CAAC-OS is preferably used as the oxide 230b. In particular, it is preferred to use a metal oxide containing indium, zinc, and one or more selected from gallium, aluminum, and tin. When CAAC-OS is used, it is possible to suppress the conductor 242a or the conductor 242b from extracting oxygen from the oxide 230b. In addition, it is possible to suppress the decrease in the conductivity of the conductors 242a and 242b.

[0177] The insulator 255 has a stacked structure of an insulator 255a and an insulator 255b on the insulator 255a. Alternatively, it can be considered that the insulator 255b is disposed inside the insulator 255a. Figure 1B and Figure 1C As shown, insulator 255 is arranged in an opening formed in insulator 280 or the like, and is in contact with the side surface of insulator 280, the side surface of insulator 275, the side surface of insulator 271a, the side surface of insulator 271b, the side surface of conductor 242a2, the side surface of conductor 242b2, the top surface of conductor 242a1, the top surface of conductor 242b1, and the top surface of insulator 222. In other words, insulator 255 is formed in contact with the side wall of the opening formed in insulator 280 or the like. That is, insulator 255 can be called a sidewall insulating film. In addition, as Figure 1B As shown, a portion of the insulator 255 may be formed so as to be in contact with the side surface of the oxide 230 and the side surface of the insulator 224 .

[0178] The insulator 255a is formed so as to be in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2, and is an inorganic insulator that protects the conductor 242a2 and the conductor 242b2. The insulator 255a is in contact with the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top surface of the conductor 242a1, the top surface of the conductor 242b1, the top surface of the insulator 222, the side surface of the oxide 230, and the side surface of the insulator 224.

[0179] Here, if Figure 1B and Figure 1C As shown, a portion of the insulator 255a that contacts the top surface of the conductor 242a1, the top surface of the conductor 242b1, or the top surface of the insulator 222 is formed with a protrusion. The end of the protrusion of the insulator 255a contacts the insulator 250. The protrusion of the insulator 255a is in a shape that protrudes toward the center of the opening formed in the insulator 280 or the like more than other portions. In other words, in the cross section in the channel length direction, the insulator 255a can also be said to have a so-called L-shaped shape.

[0180] Since the insulator 255a is exposed to an oxidizing atmosphere, it is preferably an insulator that is not easily oxidized. In addition, since the insulator 255a is in contact with the conductor 242a2 and the conductor 242b2, it is preferably an inorganic insulator that is not easily oxidized by the conductor 242a2 and the conductor 242b2. Therefore, the insulator 255a preferably uses a nitride insulator that can be used for the insulator 250c having oxygen barrier properties. For example, silicon nitride can be used as the insulator 255a.

[0181] By using such an insulator 255a, even if heat treatment is performed in an oxygen-containing atmosphere after the conductor 242a1 and the conductor 242b1 are separated and before the insulator 250 is deposited, the conductor 242a2 and the conductor 242b2 are not excessively oxidized.

[0182] Insulator 255b is provided on the protrusion of insulator 255a. The bottom surface of insulator 255b contacts the top surface of the protrusion of insulator 255a, and one side surface of insulator 255b contacts the side surface of insulator 255a. In addition, when viewed from above, the other side surface of insulator 255b is formed in a manner aligned or substantially aligned with the end of the protrusion of insulator 255a. In addition, the other side surface of insulator 255b contacts insulator 250. Therefore, unlike insulator 255a, insulator 255b does not contact the side surface of insulator 280, the side surface of insulator 275, the side surface of insulator 271a, the side surface of insulator 271b, the side surface of conductor 242a2, the side surface of conductor 242b2, the top surface of conductor 242a1, the top surface of conductor 242b1, the top surface of insulator 222, the side surface of oxide 230, and the side surface of insulator 224.

[0183] Insulator 255b preferably uses an oxide insulator that can be used for insulator 250b. For example, silicon oxide can be used as insulator 255b. Insulator 255b preferably has a lower dielectric constant than insulator 255a. In this way, by increasing the thickness by adopting a two-layer structure as insulator 255, the distance between conductor 260 and conductor 242a or conductor 242b can be increased to reduce parasitic capacitance.

[0184] In addition, as the insulator 255b, an oxide insulator that can be used for the insulator 250a can also be used. For example, as the insulator 255b, aluminum oxide or hafnium oxide can be used. As described above, aluminum oxide and hafnium oxide have the function of capturing or fixing hydrogen. By using such an oxide insulator for the insulator 255b, the hydrogen concentration in the channel formation region of the insulator 250 and the oxide 230b and in the vicinity of the channel formation region can be reduced. As a result, the V O H, and the channel formation region can be made i-type or substantially i-type.

[0185] In addition, the thickness of the insulator 255 is preferably not less than 0.5 nm and not more than 20 nm, more preferably not less than 0.5 nm and not more than 10 nm, and further preferably not less than 0.5 nm and not more than 3 nm. When the insulator 255 has the above thickness, the conductor 242a2 and the conductor 242b2 can be suppressed from being over-oxidized. Note that the insulator 255 only needs to have a region with a thickness of the above value in at least a portion thereof. In addition, since the insulator 255 is arranged in a manner in contact with the side wall of the opening formed in the insulator 280, etc., it is preferably deposited using an ALD method with high coverage. When the thickness of the insulator 255 is too large, the deposition time of the insulator 255 using the ALD method is long, resulting in a decrease in productivity, so it is preferred to set the thickness of the insulator 255 approximately within the above range.

[0186] Here, in the case where silicon nitride is used as the insulator 255a, if the thickness of the insulator 255a is made too thick, a large amount of charge trapping is formed in the insulator 255a, which may hinder the function of the transistor 200. Therefore, the thickness of the insulator 255a is preferably smaller than that of the insulator 255b. For example, the thickness of the insulator 255a is preferably greater than 0.5 nm and less than 10 nm, and more preferably greater than 1 nm and less than 3 nm. In addition, the thickness of the insulator 255b is preferably smaller than that of the insulator 255a. For example, the thickness of the insulator 255b is preferably greater than 5 nm and less than 10 nm. Note that the thickness of the insulator 255a refers to the thickness in the A1-A2 direction of at least a portion of the insulator 255a, and the thickness of the insulator 255b refers to the thickness in the A1-A2 direction of at least a portion of the insulator 255b.

[0187] In addition, in the above description, an example is shown in which both the insulator 255a and the insulator 255b use a single-layer insulating film, but one or both of the insulator 255a and the insulator 255b may have a stacked structure with more than two layers. For example, the insulator 255a and the insulator 255b may be a stacked film in which silicon nitride, hafnium oxide, and silicon oxide are stacked in sequence. In addition, the insulator 255a and the insulator 255b may be a stacked film in which silicon nitride, aluminum oxide, and silicon oxide are stacked in sequence. In addition, the insulator 255a and the insulator 255b may be a stacked film in which silicon nitride, silicon oxide, and hafnium oxide are stacked in sequence. In addition, the insulator 255a and the insulator 255b may be a stacked film in which silicon nitride, silicon oxide, and aluminum oxide are stacked in sequence.

[0188] Notice, Figure 2A and Figure 2B The structure in which the insulator 255a is arranged on the outside and the insulator 255b is arranged on the inside is shown, but the present invention is not limited to this. As long as the oxidation of the side surfaces of the conductor 242a2 and the conductor 242b2 can be sufficiently suppressed, for example, Figure 3CAs shown in FIG. 1 , a structure in which the insulator 255b is arranged on the outside and the insulator 255a is arranged on the inside may be adopted. Here, the bottom surface of the insulator 255a may be in contact with the insulator 255b.

[0189] In addition, when the conductor 242a1 and the conductor 242b1 are separated, the insulator 255 is used as a mask. Figure 1B As shown in FIG. 2 and FIG. 3 , when the transistor 200 is viewed in cross section, the side end portions of the insulator 255 are preferably aligned or substantially aligned with the side end portions of the conductor 242 a 1 and the side end portions of the conductor 242 b 1 .

[0190] When the side ends are aligned or roughly aligned in cross-section and when the top surface shapes are consistent or roughly consistent, it can be said that at least a portion of their contours overlap each other between the stacked layers when viewed from above. For example, this includes a situation where the lower portion of the side end of the upper layer contacts the upper portion of the side end of the lower layer. In addition, for example, this includes a situation where the upper layer and the lower layer are processed by the same mask pattern or a part of the same mask pattern. In addition, for example, this includes a situation where the upper layer is used as a mask to process the lower layer. However, in reality, there are situations where the contours do not overlap, and sometimes a portion of the upper layer is located on the inner side of the lower layer or a portion of the upper layer is located on the outer side of the lower layer. In this case, it can also be said that "the side ends are aligned or roughly aligned" or "the top surface shapes are consistent or roughly consistent."

[0191] Here, in the conductor 242a1, the portion on the top surface of which the insulator 255 is formed is formed so as to protrude toward the conductor 260 side from the conductor 242a2. Similarly, in the conductor 242b1, the portion on the top surface of which the insulator 255 is formed is formed so as to protrude toward the conductor 260 side from the conductor 242b2. Figure 2B As shown, when the transistor 200 is cross-sectionally viewed in the channel length direction, the distance L2 between the conductors 242a1 and 242b1 is smaller than the distance L1 between the conductors 242a2 and 242b2. Specifically, the difference between L1 and L2 is equal to or substantially equal to twice the thickness of the insulator 255.

[0192] The distance L2 between the conductor 242a1 and the conductor 242b1 is preferably very small because it reflects on the channel length of the transistor 200. For example, the distance L2 is preferably less than 60nm, less than 50nm, less than 40nm, less than 30nm, less than 20nm or less than 10nm and more than 1nm or more than 5nm. For example, the distance L2 is more preferably about more than 2nm and less than 20nm. By adopting this structure, the distance between the source and the drain can be further shortened and the channel length can be correspondingly reduced. Therefore, the on-state current of the transistor 200 can be increased, the subthreshold swing value (sometimes recorded as S value) can be reduced, and the frequency characteristics can be improved. Here, the S value refers to: the change in the gate voltage in the subthreshold region that changes the value of the drain current by one digit with a fixed drain voltage. In this way, by miniaturizing the semiconductor device, a semiconductor device with improved operating speed can be provided.

[0193] like Figure 4A As shown, a recess may be formed in the portion of oxide 230b exposed from conductor 242a1 and conductor 242b1. In other words, on the top surface of oxide 230b, the height of the region sandwiched between conductor 242a1 and conductor 242b1 may be smaller than the region overlapping with conductor 242a1 and the region overlapping with conductor 242b1.

[0194] In addition, Figure 2A In the transistor 200 shown in FIG. 1 , the sides of the conductors 242a1 and 242b1 facing each other and the sides of the conductors 242a2 and 242b2 facing each other are perpendicular or substantially perpendicular to the top surface of the oxide 230b, but the present invention is not limited thereto. Figure 4B As shown, the mutually opposing side surfaces of the conductors 242a1 and 242b1 and the mutually opposing side surfaces of the conductors 242a2 and 242b2 may also be tapered. In this case, the side surfaces of the insulators 271a, 271b, 275, and 280 may be tapered.

[0195] In addition, the taper angle of the conductors 242a1 and 242b1 may be smaller than the taper angle of the conductors 242a2 and 242b2.

[0196] In addition, if Figure 4C As shown in FIG. 1 , the upper portion of the side surface of the insulator 255a and the insulator 255b may be tapered. Figure 4C As shown in FIG. 1 , sometimes a tapered shape that is continuous or substantially continuous with the tapered shapes of the side surfaces of the insulator 255a and the insulator 255b is formed on the upper portion of the insulator 280. Figure 4CAs shown, the upper portions of the insulator 255a, the insulator 255b, and the insulator 280 may have curved surfaces. Here, the insulator 250a may contact the tapered portions of the upper portions of the insulator 255a, the upper portions of the insulator 255b, and the upper portions of the insulator 280. At this time, when the upper portions of the insulator 255 and the insulator 280 have curved surfaces, the insulator 250a can be formed with high coverage.

[0197] Note that Figure 5A As shown, transistor 200 may also have FIG. 4A to FIG. 4C That is, the portion of the oxide 230b exposed from the conductors 242a1 and 242b1 may have a recess, the side surfaces of the conductors 242a1 and 242b1 and the side surfaces of the conductors 242a2 and 242b2 may be tapered, and the upper portion of the side surface of the insulator 255 may be tapered.

[0198] In addition, Figures 1A to 1C , etc. show a structure in which the side surface of the insulator 255b on the side of the conductor 260 is aligned or substantially aligned with the end of the protruding portion of the insulator 255a when viewed from above, but the present invention is not limited to this. Figure 5B As shown in FIG. 1 , the side surface of the insulator 255b on the side of the conductor 260 may also have a shape that is set back from the end of the protruding portion of the insulator 255a. By adopting this structure, the width of the upper portion of the conductor 260 is greater than the width of the lower portion of the conductor 260. As a result, the wiring resistance of the conductor 260 can be reduced.

[0199] The insulators 271a and 271b are inorganic insulators used as etching stop layers to protect the conductors 242a2 and 242b2 during the processing of the conductors 242a2 and 242b2. In addition, since the insulators 271a and 271b are in contact with the conductors 242a2 and 242b2, inorganic insulators that are not easily oxidized by the conductors 242a and 242b are preferably used. Figure 2A As shown, it is preferred that the insulator 271a has a stacked structure of an insulator 271a1 and an insulator 271a2 on the insulator 271a1, and the insulator 271b has a stacked structure of an insulator 271b1 and an insulator 271b2 on the insulator 271b1. Here, the insulators 271a1 and 271b1 preferably use a nitride insulator that can be used for the insulator 250c so as not to oxidize the conductors 242a2 and 242b2. In addition, in order to function as an etching stop layer, the insulators 271a2 and 271b2 preferably use an oxide insulator that can be used for the insulator 250b.

[0200] Here, the insulator 271a1 is in contact with the top surface of the conductor 242a2 and a part of the insulator 275, and the insulator 271b1 is in contact with the top surface of the conductor 242b2 and a part of the insulator 275. In addition, the insulator 271a2 is in contact with the top surface of the insulator 271a1 and the bottom surface of the insulator 275, and the insulator 271b2 is in contact with the top surface of the insulator 271b1 and the bottom surface of the insulator 275. For example, silicon nitride can be used as the insulator 271a1 and the insulator 271b1, and silicon oxide can be used as the insulator 271a2 and the insulator 271b2.

[0201] The insulators to be insulators 271a and 271b are used as masks for the conductors to be conductors 242a and 242b, so that conductors 242a and 242b do not have a curved surface between the side and the top surface. Thus, the ends where the side and top surfaces of conductors 242a and 242b intersect are angular. When the ends where the side and top surfaces of conductors 242a and 242b intersect are angular, the cross-sectional areas of conductors 242a and 242b are increased compared to the case where the ends have curved surfaces. Furthermore, by using nitride insulators that are not easy to oxidize metals as insulators 271a1 and 271b1, it is possible to prevent conductors 242a and 242b from being over-oxidized. Thus, the resistance of conductors 242a and 242b is reduced, so the on-state current of the transistor can be increased.

[0202] like Figure 1B and Figure 1C As shown, the conductor 260 is arranged in the opening formed in the insulator 280 and the insulator 275. In the opening, the conductor 260 is provided so as to cover the top surface of the insulator 222, the side surface of the insulator 224, the side surface of the oxide 230a, the side surface of the oxide 230b, and the top surface of the oxide 230b via the insulator 250. In addition, the top surface of the conductor 260 is arranged so as to be consistent or substantially consistent with the height of the uppermost portion of the insulator 250, the uppermost portion of the insulator 255, and the top surface of the insulator 280.

[0203] In the opening in which the conductor 260 and the insulator 250 are arranged, the side wall of the opening may be vertical or substantially vertical to the top surface of the insulator 222, or may have a tapered shape. The tapered side wall can improve the coverage of the insulator 255 and the insulator 250 etc. provided in the opening of the insulator 280, thereby reducing defects such as voids.

[0204] The conductor 260 is used as a first gate electrode of the transistor 200. Figure 1A and Figure 1CAs shown in FIG. 1 , the conductor 260 is preferably arranged to extend in the channel width direction. By adopting such a structure, the conductor 260 can be used as wiring when a plurality of transistors are arranged.

[0205] In the case of adopting the above structure, if Figure 1C As shown, when the transistor 200 is cross-sectionally viewed in the channel width direction, a curved surface may be provided between the side surface of the oxide 230b and the top surface of the oxide 230b. That is, the end of the side surface and the end of the top surface may be curved (hereinafter also referred to as rounded).

[0206] The radius of curvature of the curved surface is preferably greater than 0 nm and less than the thickness of the oxide 230b in the region overlapping with the conductors 242a and 242b or less than half the length of the region without the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and less than 20 nm, preferably greater than 1 nm and less than 15 nm, and more preferably greater than 2 nm and less than 10 nm. By adopting the above shape, the coverage of the insulator 250 and the conductor 260 to the oxide 230b can be improved.

[0207] In this specification, etc., a transistor structure in which a channel forming region is surrounded by an electric field of at least a first gate electrode is referred to as a surrounded channel (S-channel) structure. In addition, the S-channel structure disclosed in this specification, etc. is different from a Fin-type structure and a planar structure. On the other hand, the S-channel structure disclosed in this specification, etc. can be regarded as a type of Fin-type structure. In addition, in this specification, etc., a Fin-type structure refers to a structure in which a gate electrode is configured in a manner that surrounds at least two or more surfaces of a channel (specifically, two surfaces, three surfaces, or four surfaces, etc.). By adopting a Fin-type structure and an S-channel structure, resistance to short channel effects can be improved, in other words, a transistor that is not prone to short channel effects can be realized.

[0208] By adopting the above-mentioned S-channel structure as transistor 200, the channel formation region can be electrically surrounded. The S-channel structure is a structure that electrically surrounds the channel formation region, so it can also be said that the structure is substantially the same as the GAA (Gate All Around: full surround gate) structure or the LGAA (Lateral Gate All Around: lateral full surround gate) structure. By making the transistor 200 have an S-channel structure, a GAA structure, or a LGAA structure, the channel formation region formed at or near the interface between the oxide 230 and the gate insulator can be regarded as the entire bulk of the oxide 230. Therefore, the current density flowing through the transistor can be increased, so it can be expected that the on-state current of the transistor or the field effect mobility of the transistor will be improved.

[0209] This embodiment adopts a structure in which the insulator 224 is set to an island shape. Figure 1C As shown, at least a portion of the bottom surface of the conductor 260 can be disposed below the bottom surface of the oxide 230b. Thus, the conductor 260 can be disposed in a manner opposite to the top surface and the side surface of the oxide 230b, so that the electric field of the conductor 260 can act on the top surface and the side surface of the oxide 230b. In this way, by adopting a structure in which the insulator 224 is disposed in an island shape, the transistor 200 can have an S-channel structure.

[0210] Note that as Figure 1C The transistor 200 shown is an S-channel structure transistor, but the semiconductor device of one embodiment of the present invention is not limited thereto. For example, as a structure of a transistor that can be used in one embodiment of the present invention, any one or more selected from a planar structure, a Fin structure, and a GAA structure can also be used.

[0211] exist Figure 1B In the embodiment, the conductor 260 has a two-layer structure. Here, the conductor 260 preferably includes a conductor 260a and a conductor 260b disposed on the conductor 260a. For example, the conductor 260a is preferably disposed so as to surround the bottom surface and the side surface of the conductor 260b. At this time, as the conductor 260a, it is preferable to use a conductive material that is not easily oxidized or a conductive material that has a function of inhibiting oxygen diffusion.

[0212] As the conductor 260a, it is preferred to use a conductive material having a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. In addition, it is preferred to use a conductive material having a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0213] In addition, when the conductor 260a has a function of suppressing oxygen diffusion, it is possible to suppress the decrease in conductivity caused by oxidation of the conductor 260b by oxygen contained in the insulator 280, etc. As a conductive material having a function of suppressing oxygen diffusion, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, etc. are preferably used.

[0214] In addition, the conductor 260b preferably uses a conductor with high conductivity. For example, the conductor 260b can use a conductive material with tungsten, copper or aluminum as a main component. In addition, the conductor 260b can have a laminated structure, for example, a laminated structure of titanium or titanium nitride and the above conductive materials.

[0215] In the transistor 200, the conductor 260 is formed in a self-aligned manner so as to fit into an opening formed in the insulator 280 or the like. By forming the conductor 260 in this manner, the conductor 260 can be arranged to overlap the region between the conductor 242a1 and the conductor 242b1 without alignment.

[0216] The dielectric constant of each of the insulator 216 and the insulator 280 is preferably lower than that of the insulator 222. By using a material with a low dielectric constant for the interlayer film, parasitic capacitance generated between wirings can be reduced.

[0217] For example, the insulator 216 and the insulator 280 preferably include one or more of silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, and silicon oxide having pores.

[0218] In particular, silicon oxide and silicon oxynitride are preferred because they have thermal stability. In particular, silicon oxide, silicon oxynitride, silicon oxide having pores and the like are preferred because they easily form a region containing oxygen released by heating.

[0219] In addition, the top surfaces of the insulator 216 and the insulator 280 may also be planarized.

[0220] The concentration of impurities such as water and hydrogen in the insulator 280 is preferably reduced. For example, an oxide containing silicon, such as silicon oxide or silicon oxynitride, is preferably used as the insulator 280 .

[0221] <Materials Constituting Semiconductor Devices>

[0222] The constituent materials that can be used for the semiconductor device are described below. Note that each layer constituting the semiconductor device may have a single-layer structure or a stacked-layer structure.

[0223] <<Substrate>>

[0224] As a substrate for forming a transistor, for example, an insulator substrate, a semiconductor substrate or a conductor substrate can be used. As an insulator substrate, for example, a glass substrate, a quartz substrate, a sapphire substrate, a stabilized zirconia substrate (yttria stabilized zirconia substrate, etc.) and a resin substrate can be cited. In addition, as a semiconductor substrate, for example, a semiconductor substrate made of silicon or germanium, and a compound semiconductor substrate composed of silicon carbide, silicon germanium, gallium arsenide, indium phosphide, zinc oxide or gallium oxide can be cited. In addition, a semiconductor substrate having an insulator region inside the above-mentioned semiconductor substrate can also be cited, such as an SOI (Silicon On Insulator) substrate. As a conductor substrate, for example, a graphite substrate, a metal substrate, an alloy substrate, and a conductive resin substrate can be cited. In addition, as a substrate, for example, a substrate containing a metal nitride, a substrate containing a metal oxide, an insulator substrate provided with a conductor or a semiconductor, a semiconductor substrate provided with a conductor or an insulator, and a conductor substrate provided with a semiconductor or an insulator can be cited. Alternatively, a substrate having one or more elements provided on these substrates can also be used. Examples of the element provided over the substrate include a capacitor, a resistor, a switching element, a light emitting element, and a memory element.

[0225] <<Insulator>>

[0226] Examples of the insulator include oxides, nitrides, oxynitrides, oxynitrides, metal oxides, metal oxynitrides, and metal oxynitrides having insulating properties.

[0227] For example, when miniaturization and high integration of transistors are being carried out, problems such as leakage current sometimes occur due to the thin film of the gate insulator. By using a high-k material as an insulator used as a gate insulator, it is possible to achieve low voltage when the transistor is operating while maintaining the physical thickness. On the other hand, by using a material with a low relative dielectric constant for an insulator used as an interlayer film, the parasitic capacitance generated between wirings can be reduced. Therefore, it is preferable to select a material according to the function of the insulator.

[0228] Examples of insulators having a relatively high dielectric constant include gallium oxide, hafnium oxide, zirconium oxide, oxides containing aluminum and hafnium, oxynitrides containing aluminum and hafnium, oxides containing silicon and hafnium, oxynitrides containing silicon and hafnium, or nitrides containing silicon and hafnium.

[0229] Examples of insulators having a relatively low dielectric constant include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide added with fluorine, silicon oxide added with carbon, silicon oxide added with carbon and nitrogen, silicon oxide having pores, and resins.

[0230] In addition, by surrounding a transistor using a metal oxide with an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, the electrical characteristics of the transistor can be stabilized. As an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, a single layer or stack of an insulator containing one or more of boron, carbon, nitrogen, oxygen, fluorine, magnesium, aluminum, silicon, phosphorus, chlorine, argon, gallium, germanium, yttrium, zirconium, lanthanum, neodymium, hafnium and tantalum can be used. Specifically, as an insulator having the function of inhibiting the permeation of impurities such as hydrogen and oxygen, for example, metal oxides such as aluminum oxide, magnesium oxide, gallium oxide, germanium oxide, yttrium oxide, zirconium oxide, lanthanum oxide, neodymium oxide, hafnium oxide, and tantalum oxide, and metal nitrides such as aluminum nitride, silicon oxynitride, and silicon nitride can be cited.

[0231] In addition, the insulator used as the gate insulator is preferably an insulator having a region containing oxygen that is released by heating. For example, by using a structure in which silicon oxide or silicon oxynitride having a region containing oxygen that is released by heating is in contact with oxide 230, oxygen vacancies contained in oxide 230 can be filled.

[0232] <<Conductor>>

[0233] As the conductor, it is preferred to use a metal element selected from aluminum, chromium, copper, silver, gold, platinum, tantalum, nickel, titanium, molybdenum, tungsten, hafnium, vanadium, niobium, manganese, magnesium, zirconium, beryllium, indium, ruthenium, iridium, strontium and lanthanum, an alloy with the above metal elements as a component, or an alloy combining the above metal elements. As the conductor, for example, tantalum nitride, titanium nitride, tungsten, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel can be cited. In addition, tantalum nitride, titanium nitride, a nitride containing titanium and aluminum, a nitride containing tantalum and aluminum, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, and an oxide containing lanthanum and nickel are conductive materials that are not easily oxidized or materials that absorb oxygen and maintain conductivity, so they are preferred. Alternatively, a semiconductor having high conductivity, such as polycrystalline silicon containing an impurity element such as phosphorus, or a silicide such as nickel silicide may be used.

[0234] In the case of using a conductor with a stacked structure, for example, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen, a stacked structure combining a material containing the above-mentioned metal element and a conductive material containing nitrogen, or a stacked structure combining a material containing the above-mentioned metal element, a conductive material containing oxygen, and a conductive material containing nitrogen may be used.

[0235] In addition, when an oxide is used in the channel formation region of the transistor, a laminated structure combining a material containing the above-mentioned metal element and a conductive material containing oxygen is preferably used as a conductor used as a gate electrode. In this case, the conductive material containing oxygen is preferably arranged on one side of the channel formation region. By arranging the conductive material containing oxygen on one side of the channel formation region, oxygen separated from the conductive material is easily supplied to the channel formation region.

[0236] In particular, as a conductor used as a gate electrode, it is preferred to use a conductive material containing a metal element contained in a metal oxide forming a channel and oxygen. In addition, a conductive material containing the above-mentioned metal element and nitrogen can also be used. For example, a conductive material containing nitrogen such as titanium nitride and tantalum nitride can be used. In addition, one or more of indium tin oxide, indium oxide containing tungsten oxide, indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, indium tin oxide containing titanium oxide, indium zinc oxide, and indium tin oxide added with silicon can also be used. In addition, indium gallium zinc oxide containing nitrogen can also be used. By using the above-mentioned materials, hydrogen contained in the metal oxide forming the channel can sometimes be captured. Alternatively, hydrogen mixed from an external insulator can sometimes be captured.

[0237] <<Metal Oxides>>

[0238] A metal oxide that functions as a semiconductor (oxide semiconductor) is preferably used as the oxide 230. Next, a metal oxide that can be used for the oxide 230 according to one embodiment of the present invention will be described.

[0239] The metal oxide preferably contains at least indium or zinc. In particular, it preferably contains indium and zinc. In addition, it preferably contains aluminum, gallium, yttrium, tin, antimony, etc. In addition, it may also contain one or more selected from boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, and cobalt.

[0240] Here, the case where the metal oxide is an In-M-Zn oxide containing indium, element M and zinc is considered. Note that element M is aluminum, gallium, yttrium, tin or antimony. Other elements that can be applied to element M include boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, etc. Note that as element M, multiple of the above elements can sometimes be combined. In particular, element M is preferably selected from one or more of gallium, aluminum, yttrium and tin.

[0241] In addition, in this specification and the like, a metal oxide containing nitrogen may also be referred to as a metal oxide (metal oxide). In addition, a metal oxide containing nitrogen may also be referred to as a metal oxynitride (metal oxynitride).

[0242] Hereinafter, In—Ga—Zn oxide will be described as an example of the metal oxide.

[0243] Examples of the crystalline structure of an oxide semiconductor include amorphous (including completely amorphous), CAAC (c-axis-aligned crystalline), nc (nanocrystalline), CAC (cloud-aligned composite), single crystal, and polycrystal.

[0244] In addition, when focusing on the structure of oxide semiconductors, the classification of oxide semiconductors is sometimes different from the above. For example, oxide semiconductors can be classified into single-crystal oxide semiconductors and non-single-crystal oxide semiconductors other than single-crystal oxide semiconductors. As non-single-crystal oxide semiconductors, for example, the above-mentioned CAAC-OS and nc-OS can be cited. In addition, non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, a-like OS (amorphous-like oxide semiconductor) and amorphous oxide semiconductors.

[0245] Here, the details of the above-mentioned CAAC-OS, nc-OS and a-like OS are explained.

[0246] [CAAC-OS]

[0247] CAAC-OS is an oxide semiconductor including a plurality of crystalline regions, wherein the c-axis of the plurality of crystalline regions is oriented in a specific direction. In addition, the specific direction refers to the thickness direction of the CAAC-OS film, the normal direction of the formed surface of the CAAC-OS film, or the normal direction of the surface of the CAAC-OS film. In addition, the crystalline region is a region having a periodic atomic arrangement. Note that when the atomic arrangement is regarded as a lattice arrangement, the crystalline region is also a region having a consistent lattice arrangement. Furthermore, CAAC-OS has a region where a plurality of crystalline regions are connected in the ab plane direction, and sometimes the region has distortion. In addition, distortion refers to a portion where the direction of the lattice arrangement changes between a region having a consistent lattice arrangement and other regions having a consistent lattice arrangement in a region where a plurality of crystalline regions are connected. In other words, CAAC-OS refers to an oxide semiconductor having a c-axis orientation and having no obvious orientation in the ab plane direction.

[0248] In addition, each of the above-mentioned multiple crystallization regions is composed of one or more tiny crystals (crystallizations with a maximum diameter less than 10 nm). In the case where a crystallization region is composed of one tiny crystal, the maximum diameter of the crystallization region is less than 10 nm. In addition, in the case where a crystallization region is composed of multiple tiny crystals, the maximum diameter of the crystallization region is sometimes about tens of nm.

[0249] CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries can be confirmed. Therefore, it can be said that in CAAC-OS, the reduction in electron mobility caused by grain boundaries is not easy to occur. In addition, the crystallinity of the oxide semiconductor is sometimes reduced due to the mixing of impurities or the generation of defects, so it can be said that CAAC-OS is an oxide semiconductor with few impurities and defects (oxygen vacancies, etc.). Therefore, the physical properties of the oxide semiconductor including CAAC-OS are stable. Therefore, the oxide semiconductor including CAAC-OS has high heat resistance and high reliability. In addition, CAAC-OS is also stable to high temperatures (so-called heat accumulation) in the manufacturing process. Therefore, by using CAAC-OS in the OS transistor, the degree of freedom of the manufacturing process can be expanded.

[0250] [nc-OS]

[0251] In nc-OS, the atomic arrangement in a tiny region (e.g., a region of more than 1 nm and less than 10 nm, especially a region of more than 1 nm and less than 3 nm) is periodic. In other words, nc-OS has tiny crystals. In addition, for example, the size of the tiny crystal is more than 1 nm and less than 10 nm, especially more than 1 nm and less than 3 nm, and the tiny crystal is called a nanocrystal. In addition, in nc-OS, no regularity of crystal orientation is observed between different nanocrystals. Therefore, no orientation is observed in the entire film. Therefore, sometimes nc-OS is no different from a-like OS or amorphous oxide semiconductor in certain analysis methods.

[0252] [a-like OS]

[0253] A-like OS is an oxide semiconductor having a structure between nc-OS and amorphous oxide semiconductor. A-like OS contains voids or low-density regions. In other words, the crystallinity of a-like OS is lower than that of nc-OS and CAAC-OS. In addition, the hydrogen concentration in the film of a-like OS is higher than that in the film of nc-OS and CAAC-OS.

[0254] Next, the details of the above-mentioned CAC-OS will be described. In addition, CAC-OS is related to the material composition.

[0255] [CAC-OS]

[0256] CAC-OS refers to, for example, a structure in which elements contained in a metal oxide are unevenly distributed, wherein the size of the material containing the unevenly distributed elements is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size. Note that in the following, a state in which one or more metal elements are unevenly distributed in a metal oxide and regions containing the metal elements are mixed is also referred to as a mosaic or patch shape, and the size of the region is greater than or equal to 0.5 nm and less than or equal to 10 nm, preferably greater than or equal to 1 nm and less than or equal to 3 nm, or a similar size.

[0257] Furthermore, CAC-OS refers to a composite metal oxide having a structure in which the material is divided into a first region and a second region to form a mosaic shape and the first region is distributed in the film (hereinafter also referred to as a cloud shape). That is, CAC-OS refers to a composite metal oxide having a structure in which the first region and the second region are mixed.

[0258] In addition, CAC-OS in In-Ga-Zn oxide refers to a structure in which a region (first region) in which a part of the main component is In and a region (second region) in which a part of the main component is Ga exist irregularly in a mosaic shape in a material composition containing In, Ga, Zn, and O. Therefore, it can be inferred that CAC-OS has a structure in which metal elements are unevenly distributed.

[0259] CAC-OS can be formed, for example, by sputtering without heating the substrate. When CAC-OS is formed by sputtering, as the deposition gas, any one or more selected from an inert gas (typically argon), an oxygen gas, and a nitrogen gas can be used. In addition, the lower the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition, the better. For example, the flow rate ratio of the oxygen gas in the total flow rate of the deposition gas during deposition is set to be greater than 0% and less than 30%, preferably greater than 0% and less than 10%.

[0260] Here, the first region is a region having higher conductivity than the second region. That is, when carriers flow through the first region, the conductivity as a metal oxide is exhibited. Therefore, when the first region is distributed in the metal oxide in a cloud-like manner, a high field effect mobility (μ) can be achieved.

[0261] On the other hand, the second region is a region having higher insulation than the first region. That is, when the second region is distributed in the metal oxide, leakage current can be suppressed.

[0262] Thus, when CAC-OS is used for a transistor, the complementary effect of the conductivity of the first region and the insulation of the second region can give CAC-OS a switch function (a function of controlling on / off). In other words, a portion of the CAC-OS material has a conductive function and another portion has an insulating function, and the entire material has a semiconductor function. By separating the conductive function and the insulating function, each function can be maximized. Therefore, by using CAC-OS for a transistor, a large on-state current (I on ), high field effect mobility (μ) and good switching performance.

[0263] In addition, transistors using CAC-OS have high reliability. Therefore, CAC-OS is most suitable for various semiconductor devices such as display devices.

[0264] Oxide semiconductors have various structures and various characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, a-like OS, CAC-OS, nc-OS, and CAAC-OS.

[0265] <<Other semiconductor materials>>

[0266] As the semiconductor layer of the transistor, a semiconductor material having a band gap (a semiconductor material that is not a zero-band gap semiconductor) may be used. For example, a semiconductor of a single element such as silicon or a compound semiconductor such as gallium arsenide may be used.

[0267] In addition, as the semiconductor layer of the transistor, for example, a transition metal chalcogenide used as a semiconductor is preferably used. As transition metal chalcogenides that can be used for the semiconductor layer of the transistor, specifically molybdenum sulfide (typically MoS2), molybdenum selenide (typically MoSe2), molybdenum telluride (typically MoTe2), tungsten sulfide (typically WS2), tungsten selenide (typically WSe2), tungsten telluride (typically WTe2), hafnium sulfide (typically HfS2), hafnium selenide (typically HfSe2), zirconium sulfide (typically ZrS2), zirconium selenide (typically ZrSe2), etc. can be cited. By using the above-mentioned transition metal chalcogenides for the semiconductor layer of the transistor, a semiconductor device with a large on-state current can be provided.

[0268] <Example of Method for Manufacturing Semiconductor Device>

[0269] use 6A to 17D An example of a method for manufacturing a semiconductor device according to one embodiment of the present invention is described. Figures 1A to 1D The case of the semiconductor device shown in FIG. 1 is described as an example.

[0270] A in each figure is a plan view. In addition, B in each figure is a cross-sectional view of a portion along the dashed line A1-A2 in A, which is equivalent to a cross-sectional view in the channel length direction of transistor 200. In addition, C in each figure is a cross-sectional view of a portion along the dashed line A3-A4 in A, which is equivalent to a cross-sectional view in the channel width direction of transistor 200. In addition, D in each figure is a cross-sectional view of a portion along the dashed line A5-A6 in A, which is equivalent to a cross-sectional view in the channel width direction of transistor 200. Note that for the sake of clarity, some components are omitted in the plan view of A in each figure. In addition, FIG. 15A to FIG. 15C It is an enlarged cross-sectional view of the transistor 200 in the channel length direction.

[0271] Hereinafter, the insulating material used to form an insulator, the conductive material used to form a conductor, or the semiconductor material used to form a semiconductor can be appropriately deposited using sputtering, chemical vapor deposition (CVD: Chemical Vapor Deposition), molecular beam epitaxy (MBE: Molecular Beam Epitaxy), pulsed laser deposition (PLD: Pulsed Laser Deposition), ALD, or the like.

[0272] As the sputtering method, there can be cited an RF sputtering method using a high frequency power supply as a sputtering power supply, a DC sputtering method using a direct current power supply, and a pulsed DC sputtering method in which the voltage applied to the electrode is changed in a pulsed manner. The RF sputtering method is mainly used when depositing insulating films, and the DC sputtering method is mainly used when depositing metal conductive films. In addition, the pulsed DC sputtering method is mainly used when depositing compounds such as oxides, nitrides, and carbides using a reactive sputtering method.

[0273] Note that the CVD method can be divided into a plasma enhanced CVD (PECVD) method using plasma, a thermal CVD (TCVD: Thermal CVD) method using heat, and a photo CVD (Photo CVD) method using light, etc. Furthermore, it can be classified into a metal CVD (MCVD: Metal CVD) method and an organic metal CVD (MOCVD: Metal Organic CVD) method according to the source gas used.

[0274] By utilizing the plasma CVD method, a high-quality film can be obtained at a lower temperature. In addition, since plasma is not used, the thermal CVD method is a deposition method that can reduce plasma damage to the object being processed. For example, the wiring, electrodes, components (transistors, capacitors, etc.) included in the semiconductor device sometimes generate charge accumulation due to receiving charges from plasma. At this time, the wiring, electrodes, components, etc. included in the semiconductor device are sometimes damaged due to the accumulated charges. On the other hand, since the above-mentioned plasma damage does not occur in the case of the thermal CVD method without using plasma, the yield of the semiconductor device can be improved. In addition, in the thermal CVD method, plasma damage during deposition is not generated, so a film with fewer defects can be obtained.

[0275] As the ALD method, a thermal ALD method in which a precursor and a reactant are reacted using only thermal energy, a PEALD method using a reactant excited by plasma, or the like is used.

[0276] The CVD method and the ALD method are different from the sputtering method in which particles released from a target material or the like are deposited. Therefore, the CVD method and the ALD method are deposition methods that are not easily affected by the shape of the object to be processed and have high step coverage. In particular, the ALD method has high step coverage and thickness uniformity, so the ALD method is suitable for covering the surface of an opening with a high aspect ratio. However, the deposition rate of the ALD method is relatively slow, so it is sometimes preferred to use it in combination with other deposition methods such as the CVD method with a fast deposition rate.

[0277] In addition, when the CVD method is used, a film of any composition can be deposited by adjusting the flow ratio of the source gas. For example, when the CVD method is used, a film whose composition continuously changes can be deposited by changing the flow ratio of the source gas while depositing. When depositing while changing the flow ratio of the source gas, since the time required for conveying or adjusting the pressure is not required, the deposition time can be shortened compared to the case where deposition is performed using multiple deposition chambers. Therefore, the productivity of the semiconductor device can sometimes be improved.

[0278] When the ALD method is used, a film of any composition can be deposited by introducing different precursors at the same time. Alternatively, when introducing different precursors, a film of any composition can be deposited by controlling the number of cycles of each precursor.

[0279] First, a substrate (not shown) is prepared, and an insulator 215 is deposited on the substrate (see FIG. 6A to FIG. 6D). As described above, the insulator 215 may use the same insulator as the laminated film of any one or more of the insulators 224, the insulator 282, and the insulator 283. For example, the insulator 215 may be deposited by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 215 can be reduced, so it is preferred.

[0280] Next, an insulator 216 is deposited on the insulator 215. The insulator 216 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen for a deposition gas, the hydrogen concentration in the insulator 216 can be reduced. Note that the deposition method of the insulator 216 is not limited to the sputtering method, and for example, a CVD method, an MBE method, a PLD method, an ALD method, or the like can also be used appropriately. In this embodiment, silicon oxide is deposited as the insulator 216 by a sputtering method.

[0281] The insulator 215 and the insulator 216 are preferably deposited continuously without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus may be used. Thus, the insulator 215 and the insulator 216 can be deposited while reducing hydrogen in the film, and the mixing of hydrogen into the film between each deposition step can be reduced.

[0282] Next, an opening reaching the insulator 215 is formed in the insulator 216. When forming the opening, wet etching can be used, but dry etching is preferred for micro-machining. As the insulator 215, it is preferable to select an insulator that is used as an etching stopper film when etching the insulator 216 to form a groove. For example, when silicon oxide or silicon oxynitride is used as the insulator 216 for forming the groove, silicon nitride, aluminum oxide, hafnium oxide, or the like is preferably used as the insulator 215.

[0283] After the opening is formed, a conductive film to be the conductor 205a is deposited. The conductive film to be the conductor 205a preferably includes a conductor having a function of inhibiting the transmission of oxygen. For example, tantalum nitride, tungsten nitride, titanium nitride, etc. can be used as the conductive film. In addition, the conductive film can use a laminated film of a conductor having a function of inhibiting the transmission of oxygen and tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy. The conductive film to be the conductor 205a can be deposited, for example, by sputtering, CVD, MBE, PLD, ALD, or the like.

[0284] In this embodiment, titanium nitride is deposited as a conductive film used as the conductor 205a. By using the above-mentioned metal nitride as the lower layer of the conductor 205b, it is possible to suppress the conductor 205b from being oxidized by the insulator 216. In addition, even if a metal that easily diffuses, such as copper, is used as the conductor 205b, it is possible to prevent the metal from diffusing outward from the conductor 205a.

[0285] Next, a conductive film to be the conductor 205b is deposited. As the conductive film to be the conductor 205b, for example, tantalum, tungsten, titanium, molybdenum, aluminum, copper, or a molybdenum-tungsten alloy can be used. The conductive film can be deposited by, for example, a plating method, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, tungsten is deposited as the conductive film to be the conductor 205b.

[0286] Next, a CMP treatment is performed to remove a portion of the conductive film to be the conductor 205a and the conductive film to be the conductor 205b, thereby exposing the insulator 216 (see FIG. 214 ). FIG. 6A to FIG. 6D ). As a result, the conductor 205a and the conductor 205b remain only in the opening. Note that part of the insulator 216 may be removed by the CMP process.

[0287] Next, an insulator 221 is deposited on the insulator 216 and the conductor 205 (see FIG. 7A to FIG. 7D ).

[0288] The insulator 221 may be any of the above-mentioned insulators that have barrier properties to oxygen, hydrogen, and water. The insulator 221 may be deposited, for example, by sputtering, CVD, MBE, PLD, or ALD. In this embodiment, silicon nitride is deposited by PEALD as the insulator 221 .

[0289] Next, an insulator 222 is deposited on the insulator 221 (see FIG. 7A to FIG. 7D ).

[0290] As the insulator 222, an insulator containing an oxide of one or both of aluminum and hafnium is preferably deposited. As the insulator containing an oxide of one or both of aluminum and hafnium, for example, aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), etc. are preferably used. Alternatively, hafnium zirconium oxide is preferably used. The insulator containing an oxide of one or both of aluminum and hafnium has a barrier property to oxygen, hydrogen, and water. When the insulator 222 has a barrier property to hydrogen and water, the hydrogen and water contained in the structure surrounding the transistor can be suppressed from diffusing into the inside of the transistor through the insulator 222, thereby suppressing the generation of oxygen vacancies in the oxide 230.

[0291] The insulator 222 can be deposited by, for example, sputtering, CVD, MBE, PLD, ALD, etc. In this embodiment, hafnium oxide is deposited as the insulator 222 by ALD.

[0292] Next, an insulating film 224f is deposited on the insulator 222 (see FIG. 7A to FIG. 7D ). As the insulating film 224f, an insulator corresponding to the above-mentioned insulator 224 can be used.

[0293] The insulating film 224f can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. In this embodiment, silicon oxide is deposited by a sputtering method as the insulating film 224f. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulating film 224f can be reduced. The insulating film 224f is in contact with the oxide 230a in a later step, so it is preferable that the hydrogen concentration is reduced as described above.

[0294] In addition, heat treatment may be performed before depositing the insulating film 224f. The heat treatment may also be performed under reduced pressure, wherein the insulating film 224f is continuously deposited without being exposed to the atmosphere. By performing such a treatment, moisture and hydrogen attached to the surface of the insulator 222 can be removed, and the moisture concentration and hydrogen concentration of the insulator 222 can be reduced. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 due to the heat treatment. The temperature of the heat treatment is preferably above 100°C and below 400°C. In this embodiment, the temperature of the heat treatment is set to 250°C.

[0295] Next, an oxide film 230af is deposited on the insulating film 224f, and an oxide film 230bf is deposited on the oxide film 230af (see FIG. 7A to FIG. 7D ). As the oxide film 230af, a metal oxide corresponding to the above-mentioned oxide 230a can be used, and as the oxide film 230bf, a metal oxide corresponding to the above-mentioned oxide 230b can be used. It is preferable to continuously deposit the oxide film 230af and the oxide film 230bf without exposing them to the atmospheric environment. By performing deposition without exposing them to the atmosphere, impurities or moisture from the atmospheric environment can be prevented from adhering to the oxide film 230af and the oxide film 230bf, so that the vicinity of the interface between the oxide film 230af and the oxide film 230bf can be kept clean.

[0296] The oxide film 230af and the oxide film 230bf can be deposited by, for example, sputtering, CVD, MBE, PLD, ALD, etc. In the present embodiment, sputtering is used as a method for depositing the oxide film 230af and the oxide film 230bf.

[0297] For example, when the oxide film 230af and the oxide film 230bf are deposited by sputtering, oxygen or a mixed gas of oxygen and a rare gas is used as the sputtering gas. By increasing the ratio of oxygen contained in the sputtering gas, the excess oxygen in the deposited oxide film can be increased. In addition, when the above-mentioned oxide film is deposited by sputtering, an In-M-Zn oxide target or the like can be used.

[0298] In particular, when the oxide film 230af is deposited, part of the oxygen contained in the sputtering gas may be supplied to the insulating film 224f. Therefore, the ratio of oxygen contained in the sputtering gas is preferably 70% or more, more preferably 80% or more, and further preferably 100%.

[0299] In the case of forming the oxide film 230bf by sputtering, an oxygen-excess oxide semiconductor can be formed by depositing under the condition that the ratio of oxygen contained in the sputtering gas is greater than 30% and less than 100%, preferably greater than 70% and less than 100%. A transistor using an oxygen-excess oxide semiconductor in a channel formation region can obtain relatively high reliability. Note that one embodiment of the present invention is not limited to this. In the case of forming the oxide film 230bf by sputtering, an oxygen-deficient oxide semiconductor is formed when deposition is performed under the condition that the ratio of oxygen contained in the sputtering gas is set to greater than 1% and less than 30%, preferably greater than 5% and less than 20%. A transistor using an oxygen-deficient oxide semiconductor in a channel formation region can have a higher field effect mobility. In addition, by depositing while heating the substrate, the crystallinity of the oxide film can be improved.

[0300] In this embodiment, the oxide film 230af is deposited by sputtering using an oxide target of In:Ga:Zn=1:3:2 [atomic ratio] or an oxide target of In:Ga:Zn=1:3:4 [atomic ratio]. In addition, the oxide film 230bf is deposited by sputtering using an oxide target of In:Ga:Zn=1:1:1 [atomic ratio], an oxide target of In:Ga:Zn=1:1:1.2 [atomic ratio], an oxide target of In:Ga:Zn=4:2:4.1 [atomic ratio] or an oxide target of In:Ga:Zn=1:1:2 [atomic ratio]. Each oxide film is preferably formed by appropriately selecting deposition conditions and atomic ratios according to the characteristics required for the oxide 230a and the oxide 230b.

[0301] Note that the insulating film 224f, the oxide film 230af, and the oxide film 230bf are preferably deposited by sputtering without being exposed to the atmosphere. For example, a multi-chamber deposition apparatus is preferably used. Thus, mixing of hydrogen into the insulating film 224f, the oxide film 230af, and the oxide film 230bf between each deposition step can be reduced.

[0302] In the above example, the case where the oxide film 230af and the oxide film 230bf are deposited by sputtering is shown, but the present invention is not limited to this. For example, the oxide film 230af can also be deposited by sputtering, and the oxide film 230bf can also be deposited by ALD. Here, one or both of the oxide 230a and the oxide 230b can also adopt a stacked structure. For example, the oxide film 230af can be deposited by sputtering using any of an oxide target with In:Ga:Zn=1:1:1 [atomic ratio], an oxide target with In:Ga:Zn=1:1:1.2 [atomic ratio], an oxide target with In:Ga:Zn=1:3:2 [atomic ratio], or an oxide target with In:Ga:Zn=1:3:4 [atomic ratio].

[0303] In addition, for example, as the oxide film 230bf, a stacked film in which a metal oxide layer of In:Ga:Zn=1:1:1 [atomic ratio], a metal oxide layer of In:Zn=4:1 [atomic ratio], and a metal oxide layer of In:Ga:Zn=1:3:4 [atomic ratio] are sequentially stacked can be deposited by the ALD method. In addition, for example, as the oxide film 230bf, a stacked film in which a metal oxide layer of In:Zn=4:1 [atomic ratio] and a metal oxide layer of In:Ga:Zn=1:3:4 [atomic ratio] are sequentially stacked can be deposited by the ALD method. In addition, in the above-mentioned oxide film 230bf, a metal oxide layer of In:Ga:Zn=1:3:2 [atomic ratio] or a metal oxide layer of In:Ga:Zn=1:3:4 [atomic ratio] can be used instead of the metal oxide layer of In:Ga:Zn=1:1:1 [atomic ratio]. In addition, in the above-mentioned oxide film 230bf, a metal oxide layer with In:Ga:Zn=1:3:2 [atomic ratio] or a metal oxide layer with In:Ga:Zn=1:1:1 [atomic ratio] may be used instead of the metal oxide layer with In:Ga:Zn=1:3:4 [atomic ratio].

[0304] The crystallinity of the oxide film 230af can be improved by depositing the oxide film 230af by sputtering. For example, by first improving the crystallinity of the oxide film 230af and then depositing the oxide film 230bf on the oxide film 230af, a portion or the entire oxide film 230bf can be crystallized. In other words, the crystallinity of the oxide film 230af can also be improved by improving the crystallinity of the oxide film 230bf. For example, when the oxide film 230af is an oxide semiconductor film of a CAAC structure, an oxide semiconductor of a CAAC structure can also be used as the oxide film 230bf formed on the oxide film 230af.

[0305] In addition, by depositing the oxide film 230bf using the ALD method, a thinner film can be deposited with high controllability. Thus, the oxide film 230bf can have a smaller thickness according to the design. By using the above-mentioned oxide film 230af and oxide film 230bf, the electrical characteristics and reliability of the transistor 200 can be improved.

[0306] Next, heat treatment is preferably performed. The heat treatment may be performed within a temperature range where polycrystallization does not occur in the oxide film 230af and the oxide film 230bf. The heat treatment temperature is preferably 100°C or higher, 250°C or higher, or 350°C or higher and 650°C or lower, 600°C or lower, or 550°C or lower.

[0307] The heat treatment is carried out in a nitrogen gas or inert gas atmosphere or an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10%. For example, when the heat treatment is carried out in a mixed atmosphere of nitrogen gas and oxygen gas, the ratio of the oxygen gas is preferably set to about 20%. The heat treatment can also be carried out under reduced pressure. Alternatively, the heat treatment can also be carried out in a nitrogen gas or inert gas atmosphere, and then the heat treatment is carried out in an atmosphere containing an oxidizing gas of more than 10ppm, more than 1% or more than 10% to fill the oxygen that has been separated.

[0308] In addition, the gas used in the above heat treatment is preferably highly purified. For example, the amount of water contained in the gas used in the above heat treatment is preferably 1 ppb or less, more preferably 0.1 ppb or less, and further preferably 0.05 ppb or less. By using highly purified gas for heat treatment, it is possible to prevent moisture and the like from being absorbed by the oxide film 230af and the oxide film 230bf as much as possible.

[0309] In this embodiment, as a heat treatment, a treatment is performed for 1 hour under the conditions of a flow ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 450°C. Such a heat treatment containing oxygen gas can reduce impurities such as carbon, water, and hydrogen in the oxide film 230af and the oxide film 230bf. By reducing the impurities in the film in this way, the crystallinity of the oxide film 230bf is improved, and a denser structure with a higher density can be achieved. Therefore, the crystallized area in the oxide film 230af and the oxide film 230bf can be increased, and the in-plane unevenness of the crystallized area in the oxide film 230af and the oxide film 230bf can be reduced. Therefore, the in-plane unevenness of the electrical characteristics of the transistor can be reduced.

[0310] In addition, by performing the heat treatment, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf moves to the insulator 222 and is absorbed by the insulator 222. In other words, hydrogen in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf diffuses into the insulator 222. Therefore, although the hydrogen concentration in the insulator 222 increases, the hydrogen concentration in the insulator 216, the insulating film 224f, the oxide film 230af, and the oxide film 230bf decreases. Here, when the insulator 221 is provided in contact with the bottom surface of the insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below the insulator 221 due to the heat treatment.

[0311] In particular, the insulating film 224f (later insulator 224) is used as a second gate insulator of the transistor 200, and the oxide film 230af and the oxide film 230bf (later oxide 230a and oxide 230b) are used as a channel formation region of the transistor 200. The transistor 200 formed using the insulating film 224f, the oxide film 230af, and the oxide film 230bf in which the hydrogen concentration is reduced has excellent reliability and is therefore preferred.

[0312] Next, a conductive film 242_1f is deposited on the oxide film 230bf, and a conductive film 242_2f is deposited on the conductive film 242_1f (see FIG. 7A to FIG. 7D ). A conductor corresponding to the above-mentioned conductors 242a1 and 242b1 may be used as the conductive film 242_1f, and a conductor corresponding to the above-mentioned conductors 242a2 and 242b2 may be used as the conductive film 242_2f. After the oxide film 230bf is deposited, the conductive film 242_1f is deposited on and in contact with the oxide film 230bf without an etching process or the like, so that the top surface of the oxide film 230bf can be protected by the conductive film 242_1f. Thus, since the diffusion of impurities into the oxide 230 constituting the transistor can be reduced, the electrical characteristics and reliability of the semiconductor device can be improved.

[0313] The conductive film 242_1f and the conductive film 242_2f can be deposited by, for example, sputtering, CVD, MBE, PLD, electroplating, or ALD.

[0314] In this embodiment, tantalum nitride is deposited as the conductive film 242_1f and tantalum is deposited as the conductive film 242_2f by sputtering. In addition, heat treatment may be performed before depositing the conductive film 242_1f. The heat treatment may also be performed under reduced pressure, and the conductive film 242_1f is continuously deposited without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the oxide 230b can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a and the oxide 230b can be reduced. The temperature of the heat treatment is preferably above 100°C and below 400°C. In this embodiment, the temperature of the heat treatment is set to 250°C.

[0315] Next, an insulating film 271f is deposited on the conductive film 242_1f (see FIG. 7A to FIG. 7D ). The insulating film 271f can be deposited by sputtering, CVD, MBE, PLD, ALD, or the like. The insulating film 271f preferably uses an insulating film having a function of suppressing oxygen transmission. For example, a stacked film of a silicon nitride film and a silicon oxide film on the silicon nitride film can be deposited by sputtering as the insulating film 271f.

[0316] Here, when a laminated film is used as the insulating film 271f, the deposition is continuously performed without being exposed to the atmosphere. By depositing without being exposed to the atmosphere, the vicinity of the interface of the laminated film of the insulating film 271f can be kept clean. In addition, it is more preferable to continuously deposit the conductive film 242_1f to the insulating film 271f without being exposed to the atmosphere.

[0317] In addition, heat treatment may be performed before the insulating film 271f is deposited. The heat treatment may also be performed under reduced pressure, and the insulating film 271f may be continuously deposited without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen attached to the surface of the conductive film 242_1f and the conductive film 242_2f may be removed, and the moisture concentration and hydrogen concentration in the conductive film 242_1f and the conductive film 242_2f may be reduced. The temperature of the heat treatment is preferably 100° C. or more and 400° C. or less. In this embodiment, the temperature of the heat treatment is set to 250° C.

[0318] Next, the insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f are processed into island shapes by photolithography to form the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 (see FIG. 8A to FIG. 8D ).

[0319] The above processing can be performed by dry etching or wet etching. Processing by dry etching is suitable for micro-processing. In addition, the processing of the insulating film 224f, the oxide film 230af, the oxide film 230bf, the conductive film 242_1f, the conductive film 242_2f, and the insulating film 271f can also be performed under different conditions.

[0320] Here, it is preferred that the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are processed into an island shape at one time. At this time, the side end of the conductor 242_1 and the side end of the conductor 242_2 are preferably aligned or roughly aligned with the side end of the oxide 230a and the side end of the oxide 230b. Furthermore, the side end of the insulator 224 is preferably aligned or roughly aligned with the side end of the oxide 230. In addition, the side end of the insulator 271 is preferably aligned or roughly aligned with the side end of the conductor 242_2. By adopting the above structure, the number of steps of a semiconductor device according to one embodiment of the present invention can be reduced. Thus, a method for manufacturing a semiconductor device with good productivity can be provided.

[0321] At least a portion of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 are formed to overlap with the conductor 205. In addition, the insulator 222 is exposed in a region where the insulator 222 does not overlap with the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271.

[0322] like Figure 8B As shown, the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may also have a tapered shape. The taper angle of the side surfaces of the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271 may also be, for example, 60° or more and less than 90°. In this way, by having the side surfaces have a tapered shape, the coverage of the insulator 275 and the like is improved in the subsequent process, and defects such as voids can be reduced.

[0323] The present invention is not limited to this, and the side surfaces of the insulator 224, oxide 230a, oxide 230b, conductor 242_1, conductor 242_2, and insulator 271 may be perpendicular or substantially perpendicular to the top surface of the insulator 222. With such a structure, a small area and high density can be achieved when a plurality of transistors are provided.

[0324] Note that in photolithography, first, the resist is exposed through a mask. Then, a developer is used to remove or leave the exposed area to form a resist mask. Then, an etching process is performed through the resist mask to process the conductor, semiconductor, or insulator into a desired shape. For example, a KrF excimer laser, ArF excimer laser, EUV (Extreme Ultraviolet) light, etc. can be used to expose the resist to form a resist mask. In addition, a liquid immersion technique in which the exposure is performed in a state where a liquid (for example, water) is filled between the substrate and the projection lens can also be used. In addition, an electron beam or an ion beam can also be used instead of the above-mentioned light. In addition, when an electron beam or an ion beam is used, a mask may sometimes not be used.

[0325] The resist mask that is unnecessary after processing can be removed by dry etching treatment such as ashing using oxygen plasma (hereinafter sometimes referred to as oxygen plasma treatment), wet etching treatment, dry etching treatment followed by wet etching treatment, or wet etching treatment followed by dry etching treatment.

[0326] Furthermore, a hard mask made of an insulator or a conductor may be used under the resist mask. When a hard mask is used, an insulating film or a conductive film serving as a hard mask material may be formed on the insulating film 271f and a resist mask may be formed thereon, and then the hard mask material may be etched to form a hard mask of a desired shape. The etching of the insulating film 271f and the like may be performed after removing the resist mask or without removing the resist mask. In the case of the latter, the resist mask may disappear during etching. The hard mask may be removed by etching after etching the oxide film 230bf and the like. On the other hand, in the case where the hard mask material does not affect the subsequent process or can be used in the subsequent process, it is not necessarily necessary to remove the hard mask.

[0327] In addition, a SOC (Spin On Carbon) film and a SOG (Spin On Glass) film may be deposited between the workpiece and the resist mask. By using the SOC film and the SOG film as a mask, the adhesion between the workpiece and the resist mask can be improved, thereby improving the durability of the mask pattern. For example, a SOC film, a SOG film, and a resist mask may be deposited sequentially on the workpiece to perform photolithography.

[0328] As an etching gas for dry etching treatment, an etching gas containing halogen can be used. Specifically, an etching gas containing one or more of fluorine, chlorine and bromine can be used. As an etching gas, for example, one or a mixed gas of C4F6 gas, C5F6 gas, C4F8 gas, CF4 gas, SF6 gas, CHF3 gas, CH2F2 gas, Cl2 gas, BCl3 gas, SiCl4 and BBr3 gas can be used. In addition, oxygen gas, carbon dioxide gas, nitrogen gas, helium gas, argon gas, hydrogen gas or hydrocarbon gas can be appropriately added to the above-mentioned etching gas. In addition, depending on the object to be processed by dry etching treatment, a gas that does not contain halogen gas but contains hydrocarbon gas or hydrogen gas can also be used as an etching gas. As hydrocarbons used for etching gas, methane (CH4), ethane (C2H6), propane (C3H8), butane (C4H 10 ), ethylene (C2H4), propylene (C3H6), acetylene (C2H2) and propyne (C3H4) One or more. The etching conditions can be appropriately set according to the etching object.

[0329] As a dry etching device, a capacitively coupled plasma (CCP: Capacitively Coupled Plasma) etching device including parallel plate electrodes can be used. The capacitively coupled plasma etching device including parallel plate electrodes can also adopt a structure in which a high-frequency voltage is applied to one of the parallel plate electrodes. Alternatively, a structure in which a plurality of different high-frequency voltages are applied to one of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with the same frequency is applied to each of the parallel plate electrodes can be adopted. Alternatively, a structure in which a high-frequency voltage with different frequencies is applied to each of the parallel plate electrodes can be adopted. Alternatively, a dry etching device with a high-density plasma source can be used. For example, as a dry etching device with a high-density plasma source, an inductively coupled plasma (ICP: Inductively Coupled Plasma) etching device can be used. The etching device can be appropriately set according to the etching object.

[0330] In addition, in the above-mentioned etching process, the insulator 271 can also be used as an etching stop layer for protecting the conductor 242_2. For example, when a metal hard mask is formed on the insulator 271 in the above-mentioned etching process, it is sometimes difficult to obtain an etching selectivity ratio with the conductor 242_2 when the hard mask is removed. However, by forming the insulator 271 on the conductor 242_2, the insulator 271 can be used as an etching stop layer for protecting the conductor 242_2 in the etching process for removing the hard mask. As a result, it is possible to prevent the formation of a curved surface between the side surface and the top surface of the conductor 242_2, so that the end portions where the side surfaces and the top surfaces of the conductors 242a2 and 242b2 formed later intersect have an angular shape. When the end portions where the side surfaces and the top surfaces of the conductor 242_2 intersect have an angular shape, the cross-sectional area of ​​the conductor 242_2 increases compared to the case where the end portions have a curved surface. Furthermore, excessive oxidation of the conductor 242a2 can be prevented by using a nitride insulator that does not easily oxidize metal as the insulator 271. As a result, the resistance of the conductor 242a2 and the conductor 242b2 is reduced, so that the on-state current of the transistor can be increased.

[0331] In addition, by processing the insulator 224 into an island shape, the insulator 275 can be provided in contact with the side surface of the insulator 224 and the top surface of the insulator 222. That is, the insulator 224 and the insulator 280 can be separated by the insulator 275. With such a structure, it is possible to prevent an excessive amount of impurities such as oxygen and hydrogen from being mixed into the oxide 230 through the insulator 224 from the insulator 280.

[0332] In addition, by processing the insulator 224 into an island shape, when a plurality of transistors 200 are provided, the insulator 224 of substantially the same size is provided in each transistor 200. Therefore, the amount of oxygen supplied from the insulator 224 to the oxide 230 in each transistor 200 is substantially equal. Thus, the electrical characteristics of the transistor 200 in the substrate surface can be suppressed from being uneven. Note that the present invention is not limited to this, and a structure in which the pattern of the insulator 224 is not formed similarly to the insulator 222 may be adopted.

[0333] Next, an insulator 275 is deposited to cover the insulator 224, the oxide 230a, the oxide 230b, the conductor 242_1, the conductor 242_2, and the insulator 271, and an insulator 280 is deposited on the insulator 275 (see 9A to 9D ). As the insulator 275 and the insulator 280, the above-mentioned insulators can be used.

[0334] Here, the insulator 275 is preferably in contact with the top surface of the insulator 222 .

[0335] As insulator 280, it is preferable to form an insulator with a flat top surface by forming an insulating film to be insulator 280 and then subjecting the insulating film to CMP. Alternatively, silicon nitride may be deposited on insulator 280 by, for example, sputtering and then subjected to CMP until it reaches insulator 280.

[0336] The insulator 275 and the insulator 280 can each be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0337] The insulator 275 preferably uses an insulator that has a function of inhibiting oxygen transmission. For example, silicon nitride is preferably deposited by the PEALD method as the insulator 275. In addition, aluminum oxide is preferably deposited by the sputtering method as the insulator 275, and silicon nitride is deposited thereon by the PEALD method. When the insulator 275 has the above structure, the function of inhibiting the diffusion of impurities such as water and hydrogen and oxygen can be improved.

[0338] Thus, the oxide 230a, the oxide 230b, the conductors 242_1, and the conductors 242_2 can be covered by the insulator 275 having the function of suppressing oxygen diffusion. Thus, direct diffusion of oxygen from the insulator 280 and the like into the insulator 224, the oxide 230a, the oxide 230b, the conductors 242_1, and the conductors 242_2 in a subsequent step can be reduced.

[0339] In addition, silicon oxide is preferably deposited by sputtering as the insulator 280. By depositing the insulating film to be the insulator 280 by sputtering in an oxygen-containing atmosphere, an insulator 280 containing excess oxygen can be formed. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 280 can be reduced. In addition, heat treatment can also be performed before depositing the insulating film. The heat treatment can also be performed under reduced pressure, and the insulating film is continuously deposited without being exposed to the atmosphere. By performing this treatment, moisture and hydrogen attached to the surface of the insulator 275 can be removed, and the moisture concentration and hydrogen concentration in the oxide 230a, the oxide 230b and the insulator 224 can be reduced. The heat treatment can adopt the conditions of the above-mentioned heat treatment.

[0340] Next, the conductor 242_2, the insulator 271, the insulator 275, and the insulator 280 are processed by photolithography to form openings reaching the conductor 242_1 and the insulator 222 (see FIG. 1 ). FIG. 10A to FIG. 10D). Here, the conductor 242_2 is divided to form the conductor 242a2 and the conductor 242b2, and the insulator 271 is divided to form the insulator 271a and the insulator 271b. The opening to the conductor 242_1 is formed in the region where the oxide 230b and the conductor 205 overlap. When the transistor 200 is cross-sectionally viewed in the channel length direction, the width of the opening is L1, which corresponds to Figure 2B The distance L1 between the conductor 242a2 and the conductor 242b2 is shown. That is, the width of the opening is Figure 2B The distance L2 between the conductor 242a1 and the conductor 242b1 shown is large.

[0341] The above method can be appropriately used in the photolithography method. In order to process the opening of the insulator 280 to be fine, it is preferable to use a photolithography method using light with a short wavelength such as EUV light or an electron beam.

[0342] For example, a SOC film, a SOG film, and a resist mask may be sequentially deposited and photolithography may be performed on the insulator 280. A resist mask including an opening is formed using short-wavelength light such as EUV light or an electron beam, and the SOG film, the SOC film, the insulator 280, the insulator 275, the insulator 271, and the conductor 242_2 are processed using the resist mask.

[0343] It is preferred to use dry etching to perform the above processing. In the dry etching method, anisotropic etching can be performed, so the dry etching method is more suitable for forming a high aspect ratio Figure 2B The opening of width L1 shown is suitable. Note that the dry etching conditions and dry etching apparatus can refer to the above contents. In addition, the etching process of SOG film, SOC film, insulator 280, insulator 275, insulator 271 and conductor 242_2 can also be performed under different conditions.

[0344] For example, CF4 can be used as an etching gas in the etching of SOG film. For example, H2 and N2 can be used as etching gases in the etching of SOC film. For example, when silicon oxide is used for insulator 280, C4F8, C4F6, O2 and Ar can be used as etching gases. In addition, for example, when silicon nitride is used for insulator 275, CH2F2, O2 and Ar can be used as etching gases. In addition, for example, when a laminated film of silicon nitride and silicon oxide is used for insulator 271, an ICP etching device can be used to perform etching processing using CHF3 and O2 as etching gases.

[0345] In addition, for example, when tungsten is used for the conductor 242_2 and tantalum nitride is used for the conductor 242_1, an ICP etching device can be used and CF4, Cl2, and O2 can be used as etching gases for etching. Here, since the conductor 242_2 is etched in a manner overlapping with the opening of width L1 formed in the insulator 280 or the like, the distance between the divided conductor 242a2 and the conductor 242b2 is L1. Note that in this etching, when the side surfaces of the conductor 242a2 and the conductor 242b2 are undercut, recessed portions may be formed on the side surfaces of the conductor 242a2 and the conductor 242b2.

[0346] Here, in order to form the conductors 242a1 and 242b1 with a distance L2 therebetween under the conductors 242a2 and 242b2 in the subsequent process, the etching process of this process needs to be stopped when reaching the top surface of the conductor 242_1. Therefore, in this process, the etching process is performed using an ICP etching device under the condition that the etching rate of the conductor 242_2 relative to the etching rate of the conductor 242_1 (hereinafter referred to as the etching selectivity ratio of the conductor 242_2) is large.

[0347] By reducing the bias power applied to the lower electrode of the ICP etching device, the ion incident energy can be reduced and the etching rate of the conductor 242_1 can be reduced. For example, the bias power applied to the lower electrode of the ICP etching device is set to less than 50W, preferably about 25W or less. However, the present invention is not limited to this, and the bias power applied to the lower electrode of the ICP etching device can also be set to more than 50W. By increasing the bias power, the recessed portion formed on the side of the conductor 242a2 and the conductor 242b2 can be reduced. At this time, for example, the bias power can be set to 100W.

[0348] In addition, by using CF4, Cl2, and O2 as etching gas, the tungsten of the conductor 242_2 is converted into a highly volatile reaction product such as WF6 or WOCl, and the etching rate is increased. On the other hand, the tantalum nitride on the surface of the conductor 242_1 is converted into a reaction product with extremely low volatility such as tantalum oxide or tantalum oxynitride, and etching is suppressed. Therefore, it is preferable to increase the oxygen gas flow rate ratio in the etching gas. The oxygen gas flow rate ratio in the etching gas can be set to 35% or more.

[0349] By performing the etching process for the conductor 242_2 under the above conditions, the conductor 242a2 and the conductor 242b2 can be separated from each other while preventing over-etching of the conductor 242_1. Thus, a semiconductor device having a microstructure can be processed as designed.

[0350] Alternatively, the SOC film may be removed by performing dry etching such as ashing using oxygen plasma, performing wet etching, performing dry etching followed by wet etching, or performing wet etching followed by dry etching.

[0351] The processing of the insulator 271 and the conductor 242_2 and the removal of the SOC film can be performed continuously without being exposed to the atmosphere. For example, a multi-chamber etching apparatus can be used to perform the processing continuously without being exposed to the atmosphere.

[0352] Through the above steps, the conductor 242_2 , the insulator 271 , the insulator 275 , and the insulator 280 may be processed to form an opening having a width L1 .

[0353] Next, an insulating film 255A is deposited so as to cover the insulator 280, the conductor 242_1, and the insulator 222 (see FIG. 11A to FIG. 11D The insulating film 255A is an insulating film that will become the insulator 255a in a later step, and the above-mentioned nitride insulator can be used. The insulating film 255A can be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0354] Since the insulating film 255A is deposited along the openings formed in the conductor 242a2, the conductor 242b2, the insulator 271, the insulator 275, and the insulator 280, it is preferable to have high coverage. Therefore, the insulating film 255A is preferably deposited by the ALD method or the like having high coverage. For example, as the insulating film 255A, silicon nitride is preferably deposited by the PEALD method.

[0355] Next, an insulating film 255B is deposited on the insulating film 255A (see FIG. 11A to FIG. 11D The insulating film 255B can use the above-mentioned oxide insulator. The insulating film 255B can be deposited by, for example, sputtering, CVD, MBE, PLD, or ALD.

[0356] As with the insulating film 255A, the insulating film 255B is preferably deposited along the openings formed in the conductor 242a2, the conductor 242b2, the insulator 271, the insulator 275, and the insulator 280, and therefore preferably has high coverage. Therefore, the insulating film 255B is preferably deposited using an ALD method with high coverage. For example, as the insulating film 255B, silicon oxide is preferably deposited using a PEALD method. For example, as the insulating film 255B, hafnium oxide or aluminum oxide is preferably deposited using a thermal ALD method. In addition, as the insulating film 255B, a plurality of the above-mentioned oxide insulators may be stacked and used. For example, as the insulating film 255B, a stacked film in which silicon oxide is stacked on hafnium oxide or aluminum oxide may be used. In addition, as the insulating film 255B, for example, a stacked film in which hafnium oxide or aluminum oxide is stacked on silicon oxide may be used.

[0357] The deposition of the insulating film 255A and the deposition of the insulating film 255B may be performed continuously without being exposed to the atmosphere. For example, they may be performed continuously without being exposed to the atmosphere using a multi-chamber deposition apparatus.

[0358] Next, the insulating film 255A and the insulating film 255B are partially removed by anisotropic etching to form the insulator 255 (insulator 255a and insulator 255b) in contact with the side wall of the opening (see FIG. 12A to FIG. 12D ). Thus, the insulator 255 is formed in contact with the side surface of the insulator 280, the side surface of the insulator 275, the side surface of the insulator 271a, the side surface of the insulator 271b, the side surface of the conductor 242a2, the side surface of the conductor 242b2, the top surface of the conductor 242_1, and the top surface of the insulator 222. Fig. 12C As shown, a portion of the insulator 255 is sometimes formed in contact with the side surface of the insulator 224 , the side surface of the oxide 230 , the side surface of the conductor 242_1 , and the top surface of the insulator 222 .

[0359] In addition, if Fig. 12B and Fig. 12C As shown, a protrusion is formed at a portion of the insulator 255a that contacts the top surface of the conductor 2421 or the top surface of the insulator 222. The protrusion of the insulator 255a is shaped to protrude toward the center of the opening formed in the insulator 280, etc., more than other portions. That is, when viewed in section in the channel length direction, the insulator 255a is in a so-called L-shaped shape.

[0360] The insulator 255b is formed so as to be located inside the insulator 255a. Fig. 11B and Fig. 11CAs shown, the bottom surface of the insulator 255b contacts the top surface of the protrusion of the insulator 255a, and one side surface of the insulator 255b contacts the side surface of the insulator 255a. In addition, when viewed from above, the other side surface of the insulator 255b is formed in a manner aligned or substantially aligned with the end of the protrusion of the insulator 255a. In addition, the insulator 255b does not contact the conductor 242a2, the conductor 242b2, and the conductor 242_1. Therefore, by using an oxide insulator as the insulator 255b, oxidation of the conductor 242a2, the conductor 242b2, and the conductor 242_1 can be suppressed.

[0361] When viewed in a cross section in the channel length direction, since the insulator 255a and the insulator 255b are formed in an opening having a width of L1, when the distance between the insulator 255b on the A1 side and the insulator 255b on the A2 side is set to L2, L2 is shorter than L1. Here, the distance L2 can be regarded as the distance between the end of the protruding portion of the insulator 255a on the A1 side and the end of the protruding portion of the insulator 255a on the A2 side.

[0362] It is preferable to use dry etching as anisotropic etching of the insulating film 255A and the insulating film 255B. Note that the dry etching conditions and dry etching apparatus can refer to the above description. For example, when silicon nitride is used for the insulating film 255A and silicon oxide is used for the insulating film 255B, an ICP etching apparatus can be used and CHF3 and O2 can be used as etching gases to perform etching.

[0363] In addition, for example, when hafnium oxide or aluminum oxide is used as the insulating film 255B, an ICP etching device can be used to perform etching using BCl3 as an etching gas. Note that chlorine-based etching gases such as BCl3 also have high etching performance for In-Ga-Zn oxide used for the oxide 230. Therefore, when etching the insulating film 255B, it is preferred to make the etching selectivity of the insulating film 255B relative to the insulating film 255A sufficiently large so that the insulating film 255A is not etched. As a result, during the etching of the insulating film 255B, the oxide 230 is covered by the insulating film 255A, so that the oxide 230 can be prevented from being etched by the etching gas of the insulating film 255B. After the insulating film 255B is processed into the insulator 255b, anisotropic etching of the insulating film 255A can be performed.

[0364] In addition, ions generated during etching of the insulating films 255A and 255B may collide with corners of the edges of the openings of the insulator 280, the insulator 255a, and the insulator 255b. Figure 4C As shown in FIG. 1 , the corners are sometimes polished to have a tapered shape. For example, the corners can be easily removed by making the etching gas contain an easily ionized gas such as argon or by applying a bias voltage to an electrode on the substrate side.

[0365] Alternatively, after forming the insulator 255a and the insulator 255b, isotropic etching may be performed to remove a portion of the insulator 255b. Figure 5B As shown in FIG. 1 , the side surface of the insulator 255b on the side of the conductor 260 may be set back from the end of the protruding portion of the insulator 255a. By adopting this structure, the width of the upper portion of the conductor 260 to be formed in the subsequent process can be made larger than the width of the lower portion of the conductor 260. As a result, the wiring resistance of the conductor 260 can be reduced.

[0366] Next, the portion of the conductor 242_1 exposed from the insulator 255 is removed by anisotropic etching to form the conductor 242a1 and the conductor 242b1 (see FIG. 13A to FIG. 13D ). In other words, the conductor 242_1 is processed using the insulator 255 as a mask to separate the conductor 242_1 into the conductor 242a1 and the conductor 242b1. By processing the conductor 242_1 using anisotropic etching, side etching of the insulator 255 can be suppressed. In this way, by processing the conductor 242_1 using the insulator 255 as a mask, the side end of the insulator 255 is formed to be aligned or approximately aligned with the side end of the conductor 242a1 and the side end of the conductor 242b1 when the transistor 200 is cross-sectionally viewed.

[0367] Thus, when viewed in cross section in the channel length direction, the distance between the conductor 242a1 and the conductor 242b1 is also L2. L2 is shorter than L1, and the difference between L1 and L2 is equal to or approximately equal to twice the thickness of the insulator 255. For example, when the width L1 of the opening of the insulator 280 is 28nm and the thickness of the insulator 255 is 10nm, the distance L2 between the conductor 242a1 and the conductor 242b1 can be set to 8nm. In other words, by utilizing the photolithography technology that forms an opening of 28nm, a transistor having a channel length of less than 8nm can be manufactured without performing double imaging or other processing. In this way, a wiring with a line width having a higher processing accuracy than the photolithography technology actually used can be formed. Therefore, a photolithography technology having a processing accuracy lower than the line width required by the design can be utilized, so that the manufacturing process of the semiconductor device can be simplified and the production cost can be reduced.

[0368] Dry etching is preferably used as anisotropic etching. Note that the dry etching conditions and dry etching apparatus can refer to the above description. For example, when tantalum nitride is used for the conductor 242_1, an ICP etching apparatus can be used and Cl2 and Ar can be used as etching gases for etching.

[0369] As described above, the insulator 255 is formed on the conductor 242_1 by anisotropic etching, and the conductor 242_1 is divided by using the insulator 255 as a mask, so that the insulator 255 used as a mask can be formed in a self-aligned manner. Therefore, in the manufacturing process of the semiconductor device described in this embodiment, the number of masks and the number of steps can be reduced. Therefore, a method for manufacturing a semiconductor device with high productivity can be provided.

[0370] In addition, by using the above method, the island oxide 230 can be exposed to dry etching only during the processing of the conductor 242_1. In other words, it is possible to prevent the top surface of the island oxide 230 from being exposed to dry etching when the insulator 255 is formed. As a result, the damage to the oxide 230b used as the channel formation region of the transistor 200 due to dry etching (for example, damage caused by ion collision, etc.) can be reduced. In the dry etching process of the conductor 242_1, by reducing the bias power midway, the damage to the oxide 230 can be further reduced. Note that, as Figure 4A As shown, a recessed portion may be formed in a portion of the oxide 230 exposed from the conductor 242a1 and the conductor 242b1.

[0371] In addition, if Fig. 13C As shown, conductor 242_1 is removed, and the top of insulator 255 near the side of oxide 230 is also removed. Fig. 13C In the embodiment, the insulator 255 is formed to cover the side surfaces of the oxide 230 and the side surfaces of the insulator 224, but the present invention is not limited thereto. For example, depending on the anisotropic etching conditions of the insulating film 255A, the insulating film 255B, and the conductor 242_1 and the tapered shape of the side surfaces of the oxide 230, the insulator 255 may be formed to cover a portion of the side surfaces of the oxide 230 or the insulator 255 may disappear near the side surfaces of the oxide 230.

[0372] After the conductor 242_1 is processed, an ashing treatment using oxygen plasma may also be performed. By performing such an oxygen plasma treatment, impurities generated in the above-mentioned etching process and diffused into the oxide 230 and the like can be removed. As such impurities, there can be cited impurities of components in the workpiece resulting from the above-mentioned etching process and impurities of components in the gas used in etching and the like. For example, chlorine, fluorine, tantalum, silicon, hafnium, and the like can be cited. In particular, as shown in the above-mentioned etching process, when chlorine gas is used in the processing of the conductor 242_1, the oxide 230 is exposed to an atmosphere containing chlorine gas, and therefore it is preferred to remove the chlorine attached to the oxide 230. By removing impurities attached to the oxide 230 in this way, the electrical characteristics and reliability of the transistor can be improved.

[0373] In addition, by performing the above-mentioned oxygen plasma treatment, at least a portion of the insulator 255a is sometimes oxidized. In other words, the insulator 255a sometimes contains oxygen. At this time, by performing composition analysis on the insulator 255a using SIMS or the like, a region with a high oxygen concentration is observed in the insulator 255a. Note that sometimes the oxidation of the insulator 255a progresses, and at least a portion of the insulator 255a becomes silicon oxynitride or silicon nitride oxide after the transistor 200 is formed.

[0374] The processing and oxygen plasma treatment of the insulating film 255A, the insulating film 255B, and the conductor 242_1 can be performed continuously without being exposed to the atmosphere. For example, a multi-chamber etching apparatus can be used to perform the processing and oxygen plasma treatment continuously without being exposed to the atmosphere.

[0375] In this way, the conductors 242a1 and 242b1 having oxidation resistance can be formed under the conductors 242a2 and 242b2 having high conductivity, and the insulator 255 having oxidation resistance can be formed in contact with the side surfaces of the conductors 242a2 and 242b2. With this structure, the conductors 242a2 and 242b2 having high conductivity can be used as the source electrode and the drain electrode of the transistor 200, so that the frequency characteristics of the transistor 200 can be improved and the operating speed of the semiconductor device can be increased.

[0376] In order to remove impurities and the like attached to the surface of the oxide 230b in the above-mentioned etching process, a washing process may also be performed. As a washing method, there are wet washing using a washing liquid or the like (which may also be referred to as a wet etching process), plasma treatment using plasma, washing using a heat treatment, etc., and the above-mentioned washings may be appropriately combined. Note that the above-mentioned groove may become deeper by performing this washing process.

[0377] As wet cleaning, an aqueous solution, pure water or carbonated water etc. formed by diluting one or more of ammonia, oxalic acid, phosphoric acid or hydrofluoric acid with carbonated water or pure water can be used. Alternatively, ultrasonic cleaning can be performed using the above aqueous solution, pure water or carbonated water. In addition, the above cleaning can also be appropriately combined.

[0378] Note that in this specification, etc., an aqueous solution of hydrofluoric acid diluted with pure water is sometimes referred to as dilute hydrofluoric acid, and an aqueous solution of ammonia diluted with pure water is sometimes referred to as dilute ammonia water. In addition, the concentration, temperature, etc. of the aqueous solution are appropriately adjusted according to the impurities to be removed, the structure of the semiconductor device to be washed, etc. The ammonia concentration of the dilute ammonia water is preferably set to 0.01% or more and 5% or less, and more preferably set to 0.1% or more and 0.5% or less. In addition, the hydrogen fluoride concentration of the dilute hydrofluoric acid is preferably set to 0.01ppm or more and 100ppm or less, and more preferably set to 0.1ppm or more and 10ppm or less.

[0379] In addition, it is preferable to use a frequency of 200 kHz or higher, and more preferably a frequency of 900 kHz or higher for ultrasonic cleaning. By using such a frequency, damage to the oxide 230 b and the like can be reduced.

[0380] In addition, the above-mentioned washing treatment may be performed multiple times, and the washing liquid may be changed for each washing treatment. For example, the first washing treatment may be a treatment using dilute hydrofluoric acid or dilute ammonia water, and the second washing treatment may be a treatment using pure water or carbonated water.

[0381] In this embodiment, the cleaning process is performed by wet cleaning using dilute ammonia water. This cleaning process can remove impurities attached to the surface of the oxide 230a, the oxide 230b, etc. or diffused into the inside thereof. In addition, the crystallinity of the oxide 230b can be improved.

[0382] It is preferred to perform heat treatment after the above-mentioned etching or the above-mentioned washing. The temperature of the heat treatment is preferably above 100°C, above 250°C, or above 350°C and below 650°C, below 600°C, below 550°C, or below 400°C. The heat treatment is performed in an atmosphere of nitrogen gas, inert gas, or an oxidizing gas containing 10 ppm or more, 1% or more, or 10% or more. For example, it is preferred to perform the heat treatment in an oxygen-containing atmosphere, preferably at a flow ratio of nitrogen gas to oxygen gas of 4:1 and a temperature of 350°C for 1 hour. Thus, oxygen is supplied to the oxide 230a and the oxide 230b, thereby reducing oxygen vacancies. In addition, by performing the above-mentioned heat treatment, the crystallinity of the oxide 230b can be improved. Furthermore, the hydrogen remaining in the oxide 230a and the oxide 230b reacts with the supplied oxygen and the hydrogen can be removed (dehydrated) in the form of H2O. Thus, the hydrogen remaining in the oxide 230a and the oxide 230b can be inhibited from recombinating with oxygen vacancies to form V O H. Thus, the electrical characteristics of the transistor provided with the oxide 230 can be improved and the reliability can be improved. In addition, the non-uniformity of the electrical characteristics of the plurality of transistors formed on the same substrate can be suppressed. The above-mentioned heat treatment can also be performed under reduced pressure. Alternatively, the heat treatment can be performed in an oxygen atmosphere and then continuously in a nitrogen atmosphere without being exposed to the atmosphere.

[0383] Here, as described above, the insulator 255a made of an inorganic insulator that is not easily oxidized is formed in contact with the side surface of the conductor 242a2 and the side surface of the conductor 242b2. Thus, even if a tungsten film or the like that is easily oxidized is used for the conductors 242a2 and 242b2, the conductors 242a2 and 242b2 can be prevented from being excessively oxidized by the above-mentioned heat treatment.

[0384] When heat treatment is performed in a state where the conductor 242a and the conductor 242b are in contact with the oxide 230b, the sheet resistance of the region where the oxide 230b overlaps with the conductor 242a and the region where the oxide 230b overlaps with the conductor 242b may be reduced. In addition, the carrier concentration may be increased. Therefore, the region where the oxide 230b overlaps with the conductor 242a and the region where the oxide 230b overlaps with the conductor 242b can be made low-resistance in a self-aligned manner.

[0385] Next, an insulating film 250A (see FIG. 25A ) to be the insulator 250 is deposited so as to be embedded in the opening formed in the insulator 280 or the like. FIG. 14A to FIG. 14D Here, the insulating film 250A is in contact with the insulator 280, the insulator 255, the conductor 242a1, the conductor 242b1, the insulator 222, the insulator 224, the oxide 230a, and the oxide 230b.

[0386] The insulating film 250A can be deposited by sputtering, CVD, MBE, PLD or ALD. For example, the insulating film 250A is preferably deposited by the ALD method. As with the above-mentioned insulator 250, the insulating film 250A is preferably formed thin, and the thickness non-uniformity needs to be suppressed to a small value. In this regard, the ALD method is a deposition method that alternately introduces precursors and reactants (for example, oxidants, etc.). Since the thickness of the film can be adjusted according to the number of times the cycle is repeated, the thickness can be precisely adjusted. In addition, the insulating film 250A needs to be deposited on the bottom and side surfaces of the opening with high coverage. By using the ALD method, since each atomic layer can be deposited on the bottom and side surfaces of the above-mentioned opening, the insulating film 250A can be formed in the opening with high coverage.

[0387] When the insulating film 250A is deposited by the ALD method, ozone (O3), oxygen (O2), water (H2O), etc. can be used as an oxidant. By using ozone (O3), oxygen (O2), etc. that do not contain hydrogen as an oxidant, hydrogen diffused into the oxide 230b can be reduced.

[0388] like Figure 2A As shown in FIG. 1 and FIG. 2 , the insulator 250 may also have a laminated structure. FIG. 15A to FIG. 15C Description of the insulator 250 and Figure 2A Similarly, the method of depositing the insulating film 250A having a three-layer structure of the insulator 250a, the insulator 250b, and the insulator 250c is as follows. FIG. 15A to FIG. 15C In FIG. 2 , the insulating film 250A includes an insulating film 250Aa, an insulating film 250Ab on the insulating film 250Aa, and an insulating film 250Ac on the insulating film 250Ab.

[0389] First, an insulating film 250Aa to be the insulator 250a is deposited in a manner embedded in an opening formed in the insulator 280 or the like, and an insulating film 250Ab is deposited on the insulating film 250Aa (see Fig.15A ). In this embodiment, aluminum oxide is deposited as the insulating film 250Aa by a thermal ALD method, and silicon oxide is deposited as the insulating film 250Ab by a PEALD method.

[0390] Next, microwave treatment is preferably performed in an oxygen-containing atmosphere (see Fig. 15B Here, microwave treatment refers to, for example, treatment using a device including a power source for generating high-density plasma using microwaves. In addition, in this specification, etc., microwaves refer to electromagnetic waves having a frequency of 300 MHz or more and 300 GHz or less.

[0391] Microwave treatment, for example, preferably uses a microwave processing device including a power supply that generates high-density plasma using microwaves. Here, the frequency of the microwave processing device is preferably set to be above 300 MHz and below 300 GHz, more preferably above 2.4 GHz and below 2.5 GHz, for example, it can be 2.45 GHz. By using high-density plasma, high-density oxygen free radicals can be generated. In addition, the power of the power supply that applies microwaves in the microwave processing device is preferably above 1000 W and below 10000 W, preferably above 2000 W and below 5000 W. In addition, the microwave processing device may also include a power supply that applies RF to one side of the substrate. In addition, by applying RF to one side of the substrate, the oxygen ions generated by the high-density plasma can be efficiently introduced into the oxide 230 b.

[0392] In addition, the microwave treatment is preferably carried out under reduced pressure, and the pressure is preferably 10Pa or more and 1000Pa or less, more preferably 300Pa or more and 700Pa or less. In addition, the treatment temperature is preferably 750°C or less, more preferably 500°C or less, for example, about 250°C. In addition, it is also possible to continuously perform heat treatment without being exposed to the atmosphere after the oxygen plasma treatment. The temperature of the heat treatment is, for example, preferably 100°C or more and 750°C or less, more preferably 300°C or more and 500°C or less.

[0393] In addition, for example, the above-mentioned microwave treatment can be performed using oxygen gas and argon gas. Here, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 100%. Preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 0% and less than 50%. More preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 40%. Further preferably, the oxygen flow ratio (O2 / (O2+Ar)) is greater than 10% and less than 30%. In this way, by performing microwave treatment in an oxygen-containing atmosphere, the carrier concentration in the oxide 230b can be reduced. In addition, by preventing excessive oxygen from being introduced into the processing chamber during microwave treatment, the carrier concentration in the oxide 230b can be prevented from being excessively reduced.

[0394] By performing microwave treatment in an oxygen-containing atmosphere, microwaves or high frequencies such as RF can be used to convert oxygen gas into plasma and the oxygen plasma can be applied to the region between the conductors 242a and 242b of the oxide 230b. The V O H is separated into oxygen vacancies and hydrogen, and hydrogen is removed from the region. Figure 2A When the structure shown in the figure is used, it is preferable to use an insulating film (e.g., aluminum oxide) having the function of capturing or fixing hydrogen as the insulating film 250Aa. By adopting the above structure, the insulating film 250Aa can capture or fix hydrogen generated by microwave treatment. In this way, the V contained in the channel formation region can be reduced. O H. Thus, oxygen vacancies and V O H and thus reduce the carrier concentration. In addition, by supplying oxygen radicals generated in the above oxygen plasma to oxygen vacancies formed in the channel formation region, the oxygen vacancies in the channel formation region can be further reduced, thereby reducing the carrier concentration.

[0395] As oxygen injected into the channel formation region, there are various forms such as oxygen atoms, oxygen molecules, oxygen ions and oxygen free radicals (also called O free radicals, atoms, molecules or ions containing unpaired electrons). The oxygen injected into the channel formation region can be any one or more of the above forms, and oxygen free radicals are particularly preferred. In addition, since the film quality of the insulator 250 can be improved, the reliability of the transistor is improved.

[0396] On the other hand, the oxide 230b has a region overlapping with any one of the conductors 242a and 242b. This region can be used as a source region or a drain region. Here, the conductors 242a and 242b are preferably used as a shielding film to protect against microwaves, RF and other high frequencies or oxygen plasma when microwave treatment is performed in an oxygen-containing atmosphere. Therefore, the conductors 242a and 242b preferably have a function of shielding electromagnetic waves of 300 MHz or more and 300 GHz or less, for example, 2.4 GHz or more and 2.5 GHz or less.

[0397] The conductors 242a and 242b shield the microwaves, high frequencies such as RF, oxygen plasma, etc., and thus do not act on the region of the oxide 230b that overlaps with any of the conductors 242a and 242b. Thus, the microwave treatment does not cause V to occur in the source region and the drain region. O The decrease in H and the supply of excessive oxygen can prevent the decrease in carrier concentration.

[0398] In addition, an insulator 255a having oxygen barrier properties is provided in contact with the side surfaces of the conductors 242a2 and 242b2. In addition, insulating films 250Aa and 250Ab are provided to cover the conductors 242a1 and 242b1 and the insulator 255. Therefore, it is possible to suppress the formation of oxide films on the side surfaces of the conductors 242a and 242b due to the microwave treatment.

[0399] As described above, oxygen vacancies and V can be selectively removed in the channel formation region of the oxide semiconductor. O H makes the channel formation region become i-type or substantially i-type. In addition, it is possible to suppress the region used as the source region or the drain region from being supplied with excessive oxygen and maintain the conductivity (the state of the low resistance region) before the microwave treatment. Thus, it is possible to suppress the change of the electrical characteristics of the transistor and suppress the non-uniformity of the electrical characteristics of the transistor within the substrate surface.

[0400] In addition, during the microwave treatment, sometimes the microwave and the molecules in the oxide 230b directly transfer heat energy to the oxide 230b due to electromagnetic interaction. Sometimes the oxide 230b is heated by the heat energy. Sometimes this heat treatment is called microwave annealing. By performing the microwave treatment in an oxygen-containing atmosphere, sometimes an effect equivalent to oxygen annealing can be obtained. In addition, it is considered that: when the oxide 230b contains hydrogen, the above heat energy is transferred to the hydrogen in the oxide 230b and the activated hydrogen is released from the oxide 230b.

[0401] Furthermore, by performing microwave treatment to modify the film quality of the insulating film 250Aa and the insulating film 250Ab, diffusion of hydrogen, water, impurities, etc. can be suppressed. Thus, diffusion of hydrogen, water, impurities, etc. through the insulator 250 to the oxide 230b, the oxide 230a, etc. due to post-processes such as deposition of the conductive film to be the conductor 260 or post-processes such as heat treatment can be suppressed. In this way, by improving the film quality of the insulator 250, the reliability of the transistor can be improved.

[0402] Next, an insulating film 250Ac is deposited on the insulating film 250Ab (see Fig. 15C In this embodiment, silicon nitride is deposited as the insulating film 250Ac by a PEALD method. In this way, the insulating film 250A including the insulating films 250Aa to 250Ac can be formed.

[0403] Note that in the above structure, an example of performing microwave treatment after depositing the insulating film 250Ab is shown, but the present invention is not limited to this. The microwave treatment may be performed after the deposition of the insulating film 250Ac. Alternatively, the microwave treatment may be performed before depositing the insulating film 250Aa. In addition, when the microwave treatment is performed before depositing the insulating film 250Aa, the microwave treatment may be performed after the deposition of the insulating film 250Aa. FIG. 11A to FIG. 11D The microwave treatment may be performed in the process shown in FIG. 25A. For example, the microwave treatment may be performed after the insulating film 255A is deposited. In addition, the microwave treatment may be performed after the insulating film 255B is deposited.

[0404] In addition, heat treatment can be performed while maintaining a reduced pressure state after microwave treatment. By performing such treatment, hydrogen in the insulating film, oxide 230b and oxide 230a can be efficiently removed. In addition, a portion of hydrogen is sometimes doped by conductors 242a and 242b. In addition, the step of maintaining a reduced pressure state and performing heat treatment after microwave treatment can be repeated. By repeatedly performing heat treatment, hydrogen in the insulating film, oxide 230b and oxide 230a can be further efficiently removed. Note that the heat treatment temperature is preferably above 300°C and below 500°C. The above-mentioned microwave treatment, i.e., microwave annealing, can also serve as the heat treatment. When oxide 230b and the like are sufficiently heated by microwave annealing, the heat treatment may not be performed.

[0405] Note that Figure 3A As shown in FIG. 1 , when the insulator 250 has a stacked structure of the insulator 250a and the insulator 250c, the insulating film 250Ab need not be deposited in the above process. Figure 3B As shown in FIG. 1 , when the insulator 250 has a stacked structure of an insulator 250a, an insulator 250b, an insulator 250c, and an insulator 250d, Fig. 15BAfter the microwave treatment, an insulating film to be the insulator 250d is deposited, and the microwave treatment is performed again to deposit the insulating film 250Ac. Here, hafnium oxide can be deposited by thermal ALD as the insulating film to be the insulator 250d. In this way, the microwave treatment in the oxygen-containing atmosphere can also be a multiple (at least twice) treatment.

[0406] Next, a conductive film 260A to be the conductor 260a and a conductive film 260B to be the conductor 260b are sequentially deposited (see FIG. 16A to FIG. 16D ). The conductive film 260A and the conductive film 260B can be deposited by, for example, sputtering, CVD, MBE, PLD, electroplating, or ALD. In this embodiment, titanium nitride is deposited as the conductive film 260A by the ALD method, and tungsten is deposited as the conductive film 260B by the CVD method.

[0407] Next, the insulating film 250A, the conductive film 260A, and the conductive film 260B are polished by CMP until the insulator 280 is exposed. That is, the portion of the insulating film 250A, the conductive film 260A, and the conductive film 260B exposed from the above-mentioned opening is removed. As a result, the insulator 250 and the conductor 260 (conductor 260a and conductor 260b) are formed in the opening overlapping with the conductor 205 (see FIG. 17A to FIG. 17D ).

[0408] Thus, the insulator 250 is provided in the opening so as to be in contact with the insulator 255, the conductor 242a1, the conductor 242b1, the oxide 230, the insulator 224, and the insulator 222. Furthermore, the conductor 260 is disposed so as to be embedded in the opening via the insulator 250. Thus, the transistor 200 is formed.

[0409] Next, an insulator 282 is formed on the insulator 255, the insulator 250, the conductor 260, and the insulator 280. The insulator 282 can be deposited, for example, by a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 282 is preferably deposited by a sputtering method. By using a sputtering method that does not require the use of molecules containing hydrogen as a deposition gas, the hydrogen concentration in the insulator 282 can be reduced.

[0410] In addition, by depositing the insulator 282 in an oxygen-containing atmosphere by sputtering, oxygen can be added to the insulator 280 while the deposition is being performed. Thus, the insulator 280 can contain excess oxygen. In this case, it is preferable to deposit the insulator 282 while heating the substrate. Here, as described above, when a portion of the insulator 255a is oxidized, the oxygen supplied to the insulator 280 can be appropriately supplied to the oxide 230b through the insulator 255a, the insulator 255b, and the insulator 250.

[0411] In this embodiment, aluminum oxide is deposited as the insulator 282 by sputtering using an aluminum target in an atmosphere containing an oxygen gas. The amount of oxygen injected into the lower layer of the insulator 282 can be controlled according to the magnitude of the RF power applied to the substrate. For example, the smaller the RF power, the less oxygen is injected into the lower layer of the insulator 282, and the oxygen amount is easily saturated even if the insulator 282 is thin. In addition, the greater the RF power, the more oxygen is injected into the lower layer of the insulator 282. By reducing the RF power, the amount of oxygen injected into the insulator 280 can be suppressed. Alternatively, an insulator 282 having a two-layer stacked structure can also be deposited. At this time, for example, RF power is not applied to the substrate to deposit the lower layer of the insulator 282, and RF power is applied to the substrate to deposit the upper layer of the insulator 282.

[0412] In addition, the frequency of RF is preferably 10 MHz or higher, and is typically 13.56 MHz. The higher the frequency of RF, the less damage to the substrate can be caused.

[0413] In addition, heat treatment may be performed before depositing the insulator 282. The heat treatment may be performed under reduced pressure, and the insulator 282 may be continuously deposited without being exposed to the atmosphere. By performing such treatment, moisture and hydrogen attached to the surface of the insulator 280 may be removed, and the moisture concentration and hydrogen concentration in the insulator 280 may be reduced. The temperature of the heat treatment is preferably 100° C. or higher and 400° C. or lower. In this embodiment, the temperature of the heat treatment is set to 250° C.

[0414] Next, an insulator 283 is formed on the insulator 282. The insulator 283 can be deposited by, for example, a sputtering method, a CVD method, an MBE method, a PLD method, or an ALD method. The insulator 283 is preferably deposited by a sputtering method. By using a sputtering method that does not require molecules containing hydrogen to be used for a deposition gas, the hydrogen concentration in the insulator 283 can be reduced. In this embodiment, silicon nitride is deposited by a sputtering method as the insulator 283.

[0415] Here, it is preferable to continuously deposit insulator 282 and insulator 283 without exposure to the atmosphere. By depositing without exposure to the atmosphere, impurities or moisture from the atmosphere can be prevented from adhering to insulator 282 and insulator 283, so that the vicinity of the interface between insulator 282 and insulator 283 can be kept clean.

[0416] In addition, heat treatment may be performed after the insulator 283 is deposited. The temperature of the heat treatment is preferably above 100° C. and below 400° C. By performing the heat treatment, hydrogen in the insulator 280, the insulator 250, and the oxide 230 moves to the insulator 282 and is absorbed by the insulator 282. In other words, hydrogen in the insulator 280, the insulator 250, and the oxide 230 diffuses into the insulator 282. Therefore, although the hydrogen concentration of the insulator 282 becomes higher, the hydrogen concentrations of the insulator 280, the insulator 250, and the oxide 230 all become lower. In addition, by providing the insulator 283 in contact with the top surface of the insulator 282, impurities such as moisture or hydrogen can be prevented from entering from above the insulator 283 during the heat treatment. In addition, by performing the heat treatment, hydrogen in the insulator 216, the insulator 224, and the oxide 230 moves to the insulator 222 and is absorbed by the insulator 222. In other words, hydrogen in insulator 216, insulator 224, and oxide 230 diffuses into insulator 222. Therefore, although the hydrogen concentration of insulator 222 increases, the hydrogen concentrations of insulator 216, insulator 224, and oxide 230 all decrease. By providing insulator 221 in contact with the bottom surface of insulator 222, impurities such as moisture or hydrogen can be prevented from entering from below insulator 221 during the heat treatment.

[0417] Through the above steps, the semiconductor device shown in FIG. 1 can be manufactured.

[0418] In the semiconductor device according to the present embodiment, when the conductor on the oxide semiconductor has a two-layer structure, in which a conductor that is not easily oxidized is used for the lower layer and a conductor with high conductivity is used for the upper layer, a conductor used as an electrode or wiring is provided in contact with the top surface of the oxide semiconductor. The conductor is used as the source electrode and the drain electrode of the OS transistor. In the semiconductor device according to the present embodiment, miniaturization is achieved by making the distance between the conductors of the lower layer of the source electrode and the drain electrode shorter than the distance between the conductors of the upper layer of the source electrode and the drain electrode, and the frequency characteristics and operating speed of the semiconductor device can be improved. In addition, in the semiconductor device according to the present embodiment, an insulator used as a protective film is provided in contact with the side of the conductor of the upper layer of the source electrode and the drain electrode. Thus, excessive oxidation of the upper layer of the source electrode and the drain electrode can be suppressed.

[0419] The semiconductor device according to this embodiment includes an OS transistor. The off-state current of the OS transistor is small, so a semiconductor device or a storage device with low power consumption can be realized. In addition, since the frequency characteristics of the OS transistor are high, a semiconductor device or a storage device with a fast operating speed can be realized. In addition, by using the OS transistor, a semiconductor device with good electrical characteristics, a semiconductor device with small uneven electrical characteristics of the transistor, a semiconductor device with large on-state current, and a semiconductor device or a storage device with high reliability can be realized.

[0420] This embodiment mode can be appropriately combined with other embodiment modes. In addition, in this specification, when a plurality of configuration examples are shown in one embodiment mode, the configuration examples can be appropriately combined.

[0421] (Implementation Method 2)

[0422] In this embodiment, a comparison between the OS transistor described in the above embodiment and a transistor including silicon in a channel formation region (also referred to as a Si transistor) is described.

[0423] [OS Transistor]

[0424] It is preferable to use an oxide semiconductor with a low carrier concentration for the OS transistor. For example, the carrier concentration of the channel formation region of the oxide semiconductor is 1×10 18 cm -3 Below, preferably below 1×10 17 cm -3 , more preferably less than 1×10 16 cm -3 , and more preferably less than 1×10 13 cm -3 , and further preferably less than 1×10 10 cm -3 , and is 1×10 -9 cm -3 In the case of reducing the carrier concentration of the oxide semiconductor film, the impurity concentration in the oxide semiconductor film can be reduced to reduce the defect state density. In this specification, etc., a state in which the impurity concentration is low and the defect state density is low is referred to as high-purity intrinsic or substantially high-purity intrinsic. In addition, an oxide semiconductor with a low carrier concentration is sometimes referred to as a high-purity intrinsic or substantially high-purity intrinsic oxide semiconductor.

[0425] Since high-purity intrinsic or substantially high-purity intrinsic oxide semiconductors have a low defect state density, they sometimes have a low trap state density. In addition, it takes a long time for the charges captured by the trap states of the oxide semiconductor to disappear, and sometimes they act like fixed charges. Therefore, sometimes the electrical characteristics of a transistor in which a channel formation region is formed in an oxide semiconductor with a high trap state density are unstable.

[0426] Therefore, in order to stabilize the electrical characteristics of the transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. In order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the nearby film. As impurities, hydrogen, nitrogen, etc. can be cited. Note that impurities in oxide semiconductors refer to, for example, elements other than the main components that constitute the oxide semiconductor. For example, an element with a concentration of less than 0.1 atomic % can be said to be an impurity.

[0427] In an OS transistor, when impurities and oxygen vacancies exist in the channel formation region of an oxide semiconductor, the electrical characteristics are easily changed and reliability may be reduced. In addition, in an OS transistor, hydrogen enters the oxygen vacancies in the oxide semiconductor to form defects (hereinafter sometimes referred to as V O H), electrons that become carriers may be generated. In addition, when V O When the voltage is V, the donor concentration in the channel formation region may increase. As the donor concentration in the channel formation region increases, the threshold voltage may become uneven. Therefore, when oxygen vacancies are included in the channel formation region of the oxide semiconductor, the transistor may have a normally-on characteristic (a characteristic in which a channel exists and current flows in the transistor even when no voltage is applied to the gate electrode). Therefore, in the channel formation region of the oxide semiconductor, it is preferable to minimize impurities, oxygen vacancies, and V. O H.

[0428] In addition, the band gap of the oxide semiconductor is preferably larger than the band gap of silicon (typically 1.1 eV), preferably 2 eV or more, more preferably 2.5 eV or more, and more preferably 3.0 eV or more. By using an oxide semiconductor with a larger band gap than silicon, the off-state current (also called Ioff) of the transistor can be reduced.

[0429] For example, in Si transistors, as the miniaturization of transistors progresses, short channel effects (Short Channel Effect: also called SCE) appear. Therefore, miniaturization of Si transistors is difficult. One of the reasons for the short channel effect is that the band gap of silicon is small. On the other hand, in OS transistors, oxide semiconductors, which are semiconductor materials with large band gaps, are used, so the short channel effect can be suppressed. In other words, OS transistors are transistors with no short channel effect or very little short channel effect.

[0430] The short channel effect refers to the degradation of electrical characteristics that occurs with miniaturization of transistors (reduction of channel length). Specific examples of the short channel effect include a decrease in threshold voltage, an increase in S value, and an increase in leakage current.

[0431] As an indicator of resistance to short channel effects, characteristic length is widely used. Characteristic length refers to an indicator of the curvature of the potential in the channel formation region. The smaller the characteristic length, the more rapidly the potential rises, so it can be said that the ability to resist short channel effects is high.

[0432] OS transistors are accumulation-type transistors, and Si transistors are inversion-type transistors. Therefore, compared with Si transistors, the characteristic length between the source region and the channel formation region and the characteristic length between the drain region and the channel formation region in OS transistors are smaller. Therefore, OS transistors have a higher ability to resist short channel effects than Si transistors. That is, when you want to manufacture transistors with a small channel length, OS transistors are more suitable than Si transistors.

[0433] Even when the carrier concentration of the oxide semiconductor is reduced to the point where the channel formation region is i-type or substantially i-type, the conduction band bottom of the channel formation region is lowered due to the conduction-band-lowering (CBL) effect in the short channel transistor, so the energy difference of the conduction band bottom between the source region or the drain region and the channel formation region is likely to be reduced to more than 0.1 eV and less than 0.2 eV. Thus, the OS transistor can be regarded as having n + / n - / n + The accumulation type junction-less (junctionless) transistor structure or n + / n - / n + The accumulation type non-junction transistor structure, in which the channel formation region is n - Type region, source region and drain region are n + Type area.

[0434] When the above structure is used as an OS transistor, good electrical characteristics can be achieved even if the semiconductor device is miniaturized or highly integrated. For example, even if the gate length of the OS transistor is less than 20nm, less than 15nm, less than 10nm, less than 7nm or less than 6nm and more than 1nm, more than 3nm or more than 5nm, good electrical characteristics can be obtained. On the other hand, in Si transistors, it is sometimes difficult to have a gate length of less than 20nm or less than 15nm due to the occurrence of short channel effects. Therefore, compared with Si transistors, OS transistors are more suitable for use as transistors with a small channel length. The gate length is the length of the gate electrode in the direction of the carrier movement channel formation region when the transistor is working, and is the width of the bottom surface of the gate electrode in the plan view of the transistor.

[0435] In addition, by miniaturizing the OS transistor, the high-frequency characteristics of the transistor can be improved. Specifically, the cutoff frequency of the transistor can be increased. When the gate length of the OS transistor is within the above range, for example, at room temperature, the cutoff frequency of the transistor can be above 50 GHz, preferably above 100 GHz, and more preferably above 150 GHz.

[0436] As described above, the OS transistor has advantages superior to the Si transistor, such as a small off-state current and the ability to manufacture a transistor with a small channel length.

[0437] The configuration, structure, method, and the like described in this embodiment mode can be used in combination with the configuration, structure, method, and the like described in other embodiments mode and the like as appropriate.

[0438] (Implementation method 3)

[0439] In this embodiment, refer to Fig.18 A memory device using a transistor according to one embodiment of the present invention is described below through FIG. 28 .

[0440] In this embodiment mode, a structural example of a memory device using a memory cell including the transistor described in the above embodiment mode is described. In this embodiment mode, a structural example of a memory device is described in which a layer including stacked memory cells and a layer including a functional circuit having a function of amplifying a data potential held in the memory cell and outputting it are provided.

[0441] [Configuration Example of Storage Device]

[0442] Fig.18 This is a block diagram showing a storage device according to one embodiment of the present invention.

[0443] Fig.18 The memory device 300 shown includes a driving circuit 21 and a memory array 20. The memory array 20 includes a plurality of memory cells 10 and a functional layer 50 having a plurality of functional circuits 51.

[0444] Fig.18 The example in which the memory array 20 includes a plurality of memory cells 10 arranged in a matrix of m rows and n columns (m and n are integers greater than or equal to 2) is shown. Fig.18 An example is shown in which a functional circuit 51 is provided for each wiring BL serving as a bit line, and an example is also shown in which the functional layer 50 includes a plurality of functional circuits 51 provided corresponding to n wirings BL.

[0445] exist Fig.18, the 1st row and 1st column storage cell 10 is represented as storage cell 10[1, 1], and the mth row and nth column storage cell 10 is represented as storage cell 10[m, n]. In addition, in the present embodiment, etc., sometimes "row i" is written to represent an arbitrary row. In addition, sometimes "column j" is written to represent an arbitrary column. Therefore, i is an integer greater than 1 and less than m, and j is an integer greater than 1 and less than n. In addition, in the present embodiment, etc., the i-th row and j-th column storage cell 10 is represented as storage cell 10[i, j]. Note that in the present embodiment, etc., when expressed as "i+α" (α is a positive integer or a negative integer), "i+α" is not less than 1 and not greater than m. Similarly, when expressed as "j+α", "j+α" is not less than 1 and not greater than n.

[0446] In addition, the memory array 20 includes m wirings WL extending in the row direction, m wirings PL extending in the row direction, and n wirings BL extending in the column direction. In the present embodiment and the like, the first (1st row) wiring WL is represented as wiring WL[1], and the mth (mth row) wiring WL is represented as wiring WL[m]. Similarly, the first (1st row) wiring PL is represented as wiring PL[1], and the mth (mth row) wiring PL is represented as wiring PL[m]. Similarly, the first (1st column) wiring BL is represented as wiring BL[1], and the nth (nth column) wiring BL is represented as wiring BL[n].

[0447] The plurality of memory cells 10 arranged in the i-th row are electrically connected to the i-th row wiring WL (wiring WL[i]) and the i-th row wiring PL (wiring PL[i]). The plurality of memory cells 10 arranged in the j-th column are electrically connected to the j-th column wiring BL (wiring BL[j]).

[0448] The memory array 20 can use DOSRAM (registered trademark) (Dynamic Oxide Semiconductor Random Access Memory). DOSRAM is a RAM including 1T (transistor) 1C (capacitor) type memory cells, and is a memory in which the access transistor is an OS transistor. The current flowing between the source and the drain of the OS transistor in the off state, that is, the leakage current is extremely small. In DOSRAM, by turning off the access transistor (making it in a non-conducting state), the charge based on the data stored in the capacitor element (capacitor) can be maintained for a long time. Therefore, compared with a DRAM composed of a transistor (Si transistor) containing silicon in the channel formation region, the refresh operation frequency of the DOSRAM can be lower. As a result, low power consumption can be achieved. In addition, since the frequency characteristics of the OS transistor are high, high-speed reading and writing of the storage device can be performed. Thus, a storage device with a high operating speed can be provided.

[0449] For example, Fig.18 The memory array 20 shown may include a plurality of memory arrays 20[1] to 20[m] stacked together. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is disposed, the storage density of the memory cell 10 may be increased.

[0450] Wiring BL is used as a bit line for writing and reading data. Wiring WL is used as a word line for controlling the opening or closing (conduction state or non-conduction state) of the access transistor used as a switch. Wiring PL is used as a constant potential line connected to the capacitor element. In addition, wiring CL (not shown) can be separately provided as a wiring for transmitting the back gate potential to the back gate of the OS transistor of the access transistor. In addition, a structure in which wiring PL also serves as a transmission back gate potential can also be adopted.

[0451] The memory cells 10 included in the memory arrays 20[1] to 20[m] are connected to the functional circuit 51 through the wiring BL. The wiring BL can be arranged in a direction perpendicular to the surface of the substrate on which the driving circuit 21 is provided. By arranging the wiring BL extending from the memory cells 10 included in the memory arrays 20[1] to 20[m] in a direction perpendicular to the surface of the substrate, the length of the wiring between the memory array 20 and the functional circuit 51 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the bit line can be shortened and the resistance and parasitic capacitance of the bit line can be greatly reduced, the power consumption and signal delay can be reduced. In addition, even if the capacitance of the capacitor element included in the memory cell 10 is reduced, the memory device can operate.

[0452] The functional circuit 51 has a function of amplifying the data potential held in the memory cell 10 and outputting it to the sense amplifier 46 included in the drive circuit 21 through the wiring GBL (not shown) described later. By adopting this structure, a small potential difference of the wiring BL can be amplified when reading data. The wiring GBL can be arranged in a direction perpendicular to the surface of the substrate on which the drive circuit 21 is provided, similarly to the wiring BL. By arranging the wiring BL and the wiring GBL extending from the memory cell 10 included in the memory array 20[1] to 20[m] in a direction perpendicular to the substrate surface, the length of the wiring between the functional circuit 51 and the sense amplifier 46 can be shortened. Therefore, since the signal transmission distance between the two circuits connected to the wiring GBL can be shortened and the resistance and parasitic capacitance of the wiring GBL can be greatly reduced, power consumption and signal delay can be reduced.

[0453] Furthermore, the wiring BL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the memory cell 10. Alternatively, the wiring BL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the memory cell 10 that functions as a source or a drain. Alternatively, the wiring BL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the memory cell 10 that functions as a source or a drain. That is, the wiring BL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the memory cell 10 in each layer of the memory array 20 to the functional circuit 51 in the vertical direction.

[0454] The memory array 20 can be overlapped on the drive circuit 21. By overlapping the drive circuit 21 and the memory array 20, the signal transmission distance between the drive circuit 21 and the memory array 20 can be shortened. Therefore, the resistance and parasitic capacitance between the drive circuit 21 and the memory array 20 are reduced, and the power consumption and signal delay can be reduced. In addition, the storage device 300 can be miniaturized.

[0455] By forming the functional circuit 51 with OS transistors similarly to the transistors included in the memory cell 10 of the DOSRAM, the functional circuit 51 can be freely arranged on a circuit using Si transistors similarly to the memory arrays 20[1] to 20[m], thereby making integration easy. By adopting a structure in which the functional circuit 51 amplifies the signal, the circuits such as the sense amplifier 46 of the subsequent circuit can be miniaturized, thereby miniaturizing the memory device 300.

[0456] The drive circuit 21 includes a PSW 22 (power switch), a PSW 23 , and a peripheral circuit 31 . The peripheral circuit 31 includes a peripheral circuit 41 , a control circuit 32 , and a voltage generation circuit 33 .

[0457] In the storage device 300, each circuit, each signal, and each voltage can be appropriately selected as needed. Alternatively, other circuits or other signals can be added. Signals BW, CE, GW, CLK, WAKE, ADDR, WDA, PON1, and PON2 are signals input from the outside, and signal RDA is a signal output to the outside. Signal CLK is a clock signal.

[0458] In addition, the signal BW, the signal CE, and the signal GW are control signals. The signal CE is a chip enable signal, the signal GW is a global write enable signal, and the signal BW is a byte write enable signal. The signal ADDR is an address signal. The signal WDA is write data, and the signal RDA is read data. The signal PON1 and the signal PON2 are power gating control signals. In addition, the signal PON1 and the signal PON2 can also be generated in the control circuit 32.

[0459] The control circuit 32 is a logic circuit that has the function of controlling the overall operation of the storage device 300. For example, the control circuit performs a logic operation on the signal CE, the signal GW, and the signal BW to determine the operation mode (for example, writing operation, reading operation) of the storage device 300. Alternatively, the control circuit 32 generates a control signal for the peripheral circuit 41 to execute the above operation mode.

[0460] The voltage generating circuit 33 has a function of generating a negative voltage. The signal WAKE has a function of controlling the input of the signal CLK to the voltage generating circuit 33. For example, when the signal WAKE is applied with an H level signal, the signal CLK is input to the voltage generating circuit 33, and the voltage generating circuit 33 generates a negative voltage.

[0461] The peripheral circuit 41 is a circuit for writing and reading data to the memory cell 10. In addition, the peripheral circuit 41 is a circuit for outputting various signals for controlling the functional circuit 51. The peripheral circuit 41 includes a row decoder 42, a column decoder 44, a row driver 43, a column driver 45, an input circuit 47, an output circuit 48, and a sense amplifier 46.

[0462] The row decoder 42 and the column decoder 44 have the function of decoding the signal ADDR. The row decoder 42 is a circuit for specifying a row to be accessed, and the column decoder 44 is a circuit for specifying a column to be accessed. The row driver 43 has the function of selecting the wiring WL specified by the row decoder 42. The column driver 45 has the following functions: a function of writing data to the memory cell 10; a function of reading data from the memory cell 10; a function of holding the read data, etc.

[0463] The input circuit 47 has a function of holding the signal WDA. The data held in the input circuit 47 is output to the column driver 45. The output data of the input circuit 47 is the data (Din) written to the memory cell 10. The data (Dout) read from the memory cell 10 by the column driver 45 is output to the output circuit 48. The output circuit 48 has a function of holding Dout. In addition, the output circuit 48 has a function of outputting Dout to the outside of the memory device 300. The data output from the output circuit 48 is the signal RDA.

[0464] PSW22 has a function of controlling the supply of VDD to the peripheral circuit 31. PSW23 has a function of controlling the supply of VHM to the row driver 43. Here, the high power supply voltage of the memory device 300 is VDD, and the low power supply voltage is GND (ground potential). In addition, VHM is a high power supply voltage for making the word line high level, which is higher than VDD. The on / off of PSW22 is controlled by the signal PON1, and the on / off of PSW23 is controlled by the signal PON2. Fig.18In the embodiment, the number of power domains to which VDD is supplied in the peripheral circuit 31 is one, but it may be more than one. In this case, a power switch may be provided for each power domain.

[0465] The memory array 20 includes memory arrays 20[1] to 20[m] (m is an integer greater than or equal to 2) and a functional layer 50. A plurality of layers of memory arrays 20 may be overlapped on the drive circuit 21. By overlapping a plurality of layers of memory arrays 20, the storage density of the memory cell 10 may be increased. Fig.19A 1 is a perspective view of a storage device 300 in which a functional layer 50 and five-layer (m=5) memory arrays 20 [ 1 ] to 20 [ 5 ] are stacked on a drive circuit 21 .

[0466] exist Fig.19A In the embodiment, the memory array 20 provided in the first layer is referred to as the memory array 20[1], the memory array 20 provided in the second layer is referred to as the memory array 20[2], and the memory array 20 provided in the fifth layer is referred to as the memory array 20[5]. Fig.19A The wiring WL, wiring PL, and wiring CL extending in the X direction and the wiring BL extending in the Z direction (a direction perpendicular to the substrate surface on which the driver circuit is provided) are shown. Note that in order to make the drawings easier to understand, description of a part of the wiring WL and wiring PL included in each of the memory arrays 20 is omitted.

[0467] Fig.19B Show instructions Fig.19A FIG. 1 is a schematic diagram of a structural example of a functional circuit 51 connected to the wiring BL and a memory cell 10 included in the memory array 20 [1] to 20 [5] connected to the wiring BL. Fig.19B The wiring GBL provided between the functional circuit 51 and the driving circuit 21 is shown. In addition, a structure that electrically connects one wiring BL to a plurality of memory cells (memory cells 10) is also referred to as a "memory string." Note that in the drawings, the wiring GBL is sometimes shown with a thick line for improved visibility.

[0468] Fig.19B An example of a circuit structure of a memory cell 10 connected to a wiring BL is shown. The memory cell 10 includes a transistor 11 and a capacitor 12. Regarding the transistor 11, the capacitor 12, and each wiring (wiring BL, wiring WL, etc.), for example, the wiring BL[1] and the wiring WL[1] are sometimes referred to as the wiring BL and the wiring WL, etc. Here, the transistor 11 corresponds to the transistor 200 described in Embodiment 1.

[0469] In the memory cell 10, one of the source and the drain of the transistor 11 is connected to the wiring BL. The other of the source and the drain of the transistor 11 is connected to one electrode of the capacitor 12. The other electrode of the capacitor 12 is connected to the wiring PL. The gate of the transistor 11 is connected to the wiring WL. The back gate of the transistor 11 is connected to the wiring CL.

[0470] Wiring PL is a wiring for supplying a constant potential for maintaining the potential of capacitor 12. Wiring CL is a wiring for supplying a constant potential for controlling the threshold voltage of transistor 11. Wiring PL and wiring CL may also be at the same potential. In this case, by connecting the two wirings, the number of wirings connected to memory cell 10 can be reduced.

[0471] Fig.19B The wiring GBL shown is provided so as to electrically connect the driving circuit 21 and the functional layer 50 . Fig. 20A FIG. 3 is a schematic diagram of a memory device 300 with a functional circuit 51 and memory arrays 20 [ 1 ] to 20 [ m ] as a repeating unit 70 . Fig. 20A One wiring GBL is shown in the figure, but the wiring GBL may be appropriately provided according to the number of functional circuits 51 in the functional layer 50 .

[0472] Furthermore, the wiring GBL is provided in such a manner as to be in contact with the semiconductor layer of the transistor included in the functional circuit 51. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as a source or a drain. Alternatively, the wiring GBL is provided in such a manner as to be in contact with a conductor that is in contact with a region of the semiconductor layer of the transistor included in the functional circuit 51 that functions as a source or a drain. That is, the wiring GBL can be said to be a wiring that electrically connects one of the source and the drain of the transistor included in the functional circuit 51 of the functional layer 50 to the drive circuit 21 in the vertical direction.

[0473] Alternatively, a structure may be provided in which a repeating unit 70 including a functional circuit 51 and memory arrays 20[1] to 20[m] is stacked. Fig. 20B The repeating units 70 [1] to 70 [p] (p is an integer greater than or equal to 2) may be included. The wiring GBL is connected to the functional layer 50 included in the repeating unit 70. The wiring GBL may be appropriately provided according to the number of the functional circuits 51.

[0474] In one embodiment of the present invention, while stacking OS transistors, wiring used as a bit line is arranged in a direction perpendicular to the substrate surface provided with the driver circuit 21. By providing wiring used as a bit line extending from the memory array 20 in a direction perpendicular to the substrate surface, the length of the wiring between the memory array 20 and the driver circuit 21 can be shortened. Therefore, the parasitic capacitance of the bit line can be greatly reduced.

[0475] In addition, one embodiment of the present invention includes a functional layer 50 in a layer provided with a memory array 20, and the functional layer 50 includes a functional circuit 51 having a function of amplifying the data potential held in the memory cell 10 and outputting it. By adopting this structure, a small potential difference of the wiring BL used as a bit line when reading data can be amplified to drive the sense amplifier 46 included in the drive circuit 21. Since the circuit such as the sense amplifier can be miniaturized, the memory device 300 can be miniaturized. In addition, even if the capacitance of the capacitor 12 included in the memory cell 10 is reduced, the memory device 300 can operate.

[0476] Note that, in the above, an example in which the memory cell 10 has a 1T (transistor) 1C (capacitor) type structure is shown, but the present invention is not limited to this. Fig.28A As shown, a 3T1C type memory cell can also be used for the memory device. Fig.28A The memory cell shown includes transistors 11a, 11b, 11c and a capacitor 12a. Here, the transistors 11a, 11b, 11c may have the same structure as the transistor 11, and the capacitor 12a may have the same structure as the capacitor 12. In addition, a RAM having the above structure is sometimes referred to as a NOSRAM (registered trademark) (Nonvolatile Oxide Semiconductor RAM: non-volatile oxide semiconductor RAM).

[0477] like Fig.28A As shown, one of the source and drain of transistor 11a is electrically connected to one electrode of capacitor 12a and the first gate of transistor 11b. In addition, one of the source and drain of transistor 11b is electrically connected to one of the source and drain of transistor 11c. In addition, wiring can be appropriately provided on the first gate, the other of the source and drain and the second gate of transistor 11a, the other of the source and drain and the second gate of transistor 11b, the first gate, the other of the source and drain and the second gate of transistor 11c, and the other electrode of capacitor 12a. In addition, the structure of the storage device can be appropriately deformed corresponding to the above wiring.

[0478] In addition, if Fig.28BAs shown, a 2T1C type memory cell may be used in which transistor 11a, 11b and capacitor 12a are provided instead of transistor 11c.

[0479] In addition, when the parasitic capacitance of transistor 11a and transistor 11b is sufficiently large, as shown in FIG. Fig.28C As shown, the capacitor 12a may not be provided. In this case, the memory cell is constituted by only the transistor 11a and the transistor 11b.

[0480] Note that, although a memory device having a stacked-layer memory array is described above, the present invention is not limited thereto. For example, a memory device including a single-layer memory array may be formed using the transistors according to the above embodiments.

[0481] [Configuration Example of Memory Array 20 and Functional Circuit 51]

[0482] Reference Fig.21 illustrate Fig.18 The configuration examples of the functional circuit 51 and the configuration examples of the sense amplifier 46 included in the memory array 20 and the driver circuit 21 described above are described in detail in FIG. 20 . Fig.21 The driving circuit 21 is shown, and the driving circuit 21 is connected to the wiring GBL (wiring GBL_A, wiring GBL_B), and the wiring GBL is connected to the functional circuit 51 (functional circuit 51_A, functional circuit 51_B), and the functional circuit 51 is connected to the memory cell 10 (memory cell 10_A, memory cell 10_B) connected to the different wiring BL (wiring BL_A, wiring BL_B). Fig.21 The driving circuit 21 shown in the figure shows a precharge circuit 71_A, a precharge circuit 71_B, a switch circuit 72_A, a switch circuit 72_B, and a write / read circuit 73 in addition to the sense amplifier 46 .

[0483] Transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are shown as the functional circuits 51_A and 51_B. Fig.21 The transistors 52_a, 52_b, 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b shown are OS transistors like the transistor 11 included in the memory cell 10. The functional layer 50 including the functional circuit 51 can be stacked like the memory arrays 20[1] to 20[m].

[0484] The wiring BL_A is connected to the gate of the transistor 52_a, and the wiring BL_B is connected to the gate of the transistor 52_b. The wiring GBL_A is connected to one of the source and drain of the transistors 53_a and 54_a. The wiring GBL_B is connected to one of the source and drain of the transistors 53_b and 54_b. Similar to the wiring BL_A and BL_B, the wiring GBL_A and GBL_B are arranged in the vertical direction and connected to the transistors included in the driving circuit 21. Fig.21 As shown, the gates of the transistors 53_a, 53_b, 54_a, 54_b, 55_a, and 55_b are supplied with the selection signal MUX, the control signal WE, or the control signal RE.

[0485] constitute Fig.21 The transistors 81_1 to 81_6 and 82_1 to 82_4 of the sense amplifier 46, the precharge circuit 71_A and the precharge circuit 71_B shown are composed of Si transistors. The switches 83_A to 83_D constituting the switch circuit 72_A and the switch circuit 72_B can also be composed of Si transistors. One of the source and drain of the transistors 53_a, 53_b, 54_a, and 54_b is connected to the transistor or switch constituting the precharge circuit 71_A, the precharge circuit 71_B, the sense amplifier 46, and the switch circuit 72_A.

[0486] Precharge circuit 71_A includes n-channel transistors 81_1 to 81_3 and precharges wiring BL_A and wiring BL_B to an intermediate potential VPC corresponding to VDD / 2 between high power supply potential (VDD) and low power supply potential (VSS) according to a precharge signal supplied to precharge line PCL1.

[0487] The precharge circuit 71_B includes n-channel transistors 81_4 to 81_6 and precharges the wirings GBL_A and GBL_B to an intermediate potential VPC corresponding to a potential VDD / 2 between VDD and VSS in accordance with a precharge signal supplied to the precharge line PCL2.

[0488] The sense amplifier 46 includes p-channel transistors 82_1 and 82_2 and n-channel transistors 82_3 and 82_4 connected to the wiring VHH or the wiring VLL. The wiring VHH or the wiring VLL is a wiring having a function of supplying VDD or VSS. The transistors 82_1 to 82_4 are transistors constituting an inverter loop. The potential of the wiring BL_A and the wiring BL_B precharged by selecting the memory cells 10_A and 10_B changes, and the potential of the wiring GBL_A and the wiring GBL_B is set to VDD or VSS according to the change. The potential of the wiring GBL_A and the wiring GBL_B can be output to the outside through the switch 83_C and the switch 83_D and the write-read circuit 73. The wiring BL_A and the wiring BL_B and the wiring GBL_A and the wiring GBL_B are equivalent to a bit line pair. The writing of the data signal of the write-read circuit 73 is controlled by the signal EN_data.

[0489] The switch circuit 72_A is a circuit for controlling the conduction state between the sense amplifier 46 and the wiring GBL_A and the wiring GBL_B. The switch circuit 72_A can be switched on or off by controlling the switching signal CSEL1. In the case where the switches 83_A and 83_B are n-channel transistors, they are turned on when the switching signal CSEL1 is at a high level, and are turned off when the switching signal CSEL1 is at a low level. The switch circuit 72_B is a circuit for controlling the conduction state between the write read circuit 73 and the bit line pair connected to the sense amplifier 46. The switch circuit 72_B can be switched on or off by controlling the switching signal CSEL2. The switches 83_C and 83_D can be the same as the switches 83_A and 83_B.

[0490] like Fig.21 As shown, the memory device 300 may have a structure in which the memory cell 10, the functional circuit 51, and the sense amplifier 46 are connected by the wiring BL and the wiring GBL arranged in the shortest vertical direction. Although the functional layer 50 including the transistor constituting the functional circuit 51 increases, the load of the wiring BL is reduced, so that the writing time can be shortened and the data can be easily read.

[0491] In addition, if Fig.21 As shown, each transistor included in the functional circuit 51_A, 51_B is controlled by the control signal WE, RE and the selection signal MUX. Each transistor can output the potential of the wiring BL to the driving circuit 21 through the wiring GBL according to the control signal and the selection signal. The functional circuits 51_A, 51_B can be used as a sense amplifier composed of OS transistors. By adopting this structure, a small potential difference of the wiring BL can be amplified during reading, and the sense amplifier 46 using Si transistors can be driven.

[0492] <Structure example of storage unit>

[0493] use Fig. 22 A configuration example of the storage unit 10 used in the above-mentioned storage device will be described.

[0494] Note that Fig. 22 In the figure, the X direction is parallel to the channel width direction of the transistor, the Y direction is perpendicular to the X direction, and the Z direction is perpendicular to the X direction and the Y direction.

[0495] like Fig. 22 As shown, the memory cell 10 includes a transistor 11 and a capacitor 12. An insulator 285 is provided on the transistor 11 and an insulator 284 is provided on the insulator 285. The insulator 285 and the insulator 284 can use an insulator that can be used as the insulator 216. In addition, the transistor 11 has the same structure as the transistor 200 shown in the above embodiment, and the same symbols are attached to the same components. For details of the transistor 200, refer to the above embodiment. In addition, the conductor 240 is provided in a manner of contacting one of the source and the drain of the transistor 11 (conductor 242a). The conductor 240 extends in the Z direction and is used as the wiring BL.

[0496] The capacitor 12 includes a conductor 153 on the conductor 242 b , an insulator 154 on the conductor 153 , and a conductor 160 (a conductor 160 a and a conductor 160 b ) on the insulator 154 .

[0497] At least a portion of each of the conductor 153, the insulator 154, and the conductor 160 is disposed inside the opening provided in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285. An end portion of each of the conductor 153, the insulator 154, and the conductor 160 is located at least on the insulator 282, preferably on the insulator 285. The insulator 154 is provided so as to cover the end portion of the conductor 153. Thus, the conductor 153 and the conductor 160 can be electrically insulated.

[0498] The deeper the depth of the openings provided in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 (that is, the thickness of one or more of the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283, and the insulator 285 is increased), the greater the electrostatic capacitance of the capacitor 12 can be. By increasing the electrostatic capacitance of the capacitor 12 per unit area, miniaturization or high integration of semiconductor devices can be achieved.

[0499] The conductor 153 has a region serving as one electrode (lower electrode) of the capacitor 12. The insulator 154 has a region serving as a dielectric of the capacitor 12. The conductor 160 has a region serving as the other electrode (upper electrode) of the capacitor 12. The capacitor 12 forms a MIM (Metal-Insulator-Metal) capacitor.

[0500] The conductor 242 b provided on the oxide 230 so as to overlap with the oxide 230 is used as a wiring electrically connected to the conductor 153 of the capacitor 12 .

[0501] The conductor 153 and the conductor 160 included in the capacitor 12 can be formed using various conductors that can be used for the conductor 205 or the conductor 260. The conductor 153 and the conductor 160 are preferably deposited using a deposition method with high coverage such as an ALD method or a CVD method. For example, titanium nitride or tantalum nitride deposited using an ALD method or a CVD method can be used as the conductor 153.

[0502] The bottom surface of the conductor 153 is in contact with the top surface of the conductor 242b2. Here, by using a conductive material with good conductivity as the conductor 242b2, the contact resistance between the conductor 153 and the conductor 242b can be reduced.

[0503] Alternatively, titanium nitride deposited by ALD or CVD may be used as conductor 160a, and tungsten deposited by CVD may be used as conductor 160b. Here, when the adhesion of tungsten to insulator 154 is sufficiently high, a single layer structure of tungsten deposited by CVD may be used as conductor 160.

[0504] A high-k material (a material with a high relative dielectric constant) is preferably used for the insulator 154 in the capacitor 12. The insulator 154 is preferably deposited by a deposition method with high coverage, such as ALD or CVD.

[0505] As insulators of high dielectric constant (high-k) materials, for example, oxides, oxynitrides, oxynitrides and nitrides containing one or more metal elements selected from aluminum, hafnium, zirconium and gallium can be cited. In addition, the above oxides, oxynitrides, nitride oxides or nitrides can also contain silicon. Insulators composed of the above materials can also be used in a stacked manner.

[0506] For example, as an insulator of a high dielectric constant (high-k) material, aluminum oxide, hafnium oxide, zirconium oxide, an oxide containing aluminum and hafnium, an oxynitride containing aluminum and hafnium, an oxide containing silicon and hafnium, an oxynitride containing silicon and hafnium, an oxide containing silicon and zirconium, an oxynitride containing silicon and zirconium, an oxide containing hafnium and zirconium, and an oxynitride containing hafnium and zirconium. By using such a high-k material, the insulator 154 can be thickened to a degree that can suppress leakage current, and the electrostatic capacitance of the capacitor 12 can also be sufficiently ensured.

[0507] In addition, it is preferred that the insulator composed of the above-mentioned materials is used in a laminated manner, and it is preferred to use a laminated structure of a material having a dielectric strength greater than that of a high dielectric constant (high-k) material. For example, as an insulator 154, an insulator stacked in the order of zirconium oxide, aluminum oxide, and zirconium oxide can be used. In addition, for example, an insulator stacked in the order of zirconium oxide, aluminum oxide, zirconium oxide, and aluminum oxide can be used. In addition, for example, an insulator stacked in the order of hafnium zirconium oxide, aluminum oxide, hafnium zirconium oxide, and aluminum oxide can be used. By using an insulator having a relatively large dielectric strength such as aluminum oxide in a laminated manner, the dielectric strength is improved, and therefore the electrostatic destruction of the capacitor 12 can be suppressed.

[0508] The deeper the depth of the openings provided in the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283 and the insulator 285 (that is, the thickness of one or more of the insulator 271b, the insulator 275, the insulator 280, the insulator 282, the insulator 283 and the insulator 285 becomes larger), the greater the electrostatic capacitance of the capacitor 12 can be. Here, since the insulator 271b, the insulator 275, the insulator 282 and the insulator 283 are used as blocking insulators, it is preferred to set the thickness according to the blocking property required for the semiconductor device. In addition, since the thickness of the conductor 260 used as the gate electrode is determined according to the thickness of the insulator 280, the thickness of the insulator 280 is preferably set according to the thickness of the conductor 260 required for the semiconductor device.

[0509] Therefore, it is preferred that the electrostatic capacitance of the capacitor element 12 is set by adjusting the thickness of the insulator 285. For example, the thickness of the insulator 285 is set within a range of more than 50nm and less than 250nm, and the depth of the above-mentioned opening is about more than 150nm and less than 350nm. By forming the capacitor element 12 within the above-mentioned range, the capacitor element 12 has sufficient electrostatic capacitance, and in a semiconductor device with a layer of stacked multiple memory cells, the height of one layer can be prevented from being excessively increased. In each of the layers of multiple memory cells, the electrostatic capacitance of the capacitor element arranged in each memory cell can be made different. When adopting this structure, for example, the thickness of the insulator 285 arranged in the layer of each memory cell can be made different.

[0510] In the opening portion provided in the insulator 285 etc. where the capacitor element 12 is arranged, the side wall of the opening portion may be vertical or substantially vertical to the top surface of the insulator 222, or may have a tapered shape. When the side wall has a tapered shape, the coverage of the conductor 153 etc. provided in the opening portion of the insulator 285 etc. can be improved, thereby reducing defects such as voids.

[0511] The conductor 242a provided on the oxide 230 so as to overlap with the oxide 230 is used as a wiring electrically connected to the conductor 240. For example, in Fig. 22 In the embodiment, the top surface and the side end of the conductor 242a are electrically connected to the conductor 240 extending in the Z direction. Fig. 22 In the embodiment, the top surface and side ends of the conductor 242a2 and the side ends of the conductor 242a1 are in contact with the conductor 240.

[0512] When the conductor 240 is in direct contact with at least one of the top surface and the side end of the conductor 242a, there is no need to set up an electrode for connection, so the area occupied by the memory array can be reduced. In addition, the integration of the memory cell is improved, and the storage capacity of the memory device can be increased. In addition, the conductor 240 is preferably in contact with a portion of the top surface and the side end of the conductor 242a. By having the conductor 240 contact multiple surfaces of the conductor 242a, the contact resistance between the conductor 240 and the conductor 242a can be reduced. In particular, if Fig. 22 As shown, when the conductor 240 contacts a part of the top surface and the side end of the conductor 242a2 having high conductivity, the contact resistance between the conductor 240 and the conductor 242a can be further reduced.

[0513] The conductor 240 is disposed in the openings formed in the insulator 216 , the insulator 221 , the insulator 222 , the insulator 275 , the insulator 280 , the insulator 282 , the insulator 283 , the insulator 285 , and the insulator 284 .

[0514] The conductor 240 preferably has a laminated structure of a conductor 240a and a conductor 240b. Fig. 22 As shown in FIG. 1 , the conductor 240 may have a structure in which the conductor 240a is provided in contact with the inner wall of the opening and the conductor 240b is provided inside the conductor 240a. That is, the conductor 240a is arranged near the insulator 216, the insulator 221, the insulator 222, the insulator 275, the insulator 280, the insulator 282, the insulator 283, the insulator 285, and the insulator 284, compared with the conductor 240b. In addition, the conductor 240a is in contact with the top surface and the side end of the conductor 242a.

[0515] As the conductor 240a, it is preferable to use a conductive material having a function of inhibiting the penetration of impurities such as water and hydrogen. The conductor 240a may have a single-layer structure or a stacked-layer structure using, for example, one or more of tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, and ruthenium oxide. Thus, impurities such as water and hydrogen can be inhibited from mixing into the oxide 230 through the conductor 240.

[0516] In addition, since the conductor 240 is also used as wiring, it is preferable to use a conductor with high conductivity. For example, a conductive material mainly composed of tungsten, copper, or aluminum can be used for the conductor 240b.

[0517] For example, it is preferable to use titanium nitride as the conductor 240a and to use tungsten as the conductor 240b. In this case, the conductor 240a is a conductor containing titanium and nitrogen, and the conductor 240b is a conductor containing tungsten.

[0518] Furthermore, the conductor 240 may have a single-layer structure or a stacked-layer structure of three or more layers.

[0519] In addition, if Fig. 22 As shown, it is preferable to provide the insulator 241 in contact with the side surface of the conductor 240. Specifically, the insulator 241 is provided in contact with the inner wall of the openings of the insulator 216, the insulator 221, the insulator 222, the insulator 275, the insulator 280, the insulator 282, the insulator 283, the insulator 285, and the insulator 284. In addition, the insulator 241 is also formed on the side surfaces of the insulator 224, the oxide 230, and the conductor 242a formed to protrude in the opening. Here, at least a portion of the conductor 242a is exposed from the insulator 241 and is in contact with the conductor 240. That is, the conductor 240 is provided in a manner embedded in the inside of the above-mentioned opening via the insulator 241.

[0520] like Fig. 22As shown in FIG. 1 , the uppermost portion of the insulator 241 formed below the conductor 242a is preferably located below the top surface of the conductor 242a. By adopting this structure, the conductor 240 can be in contact with at least a portion of the side end portion of the conductor 242a. In addition, the insulator 241 formed below the conductor 242a preferably includes a region in contact with the side surface of the oxide 230. By adopting this structure, impurities such as water and hydrogen contained in the insulator 280 and the like can be suppressed from mixing into the oxide 230 through the conductor 240.

[0521] As the insulator 241, a blocking insulating film that can be used for the insulator 275 or the like can be used. For example, an insulator such as silicon nitride, aluminum oxide, or silicon oxynitride can be used for the insulator 241. By adopting this structure, it is possible to suppress impurities such as water and hydrogen contained in the insulator 280 or the like from being mixed into the oxide 230 through the conductor 240. In particular, silicon nitride is preferred because it has a high barrier property against hydrogen. In addition, it is possible to suppress the absorption of oxygen contained in the insulator 280 by the conductor 240.

[0522] Fig. 22 The insulator 241 is shown as a single-layer structure, but the present invention is not limited thereto. The insulator 241 may also have a stacked structure of two or more layers.

[0523] When the insulator 241 has a two-layer stacked structure, the first layer of the inner wall of the opening in contact with the insulator 280 or the like may be an oxygen blocking insulating film and the second layer inside thereof may be a hydrogen blocking insulating film. For example, aluminum oxide deposited by the ALD method may be used as the first layer and silicon nitride deposited by the PEALD method may be used as the second layer. By adopting this structure, oxidation of the conductor 240 can be suppressed, and mixing of hydrogen from the conductor 240 into the oxide 230 or the like can be reduced. Thus, the electrical characteristics and reliability of the transistor 11 can be improved.

[0524] In the opening where the conductor 240 and the insulator 241 are arranged, the side wall of the opening may be perpendicular or substantially perpendicular to the top surface of the insulator 222, or may be tapered. The tapered side wall improves the coverage of the insulator 241 and the like provided in the opening.

[0525] <Configuration Example of Storage Device 300>

[0526] use Fig.23 A configuration example of the above-mentioned storage device 300 will be described.

[0527] The memory device 300 includes: a driver circuit 21 including a layer of transistors 310 and the like; a functional layer 50 including a layer of transistors 52, 53, 54, 55 and the like on the driver circuit 21; and a memory array 20[1] to 20[m] ( Fig.23Only memory arrays 20[1] and 20[2] are shown. Transistor 52 corresponds to the above-mentioned transistors 52_a and 52_b, transistor 53 corresponds to the above-mentioned transistors 53_a and 53_b, transistor 54 corresponds to the above-mentioned transistors 54_a and 54_b, and transistor 55 corresponds to the above-mentioned transistors 55_a and 55_b.

[0528] Fig.23 2 shows a transistor 310 included in the driving circuit 21. The transistor 310 is provided on a substrate 311 and includes a conductor 316 used as a gate, an insulator 315 used as a gate insulator, a semiconductor region 313 including a portion of the substrate 311, and a low resistance region 314a and a low resistance region 314b used as a source region or a drain region. The transistor 310 may be a p-channel transistor or an n-channel transistor. As the substrate 311, for example, a single crystal silicon substrate may be used.

[0529] Here, in Fig.23 In the transistor 310 shown, the semiconductor region 313 (a part of the substrate 311) forming the channel has a convex shape. In addition, a conductor 316 is provided in a manner that covers the side and top surfaces of the semiconductor region 313 via an insulator 315. In addition, the conductor 316 can use a material that adjusts the work function. Because the convex portion of the semiconductor substrate is utilized, this transistor 310 is also referred to as a FIN-type transistor. In addition, an insulator having a mask for forming a convex portion in a manner that contacts the upper portion of the convex portion may also be provided. In addition, although a portion of the semiconductor substrate is shown here to be processed to form a convex portion, an SOI substrate may also be processed to form a semiconductor film having a convex shape.

[0530] Notice, Fig.23 The structure of the transistor 310 shown is just an example and is not limited to the above structure, and an appropriate transistor can be used according to the circuit structure or driving method.

[0531] A wiring layer including an interlayer film, wiring, and plugs may be provided between the structures. In addition, the wiring layer may be provided in a plurality of layers according to the design. In addition, in this specification, wiring and a plug electrically connected to the wiring may also be one component. That is, a part of the conductor may be used as wiring, and a part of the conductor may be used as a plug.

[0532] For example, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are sequentially stacked as interlayer films on the transistor 310. In addition, a conductor 328 and the like are embedded in the insulator 320 and the insulator 322. In addition, a conductor 330 and the like are embedded in the insulator 324 and the insulator 326. In addition, the conductor 328 and the conductor 330 are used as contact plugs or wirings.

[0533] Furthermore, the insulator used as an interlayer film may also be used as a planarization film to cover the concavo-convex shape thereunder. For example, in order to improve the flatness of the top surface of the insulator 322, planarization may be achieved by a planarization process such as chemical mechanical polishing (CMP).

[0534] also, Fig.23 Transistors 52, 53, and 55 are shown in the functional layer 50. The transistors 52, 53, and 55 have the same structure as the transistor 11 in the memory cell 10. The sources and drains of the transistors 52, 53, and 55 are connected in series.

[0535] An insulator 208 is provided on transistors 52, 53, and 55, and a conductor 207 is provided in an opening formed in the insulator 208. Furthermore, an insulator 210 is provided on the insulator 208, and a conductor 209 is provided in an opening formed in the insulator 210. Furthermore, an insulator 212 is provided on the insulator 210, and an insulator 214 is provided on the insulator 212. A portion of the conductor 240 provided in the memory array 20[1] is embedded in the openings formed in the insulators 212 and 214. Here, an insulator that can be used as the insulator 216 can be used as the insulator 208 and the insulator 210. In addition, an insulator that can be used as the insulator 283 can be used as the insulator 212. In addition, an insulator that can be used as the insulator 282 can be used as the insulator 214.

[0536] The bottom surface of the conductor 207 is provided in contact with the top surface of the conductor 260 of the transistor 52. In addition, the top surface of the conductor 207 is provided in contact with the bottom surface of the conductor 209. In addition, the top surface of the conductor 209 is in contact with the bottom surface of the conductor 240 provided in the memory array 20[1]. By adopting this structure, the conductor 240 corresponding to the wiring BL can be electrically connected to the gate of the transistor 52.

[0537] Each of the memory arrays 20[1] to 20[m] includes a plurality of memory cells 10. The conductor 240 included in each memory cell 10 is electrically connected to the conductor 240 of the upper layer and the conductor 240 of the lower layer.

[0538] like Fig.23 As shown, the adjacent memory cells 10 share the conductor 240. In addition, in the adjacent memory cells 10, the structure on the right and the structure on the left are arranged symmetrically with the conductor 240 as the boundary.

[0539] Here, the conductor 160 used as the upper electrode of the capacitor element 12 of the lower layer (e.g., the layer of the memory array 20[1]) and the conductor 261 used as the second gate electrode of the transistor 11 of the upper layer (e.g., the layer of the memory array 20[2]) can be formed in the same layer. In other words, the conductor 160 of the capacitor element 12 of the lower layer and the conductor 261 of the transistor 11 of the upper layer are formed in a manner embedded in an opening formed in the same insulator 216. The conductor 160 of the capacitor element 12 of the lower layer and the conductor 261 of the transistor 11 of the upper layer are formed by processing a conductive film, and have the above structure. At this time, the conductor 160 of the capacitor element 12 of the lower layer contains the same material as the conductor 261 of the transistor 11 of the upper layer.

[0540] As described above, by forming the conductor 160 of the lower capacitor 12 and the conductor 261 of the upper transistor 11 at the same time, the manufacturing process of the memory device according to this embodiment can be shortened, thereby improving the productivity of the memory device.

[0541] In the memory array 20, a plurality of memory arrays 20[1] to 20[m] may be stacked. By arranging the memory arrays 20[1] to 20[m] included in the memory array 20 in a direction perpendicular to the substrate surface on which the drive circuit 21 is disposed, the storage density of the memory cell 10 may be increased. In addition, the memory array 20 may be manufactured repeatedly using the same manufacturing process in the vertical direction. The memory device 300 may reduce the manufacturing cost of the memory array 20.

[0542] In addition, the above shows a structure in which the drive circuit 21, the functional layer 50 and the memory array 20 are sequentially stacked on the substrate 311, that is, a monolithic structure, but the present invention is not limited to this. By bonding multiple chips, a stacked structure of the drive circuit 21, the functional layer 50 and the memory array 20 can also be formed.

[0543] For example, Fig.24 As shown, a chip 60 including the driving circuit 21 and the functional layer 50 and a chip 61 including the memory array 20 may be bonded together to form a storage device.

[0544] Chip 60 has Fig.23 The drive circuit 21 and the functional layer 50 of the memory device shown in the figure have substantially the same structure. In the chip 60, an insulator 346 is provided on the upper part of the functional layer 50, and an insulator 336 is provided on the insulator 346. The conductor 341 is provided in the insulator 336, and a part of the conductor 225 is provided in the insulator 346. The insulator 346 is an insulator used as a blocking insulator, and can suppress the diffusion of impurities into the oxide semiconductor of the functional layer 50 and the substrate 311. As the insulator 346, an inorganic insulating film that can be used for the insulator 283 or the like can be used.

[0545] In addition, in the chip 60, a wiring layer 25 is shown between the driving circuit 21 and the functional layer 50. In the wiring layer 25, a conductor 228 used as wiring is embedded in the interlayer film. In addition, a conductor used as a contact plug is also provided in the wiring layer 25. Note that although Fig.24 The wiring layer 25 shown in the figure shows only one layer of the conductor 228, but the present invention is not limited thereto, and the conductor used as the wiring may be divided into a plurality of layers and stacked. In other words, the wiring layer 25 may be a multi-layer wiring.

[0546] In addition, the conductor 225, the conductor 226, the conductor 207, and the conductor 227 are embedded in the interlayer film of the functional layer 50. Here, the conductor 226 is used as a wiring, and the conductor 225, the conductor 207, and the conductor 227 are used as a contact plug. The conductor 225, the conductor 226, and the conductor 207 electrically connect the conductor 341 to the gate of the transistor 52. In addition, the conductor 226 and the conductor 227 electrically connect one of the source and the drain of the transistor 55 to the conductor 228 of the wiring layer 25.

[0547] The chip 61 has a substrate 351 provided on the Fig.23 The structure of the memory array 20 shown in FIG. 3 is a diagram. An insulator 345 is provided on the back surface of the substrate 351, and an insulator 335 is provided under the insulator 345. A conductor 342 is provided in the insulator 335. Here, the insulator 345 is an insulator used as a blocking insulator, and can suppress the diffusion of impurities into the substrate 351. As the insulator 345, an inorganic insulating film that can be used for the insulator 283 or the like can be used. In addition, as the substrate 351, a substrate similar to the substrate 311 can be used, for example, a single crystal silicon substrate can be used.

[0548] The substrate 351 is provided with a conductor 343 that passes through the substrate 351 and the insulator 345. The conductor 343 is a TSV (Through Silicon Via) that passes through the silicon substrate, and its upper end is in contact with the conductor 209, and its lower end is in contact with the conductor 342. Here, it is preferable to provide an insulator 344 to cover the side of the conductor 343. The insulator 344 is an insulating layer used as a blocking insulator, and can suppress the diffusion of impurities into the substrate 351. As the insulator 344, an inorganic insulating film that can be used for the insulator 241 can be used.

[0549] like Fig.24 As shown, the insulator 336 and the conductor 341 of the chip 60 are bonded to the insulator 335 and the conductor 342 of the chip 61 on the bonding surface B. Here, hybrid bonding is formed on the bonding surface B, in which the conductor 341 is in contact with the conductor 342, and the insulator 336 is in contact with the insulator 335.

[0550] Here, the main components of the conductor 341 and the conductor 342 are preferably the same metal element. In addition, the insulator 336 and the insulator 335 are preferably composed of the same component.

[0551] For example, Cu, Al, Sn, Zn, W, Ag, Pt, or Au can be used as the conductor 341 and the conductor 342. From the viewpoint of ease of bonding, Cu, Al, W, or Au is preferably used. In addition, a metal nitride containing the above metal element as a component may be formed on at least a portion of the conductor 341 and the conductor 342.

[0552] For example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon nitride, titanium nitride, or the like can be used for the insulator 336 and the insulator 335. Alternatively, a polymer material such as polyimide can be used for the insulator 336 and the insulator 335.

[0553] That is, it is preferable that the same metal material as the above-mentioned metal material is used as both the conductor 341 and the conductor 342. In addition, it is preferable that the same insulating material as the above-mentioned insulating material is used as both the insulator 336 and the insulator 335. By adopting this structure, the chip 60 and the chip 61 can be bonded with the boundary between them as the bonding surface B.

[0554] In addition, the conductors 341 and 342 may also have a multilayer structure with multiple layers, in which case the surface layer (joining surface) may be made of the same metal material. In addition, the insulators 336 and 335 may also have a multilayer structure with multiple layers, in which case the surface layer (joining surface) may be made of the same insulating material.

[0555] By performing this bonding, the conductor 341 and the conductor 342 can be electrically connected. In addition, the insulator 336 and the insulator 335 can be connected so as to have mechanical strength.

[0556] When the conductors are bonded to each other, a surface activation bonding method can be used, in which the oxide film and impurity adsorption layer on the surface are removed by sputtering treatment, etc., and the cleaned and activated surfaces are brought into contact for bonding. Alternatively, a diffusion bonding method that uses temperature and pressure to bond the surfaces can be used. The above methods can all produce atomic-level bonding, so excellent bonding can be obtained both electrically and mechanically.

[0557] In addition, when insulators are bonded to each other, a hydrophilic bonding method can be used, in which surfaces treated with hydrophilicity by oxygen plasma or the like are brought into contact for temporary bonding, and then dehydrated by heat treatment to achieve formal bonding. The hydrophilic bonding method also produces atomic-level bonding, so that mechanically excellent bonding can be obtained.

[0558] When the chip 60 and the chip 61 are bonded together, since the insulating layer and the metal layer are mixed at each bonding surface, for example, a surface activation bonding method and a hydrophilic bonding method may be combined.

[0559] For example, a method of bonding can be adopted in which the surface is cleaned, the surface of the conductor is subjected to an anti-oxidation treatment, and then a hydrophilic treatment is performed. In addition, a difficultly oxidizable metal such as Au can be used as the surface of the conductor and a hydrophilic treatment can be performed. In addition, bonding methods other than the above methods can also be used.

[0560] Through the above bonding, the memory array 20 included in the chip 61 and the functional layer 50 and the driving circuit 21 included in the chip 60 can be electrically connected.

[0561] In addition, Fig.24 In the memory device shown in FIG. 1 , an example is shown in which a plurality of transistor layers have a monolithic structure in each of the chips 60 and 61 , but the present invention is not limited thereto. Fig.25 As shown, a driving circuit 21 including a transistor 310 may be provided in the chip 60, and a memory array 20[1] including a transistor 11 may be provided in the chip 61.

[0562] Fig.25 The chip 60 shown is Fig.24 The chip 60 shown differs in that the chip 60 does not include the functional layer 50. Fig.25 In the illustrated chip 60 , an insulator 336 , an insulator 346 , a conductor 341 , a conductor 225 , a conductor 226 , and a conductor 207 are provided in the wiring layer 25 .

[0563] exist Fig.25 In the chip 61 shown, the memory array 20[1] is provided on the substrate 351. An insulator 345, an insulator 335 and a conductor 342 are provided on the back side of the substrate 351. A conductor 343 and an insulator 344 are provided so as to penetrate the substrate 351 and the insulator 345.

[0564] exist Fig.25 In the chip 60 and the chip 61 shown, the structure near the bonding surface B is similar to Fig.24 Thus, the chip 60 and the chip 61 can be bonded together, and the memory array 20 and the drive circuit 21 can be electrically connected.

[0565] In addition, by utilizing the above-mentioned lamination technology, multiple Fig.23 The storage device shown.

[0566] For example, Fig.26 As shown, it is also possible to Fig.23A chip 61 including a functional layer 50 and a memory array 20 is stacked on a chip 60 having the same structure as the memory device shown.

[0567] exist Fig.26 In the chip 60 shown in FIG. 1 , an insulator 346, an insulator 336, and a conductor 341 are provided on the memory array 20. In addition, wiring and contact plugs are provided to electrically connect the conductor 341 to the transistors of the functional layer 50 and the transistors of the drive circuit 21. Fig.26 Although not shown in the figure, a wiring layer may be provided between the driving circuit 21 and the functional layer 50 .

[0568] exist Fig.26 In the chip 61 shown, a functional layer 50 is provided on a substrate 351. An insulator 345, an insulator 335, and a conductor 342 are provided on the back side of the substrate 351. A conductor 343 and an insulator 344 are provided so as to pass through the substrate 351 and the insulator 345. In addition, wiring and contact plugs are provided to electrically connect the conductor 343 to the transistor of the functional layer 50.

[0569] exist Fig.26 In the chip 60 and the chip 61 shown, the structure near the bonding surface B is similar to Fig.24 Thus, the chip 60 and the chip 61 can be bonded together, and the functional layer 50 of the chip 61 and the functional layer 50 of the chip 60 can be electrically connected to the drive circuit 21 .

[0570] in addition, Fig.26 The storage device shown has a so-called Face to Back structure in which the top surface of the chip 60 and the bottom surface of the chip 61 are attached to each other, but the present invention is not limited to this. Fig. 27 As shown, a so-called face-to-face structure in which the top surface of the chip 60 and the top surface of the chip 61 are bonded together may be adopted.

[0571] exist Fig. 27 In the chip 61 shown, a functional layer 50 is provided on a substrate 351 with reference to the substrate 351. An insulator 345, an insulator 335 and a conductor 342 are provided on the memory array 20 side. In addition, wiring and contact plugs are provided to electrically connect the conductor 342 and the transistors of the functional layer 50.

[0572] exist Fig. 27 In the memory device shown, since a silicon substrate is not provided near the bonding surface B, it is not necessary to provide a conductor used as a TSV.

[0573] This embodiment mode can be combined with other embodiment modes as appropriate.

[0574] (Implementation 4)

[0575] In this embodiment, an example of a chip on which a storage device according to one embodiment of the present invention is mounted is described with reference to FIG. 29 .

[0576] exist Fig.29A and Fig.29B A plurality of circuits (systems) are mounted on the illustrated chip 1200. The technology of integrating a plurality of circuits (systems) on one chip is sometimes referred to as a system on chip (SoC).

[0577] like Fig.29A As shown, the chip 1200 includes a CPU 1211, a GPU 1212, one or more simulation operation units 1213, one or more storage controllers 1214, one or more interfaces 1215, one or more network circuits 1216, and the like.

[0578] Chip 1200 is provided with bumps (not shown). Fig.29B As shown in FIG. 1 , the first surface of the package substrate 1201 is connected to the first surface of the package substrate 1201 . In addition, a plurality of bumps 1202 are provided on the back side of the first surface of the package substrate 1201 , and the bumps 1202 are connected to the motherboard 1203 .

[0579] In addition, a storage device such as DRAM 1221 and flash memory 1222 may be provided on the motherboard 1203. For example, the DOS RAM described in the above embodiment may be used for DRAM 1221. Thus, the DRAM 1221 can have low power consumption, high speed, and large capacity.

[0580] The CPU 1211 preferably has a plurality of CPU cores. In addition, the GPU 1212 preferably has a plurality of GPU cores. In addition, the CPU 1211 and the GPU 1212 may each have a memory for temporarily storing data. Alternatively, a memory commonly used by the CPU 1211 and the GPU 1212 may be provided on the chip 1200. The above-mentioned DOSRAM may be used for the memory. In addition, the GPU 1212 is suitable for parallel calculation of a plurality of data, which may be used for image processing or product-sum operations. By providing an image processing circuit or product-sum operation circuit using the OS transistor shown in the above-mentioned embodiment as the GPU 1212, image processing or product-sum operations may be performed with low power consumption.

[0581] In addition, since CPU1211 and GPU1212 are provided on the same chip, the wiring between CPU1211 and GPU1212 can be shortened, and data can be transferred from CPU1211 to GPU1212, data can be transferred between memories possessed by CPU1211 and GPU1212, and calculation results can be transferred from GPU1212 to CPU1211 after calculations in GPU1212 are completed at high speed.

[0582] The analog operation unit 1213 includes one or both of an A / D (analog / digital) conversion circuit and a D / A (digital / analog) conversion circuit. In addition, the analog operation unit 1213 may also include the above-mentioned product-sum operation circuit.

[0583] The memory controller 1214 has a circuit that functions as a controller of the DRAM 1221 and a circuit that functions as an interface of the flash memory 1222 .

[0584] The interface 1215 has an interface circuit with external connection devices such as a display device, a speaker, a microphone, a camera, a controller, etc. The controller includes a mouse, a keyboard, a game console controller, etc. As the above-mentioned interface, USB (Universal Serial Bus), HDMI (High-Definition Multimedia Interface) (registered trademark), etc. can be used.

[0585] The network circuit 1216 includes a network circuit such as a LAN (Local Area Network) and may also include a network security circuit.

[0586] The above circuits (systems) can be formed on the chip 1200 through the same manufacturing process. Therefore, even if the number of circuits required for the chip 1200 increases, there is no need to increase the manufacturing process, and the chip 1200 can be manufactured at a low cost.

[0587] The motherboard 1203 including the package substrate 1201 provided with the chip 1200 having the GPU 1212 , the DRAM 1221 , and the flash memory 1222 may be referred to as a GPU module 1204 .

[0588] The GPU module 1204 can reduce its size due to having the chip 1200 using SoC technology. In addition, the GPU module 1204 is suitable for portable electronic devices such as smartphones, tablet terminals, laptop personal computers, and portable (portable) game consoles due to its high image processing capabilities. In addition, by utilizing the product-sum operation circuit using the GPU 1212, methods such as deep neural networks (DNN), convolutional neural networks (CNN), recurrent neural networks (RNN), autoencoders, deep Boltzmann machines (DBM), and deep belief networks (DBN) can be performed, thereby using the chip 1200 as an AI chip, or the GPU module 1204 can be used as an AI system module.

[0589] This embodiment mode can be combined with other embodiment modes as appropriate.

[0590] (Implementation method 5)

[0591] In this embodiment, electronic components, electronic devices, mainframe computers, space equipment, and data centers (also referred to as DC) that can use the semiconductor device described in the above embodiment are described. Electronic components, electronic devices, mainframe computers, space equipment, and data centers that use a semiconductor device in one embodiment of the present invention are effective in achieving high performance such as low power consumption.

[0592] [Electronic components]

[0593] Fig. 30A A perspective view of a substrate (circuit board 704 ) on which an electronic component 700 is mounted is shown. Fig. 30A The electronic component 700 shown includes a semiconductor device 710 within a mold 711. Fig. 30A 700 is partially omitted to show the inside thereof. The electronic component 700 includes a land 712 on the outside of the mold 711. The land 712 is electrically connected to the electrode pad 713, and the electrode pad 713 is electrically connected to the semiconductor device 710 through the lead 714. The electronic component 700 is mounted on, for example, a printed circuit board 702. By combining a plurality of these electronic components and electrically connecting them on the printed circuit board 702, a circuit board 704 is completed.

[0594] In addition, the semiconductor device 710 includes a driving circuit layer 715 and a storage layer 716. The storage layer 716 has a structure in which a plurality of memory cell arrays are stacked. The structure in which the driving circuit layer 715 and the storage layer 716 are stacked can adopt a monolithic stacked structure. In the monolithic stacked structure, it is possible to connect the layers without using through-electrode technologies such as TSV (Through Silicon Via) and bonding technologies such as Cu-Cu direct bonding. When the driving circuit layer 715 and the storage layer 716 are stacked in a monolithic manner, for example, a so-called on-chip memory structure in which a memory is directly formed on a processor can be realized. By adopting the on-chip memory structure, high-speed operation of the interface portion between the processor and the memory can be achieved.

[0595] In addition, by adopting an on-chip memory structure, the size of the connection wiring can be reduced compared to the technology using through-electrodes such as TSV, so the number of pins can be increased. By increasing the number of pins, parallel operation can be performed, thereby increasing the bandwidth of the memory (also called memory bandwidth).

[0596] In addition, it is preferred that multiple memory cell arrays in the storage layer 716 are formed using OS transistors, and the multiple memory cell arrays are stacked in a monolithic manner. When multiple memory cell arrays are stacked in a monolithic manner, either or both of the bandwidth of the memory and the access delay of the memory can be improved. Bandwidth refers to the amount of data transmitted per unit time, and access delay refers to the time between access and the start of data exchange. When Si transistors are used in the storage layer 716, it is more difficult to implement a monolithic stacked structure compared to OS transistors. Therefore, in a monolithic stacked structure, OS transistors are superior to Si transistors.

[0597] In addition, the semiconductor device 710 may be referred to as a bare chip. In this specification, etc., a bare chip refers to a chip obtained by forming a circuit pattern on a disc-shaped substrate (also called a wafer) in the manufacturing process of a semiconductor chip, for example, and cutting it into rectangular small pieces. As semiconductor materials that can be used for bare chips, for example, silicon (Si), silicon carbide (SiC) or gallium nitride (GaN) can be cited. For example, a bare chip obtained from a silicon substrate (also called a silicon wafer) is sometimes called a silicon chip.

[0598] then, Fig. 30B The electronic component 730 is a perspective view. The electronic component 730 is an example of a SiP (System in Package) or an MCM (Multi Chip Module). In the electronic component 730, an interposer 731 is provided on a package substrate 732 (printed circuit board), and a semiconductor device 735 and a plurality of semiconductor devices 710 are provided on the interposer 731.

[0599] The electronic component 730 shows an example of using the semiconductor device 710 as a high bandwidth memory (HBM). In addition, the semiconductor device 735 can be used in an integrated circuit such as a CPU (Central Processing Unit), a GPU (Graphics Processing Unit), or an FPGA (Field Programmable Gate Array).

[0600] The package substrate 732 may be, for example, a ceramic substrate, a plastic substrate, or a glass epoxy substrate. The interposer 731 may be, for example, a silicon interposer or a resin interposer.

[0601] The interposer 731 has a plurality of wirings and has the function of electrically connecting a plurality of integrated circuits with different terminal spacings. The plurality of wirings are composed of a single layer or a plurality of layers. In addition, the interposer 731 has the function of electrically connecting the integrated circuit disposed on the interposer 731 to the electrode disposed on the package substrate 732. Therefore, the interposer is sometimes also referred to as a "rewiring substrate" or "intermediate substrate". In addition, sometimes a through electrode is provided in the interposer 731, and the integrated circuit is electrically connected to the package substrate 732 through the through electrode. In addition, in the case of using a silicon interposer, TSV can also be used as a through electrode.

[0602] In HBM, many wirings need to be connected to achieve a wide memory bandwidth. For this reason, it is required that fine wirings can be formed at a high density on the interposer on which the HBM is mounted. Therefore, a silicon interposer is preferably used as the interposer on which the HBM is mounted.

[0603] In addition, in SiP and MCM using silicon interposers, the reliability degradation caused by the difference in expansion coefficient between the integrated circuit and the interposer is not easy to occur. In addition, since the surface flatness of the silicon interposer is high, the connection between the integrated circuit arranged on the silicon interposer and the silicon interposer is not easy to occur. It is particularly preferred to use the silicon interposer for 2.5D packaging (2.5D mounting) in which a plurality of integrated circuits are arranged horizontally and configured on the interposer.

[0604] On the other hand, when a plurality of integrated circuits with different terminal pitches are electrically connected using silicon interposers and TSV, etc., a space such as the width of the terminal pitch is required. Therefore, when the size of the electronic component 730 is to be reduced, the width of the terminal pitch becomes a problem, and it is sometimes difficult to set up a large number of wirings required to achieve a wider memory bandwidth. Therefore, as described above, a monolithic stacked structure using OS transistors is preferred. In addition, a composite structure combining a memory cell array stacked using TSV and a memory cell array stacked in a monolithic manner can also be used.

[0605] In addition, a heat sink (heat sink plate) may be provided so as to overlap with the electronic component 730. When a heat sink is provided, it is preferable to make the heights of the integrated circuits provided on the interposer 731 consistent. For example, in the electronic component 730 shown in this embodiment, it is preferable to make the heights of the semiconductor device 710 and the semiconductor device 735 consistent.

[0606] In order to mount the electronic component 730 on another substrate, an electrode 733 may be provided on the bottom of the package substrate 732 . Fig. 30B An example of forming the electrode 733 using solder balls is shown. By arranging solder balls in a matrix on the bottom of the package substrate 732, BGA (Ball Grid Array) mounting can be achieved. Alternatively, the electrode 733 can be formed using conductive needles. By arranging conductive needles in a matrix on the bottom of the package substrate 732, PGA (Pin Grid Array) mounting can be achieved.

[0607] The electronic component 730 can be mounted on other substrates by various mounting methods, not limited to BGA and PGA. Examples of mounting methods include SPGA (Staggered Pin Grid Array), LGA (Land Grid Array), QFP (Quad Flat Package), QFJ (Quad Flat J-leaded package), and QFN (Quad Flat Non-leaded package).

[0608] [Electronic equipment]

[0609] then, Fig.31A A perspective view of electronic device 6500 is shown. Fig.31A The electronic device 6500 shown is a portable information terminal that can be used as a smartphone. The electronic device 6500 includes a housing 6501, a display unit 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, a light source 6508, and a control device 6509. The control device 6509 includes, for example, any one or more selected from a CPU, a GPU, and a storage device. The semiconductor device of one embodiment of the present invention can be used for the display unit 6502, the control device ...

Claims

1. A semiconductor device comprising: Oxide on substrate; A first conductor and a second conductor separated from each other on the oxide; a third electrical conductor in contact with a portion of a top surface of the first electrical conductor; a fourth electrical conductor in contact with a portion of a top surface of the second electrical conductor; a first insulator disposed on the third conductor and the fourth conductor and having an opening overlapping a region between the third conductor and the fourth conductor; a second insulator disposed in the opening of the first insulator and in contact with another portion of the top surface of the first conductor, another portion of the top surface of the second conductor, a side surface of the third conductor, and a side surface of the fourth conductor; a third insulator disposed in the opening of the first insulator and in contact with a top surface of the oxide, a side surface of the first conductor, a side surface of the second conductor, and a side surface of the second insulator; as well as a fifth conductor disposed on the third insulator in the opening of the first insulator and having a region overlapping with the oxide via the third insulator, The distance between the first conductor and the second conductor is smaller than the distance between the third conductor and the fourth conductor. The second insulator includes a first layer and a second layer on the first layer, The first layer comprises a nitride insulator, Furthermore, the second layer includes an oxide insulator.

2. The semiconductor device according to claim 1, wherein the first layer is in contact with the first conductor, the second conductor, the third conductor, the fourth conductor and the first insulator, Furthermore, the second layer does not contact the first conductor, the second conductor, the third conductor, the fourth conductor, and the first insulator.

3. The semiconductor device according to claim 1, The first layer comprises silicon nitride.

4. The semiconductor device according to claim 3, The second layer comprises silicon oxide.

5. The semiconductor device according to claim 3, The second layer comprises aluminum oxide.

6. The semiconductor device according to claim 3, The second layer comprises hafnium oxide.

7. The semiconductor device according to claim 1, The first conductor and the second conductor include metal nitride.

8. The semiconductor device according to claim 1, The first conductor and the second conductor include tantalum nitride.

9. The semiconductor device according to claim 1, wherein the first conductor and the second conductor comprise tantalum nitride, Furthermore, the third conductor and the fourth conductor include tungsten.

10. The semiconductor device according to claim 1, The difference between the distance between the third conductor and the fourth conductor and the distance between the first conductor and the second conductor is equal to or substantially equal to twice the thickness of the second insulator.

11. The semiconductor device according to claim 1, The side surface of the opening of the first insulator is aligned or substantially aligned with the side surface of the third conductor and the side surface of the fourth conductor when viewed from above.

12. A storage device, comprising: The semiconductor device according to any one of claims 1 to 11; as well as Capacitor components, One electrode of the capacitor is electrically connected to the third conductor of the semiconductor device.

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