Semiconductor package

Abstract

Disclosed is a semiconductor package including: an interposer; a first semiconductor die under the interposer; and a first dummy die, a second dummy die, and a second semiconductor die over the interposer. The first semiconductor die, the second semiconductor die, the first dummy die, and the second dummy die overlap the interposer. The first semiconductor die overlaps the second semiconductor die. The second semiconductor die is between the first dummy die and the second dummy die.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority from Korean Patent Application No. 10-2023-0108377 filed in the Korean Intellectual Property Office on August 18, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The inventive concept relates to a semiconductor package, and more particularly, to a semiconductor package including an interposer and a method of manufacturing the semiconductor package. Background Art

[0004] A semiconductor package is provided to implement an integrated circuit chip that is eligible for use in an electronic product. Typically, a semiconductor package is configured such that a semiconductor chip is mounted on a printed circuit board (PCB) and the semiconductor chip is electrically connected to the printed circuit board using bonding wires or bumps. With the development of the electronics industry, various studies have been conducted to improve the reliability and durability of semiconductor packages. Summary of the invention

[0005] Some example embodiments of the inventive concepts provide a semiconductor package having improved electrical characteristics and enhanced reliability.

[0006] According to some example embodiments of the inventive concept, a semiconductor package may include: an interposer; a first semiconductor die below the interposer; and a first dummy die, a second dummy die, and a second semiconductor die above the interposer. The first semiconductor die, the second semiconductor die, the first dummy die, and the second dummy die may overlap with the interposer. The first semiconductor die may overlap with the second semiconductor die. The second semiconductor die may be located between the first dummy die and the second dummy die.

[0007] According to some example embodiments of the present inventive concept, a semiconductor package may include: an interposer; a first semiconductor die below the interposer; and a first dummy die, a second dummy die, and a second semiconductor die above the interposer. The second semiconductor die may be located between the first dummy die and the second dummy die. The width of the interposer may be greater than the sum of the width of the first dummy die, the width of the second dummy die, and the width of the second semiconductor die. The width of the interposer may be greater than the width of the first semiconductor die.

[0008] According to some example embodiments of the inventive concept, a semiconductor package may include: a package substrate; a reinforcement member in contact with the package substrate; a first semiconductor die over the package substrate; an inserter over the first semiconductor die; a first dummy die, a second dummy die, a third dummy die, a fourth dummy die, and a plurality of second semiconductor die over the inserter; a first molding layer surrounding the first semiconductor die; and a second molding layer surrounding the first to fourth dummy die and the plurality of second semiconductor die. The plurality of second semiconductor die may be located between the first dummy die and the second dummy die. The first dummy die and the second dummy die and the plurality of second semiconductor die may be located between the third dummy die and the fourth dummy die.

[0009] According to some example embodiments of the inventive concept, a method of manufacturing a semiconductor package may include: connecting a first semiconductor die to a bottom surface of an interposer; connecting a second semiconductor die, a first dummy die, and a second dummy die to a top surface of the interposer; forming a reinforcement on a package substrate; and connecting the first semiconductor die to the package substrate. The interposer may have a width greater than a width of the first semiconductor die. The second semiconductor die may be located between the first dummy die and the second dummy die. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Figure 1 A plan view showing a semiconductor package according to some example embodiments is shown.

[0011] Figure 2 Shown along Figure 1 A cross-sectional view taken along line AA'.

[0012] Figure 3 Shown Figure 2 An enlarged view of part E of FIG.

[0013] Figure 4 A plan view showing the reinforcement is shown.

[0014] Figure 5 , Figure 6 , Figure 7 and Figure 8 A cross-sectional view illustrating a method of manufacturing a semiconductor package according to some example embodiments is shown.

[0015] Fig. 9 An enlarged cross-sectional view showing a semiconductor package according to some example embodiments is shown.

[0016] Fig.10 An enlarged cross-sectional view showing a semiconductor package according to some example embodiments is shown.

[0017] Fig.11A cross-sectional view showing a semiconductor package according to some example embodiments is shown.

[0018] Fig.12 A cross-sectional view showing a semiconductor package according to some example embodiments is shown.

[0019] Fig.13 A cross-sectional view showing a semiconductor package according to some example embodiments is shown.

[0020] Fig.14 A cross-sectional view showing a semiconductor package according to some example embodiments is shown. DETAILED DESCRIPTION

[0021] Semiconductor packages and methods of manufacturing the same according to some example embodiments of the inventive concept will be described in detail below with reference to the accompanying drawings.

[0022] Figure 1 A plan view showing a semiconductor package according to some example embodiments is shown. Figure 2 Shown along Figure 1 A cross-sectional view taken along line AA'. Figure 3 Shown Figure 2 An enlarged view of part E of FIG. Figure 4 A plan view showing the reinforcement is shown.

[0023] Reference Figure 1 and Figure 2 The semiconductor package may include a terminal TE, a package substrate PS, a reinforcement ST, a first molding layer MD1, a first bump BP1, a second bump BP2, a third bump BP3, a first semiconductor die SD1, an insert IN, a second semiconductor die SD2, a first dummy die DD1, a second dummy die DD2, a third dummy die DD3, a fourth dummy die DD4, an adhesive layer AD and a second molding layer MD2.

[0024] The reinforcement ST may be disposed on the package substrate PS. The reinforcement ST may be in contact with the top surface of the package substrate PS. The terminal TE may be disposed under the package substrate PS. The semiconductor package may be electrically connected to an external device through the terminal TE.

[0025] In some example embodiments, the package substrate PS may be a printed circuit board (PCB). The reinforcement ST may be used to prevent warping of the package substrate PS. The reinforcement ST may include a conductive material. For example, the reinforcement ST may include at least one selected from copper, aluminum, and stainless steel.

[0026] The terminal TE may include an electrically conductive material.

[0027] The first semiconductor die SD1 may be disposed on (or above) the package substrate PS. The stiffener ST may surround at least a portion of the first semiconductor die SD1. The upper portion of the stiffener ST and the lower portion of the first semiconductor die SD1 may be located at substantially the same level or at the same level. The first semiconductor die SD1 may include a first lower protective layer 11, a first substrate 12 on the first lower protective layer 11, a first wiring structure 13 on the first substrate 12, a first upper protective layer 14 on the first wiring structure 13, a first lower pad 15 in the first lower protective layer 11, a first upper pad 16 in the first upper protective layer 14, and a first through-piece 17 passing through the first substrate 12. In some example embodiments, the first wiring structure 13 may be disposed between the first lower protective layer 11 and the first substrate 12.

[0028] The first substrate 12 may have a plate shape extending along a plane defined in the first direction D1 and the second direction D2. The first direction D1 and the second direction D2 may intersect each other. For example, the first direction D1 and the second direction D2 may be horizontal directions orthogonal to each other. The first substrate 12 may be a semiconductor substrate. For example, the first substrate 12 may include silicon, germanium, silicon-germanium, gallium-phosphorus, or gallium-arsenic. In some example embodiments, the first substrate 12 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0029] The first lower protective layer 11 may include a dielectric material. For example, the first lower protective layer 11 may include an oxide. In some example embodiments, the first lower protective layer 11 may be a multilayer including a plurality of dielectric layers.

[0030] The first upper protective layer 14 may include a dielectric material. For example, the first upper protective layer 14 may include an oxide. In some example embodiments, the first upper protective layer 14 may be a multilayer including a plurality of dielectric layers.

[0031] The first lower pad 15 may be surrounded by the first lower protective layer 11. The first lower pad 15 may include a conductive material. For example, the first lower pad 15 may include copper.

[0032] The first upper pad 16 may be surrounded by the first upper protective layer 14. The first upper pad 16 may include a conductive material. For example, the first upper pad 16 may include copper.

[0033] The first through-piece 17 may be connected to the first lower pad 15 and the first wiring structure 13. The first through-piece 17 may pass through the first substrate 12 in the third direction D3 to electrically connect the first lower pad 15 to the first wiring structure 13. The third direction D3 may intersect the first direction D1 and the second direction D2. For example, the third direction D3 may be a vertical direction perpendicular to the first direction D1 and the second direction D2. The first through-piece 17 may include a conductive material.

[0034] The first semiconductor die SD1 may further include a semiconductor device. For example, the first semiconductor die SD1 may be a logic semiconductor die including a logic semiconductor device. For example, the logic semiconductor die may be a central processing unit (CPU), a graphics processing unit (GPU), or an application processor (AP).

[0035] The first bump BP1 may be disposed between the first semiconductor die SD1 and the package substrate PS. The first bump BP1 may electrically connect the first semiconductor die SD1 to the package substrate PS. The first bump BP1 may contact the first lower pad 15. The first bump BP1 may include a conductive material.

[0036] The insert IN may be disposed on (or above) the first semiconductor die SD1. The insert IN may overlap with the first semiconductor die SD1 in the third direction D3. The first semiconductor die SD1 may be disposed below the insert IN. The top surface of the first semiconductor die SD1 may contact the bottom surface of the insert IN. The insert IN may include a second lower protective layer 21, a lower wiring structure 40 on the second lower protective layer 21, a second substrate 22 on the lower wiring structure 40, an upper wiring structure 50 on the second substrate 22, a second upper protective layer 24 on the upper wiring structure 50, a second lower pad 25 in the second lower protective layer 21, a second upper pad 26 in the second upper protective layer 24, and a second through-piece 27 passing through the second substrate 22. The bottom surface of the insert IN may face the top surface of the stiffener ST.

[0037] The second substrate 22 may be a semiconductor substrate. In some example embodiments, the second substrate 22 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0038] The second lower protective layer 21 may include a dielectric material. In some example embodiments, the second lower protective layer 21 may be a multilayer including a plurality of dielectric layers. The second upper protective layer 24 may include a dielectric material. In some example embodiments, the second upper protective layer 24 may be a multilayer including a plurality of dielectric layers.

[0039] The second lower pad 25 may be surrounded by the second lower protective layer 21. The second lower pad 25 may include a conductive material. For example, the second lower pad 25 may include copper. The second upper pad 26 may be surrounded by the second upper protective layer 24. The second upper pad 26 may include a conductive material. For example, the second upper pad 26 may include copper.

[0040] The second vias 27 may connect the lower wiring structure 40 to the upper wiring structure 50. The second vias 27 may pass through the second substrate 22 in the third direction D3 to electrically connect the lower wiring structure 40 to the upper wiring structure 50. The second vias 27 may include a conductive material.

[0041] The interposer IN may be bonded to the first semiconductor die SD1 using a hybrid wafer bonding process. The bottom surface of the second lower pad 25 may contact the top surface of the first upper pad 16. The bottom surface of the second lower protective layer 21 may contact the top surface of the first upper protective layer 14. In some example embodiments, the interposer IN and the first semiconductor die SD1 may be electrically connected via a bump therebetween.

[0042] The first mold layer MD1 may be disposed between the package substrate PS and the insert IN. The first mold layer MD1 may include a portion inserted between the stiffener ST and the insert IN, a portion inserted between the stiffener ST and the first semiconductor die SD1, and a portion inserted between the package substrate PS and the first semiconductor die SD1. The first mold layer MD1 may surround the first semiconductor die SD1. The first mold layer MD1 may contact the top surface of the stiffener ST, the inner side wall ST_IS of the stiffener ST, the outer side wall SD1_OS of the first semiconductor die SD1, the top surface of the package substrate PS, and the bottom surface of the insert IN. The first mold layer MD1 may include a polymer material. For example, the first mold layer MD1 may include an epoxy resin.

[0043] A plurality of second semiconductor die SD2 may be disposed on (or above) the insert IN. A plurality of second semiconductor die SD2 may overlap each other in the third direction D3. A plurality of second semiconductor die SD2 may overlap the insert IN and the first semiconductor die SD1 in the third direction D3. The second semiconductor die SD2 may include a third lower protective layer 31, a second wiring structure 33 on the third lower protective layer 31, a third substrate 32 on the second wiring structure 33, a third upper protective layer 34 on the third substrate 32, a third lower pad 35 in the third lower protective layer 31, a third upper pad 36 in the third upper protective layer 34, and a third through-piece 37 passing through the third substrate 32. In some example embodiments, the second wiring structure 33 may be disposed between the third substrate 32 and the third upper protective layer 34.

[0044] The third substrate 32 may be a semiconductor substrate. In some example embodiments, the third substrate 32 may be a silicon-on-insulator (SOI) substrate or a germanium-on-insulator (GOI) substrate.

[0045] The third lower protective layer 31 may include a dielectric material. In some example embodiments, the third lower protective layer 31 may be a multilayer including a plurality of dielectric layers. The third upper protective layer 34 may include a dielectric material. In some example embodiments, the third upper protective layer 34 may be a multilayer including a plurality of dielectric layers.

[0046] The third lower pad 35 may be surrounded by the third lower protective layer 31. The third lower pad 35 may include a conductive material. For example, the third lower pad 35 may include copper. The third upper pad 36 may be surrounded by the third upper protective layer 34. The third upper pad 36 may include a conductive material. For example, the third upper pad 36 may include copper.

[0047] The third vias 37 may connect the second wiring structure 33 to the third upper pads 36. The third vias 37 may pass through the third substrate 32 in the third direction D3 to electrically connect the second wiring structure 33 to the third upper pads 36. The third vias 37 may include a conductive material.

[0048] The second semiconductor die SD2 may also include a semiconductor device. For example, the second semiconductor die SD2 may be a memory semiconductor die including a memory semiconductor device. For example, the memory semiconductor device may be a dynamic random access memory (DRAM) semiconductor device, a static RAM (SRAM) semiconductor device, a thyristor RAM (TRAM) semiconductor device, a zero capacitor RAM (ZRAM) semiconductor device, a two-transistor RAM (TTRAM) semiconductor device, a flash memory semiconductor device, a magnetic RAM (MRAM) semiconductor device, a spin-transfer torque RAM (STT-MRAM) semiconductor device, a ferroelectric RAM (FRAM) semiconductor device, a phase change RAM (PRAM) semiconductor device, a polymer RAM semiconductor device, or an insulator resistance change memory semiconductor device.

[0049] The uppermost semiconductor die USD may be disposed on top of the second semiconductor die SD2 . The uppermost semiconductor die USD may not include the third upper protection layer 34 , the third upper pad 36 , and the third through-via 37 .

[0050] The second bump BP2 may be disposed between the second semiconductor die SD2 and the interposer IN. The second bump BP2 may electrically connect the second semiconductor die SD2 to the interposer IN. The second bump BP2 may contact the second upper pad 26 and the third lower pad 35. The second bump BP2 may include a conductive material.

[0051] The third bump BP3 may be disposed between the respective second semiconductor dies SD2. The third bump BP3 may electrically connect the respective second semiconductor dies SD2 to each other. The third bump BP3 may contact the third upper pad 36 and the third lower pad 35. The third bump BP3 may include a conductive material.

[0052] The first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may be disposed on (or above) the inserter IN. The first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may overlap the inserter IN in the third direction D3. Each of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may include a portion overlapping a portion of the first semiconductor die SD1 in the third direction D3.

[0053] The first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may be spaced apart from the second semiconductor die SD2. The first dummy die DD1 and the second dummy die DD2 may be spaced apart from the second semiconductor die SD2 in the first direction D1. The third dummy die DD3 and the fourth dummy die DD4 may be spaced apart from the second semiconductor die SD2, the first dummy die DD1, and the second dummy die DD2 in the second direction D2.

[0054] Each of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may not include a semiconductor device. Each of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may include a large block of silicon or a large block of metal (e.g., a large block of copper or a large block of aluminum). For example, the first dummy die DD1 may be a large block of silicon formed as a whole block of silicon or a large block of metal formed as a whole block of metal (e.g., a large block of copper or a large block of aluminum).

[0055] The width W1 of the insert IN in the first direction D1 may be greater than the width W2 of the first semiconductor die SD1 in the first direction D1. The width W1 of the insert IN in the first direction D1 may be greater than the width W2 of the first semiconductor die SD1 in the first direction D1 by about 1 mm or exactly 1 mm to about 90 mm or exactly 90 mm. The width W1 of the insert IN in the first direction D1 may be greater than the sum of the width W3 of the second semiconductor die SD2 in the first direction D1, the width W4 of the first dummy die DD1 in the first direction D1, and the width W5 of the second dummy die DD2 in the first direction D1. The width W1 of the insert IN in the first direction D1 may be greater than the width W3 of the second semiconductor die SD2 in the first direction D1 by about 1 mm or exactly 1 mm to about 90 mm or exactly 90 mm. The width W1 of the insert IN in the first direction D1 may be greater than the width of the third dummy die DD3 in the first direction D1 and the width of the fourth dummy die DD4 in the first direction D1.

[0056] The width W11 of the insert IN in the second direction D2 may be greater than the width W12 of the first semiconductor die SD1 in the second direction D2. The width W11 of the insert IN in the second direction D2 may be greater than the width W12 of the first semiconductor die SD1 in the second direction D2 by about 1 mm or exactly 1 mm to about 90 mm or exactly 90 mm. The width W11 of the insert IN in the second direction D2 may be greater than the sum of the width W13 of the second semiconductor die SD2 in the second direction D2, the width W14 of the third dummy die DD3 in the second direction D2, and the width W15 of the fourth dummy die DD4 in the second direction D2. The width W11 of the insert IN in the second direction D2 may be greater than the width W13 of the second semiconductor die SD2 in the second direction D2 by about 1 mm or exactly 1 mm to about 90 mm or exactly 90 mm. The width W11 of the insert IN in the second direction D2 may be greater than the width W13 of the second semiconductor die SD2 in the second direction D2 by about 1 mm or exactly 1 mm to about 90 mm or exactly 90 mm. The width W11 of the insert IN in the second direction D2 may be greater than the width of the first dummy die DD1 in the second direction D2 and the width of the second dummy die DD2 in the second direction D2.

[0057] A width W1 of the interposer IN in the first direction D1 may be substantially the same as or the same as a width of the package substrate PS in the first direction D1. In some example embodiments, a width W1 of the interposer IN in the first direction D1 may be smaller than a width of the package substrate PS in the first direction D1.

[0058] A width W11 of the interposer IN in the second direction D2 may be substantially the same as or the same as a width of the package substrate PS in the second direction D2. In some example embodiments, a width W11 of the interposer IN in the second direction D2 may be smaller than a width of the package substrate PS in the second direction D2.

[0059] The top surfaces DD_T of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may be coplanar with the top surface USD_T of the uppermost semiconductor die USD and the top surface MD2_T of the second mold layer MD2. The top surfaces DD_T of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may be located at substantially the same level or at the same level as the top surface USD_T of the uppermost semiconductor die USD and the top surface MD2_T of the second mold layer MD2. The distance between the insert IN and the top surface DD_T of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3 and the fourth dummy die DD4 in the third direction D3 may be substantially the same as or the same as the distance between the insert IN and the top surface USD_T of the topmost semiconductor die USD in the third direction D3 and the distance between the insert IN and the top surface MD2_T of the second molding layer MD2 in the third direction D3.

[0060] The height of each of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may be greater than the height of each of the plurality of second semiconductor die SD2, greater than the height of the insert IN, and greater than the height of the first semiconductor die SD1. The length of each of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 in the third direction D3 may be greater than the length of each of the plurality of second semiconductor die SD2 in the third direction D3, greater than the length of the insert IN in the third direction D3, and greater than the length of the first semiconductor die SD1 in the third direction D3.

[0061] An adhesive layer AD may be disposed between the interposer IN and each of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4. Each of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may be attached to the interposer IN by the adhesive layer AD. The adhesive layer AD may include a polymer material.

[0062] The second mold layer MD2 may be provided to surround the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4, the adhesive layer AD, and the second semiconductor die SD2. The second mold layer MD2 may include a portion interposed between the second semiconductor die SD2 and the dummy die DD1, DD2, DD3, and DD4 and a portion interposed between the dummy die DD1, DD2, DD3, and DD4. The second mold layer MD2 may include a polymer material. For example, the second mold layer MD2 may include an epoxy resin.

[0063] In some example embodiments, the insert IN may have an outer sidewall IN_OS coplanar with the outer sidewall MD2_OS of the second mold layer MD2 , the outer sidewall MD1_OS of the first mold layer MD1 , the outer sidewall ST_OS of the reinforcement ST, and the outer sidewall PS_OS of the package substrate PS.

[0064] When Figure 1 As shown, when viewed in a plane, the first and second semiconductor dies SD1 and SD2 and the first, second, third, and fourth dummy dies DD1, DD2, DD3, and DD4 may be disposed between outer sidewalls IN_OS of the insert IN extending in the first direction D1.

[0065] Reference Figure 3, the lower wiring structure 40 of the insert IN may include a lower wiring dielectric layer 41 and a lower conductive structure 42 in the lower wiring dielectric layer 41. The lower wiring dielectric layer 41 may be disposed on the second lower protective layer 21. The lower wiring dielectric layer 41 may be in contact with the top surface of the second lower protective layer 21 and the bottom surface of the second substrate 22. The lower wiring dielectric layer 41 may include a dielectric material. In some example embodiments, the lower wiring dielectric layer 41 may be a multi-dielectric layer including a plurality of dielectric layers.

[0066] The lower conductive structure 42 may be surrounded by the lower wiring dielectric layer 41. Each of the lower conductive structures 42 may be a conductive pad, a conductive line, or a conductive through-piece. The lower conductive structures 42 may be connected to each other. The second through-piece 27 and the second lower pad 25 may be electrically connected through the lower conductive structure 42. The lower conductive structure 42 may include a conductive material.

[0067] The upper wiring structure 50 of the insert IN may include an upper wiring dielectric layer 51 and an upper conductive structure 52 in the upper wiring dielectric layer 51. The upper wiring dielectric layer 51 may be disposed on the second substrate 22. The upper wiring dielectric layer 51 may be disposed on the top surface of the second substrate 22 and the bottom surface of the second upper protective layer 24. The upper wiring dielectric layer 51 may include a dielectric material. In some example embodiments, the upper wiring dielectric layer 51 may be a multi-dielectric layer including a plurality of dielectric layers.

[0068] The upper conductive structure 52 may be surrounded by the upper wiring dielectric layer 51. Each of the upper conductive structures 52 may be a conductive pad, a conductive line, or a conductive through-piece. The upper conductive structures 52 may be connected to each other. The second through-piece 27 and the second upper pad 26 may be electrically connected through the upper conductive structure 52. The upper conductive structure 52 may include a conductive material.

[0069] The first wiring structure 13 of the first semiconductor die SD1 and the second wiring structure 33 of the second semiconductor die SD2 may each have a structure similar to that of the lower wiring structure 40 or the upper wiring structure 50. The first wiring structure 13 of the first semiconductor die SD1 and the second wiring structure 33 of the second semiconductor die SD2 may each include a wiring dielectric layer and a conductive structure in the wiring dielectric layer.

[0070] Reference Figure 4, the stiffener ST may include a first portion ST1 extending in the first direction D1 and a second portion ST2 extending in the second direction D2. The first portions ST1 of the stiffener ST may be spaced apart from each other in the second direction D2. The first semiconductor die SD1 and the second portion ST2 of the stiffener ST may be disposed between the first portions ST1 of the stiffener ST. The second portions ST2 of the stiffener ST may be spaced apart from each other in the first direction D1. The first semiconductor die SD1 and the first portion ST1 of the stiffener ST may be disposed between the second portions ST2 of the stiffener ST. The lower portion of the first semiconductor die SD1 may be surrounded by the first portion ST1 and the second portion ST2 of the stiffener ST.

[0071] The first portion ST1 of the reinforcer ST may overlap the third dummy die DD3 or the fourth dummy die DD4 in the third direction D3. In some example embodiments, a portion of the first portion ST1 of the reinforcer ST may overlap a portion of the third dummy die DD3 or a portion of the fourth dummy die DD4 in the third direction D3.

[0072] The second portion ST2 of the reinforcer ST may overlap the first dummy die DD1, the third dummy die DD3, and the fourth dummy die DD4 in the third direction D3, or may overlap the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 in the third direction D3. In some example embodiments, a portion of the second portion ST2 of the reinforcer ST may overlap a portion of each of the first dummy die DD1, the third dummy die DD3, and the fourth dummy die DD4 in the third direction D3, or may overlap a portion of each of the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 in the third direction D3.

[0073] The reinforcer ST may not overlap with any of the first semiconductor die SD1 and the second semiconductor die SD2 in the third direction D3. The reinforcer ST may be spaced apart from the first semiconductor die SD1 and the second semiconductor die SD2 in the first direction D1 and the second direction D2. The first portion ST1 and the second portion ST2 of the reinforcer ST may overlap with the insert IN, the second mold layer MD2, and the first mold layer MD1 in the third direction D3.

[0074] In the semiconductor package according to some example embodiments, since the interposer IN and the first semiconductor die SD1 are hybrid-bonded, heat transfer between the first semiconductor die SD1 and the interposer IN may be improved to effectively release heat generated from the first semiconductor die SD1 .

[0075] In the semiconductor package according to some example embodiments, since the insert IN is disposed between the first semiconductor die SD1 and the second semiconductor die SD2 and since the width of the insert IN is increased, heat released from the first semiconductor die SD1 can be effectively dispersed in the insert IN and the heat radiation characteristics of the semiconductor can be improved.

[0076] In the semiconductor package according to some example embodiments, since the first dummy die DD1, the second dummy die DD2, the third dummy die DD3 and the fourth dummy die DD4 are included, heat can be released outward from the insert IN through the first dummy die DD1, the second dummy die DD2, the third dummy die DD3 and the fourth dummy die DD4, and the thermal radiation characteristics of the semiconductor package can be improved.

[0077] Figure 5 , Figure 6 , Figure 7 and Figure 8 A cross-sectional view illustrating a method of manufacturing a semiconductor package according to some example embodiments is shown.

[0078] Reference Figure 5 , the first semiconductor die SD1 may be connected to the bottom surface of the insert IN. The insert IN and the first semiconductor die SD1 may be connected by a hybrid wafer bonding process. The bottom surface of the second lower pad 25 may be allowed to contact the top surface of the first upper pad 16. The bottom surface of the second lower protective layer 21 may be allowed to contact the top surface of the first upper protective layer 14.

[0079] The first bump BP1 may be formed on a bottom surface of the first semiconductor die SD1 .

[0080] Reference Figure 6 , the second semiconductor die SD2 may be connected to the top surface of the interposer IN. In some example embodiments, the third bumps BP3 may be used to connect the second semiconductor die SD2 to each other, and then the second bumps BP2 may be used to connect the second semiconductor die SD2 to the interposer IN.

[0081] The first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4 may be connected to the top surface of the interposer IN. In some example embodiments, an adhesive layer AD may be formed on a bottom surface of each of the first dummy die DD1, the second dummy die DD2, the third dummy die DD3, and the fourth dummy die DD4, and then the adhesive layer AD may be allowed to contact the interposer IN.

[0082] Reference Figure 7 , the stiffener ST may be formed on the package substrate PS. The terminal TE may be formed on the bottom surface of the package substrate PS.

[0083] Reference Figure 8 , the first semiconductor die SD1 may be connected to the top surface of the package substrate PS. The first bump BP1 may be allowed to contact the top surface of the package substrate PS.

[0084] Reference Figure 2 , a first mold layer MD1 may be formed. The first mold layer MD1 may fill a space between the stiffener ST and the inserter IN, a space between the stiffener ST and the first semiconductor die SD1, and a space between the package substrate PS and the first semiconductor die SD1.

[0085] The second mold layer MD2 may be formed The second mold layer MD2 may fill spaces between the second semiconductor die SD2 and the first, second, third, and fourth dummy dies DD1, DD2, DD3, and DD4.

[0086] In some example embodiments, the first mold layer MD1 and the second mold layer MD2 may be formed by one process. In some example embodiments, the first mold layer MD1 and the second mold layer MD2 may be formed by independent processes.

[0087] Fig. 9 An enlarged cross-sectional view showing a semiconductor package according to some example embodiments is shown. In addition to the following discussion, Fig. 9 The semiconductor package can be similar to Figures 1 to 4 semiconductor packages.

[0088] Reference Fig. 9 , the insert IN may not include an upper wiring structure between the second substrate 22 and the second upper protection layer 24. The top surface of the second substrate 22 may contact the bottom surface of the second upper protection layer 24. The top surface of the second through-piece 27 may contact the bottom surface of the second upper pad 26.

[0089] Fig.10 An enlarged cross-sectional view showing a semiconductor package according to some example embodiments is shown. In addition to the following discussion, Fig.10 The semiconductor package can be similar to Figures 1 to 4 semiconductor packages.

[0090] Reference Fig.10 , the insert IN may not include a lower wiring structure between the second substrate 22 and the second lower protective layer 21. The top surface of the second lower protective layer 21 may contact the bottom surface of the second substrate 22. The top surface of the second lower pad 25 may contact the bottom surface of the second through member 27.

[0091] Fig.11 A cross-sectional view showing a semiconductor package according to some example embodiments is shown. In addition to the following discussion, Fig.11The semiconductor package can be similar to Figures 1 to 4 semiconductor packages.

[0092] Reference Fig.11 , a plurality of second semiconductor die SD2 may be hybrid-bonded to each other. The third upper pad 36 may contact the third lower pad 35. The third upper protection layer 34 may contact the third lower protection layer 31.

[0093] The lowermost one of the plurality of second semiconductor die SD2 may be hybrid-bonded to the interposer IN. The third lower pad 35 of the lowermost second semiconductor die SD2 may contact the second upper pad 26 of the interposer IN. The third lower protection layer 31 of the lowermost second semiconductor die SD2 may contact the second upper protection layer 24.

[0094] Fig.12 A cross-sectional view showing a semiconductor package according to some example embodiments is shown. In addition to the following discussion, Fig.12 The semiconductor package can be similar to Figures 1 to 4 semiconductor packages.

[0095] Reference Fig.12 , the dummy bump DB may be disposed between the dummy die DD and the interposer IN. The dummy bump DB may contact the bottom surface of the dummy die DD and the second upper pad 26 of the interposer IN. The dummy bump DB may pass through the adhesive layer AD. The adhesive layer AD may surround the dummy bump DB. The dummy bump DB may include a conductive material.

[0096] The dummy bump DB may relatively greatly increase the bonding force between the dummy die DD and the interposer IN.

[0097] In some example embodiments, the dummy die DD and the interposer IN may be bonded only by the dummy bump DB without the adhesive layer AD.

[0098] In some example embodiments, the dummy die DD may be a logic semiconductor die including a logic semiconductor device or a memory semiconductor die including a memory semiconductor device. In this case, the dummy die DD may be electrically connected to the interposer IN through the dummy bump DB.

[0099] Fig.13 A cross-sectional view showing a semiconductor package according to some example embodiments is shown. In addition to the following discussion, Fig.13 The semiconductor package can be similar to Figures 1 to 4 semiconductor packages.

[0100] Reference Fig.13, the reinforcement member ST may surround the first mold layer MD1, the first semiconductor die SD1, the insert IN, the second semiconductor die SD2, the dummy die DD, and the second mold layer MD2. The reinforcement member ST may contact the top surface of the package substrate PS, the outer sidewall MD1_OS of the first mold layer MD1, the outer sidewall IN_OS of the insert IN, the outer sidewall MD2_OS of the second mold layer MD2, the top surface MD2_T of the second mold layer MD2, the top surface DD_T of the dummy die DD, and the top surface USD_T of the uppermost semiconductor die USD. The reinforcement member ST may be used as a heat sink.

[0101] Fig.14 A cross-sectional view showing a semiconductor package according to some example embodiments is shown. In addition to the following discussion, Fig.14 The semiconductor package can be similar to Figures 1 to 4 semiconductor packages.

[0102] Reference Fig.14 The semiconductor package may have a chip-on-substrate structure. The first underfill layer UN1 may be disposed between the package substrate PS and the first semiconductor die SD1. The first underfill layer UN1 may surround the first bump BP1. The first underfill layer UN1 may include a polymer material.

[0103] The molding layer may not be disposed between the package substrate PS and the interposer IN. An empty space may be disposed between the package substrate PS and the interposer IN.

[0104] The second underfill layer UN2 may be disposed between the interposer IN and the second semiconductor die SD2. The second underfill layer UN2 may surround the second bump BP2. The second underfill layer UN2 may include a polymer material.

[0105] A third underfill layer UN3 may be provided. The third underfill layer UN3 may be provided between the respective second semiconductor die SD2. The third underfill layer UN3 may surround the third bump BP3.

[0106] The third underfill layer UN3 may include a polymer material.

[0107] A mold layer may not be disposed between the dummy die DD and the second semiconductor die SD2. An empty space may be disposed between the dummy die DD and the second semiconductor die SD2.

[0108] In the semiconductor package according to some example embodiments of the inventive concepts, since the interposer and the logic semiconductor die are hybrid-bonded to each other, heat transfer between the logic semiconductor die and the interposer may be improved to effectively release heat generated from the logic semiconductor die.

[0109] In the semiconductor package of some example embodiments conceived according to the present invention, since the interposer is disposed between the logic semiconductor die and the memory semiconductor die, and since the interposer has a relatively large width, heat released from the logic semiconductor die can be effectively diffused in the interposer, and the thermal radiation characteristics of the semiconductor package can be improved.

[0110] In the semiconductor package according to some example embodiments of the inventive concepts, since a dummy die is included, heat may be released outward from the interposer through the dummy die, and heat radiation characteristics of the semiconductor package may be improved.

[0111] When the term "about" or "substantially" is used in conjunction with a numerical value in this specification, it is intended that the associated numerical value includes a manufacturing tolerance or operating tolerance of about (e.g., ±10%) the listed numerical value. Moreover, when the words "generally" and "substantially" are used in conjunction with a geometric shape, it is intended that the accuracy of the geometric shape is not required, but the freedom of the shape is within the scope of the present disclosure. In addition, regardless of whether a numerical value or shape is modified by "about" or "substantially", it should be understood that these values ​​and shapes should include a manufacturing tolerance or operating tolerance of about (e.g., ±10%) the listed numerical value or shape.

[0112] Although the present invention has been described in conjunction with some exemplary embodiments of the inventive concept shown in the accompanying drawings, it should be understood by those skilled in the art that changes in form and detail may be made without departing from the spirit and essential features of the inventive concept. The examples of the embodiments disclosed above should be considered illustrative rather than restrictive.

Claims

1. A semiconductor package, comprising: Inserts; a first semiconductor die below the insert; as well as a first dummy die, a second dummy die, and a second semiconductor die above the insert, The first semiconductor die, the second semiconductor die, the first dummy die, and the second dummy die overlap with the insert. The first semiconductor die overlaps the second semiconductor die, and The second semiconductor die is between the first dummy die and the second dummy die.

2. The semiconductor package according to claim 1, wherein: The first semiconductor die and the second semiconductor die are electrically connected through the interposer. 3 . The semiconductor package of claim 1 , further comprising a package substrate below the first semiconductor die.

4. The semiconductor package according to claim 3, further comprising a reinforcing member on the package substrate, in, The reinforcement surrounds at least a portion of the first semiconductor die.

5. The semiconductor package according to claim 1, wherein: Each of the first dummy die and the second dummy die is a large metal block or a large silicon block.

6. The semiconductor package according to claim 1, further comprising: a first adhesive layer between the first dummy die and the interposer; as well as A second adhesive layer is provided between the second dummy die and the interposer.

7. The semiconductor package according to claim 1, wherein: The insert has a width greater than a sum of a width of the second semiconductor die, a width of the first dummy die, and a width of the second dummy die.

8. The semiconductor package according to claim 7, wherein: The width of the interposer is greater than a width of the first semiconductor die.

9. The semiconductor package according to claim 8, wherein: The width of the interposer is 1 mm to 90 mm greater than the width of the first semiconductor die.

10. A semiconductor package, comprising: Inserts; a first semiconductor die below the insert; as well as a first dummy die, a second dummy die, and a second semiconductor die above the insert, The second semiconductor die is between the first dummy die and the second dummy die. The insert has a width greater than the sum of a width of the first dummy die, a width of the second dummy die, and a width of the second semiconductor die, and The width of the interposer is greater than a width of the first semiconductor die.

11. The semiconductor package according to claim 10, wherein: The insert comprises a lower protective layer and a lower pad surrounded by the lower protective layer, The first semiconductor bare die includes an upper protective layer and an upper pad surrounded by the upper protective layer, The lower protective layer is in contact with the upper protective layer, and The lower pad contacts the upper pad.

12. The semiconductor package according to claim 11, wherein The insert comprises: A lower wiring structure on the lower pad; A substrate on the lower wiring structure; and A via passes through the substrate.

13. The semiconductor package according to claim 12, wherein: The lower wiring structure comprises: a lower wiring dielectric layer between the lower protection layer and the substrate; and a lower conductive structure in the lower wiring dielectric layer, and The lower conductive structure electrically connects the lower pad to the via.

14. The semiconductor package according to claim 10, wherein: The second semiconductor die includes a plurality of second semiconductor die, A top surface of an uppermost semiconductor die of the plurality of second semiconductor dies is coplanar with a top surface of the first dummy die and a top surface of the second dummy die.

15. The semiconductor package according to claim 10, wherein: The first semiconductor die is a logic semiconductor die, and The second semiconductor die is the memory semiconductor die.

16. The semiconductor package according to claim 10, further comprising: a package substrate below the first semiconductor die; as well as The reinforcing member on the package substrate, The reinforcing member surrounds the first semiconductor die, the insert, the first dummy die, the second dummy die and the second semiconductor die.

17. The semiconductor package according to claim 10, wherein: The insert comprises an upper protective layer and an upper pad surrounded by the upper protective layer, The second semiconductor bare die includes a lower protective layer and a lower pad surrounded by the lower protective layer, The lower protective layer is in contact with the upper protective layer, and The lower pad contacts the upper pad.

18. The semiconductor package according to claim 10, wherein: A height of the first dummy die and a height of the second dummy die are greater than a height of the second semiconductor die.

19. A semiconductor package, comprising: Package substrate; a reinforcing member in contact with the package substrate; a first semiconductor die above the package substrate; an insert above the first semiconductor die; a first dummy die, a second dummy die, a third dummy die, a fourth dummy die and a plurality of second semiconductor die above the insert; a first molding layer surrounding the first semiconductor die; as well as a second molding layer surrounding the first to fourth dummy dies and the plurality of second semiconductor dies, The plurality of second semiconductor bare crystals are between the first dummy bare crystal and the second dummy bare crystal, and The first dummy die, the second dummy die, and the plurality of second semiconductor dies are between the third dummy die and the fourth dummy die.

20. The semiconductor package according to claim 19, wherein The reinforcing member overlaps the first to fourth dummy dies, and The reinforcement member does not overlap with any of the first semiconductor die and the plurality of second semiconductor dies.

Images