High-precision integrated temperature sensor circuit and application

Abstract

The invention discloses a high-precision integrated temperature sensor circuit and application, and relates to the technical field of integrated circuits, and the high-precision integrated temperature sensor circuit comprises a band-gap reference circuit, a buffer circuit, an analog-to-digital conversion circuit, a two-phase non-overlapping clock generation circuit and an FIR (Finite Impulse Response) digital filter. It needs to be explained that a key circuit sigma-delta modulator adopts an integrator cascade feed-forward structure CIFF, compared with a CIFB with a feedback structure, an STF function of an ADC of a feed-forward structure is close to 1, a peak value can appear only at a high frequency, only a very small error signal can pass through a whole loop, and therefore the stability of the analog-to-digital converter is greatly improved. Therefore, the gain of the amplifier in the first-stage integrator can be made relatively large, and noise and nonlinearity generated by the rear-stage integrator are effectively suppressed. Moreover, each stage of integrator does not process a feedback signal with high-frequency noise, so that the bandwidth requirement on the next stage of operational amplifier is reduced, the power consumption required by the CIFF structure is lower, and meanwhile, the output swing has better stability due to no feedback structure.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a high-precision integrated temperature sensor circuit and application thereof. Background Art

[0002] Temperature measurement plays a vital role in many fields, including industrial control, medical equipment, environmental monitoring, and automotive electronics. Traditional temperature measurement methods often rely on discrete components, such as thermocouples and thermal resistors. Although these methods can measure temperature, they have many limitations. Among them, discrete temperature sensors usually have a large volume, which is not conducive to the development trend of integration and miniaturization, and their accuracy and stability may be affected by many factors, such as environmental interference, installation errors, etc., resulting in inaccurate and unstable measurement results.

[0003] It should be noted that with the rapid development of semiconductor technology and integrated circuit technology, high-precision integrated temperature sensors have come into being. This type of sensor integrates temperature sensing elements and signal processing circuits on a single chip, and has the advantages of small size, low power consumption, fast response speed and high accuracy.

[0004] It should be further explained that the design focus of the integrated temperature sensor is how to accurately convert the measured ambient temperature into a circuit signal. In circuit design, devices that can sense temperature usually include thermistors, metals, etc. After years of development, temperature sensors composed of thermistors have achieved high accuracy. However, traditional thermistors have many serious defects: poor compatibility between temperature sensors and CMOS integration processes; serious nonlinearity between resistance and temperature; poor sensitivity and high power consumption when measuring low temperatures; the temperature measurement range is limited to measuring temperatures above zero, etc. This does not meet the requirements of high precision, and also poses a huge challenge to the matching of the back-end temperature readout circuit designed for analog-to-digital conversion under the CMOS process and the front-end analog temperature sensing circuit. Summary of the invention

[0005] The object of the present invention is to provide a high-precision integrated temperature sensor circuit and application to solve the problems raised in the above background technology.

[0006] To achieve the above object, the present invention provides the following technical solutions:

[0007] A high-precision integrated temperature sensor circuit comprises a bandgap reference circuit, a buffer circuit connected to the bandgap reference circuit, an analog-to-digital conversion circuit connected to the buffer circuit of the buffer, a two-phase non-overlapping clock generating circuit connected to the analog-to-digital conversion circuit, and an FIR digital filter connected to the analog-to-digital conversion circuit.

[0008] Furthermore, in a preferred embodiment of the present invention, the bandgap reference circuit includes a startup circuit, a bandgap circuit and a bias circuit, and the startup circuit and the bias circuit are both connected to the bandgap circuit, wherein the startup circuit is connected to the bandgap circuit for starting the bandgap circuit, and the bias circuit is connected to the bandgap circuit for providing a bias for the bandgap circuit.

[0009] Furthermore, in a preferred embodiment of the present invention, the bandgap reference circuit includes a first operational amplifier and two parallel parasitic bipolar PNP transistors, and the two parallel parasitic bipolar PNP transistors are respectively connected to two corresponding input terminals of the first operational amplifier.

[0010] Furthermore, in a preferred embodiment of the present invention, the structure of the first operational amplifier is a folded cascode differential operational amplifier; and the parasitic bipolar PNP transistor is a temperature sensing device.

[0011] Further, in a preferred embodiment of the present invention, the buffer circuit includes a second operational amplifier, C4, M0, R0 and R1, wherein the gate of M0 is connected to the output terminal of the second operational amplifier, the C4 is connected across the gate and drain of the M0, the R0 and the R1 are connected in series and then connected to the drain of the M0, the positive input terminal of the second operational amplifier is connected between the R0 and the R1, and a resistance trimming module Trimming is connected between the R0 and the C4;

[0012] The bandgap reference circuit generates a reference voltage V REF The input to the second op amp is V IN An input terminal is connected to the M0 gate, and an output terminal of the second operational amplifier is connected to the M0 gate.

[0013] Further, in a preferred embodiment of the present invention, the analog-to-digital conversion circuit is a Σ-Δ modulator structure of a second-order CIFF structure, and its effective number of bits is 16 bits;

[0014] The Σ-Δ modulator is composed of an adder, an integrator, a one-bit quantizer, a latch circuit and a clock circuit. The integrator, the adder, the one-bit quantizer and the latch circuit are connected in sequence. The clock circuit is the two-phase non-overlapping clock generating circuit. The adder, the integrator and the one-bit quantizer are all connected to the clock circuit, and the clock circuit provides corresponding clock signals to the adder, the integrator and the one-bit quantizer respectively.

[0015] Furthermore, in a preferred embodiment of the present invention, the adder is a switched capacitor adder, which includes 6 first capacitors and multiple first analog switches. The 6 first capacitors are connected in parallel to form 6 branches of the adder, and two of the first analog switches are connected at both ends of each first capacitor.

[0016] Further, in a preferred embodiment of the present invention, the integrator is a switched capacitor integrator, which includes a plurality of second analog switches, four second capacitors and a folded common source and common gate operational amplifier, the four second capacitors are C0, C1, C2 and C3, wherein C0 and C1 are integrating capacitors, and C2 and C3 are sampling capacitors;

[0017] The C0 and the C1 are respectively connected between the input and output ends of the folded cascode operational amplifier in the integrator, and the two ends of the C2 and the C3 are respectively connected to two of the second analog switches, and then respectively connected to the two input ends of the folded cascode operational amplifier.

[0018] Further, in a preferred embodiment of the present invention, the clock signals output by the two-phase non-overlapping clock generating circuit include PH1, PH2, PH1d and PH2d, wherein the PH1 and the PH2 are opposite in phase, and the PH1d and the PH2d are delayed clock signals of the PH1 and the PH2, respectively;

[0019] The frequencies of the four clock signals are all 200KHz signals, and the output end of the two-phase non-overlapping clock generating circuit is connected to the buffer circuit to output the corresponding clock signal.

[0020] The present invention also provides an application of a high-precision integrated temperature sensor circuit, which comprises: configuring the above-mentioned high-precision integrated temperature sensor circuit in a temperature sensor.

[0021] The beneficial effects of a high-precision integrated temperature sensor circuit and application of the present invention are:

[0022] In the design process of the ADC circuit in the present invention, the Matlab Simulink function is first used to perform system-level modeling of the modulator, and then the design is applied to the actual process simulation. This design step can shorten the simulation time. The required order and number of bits of the ADC are first determined based on the modeling test, thereby determining the architecture of the modulator, and then the design is transplanted to the integrated circuit level simulation of Cadence, thereby increasing the design efficiency.

[0023] Furthermore, the key circuit Σ-Δ modulator in the present invention adopts the integrator cascade feedforward structure CIFF. Compared with the CIFB with feedback structure, the signal transfer function (i.e., STF function) of the ADC of the feedforward architecture is close to 1, and only peaks appear at high frequencies, and only a small error signal can pass through the entire loop. Therefore, the amplifier gain in the first-stage integrator can be made relatively large, which can effectively suppress the noise and nonlinearity generated by the subsequent integrator. In addition, each stage of the integrator does not process the feedback signal with high-frequency noise, so the bandwidth requirement for the subsequent stage op amp will be reduced. At the same time, the power consumption required by the CIFF structure is low, and the output swing has better stability due to the structure without feedback.

[0024] Furthermore, the design of the operational amplifier in the bandgap reference source is very important, and the offset of the operational amplifier is a major error source of the reference source. Due to asymmetry, the operational amplifier will be affected by the input offset. The first operational amplifier in the bandgap reference circuit of the present invention is optimized to achieve a higher common mode rejection ratio PSRR and a lower offset, thereby reducing the sensitivity of the temperature detection result to the process. Specifically, in view of the problem of operational amplifier offset, high-order curvature compensation is used to achieve the optimization of operational amplifier offset. Since the bandgap reference circuit in the present invention is a current mode structure, the current generated by the voltage difference of the BE junctions of two parasitic bipolar PNP transistors can be directly used for high-order compensation; in addition, in the problem of improving the common mode rejection ratio, the chopping technology is used. The chopping technology compares the common mode interference in the input signal and the common mode interference in the output signal, and then uses the characteristics of the internal circuit to reduce the common mode interference to a very low level, so the common mode interference in the output signal is greatly reduced, thereby improving the quality and stability of the signal.

[0025] Furthermore, the feedback resistor samples the output voltage of the bandgap circuit and transmits the obtained feedback voltage to the non-inverting input terminal of the second operational amplifier, so that the output voltage of the second operational amplifier changes, thereby adjusting the gate voltage of the M0 transistor. In addition, due to process deviations, some resistors may be mismatched, and the resistance values ​​may deviate from the preset values, thereby affecting the accuracy of the buffer output voltage. To address the above problems, when designing the feedback resistors R0 and R1 in the buffer circuit, a trimming circuit composed of multiple resistors and transistors is added, and the conduction and cutoff of the corresponding MOS switch are controlled by a control signal to adjust the equivalent resistance value of the resistor string, thereby reducing the error caused by the mismatch of the feedback resistors. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 A schematic diagram of a high-precision integrated temperature sensor circuit provided by an embodiment of the present invention;

[0027] Figure 2A circuit diagram of a bandgap reference circuit in a high-precision integrated temperature sensor circuit provided by an embodiment of the present invention;

[0028] Figure 3 is a buffer circuit diagram in an embodiment of the present invention;

[0029] Figure 4 is an operational amplifier circuit in the buffer circuit in the embodiment of the present invention;

[0030] Figure 5 Schematic diagram of the overall structure of a Σ-Δ modulator circuit in an embodiment of the present invention;

[0031] Figure 6 Schematic diagram of the structure of a Σ-Δ modulator with a second-order input feedforward structure in an embodiment of the present invention;

[0032] Figure 7 is a circuit diagram of an operational amplifier in a feedforward Σ-Δ modulator in an embodiment of the present invention;

[0033] Figure 8 is a circuit diagram of an integrator in a feedforward Σ-Δ modulator in an embodiment of the present invention;

[0034] Fig. 9 is a circuit diagram of an adder in a feedforward Σ-Δ modulator in an embodiment of the present invention;

[0035] Fig.10 is a circuit diagram of a quantizer in a feedforward Σ-Δ modulator in an embodiment of the present invention;

[0036] Fig.11 is a latch circuit diagram in a feedforward Σ-Δ modulator in an embodiment of the present invention;

[0037] Fig.12 A two-phase non-overlapping clock circuit diagram in an embodiment of the present invention;

[0038] Fig.13 The figure is an overall circuit diagram of a high-precision integrated temperature sensor provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0039] The technical solutions in the embodiments of the present invention will be described clearly and completely below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, rather than all the embodiments.

[0040] Please refer to Figure 1 and Fig.13, an embodiment of the present invention provides a high-precision integrated temperature sensor circuit, which includes a bandgap reference circuit, a buffer circuit connected to the bandgap reference circuit, an analog-to-digital converter (ADC) circuit connected to the buffer circuit of the buffer, a two-phase non-overlapping clock generation circuit connected to the analog-to-digital conversion circuit, and a FIR digital filter connected to the analog-to-digital conversion circuit. It should be noted that the FIR digital filter, that is, the finite impulse response filter, is designed and implemented using Matlab, and its unit impulse response decays to zero within a finite time, ensuring the stability of the system. It should be emphasized that the FIR digital filter processes the quantized output of the Σ-Δ modulator to obtain a binary number. By induction, a temperature digital code output relationship curve can be obtained, and then a function analytical expression of the output digital code and the actual temperature is obtained by induction, and the measured temperature of the final temperature sensor is obtained.

[0041] For further information, please refer to Figure 2 In an embodiment of the present invention, the bandgap reference circuit includes a startup circuit, a bandgap circuit and a bias circuit, and the startup circuit and the bias circuit are both connected to the bandgap circuit, wherein the startup circuit is connected to the bandgap circuit for starting the bandgap circuit, that is, the bandgap circuit can be started normally; and the bias circuit is connected to the bandgap circuit for providing a suitable bias for the bandgap circuit.

[0042] In addition, the bandgap reference circuit includes a first operational amplifier and two parallel parasitic bipolar PNP transistors, and the two parallel parasitic bipolar PNP transistors are respectively connected to two corresponding input terminals of the first operational amplifier. The structure of the first operational amplifier is a folded common-source common-gate differential operational amplifier; and the parasitic bipolar PNP transistor is a temperature sensing device.

[0043] Further, please refer to Figure 1 , Figure 2 , Figure 3 as well as Figure 4 In an embodiment of the present invention, the buffer circuit includes a second operational amplifier, C4, M0, R0 and R1, wherein the gate of M0 is connected to the output of the second operational amplifier, C4 is connected across the gate and drain of M0, R0 and R1 are connected in series to the drain of M0, the positive input of the second operational amplifier is connected between R0 and R1, and a resistance trimming module is connected between R0 and C4. It should be noted that C4 is a capacitor, M0 is a PMOS transistor, R0 and R1 are fixed resistors; in addition, it should be noted that the reference voltage V generated by the bandgap reference circuit REFThe input to the second op amp is V IN An input terminal is connected to the M0 gate, and an output terminal of the second operational amplifier is connected to the M0 gate.

[0044] For further information, please refer to Figure 5-Figure 11 In an embodiment of the present invention, the analog-to-digital conversion circuit is a Σ-Δ modulator structure of a second-order CIFF structure, and its effective number of bits is 16 bits. Specifically, the Σ-Δ modulator is composed of an adder, an integrator, a one-bit quantizer, a latch circuit and a clock circuit. The integrator, the adder, the one-bit quantizer and the latch circuit are connected in sequence. The clock circuit is the two-phase non-overlapping clock generation circuit. The adder, the integrator and the one-bit quantizer are all connected to the clock circuit, and the clock circuit provides corresponding clock signals to the adder, the integrator and the one-bit quantizer respectively. It should be noted that the quantizer adopts a one-bit quantizer, and the quantizer compares the input analog signal with a fixed reference level. This reference level determines the quantization threshold, and the comparison result will generate a 1-bit digital signal;

[0045] In addition, it should be noted that the latch corresponding to the latch circuit adopts an SR latch composed of a NAND gate, V on1 、V op1 is the latch input, V op 、V on is the latch output. Specifically, the latch is implemented by two cross-coupled NAND gates (NAND1 and NAND2): the output of NAND1 is connected to an input of NAND2, and the output of NAND2 is connected to an input of NAND1; NAND1 and NAND2 each have one remaining input, which is respectively connected to the two outputs V of the one-bit quantizer. on1 and V op1 .

[0046] Further specifically, in an embodiment of the present invention, the adder is a switched capacitor adder, which includes 6 first capacitors and a plurality of first analog switches, the 6 first capacitors are connected in parallel to form 6 branches of the adder, and two ends of each first capacitor are connected to two first analog switches respectively. It should be noted that these first capacitors are charged and discharged under the control of the first analog switches, thereby performing mathematical operations.

[0047] Further specifically, in an embodiment of the present invention, the integrator is a switched capacitor integrator, which includes a plurality of second analog switches, four second capacitors and a folded common source and common gate operational amplifier, the four second capacitors are C0, C1, C2 and C3, wherein C0 and C1 are integrating capacitors, and C2 and C3 are sampling capacitors;

[0048] In addition, the C0 and C1 are respectively connected between the input and output of the folded cascode operational amplifier in the integrator, and the two ends of the C2 and C3 are respectively connected to two of the second analog switches, and then respectively connected to the two input ends of the folded cascode operational amplifier. It should be noted that the folded cascode operational amplifier is used to maintain the voltage stability of the integrator and provide the required gain; the switched capacitor integrator periodically changes the connection mode of the capacitor through the control of the switch to achieve sampling and integration of the input signal.

[0049] For further information, please refer to Fig.12 In an embodiment of the present invention, the clock signals output by the two-phase non-overlapping clock generating circuit include PH1, PH2, PH1d and PH2d, wherein the PH1 and the PH2 are in opposite phases, and the PH1d and the PH2d are delayed clock signals of the PH1 and the PH2, respectively; it should be noted that the frequencies of the four clock signals are all 200KHz signals, and the output end of the two-phase non-overlapping clock generating circuit is connected to the buffer circuit to output the corresponding clock signal.

[0050] The embodiment of the present invention further provides an application of a high-precision integrated temperature sensor circuit, which includes: configuring the above-mentioned high-precision integrated temperature sensor circuit in a temperature sensor, and its specific overall circuit diagram is as follows: Fig.13 It should be emphasized that the temperature sensor in the embodiment of the present invention may be a high-precision integrated temperature sensor, and in other embodiments of the present invention, the temperature sensor may also be other types of temperature sensors, which are specifically subject to actual configuration requirements.

[0051] In addition, in order to make the purpose, technical scheme and advantages of the specific embodiments of the present application clearer, the technical scheme in the specific embodiments of the present application will be described more clearly and completely below. If no specific conditions are specified in the specific embodiments, they shall be carried out under normal conditions or conditions recommended by the manufacturer. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those generally understood by those skilled in the art. The terms used in the specification herein are only for the purpose of describing specific embodiments and are not intended to limit the present application. The term "and / or" used herein includes any and all combinations of one or more related listed items.

[0052] Combined with reference Figures 1 to 13The high-precision integrated temperature sensor circuit of the embodiment of the present invention includes a bandgap reference circuit, a buffer circuit connected to the bandgap reference circuit, an analog-to-digital conversion (ADC) circuit connected to the buffer circuit, a two-phase non-overlapping clock generation circuit connected to the analog-to-digital conversion (ADC) circuit, and a FIR digital filter connected to the analog-to-digital conversion (ADC) circuit. The bandgap reference circuit is used to provide two voltages: a voltage V proportional to temperature and a voltage V PTAT and a temperature-independent reference voltage V REF ; The bandgap reference circuit is divided into three parts: bandgap circuit, startup circuit, and bias circuit. Figure 2 It should be noted that the role of the parasitic transistor in the bandgap reference circuit is to convert the external temperature signal into a one-to-one corresponding voltage signal, and considering the layout factors, the ratio of the emitter junction area of ​​the two parasitic transistors Q0 and Q1 in the circuit is 8:1. The structure of the operational amplifier in the circuit is a folded common source and common gate differential operational amplifier, which provides two feedback loops for the circuit, positive feedback and negative feedback. Due to the "virtual short" of the amplifier input, the potential of the two differential input terminals is the same, making the V BE The difference ΔV BE Reflected in the resistor R 1 The voltage difference between the two ends generates a current I with a positive temperature coefficient. PTAT .

[0053] I PTAT The expression is as follows:

[0054]

[0055] According to formula (1), I PTAT The current mirror is copied to the voltage generation circuit to generate V PTAT and V REF .

[0056] V PTAT The expression is as follows:

[0057] V PTAT =I PTAT R 2 (2)

[0058] V REF The expression is as follows:

[0059]

[0060] In formula (3), N = 8, which is determined by the ratio of the emitter junction area of ​​transistors Q1 and Q2, which is 8:1. BE is the negative temperature coefficient voltage, ΔV BEIt is a positive temperature coefficient voltage. By adjusting the size of resistors R1 and R2, V REF Does not change with temperature, that is And V PTAT Due to its good positive temperature characteristics, after the buffer circuit enhances its load capacity, it will be used as the temperature sensing voltage in this design.

[0061] The bandgap reference circuit generates the V PTAT and V REF , cannot effectively drive the subsequent modulator circuit, and the reference voltage V generated by the bandgap reference circuit REF It is easily affected by the subsequent circuit, so the present invention uses two buffers to process the output voltage of the bandgap reference circuit, such as Figure 3 shown.

[0062] The resistance adjustment module in the buffer is analyzed as follows:

[0063] According to the virtual short and virtual break principle of the second operational amplifier, the voltage at node 3 is:

[0064] V FB =V REF

[0065] Feedback resistor R0, R1 ratio:

[0066]

[0067] M0 Current The resistance values ​​of R0 and R1 are determined in this way. A trimming circuit consisting of resistors R13-R16 and transistors M32-M35 is added to the feedback resistor network. After adding the trimming circuit, the output voltage expression of the buffer is:

[0068]

[0069] Where A 0 -A 3 It is a variable affected by the control signal TRIM0-TRIM3. When the control signal is high, M32-M35 is turned on. At this time, A 0 -A 3 When the control signal is low, M32-M35 is cut off. 0 -A 3 is 1, thereby achieving the adjustment of the feedback resistors R0 and R1.

[0070] The structure of the Σ-Δ modulator of the second-order input feedforward structure is as follows Figure 6 As shown, the response of each node is listed as follows:

[0071]

[0072]

[0073] Y 2 =-(1+Z -1 )Z -1 E (6)

[0074] Y 3 =-Z -2 E (7)

[0075] Y 4 =U+(-2Z -1 +Z -2 )E (8)

[0076] In the above equations, E is the quantization noise of the circuit. From equations (4) to (8), we can see that the loop only needs to deal with the quantization noise, that is, node Y 1 , Y 2 , Y 3 is just a function of quantization noise, while Y 2 , Y 3 is the output of integrator 1 and integrator 2, so the integrator output swing is only affected by the quantization noise, not by the input signal, and the swing is reduced. At the same time, the higher the quantizer accuracy, the smaller the quantization noise, the smaller the integrator swing, and the better the linearity of the modulator. Therefore, the feedforward structure plays a good role in reducing quantization noise, improving signal-to-noise ratio (SNR), and improving linearity. The second-order modulator provides a better noise shaping effect through its loop filter, pushing the quantization noise to a higher frequency, thereby improving the signal-to-noise ratio and dynamic range at low frequencies. In addition, adding a low-pass filter later will greatly reduce the quantization noise. The reduction of quantization noise will lead to a reduction in the integrator swing, thereby improving the linearity of the entire modulator. Therefore, it is necessary to add a feedforward structure to the Σ-Δ modulator.

[0077] The integrator circuit in the feedforward Σ-Δ modulator needs an operational amplifier structure, as shown in the circuit diagram Figure 7 The op amp used here has the same structure as the op amp in the bandgap reference circuit, except that the MOS tube parameters are different. In addition, the amplifier parameters in the first-stage integrator and the second-stage integrator are also different. Because for the first-stage integrator, it is necessary to consider reducing the impact of noise, which is usually achieved by increasing the size of the MOS. In the second-stage integrator, due to the effect of noise shaping, the impact of its noise can be ignored.

[0078] Further, the circuit diagram of the switched capacitor integrator in the feedforward Σ-Δ modulator is as follows: Figure 8, the basic working principle is to convert the analog signal into digital form through the periodic action of the switch, and then process the signal by integration. In the fully differential configuration, the circuit has two identical branches, which process the positive and negative parts of the input signal respectively, so that even-order harmonics and common-mode noise can be effectively suppressed. In the fully differential switched capacitor integrator, sampling capacitors, integrating capacitors and operational amplifiers are usually included. The operational amplifier is used to maintain the voltage stability of the integrator and provide the required gain. The switched capacitor integrator periodically changes the connection mode of the capacitor through the control of the switch to achieve sampling and integration of the input signal. Specifically, the operation of the fully differential switched capacitor integrator can be summarized as follows: in the sampling stage, the switch is closed, the input signal is sampled through the sampling capacitor, and the analog signal is converted into a discrete time signal; in the charge transfer stage, the switch is opened, and the charge on the sampling capacitor is transferred to the integrating capacitor to achieve signal integration; in the feedback stage, the operational amplifier provides feedback to ensure that the output voltage of the integrator remains stable while providing the required gain. In the fully differential configuration, due to the presence of two branches, the errors caused by factors such as device mismatch and temperature change can be effectively offset, thereby improving the overall performance and accuracy of the circuit.

[0079] Further, the circuit diagram of the switched capacitor adder in the feedforward Σ-Δ modulator is as follows: Fig. 9 , the adder uses a combination of capacitors and switches to perform mathematical operations such as addition and subtraction without the use of resistors. Since resistors are not required, the switched capacitor adder can avoid the temperature drift and noise problems caused by resistors, while also reducing the chip area and improving the integration. The specific working process is as follows: It consists of a series of capacitors and switches, which are charged and discharged under the control of the switches. At the beginning of each sampling cycle, the input signal is sampled and stored in the capacitor. The switches of the switched capacitor adder operate according to a specific timing. The opening and closing of the switch causes the charge to be transferred between the capacitors. If the input signal is higher than the reference voltage, the switch transfers the charge from the input capacitor to the output capacitor; if the input signal is lower than the reference voltage, the charge is transferred from the output capacitor to the input capacitor.

[0080] Furthermore, the quantizer circuit diagram in the feedforward Σ-Δ modulator is as follows: Fig.10, the quantizer is one of the core parts of the entire modulator, which is responsible for converting the analog signal into a digital signal. The present invention uses a one-bit quantizer to design a Σ-Δ modulator. Its working process is as follows: the analog signal is first sent to the quantizer. The quantizer compares the input analog signal with a fixed reference level. This reference level determines the quantization threshold. The result of the comparison will generate a 1-bit digital signal. If the analog signal is higher than the reference level, the quantizer outputs a logic "1"; if the analog signal is lower than the reference level, the quantizer outputs a logic "0".

[0081] Furthermore, the latch in the feedforward Σ-Δ modulator works as follows: At the beginning of each sampling period, the latch is activated by a switch (usually controlled by a clock signal), allowing the signal output from the quantizer to pass through and be stored on the capacitor of the latch. Once the signal is sampled and stored, the switch is closed. At this time, even if the input signal changes, the latch output remains unchanged. In this way, the signal output by the latch represents the input value at the sampling moment. The latch circuit diagram used in the present invention is shown in FIG. Fig.11 , that is, the SR latch composed of NAND gates. The latch circuit function is mainly to maintain the output value of the Σ-Δ modulator. OP and V ON It is the output port of the latch and also the output end of the Σ-Δ modulator of this design, which outputs a quantized digital square wave.

[0082] In addition, the two-phase non-overlapping clock circuit designed by the present invention is as follows Fig.12 , where PH1 and PH2 are in opposite phases, PH1d and PH2d are the delayed clock signals of PH1 and PH2 respectively, and PH is a signal with a frequency of 200KHz. In addition, a buffer circuit is added to the output end of the clock circuit. The buffer circuit can provide stronger driving capability and drive more loads to ensure that the clock signal can be stably transmitted to various parts of the circuit. The buffer circuit can also isolate the clock signal source and load, reduce the impact of load changes on the quality of the clock signal, and maintain the stability and integrity of the clock signal.

[0083] Finally, it should be noted that the FIR digital filter designed in the present invention is implemented by Matlab. The quantized output of the Σ-Δ modulator is passed through the FIR digital filter to obtain a binary number. By induction, the corresponding expression between the temperature and the digital code output by the FIR digital filter can be obtained, thereby obtaining the specific output temperature.

[0084] In summary, in the design process of the ADC circuit of the present invention, the Matlab Simulink function is first used to model the modulator at the system level, and then the design is applied to the actual process simulation. This design step can shorten the simulation time. First, the required order and number of bits of the ADC are determined according to the modeling test, so as to determine the architecture of the modulator, and then the design is transplanted to the integrated circuit level simulation of Cadence, thereby increasing the design efficiency. In addition, the key circuit Σ-Δ modulator in the present application adopts the integrator cascade feedforward structure CIFF. Compared with the CIFB with feedback structure, the STF function of the ADC of the feedforward architecture is close to 1, and only peaks will appear at high frequencies. Only a small error signal can pass through the entire loop, so the amplifier gain in the first-stage integrator can be made relatively large, which can effectively suppress the noise and nonlinearity generated by the subsequent integrator. At the same time, each stage of the integrator does not process the feedback signal with high-frequency noise, so the bandwidth requirement of the subsequent stage op amp will be reduced, and the power consumption required by the CIFF structure is low, and the output swing has better stability due to the structure without feedback.

[0085] The above description is only a preferred specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any technician familiar with the technical field can make equivalent replacements or changes according to the technical scheme and inventive concept of the present invention within the technical scope disclosed by the present invention, which should be covered by the protection scope of the present invention.

Claims

1. A high-precision integrated temperature sensor circuit, characterized in that: It includes a bandgap reference circuit, a buffer circuit connected to the bandgap reference circuit, an analog-to-digital conversion circuit connected to the buffer circuit of the buffer, a two-phase non-overlapping clock generating circuit connected to the analog-to-digital conversion circuit, and a FIR digital filter connected to the analog-to-digital conversion circuit.

2. The high-precision integrated temperature sensor circuit according to claim 1, characterized in that: The bandgap reference circuit includes a startup circuit, a bandgap circuit and a bias circuit, wherein the startup circuit and the bias circuit are both connected to the bandgap circuit, wherein the startup circuit is connected to the bandgap circuit for starting the bandgap circuit, and the bias circuit is connected to the bandgap circuit for providing a bias for the bandgap circuit.

3. The high-precision integrated temperature sensor circuit according to claim 2, characterized in that: The bandgap reference circuit includes a first operational amplifier and two parallel parasitic bipolar PNP transistors, and the two parallel parasitic bipolar PNP transistors are respectively connected to two corresponding input terminals of the first operational amplifier.

4. The high-precision integrated temperature sensor circuit according to claim 3, characterized in that: The structure of the first operational amplifier is a folded common-source common-gate differential operational amplifier; the parasitic bipolar PNP transistor is a temperature sensing device.

5. The high-precision integrated temperature sensor circuit according to claim 1, characterized in that: The buffer circuit includes a second operational amplifier, C4, M0, R0 and R1, wherein the gate of M0 is connected to the output terminal of the second operational amplifier, C4 is connected across the gate and drain of M0, R0 and R1 are connected in series and then connected to the drain of M0, the positive input terminal of the second operational amplifier is connected between R0 and R1, and a resistance trimming module Trimming is connected between R0 and C4; The bandgap reference circuit generates a reference voltage V REF The input to the second op amp is V IN An input terminal is connected to the M0 gate, and an output terminal of the second operational amplifier is connected to the M0 gate.

6. The high-precision integrated temperature sensor circuit according to claim 1, characterized in that: The analog-to-digital conversion circuit is a Σ-Δ modulator structure of a second-order CIFF structure, and its effective number of bits is 16 bits; The Σ-Δ modulator is composed of an adder, an integrator, a one-bit quantizer, a latch circuit and a clock circuit. The integrator, the adder, the one-bit quantizer and the latch circuit are connected in sequence. The clock circuit is the two-phase non-overlapping clock generating circuit. The adder, the integrator and the one-bit quantizer are all connected to the clock circuit, and the clock circuit provides corresponding clock signals to the adder, the integrator and the one-bit quantizer respectively.

7. The high-precision integrated temperature sensor circuit according to claim 6, characterized in that: The adder is a switched capacitor adder, which includes six first capacitors and a plurality of first analog switches. The six first capacitors are connected in parallel to form six branches of the adder, and two ends of each first capacitor are connected to two first analog switches respectively.

8. The high-precision integrated temperature sensor circuit according to claim 7, characterized in that: The integrator is a switched capacitor integrator, which includes a plurality of second analog switches, four second capacitors and a folded common-source common-gate operational amplifier, wherein the four second capacitors are C0, C1, C2 and C3, wherein C0 and C1 are integrating capacitors, and C2 and C3 are sampling capacitors; The C0 and the C1 are respectively connected between the input and output ends of the folded cascode operational amplifier in the integrator, and the two ends of the C2 and the C3 are respectively connected to two of the second analog switches, and then respectively connected to the two input ends of the folded cascode operational amplifier.

9. The high-precision integrated temperature sensor circuit according to claim 1, characterized in that: The clock signals output by the two-phase non-overlapping clock generating circuit include PH1, PH2, PH1d and PH2d, wherein the PH1 and the PH2 are in opposite phases, and the PH1d and the PH2d are delayed clock signals of the PH1 and the PH2 respectively; The frequencies of the four clock signals are all 200KHz signals, and the output end of the two-phase non-overlapping clock generating circuit is connected to the buffer circuit to output the corresponding clock signal.

10. An application of a high-precision integrated temperature sensor circuit, characterized in that: The high-precision integrated temperature sensor circuit described in any one of claims 1 to 9 is configured in a temperature sensor.

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