Performance testing and screening method for computing chip

Abstract

The invention provides a performance testing and screening method for a computing chip. The method comprises the steps that a reference chip and a chip to be tested are connected into a loop through an HSIO interface, and the loop is used for achieving data communication between the reference chip and the chip to be tested; the reference chip and the to-be-tested chip operate corresponding performance test software according to a performance test instruction sent by the remote computer to respectively obtain performance parameters of the reference chip and the to-be-tested chip, and the performance parameters are uploaded to the remote computer; and the remote computer determines whether the to-be-tested chip is a qualified chip or not by comparing the performance parameters of the reference chip and the to-be-tested chip, and rejects the unqualified to-be-tested chip. According to the invention, the to-be-tested chips are screened based on comparison of the performance parameters of the reference chip and the to-be-tested chips, so that the screening precision can be improved; one reference chip is connected with a plurality of chips to be tested at the same time, so that the speed of performance parameter measurement and chip screening of the chips to be tested can be obviously improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of computing chip performance testing, and in particular relates to a computing chip performance testing and screening method. Background Art

[0002] With the rise of scientific and technological revolution and industrial transformation, the new generation of information technology industry has risen rapidly, and the digital transformation of various industries has accelerated. As the core of the digital economy, the construction of computing power can stimulate the innovative vitality of data elements, give birth to new technologies and new industries, and support high-quality economic development. New technologies, new industries, and high development are inseparable from the assistance and support of modern scientific computing tools. Among them, supercomputers, as a high-performance computing device, are particularly suitable for processing large-scale, high-concurrency computing tasks, and are an important part of the computing power infrastructure. It can complete a large number of complex calculations in a very short time, and is widely used in science, engineering, technology and other fields. It is of great significance to promote the digitalization process and the healthy development of the economy.

[0003] At present, most of the mainstream supercomputer architectures use a two-dimensional computing space composed of general-purpose chips. Their computing efficiency and communication efficiency in three-dimensional microscopic particle simulation are too low, and their energy consumption is huge, which cannot meet the needs of three-dimensional simulation scientific computing. In order to further improve computing efficiency and performance, countries have begun to develop supercomputers or 3D scientific computers with three-dimensional computing space. Such supercomputers or 3D scientific computers can make full use of computing resources in three-dimensional space, achieve higher density computing and more efficient energy efficiency, and provide more powerful computing support for various industries.

[0004] The performance of 3D scientific computers depends to a large extent on the quality of computing chips, so it is very necessary to select high-quality computing chips. To this end, the present invention provides a performance test and screening method for computing chips. Summary of the invention

[0005] In order to solve the above problems existing in the prior art, the present invention provides a performance testing and screening method for a computing chip.

[0006] In order to achieve the above object, the present invention adopts the following technical solutions.

[0007] A performance testing and screening method for a computing chip comprises the following steps:

[0008] The reference chip and the chip under test mounted on the test circuit board are connected into a loop through the HSIO interface to realize data communication between the reference chip and the chip under test;

[0009] The remote computer sends a performance test instruction signal to the reference chip and the chip to be tested through the network, and the reference chip and the chip to be tested receive the signal and parse the performance test instruction therefrom;

[0010] The reference chip and the chip to be tested run corresponding performance testing software according to the performance testing instruction to obtain performance parameters of the reference chip and the chip to be tested respectively, and upload the performance parameters to a remote computer;

[0011] The remote computer determines whether the chip to be tested is a qualified chip by comparing the performance parameters of the reference chip and the chip to be tested, and eliminates unqualified chips to be tested.

[0012] Furthermore, the performance parameters include:

[0013] High-speed transmission performance parameters: used to verify chip data transmission latency, throughput and error rate;

[0014] Core computing performance parameters: used to verify the computing power of the chip;

[0015] Accumulated performance parameters: used to verify the consistency of chip calculation results by using the same test method;

[0016] Frequency adjustment performance parameters: used to adjust the chip's main frequency to verify the chip's computing efficiency, power consumption and temperature under different main frequencies;

[0017] Buck-boost performance parameters: used to verify the chip's computing efficiency, power consumption and temperature under different voltage conditions by adjusting the chip's operating voltage.

[0018] Furthermore, each benchmark chip and the chip under test is configured with 6 HSIO interfaces, namely HSIO0, HSIO1, HSIO2, HSIO3, HSIO4 and HSIO5.

[0019] Furthermore, by setting the polarity of the HSIO interface, the six HSIO interfaces of the benchmark chip are set to X0+, X0-, Y0+, Y0-, Z0+, and Z0-, and the six HSIO interfaces of the chip to be tested are set to X1+, X1-, Y1+, Y1-, Z1+, and Z1-, respectively; by connecting X0+ with X1-, X0- with X1+, Y0+ with Y1-, Y0- with Y1+, and Z0+ with Z1-, and Z0- with Z1+, a three-dimensional computing space with six axes of X+, X-, Y+, Y-, Z+, and Z- can be established.

[0020] Furthermore, the (n+1) 3 The chips are connected through the HSIO interface to form a cube three-dimensional computing space, and the edges of each dimension of the cube are provided with n+1 chips interconnected into a loop through the HSIO interface; wherein, numbers 000 to nnn are n+1 base numbers, and the chips include a reference chip and a chip to be tested.

[0021] Furthermore, at least one reference chip and one chip to be tested are arranged on the test circuit board, and one reference chip is connected to at least one chip to be tested and is connected to at most 6 chips to be tested.

[0022] Furthermore, the test circuit board is also provided with a serial port COM, a network LAN and a DC power supply.

[0023] Furthermore, the method of obtaining high-speed transmission performance parameters using performance testing software includes:

[0024] The reference chip sends data to the chip under test connected to it through the HSIO interface;

[0025] After receiving the data sent by the reference chip, the chip under test returns the data to the reference chip through the HSIO interface;

[0026] The performance testing software is used to calculate the high-speed transmission performance parameters of the benchmark chip and the chip under test, including transmission delay, throughput and error rate.

[0027] Furthermore, the method further comprises:

[0028] If the chip under test does not receive the data after the reference chip sends the data, the chip under test is considered to be an unqualified chip;

[0029] If the reference chip does not receive the returned data after the chip under test returns data to the reference chip, the chip under test is considered to be a failed chip.

[0030] Furthermore, the method for determining whether the chip to be tested is a qualified chip according to the performance parameter test result includes:

[0031] If the performance parameters of the chip under test are better than the performance parameters of the reference chip, the chip under test is a qualified chip;

[0032] If the performance parameters of the chip under test are inferior to those of the reference chip, the difference between the two performance parameters is calculated. If the absolute value of the difference is less than a set threshold, the chip under test is a qualified chip; otherwise, it is an unqualified chip.

[0033] Compared with the prior art, the present invention has the following beneficial effects.

[0034] The present invention connects a reference chip and a chip to be tested into a loop through an HSIO interface to realize data communication between the reference chip and the chip to be tested. A remote computer sends a performance test instruction signal to the reference chip and the chip to be tested through a network. The reference chip and the chip to be tested run corresponding performance test software according to the performance test instruction to obtain performance parameters of the reference chip and the chip to be tested respectively. The remote computer determines whether the chip to be tested is a qualified chip by comparing the performance parameters of the reference chip and the chip to be tested, and removes unqualified chips to be tested, thereby realizing performance testing and screening of computing chips. The present invention can improve the screening accuracy of the chip to be tested by simultaneously measuring the performance parameters of the reference chip and the chip to be tested connected through HSIO, and screening the chip to be tested based on the comparison of the performance parameters of the two chips; by connecting a reference chip to multiple chips to be tested at the same time, the speed of measuring the performance parameters of the chip to be tested and the speed of chip screening can be significantly improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 The present invention is a flowchart of a method for testing and screening performance of a computing chip according to an embodiment of the present invention.

[0036] Figure 2 This is a schematic diagram of the hardware structure of the test circuit board.

[0037] Figure 3 Schematic diagram of a three-dimensional computing space consisting of 8×8×8 interconnected computing chips.

[0038] Figure 4 Schematic diagram of connecting a reference chip M0 to multiple chips M1 to be tested. DETAILED DESCRIPTION

[0039] In order to make the purpose, technical solution and advantages of the present invention clearer and more understandable, the present invention is further described below in conjunction with the accompanying drawings and specific implementation methods. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0040] Figure 1 This is a flow chart of a performance test and screening method for a computing chip according to an embodiment of the present invention, comprising the following steps:

[0041] Step 101, connecting the reference chip and the chip under test mounted on the test circuit board into a loop through the HSIO interface to achieve data communication between the reference chip and the chip under test;

[0042] Step 102, the remote computer sends a performance test instruction signal to the reference chip and the chip under test through the network, and the reference chip and the chip under test receive the signal and parse the performance test instruction therefrom;

[0043] Step 103, the reference chip and the chip to be tested run corresponding performance testing software according to the performance testing instruction to obtain performance parameters of the reference chip and the chip to be tested respectively, and upload the performance parameters to a remote computer;

[0044] Step 104 , the remote computer determines whether the chip to be tested is a qualified chip by comparing the performance parameters of the reference chip and the chip to be tested, and removes unqualified chips to be tested.

[0045] In this embodiment, step 101 is mainly used to set up test equipment. In this embodiment, a test circuit board is used to perform performance testing of a computing chip. The test circuit board mainly includes a reference chip and a chip to be tested. The reference chip is a verified and reliable chip, and its various performance indicators meet the requirements. The reference chip and the chip to be tested are connected to form a loop through their respective HSIO (High Speed ​​Input / Output) interfaces, thereby realizing two-way data communication between the reference chip and the chip to be tested. The loop is formed by connecting the input port and output port of an HSIO interface of the reference chip to the output port and input port of an HSIO interface of the chip to be tested, respectively.

[0046] In this embodiment, step 102 is mainly used for sending and receiving instructions. The performance test of this embodiment is remotely controlled by a remote computer. The remote computer sends a signal containing a performance test instruction to the reference chip and the chip to be tested through the network. The reference chip and the chip to be tested receive the signal and parse the performance test instruction therefrom.

[0047] In this embodiment, step 103 is mainly used to perform performance testing on the reference chip and the chip to be tested. In this embodiment, the performance testing software is used to perform performance testing on the reference chip and the chip to be tested. The performance testing instruction includes performance parameters to be tested, and different performance parameters correspond to different testing methods. The reference chip and the chip to be tested respectively obtain the performance parameters of the reference chip and the chip to be tested by running the corresponding testing method in the performance testing software, and upload the performance parameters to the remote computer.

[0048] In this embodiment, step 104 is mainly used to screen the chips to be tested based on the performance test results and select qualified chips to be tested. In this embodiment, the chip screening is implemented by a remote computer, and by comparing the performance parameters of the reference chip and the chip to be tested, the chips to be tested whose performance parameters are close to the performance parameters of the reference chip are identified as qualified chips, and unqualified chips to be tested are eliminated.

[0049] The existing computing chip performance test method and chip screening method are generally only performed on the chip to be tested, that is, only the chip to be tested is provided on the test circuit board. In this embodiment, a reference chip connected to the chip to be tested through an HSIO interface is set, and the performance parameters of the reference chip and the chip to be tested are measured at the same time. The chip to be tested is screened based on the comparison of the two performance parameters, which can improve the screening accuracy of the chip to be tested relative to the prior art. The technical principle is: the prior art only measures the performance parameters of the chip to be tested, and then compares the performance parameters of the chip to be tested with the set threshold value to determine whether the chip to be tested is a qualified chip. Since the performance parameters obtained in different test environments are also different, it is difficult to ensure the screening accuracy of the chip under different test environments by using a fixed set threshold value. In this embodiment, a reference chip is set in the same test environment as the chip to be tested, and the performance parameters of the measured chip to be tested and the reference chip are compared to determine whether the chip to be tested is a qualified chip, which can solve the above-mentioned problems existing in the prior art, thereby improving the screening accuracy of the chip. In addition, this embodiment is connected to multiple chips to be tested at the same time through a reference chip, which can significantly improve the speed of measuring the performance parameters of the chip to be tested and chip screening relative to the prior art.

[0050] As an optional embodiment, the performance parameters include:

[0051] High-speed transmission performance parameters: used to verify chip data transmission latency, throughput and error rate;

[0052] Core computing performance parameters: used to verify the computing power of the chip;

[0053] Accumulated performance parameters: used to verify the consistency of chip calculation results by using the same test method;

[0054] Frequency adjustment performance parameters: used to adjust the chip's main frequency to verify the chip's computing efficiency, power consumption and temperature under different main frequencies;

[0055] Buck-boost performance parameters: used to verify the chip's computing efficiency, power consumption and temperature under different voltage conditions by adjusting the chip's operating voltage.

[0056] This embodiment provides several commonly used performance parameters of computing chips, including high-speed transmission performance parameters, core computing performance parameters, accumulation performance parameters, frequency-up / down performance parameters, and voltage-down / down performance parameters. The functions of the performance parameters per ton are as above and will not be repeated here.

[0057] As an optional embodiment, each of the reference chip and the chip under test is configured with six HSIO interfaces, namely HSIO0, HSIO1, HSIO2, HSIO3, HSIO4 and HSIO5.

[0058] This embodiment limits the number of HSIO interfaces of the reference chip and the chip to be tested. In this embodiment, six HSIO interfaces are configured for each reference chip and the chip to be tested, which are respectively recorded as HSIO0, HSIO1, HSIO2, HSIO3, HSIO4 and HSIO5.

[0059] As an optional embodiment, by setting the polarity of the HSIO interface, the six HSIO interfaces of the reference chip are set to X0+, X0-, Y0+, Y0-, Z0+, and Z0-, and the six HSIO interfaces of the chip to be tested are set to X1+, X1-, Y1+, Y1-, Z1+, and Z1-; by connecting X0+ with X1-, X0- with X1+, Y0+ with Y1-, Y0- with Y1+, and Z0+ with Z1-, and Z0- with Z1+, a three-dimensional computing space with six axes of X+, X-, Y+, Y-, Z+, and Z- can be established.

[0060] This embodiment provides a technical solution for connecting a reference chip and a chip to be tested into a three-dimensional computing space with six axes: X+, X-, Y+, Y-, Z+, and Z-. Since each reference chip and chip to be tested are provided with six HSIO interfaces, by defining the polarity of the six HSIO interfaces, each chip can have six axes: X+, X-, Y+, Y-, Z+, and Z-. When simulating chip operations in the X dimension, the HSIO of the standard chip and the chip to be tested are defined as X+ and X-; when simulating chip operations in the Y dimension, the HSIO of the standard chip and the chip to be tested are defined as Y+ and Y_; when simulating chip operations in the Z dimension, the HSIO of the standard chip and the chip to be tested are defined as Z+ and Z-. The chips are connected to each other in pairs to form a three-dimensional computing space, such as Figure 3 shown.

[0061] As an optional embodiment, the (n+1) numbered from 000 to nnn 3 The chips are connected through the HSIO interface to form a cube three-dimensional computing space, and the edges of each dimension of the cube are provided with n+1 chips interconnected into a loop through the HSIO interface; wherein, numbers 000 to nnn are n+1 base numbers, and the chips include a reference chip and a chip to be tested.

[0062] This embodiment provides a technical solution for connecting the reference chip and the chip to be tested into a cube three-dimensional computing space. The side length of the cube is n+1, and each side of the cube has n+1 chips interconnected into a loop through the HSIO interface. The cube contains a total of (n+1) 3 The chips are numbered from 000 to nnn, and the numbers 000 to nnn are n+1 numbers. When n=7, the cube is as follows Figure 3 As shown, the chip numbers are 000 to 777, a total of 83 A chip.

[0063] As an optional embodiment, at least one reference chip and one chip to be tested are provided on the test circuit board, and one reference chip is connected to at least one chip to be tested and is connected to at most six chips to be tested.

[0064] This embodiment limits the number of reference chips and chips to be tested on the test circuit board. In this embodiment, at least one reference chip and one chip to be tested connected via the HSIO interface are installed; in order to improve the performance test of the computing chip and the chip screening speed, multiple reference chips can be installed, and each reference chip can be connected to up to 6 chips to be tested. The schematic diagram of the connection between the reference chip M0 and multiple chips to be tested M1 is shown in FIG. Figure 4 shown.

[0065] As an optional embodiment, the test circuit board is also provided with a serial port COM, a network LAN and a DC power supply.

[0066] This embodiment provides the hardware structure of the test circuit board. Figure 2 As shown in the figure, the test circuit board includes not only the reference chip and the chip to be tested (the number can be multiple) and the HSIO interface, but also the serial port COM, the network LAN and the DC power supply. The DC power supply supplies power to the mainboard and the chip, and the serial port COM and the network LAN are used for chip debugging, configuration and sending of relevant parameters, and obtaining test results.

[0067] As an optional embodiment, the method of obtaining high-speed transmission performance parameters using performance testing software includes:

[0068] The reference chip sends data to the chip under test connected to it through the HSIO interface;

[0069] After receiving the data sent by the reference chip, the chip under test returns the data to the reference chip through the HSIO interface;

[0070] The performance testing software is used to calculate the high-speed transmission performance parameters of the benchmark chip and the chip under test, including transmission delay, throughput and error rate.

[0071] This embodiment provides a technical solution for measuring high-speed transmission performance parameters. This embodiment uses performance testing software to measure the high-speed transmission performance parameters of computing chips. After receiving the high-speed transmission performance parameter measurement instruction sent by the remote computer, the reference chip sends data to the corresponding interface of the chip to be tested connected to it through the HSIO interface, and the chip to be tested receives the data sent by the reference chip through the HSIO interface and returns data to the reference chip. The performance testing software measures the interface transceiver performance indicators according to the set measurement scheme, including transmission delay, throughput, error rate, etc.

[0072] As an optional embodiment, the method further includes:

[0073] If the chip under test does not receive the data after the reference chip sends the data, the chip under test is considered to be an unqualified chip;

[0074] If the reference chip does not receive the returned data after the chip under test returns data to the reference chip, the chip under test is considered to be a failed chip.

[0075] This embodiment provides a solution or pre-screening solution for quickly screening unqualified chips. The so-called pre-screening refers to a preliminary screening performed before performing chip performance parameter testing, identifying a portion of unqualified chips from the chips to be tested, eliminating these unqualified chips, reducing the chips for performance testing, and thus improving the speed of performance testing and chip screening. The technical principle of preliminary screening is to determine whether the reference chip and the chip to be tested can perform normal data communication. If not, since the reference chip is normal, the abnormal chip must be the chip to be tested. The method for determining whether normal data communication can be performed is based on whether the chip to be tested can receive the data sent by the reference chip and whether the reference chip can receive the return data from the chip to be tested. Since the method for detecting whether normal data communication can be performed is much simpler and less time-consuming than the method for performing performance testing, preliminary screening can reduce the total performance testing time.

[0076] As an optional embodiment, a method for determining whether a chip to be tested is a qualified chip according to a performance parameter test result includes:

[0077] If the performance parameters of the chip under test are better than the performance parameters of the reference chip, the chip under test is a qualified chip;

[0078] If the performance parameters of the chip under test are inferior to those of the reference chip, the difference between the two performance parameters is calculated. If the absolute value of the difference is less than a set threshold, the chip under test is a qualified chip; otherwise, it is an unqualified chip.

[0079] This embodiment provides a technical solution for determining whether the chip to be tested is a qualified chip. This embodiment determines whether the chip to be tested is a qualified chip by comparing the performance parameters of the reference chip and the chip to be tested according to the performance parameter test results. The specific comparison method is: if the performance parameters of the chip to be tested are better than the performance parameters of the reference chip, the chip to be tested must be a qualified chip; if the performance parameters of the chip to be tested are worse than the performance parameters of the reference chip, but the difference is small (less than a set threshold), the chip to be tested can also be considered a qualified chip; if the difference is large (exceeding the set threshold), it is considered an unqualified chip.

[0080] It is worth mentioning that when comparing performance parameters here, we use "better than" and "worse than" instead of "greater than" and "less than". The reason is that for some performance parameters, the larger the better, such as computing efficiency; while for some performance parameters, the smaller the better, such as error rate.

[0081] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A performance testing and screening method for a computing chip, characterized in that: The following steps are involved: The reference chip and the chip under test mounted on the test circuit board are connected into a loop through the HSIO interface to realize data communication between the reference chip and the chip under test; The remote computer sends a performance test instruction signal to the reference chip and the chip to be tested through the network, and the reference chip and the chip to be tested receive the signal and parse the performance test instruction therefrom; The reference chip and the chip to be tested run corresponding performance testing software according to the performance testing instruction to obtain performance parameters of the reference chip and the chip to be tested respectively, and upload the performance parameters to a remote computer; The remote computer determines whether the chip to be tested is a qualified chip by comparing the performance parameters of the reference chip and the chip to be tested, and eliminates unqualified chips to be tested.

2. The performance testing and screening method of computing chips according to claim 1, characterized in that: The performance parameters include: High-speed transmission performance parameters: used to verify chip data transmission latency, throughput and error rate; Core computing performance parameters: used to verify the computing power of the chip; Accumulated performance parameters: used to verify the consistency of chip calculation results by using the same test method; Frequency adjustment performance parameters: used to adjust the chip's main frequency to verify the chip's computing efficiency, power consumption and temperature under different main frequencies; Buck-boost performance parameters: used to verify the chip's computing efficiency, power consumption and temperature under different voltage conditions by adjusting the chip's operating voltage.

3. The performance testing and screening method of computing chips according to claim 1, characterized in that: Each benchmark chip and the chip under test are configured with six HSIO interfaces, namely HSIO0, HSIO1, HSIO2, HSIO3, HSIO4 and HSIO5.

4. The performance testing and screening method of computing chips according to claim 3, characterized in that: By setting the polarity of the HSIO interface, the six HSIO interfaces of the benchmark chip are set to X0+, X0-, Y0+, Y0-, Z0+, and Z0-, and the six HSIO interfaces of the chip to be tested are set to X1+, X1-, Y1+, Y1-, Z1+, and Z1-; by connecting X0+ with X1-, X0- with X1+, Y0+ with Y1-, Y0- with Y1+, Z0+ with Z1-, and Z0- with Z1+, a three-dimensional computing space with six axes of X+, X-, Y+, Y-, Z+, and Z- can be established.

5. The performance testing and screening method of computing chips according to claim 4, characterized in that: The (n+1) numbers from 000 to nnn 3 The chips are connected through the HSIO interface to form a cube three-dimensional computing space, and n+1 chips interconnected into a loop through the HSIO interface are arranged on the edge of each dimension of the cube; wherein, numbers 000 to nnn are n+1 base numbers, and the chips include a reference chip and a chip to be tested.

6. The performance testing and screening method of computing chips according to claim 3, characterized in that: The test circuit board is provided with at least one reference chip and one chip to be tested. One reference chip is connected to at least one chip to be tested and is connected to at most 6 chips to be tested.

7. The performance testing and screening method of computing chips according to claim 1, characterized in that: The test circuit board is also provided with a serial port COM, a network LAN and a direct current power supply.

8. The performance testing and screening method of computing chips according to claim 2, characterized in that: Methods for obtaining high-speed transmission performance parameters using performance testing software include: The reference chip sends data to the chip under test connected to it through the HSIO interface; After receiving the data sent by the reference chip, the chip under test returns the data to the reference chip through the HSIO interface; The performance testing software is used to calculate the high-speed transmission performance parameters of the benchmark chip and the chip under test, including transmission delay, throughput and error rate.

9. The method for performance testing and screening of computing chips according to claim 8, characterized in that: The method further comprises: If the chip under test does not receive the data after the reference chip sends the data, the chip under test is considered to be an unqualified chip; If the reference chip does not receive the returned data after the chip under test returns data to the reference chip, the chip under test is considered to be a failed chip.

10. The performance testing and screening method of computing chips according to claim 1, characterized in that: The method for determining whether the chip to be tested is a qualified chip according to the performance parameter test results includes: If the performance parameters of the chip under test are better than the performance parameters of the reference chip, the chip under test is a qualified chip; If the performance parameters of the chip under test are inferior to those of the reference chip, the difference between the two performance parameters is calculated. If the absolute value of the difference is less than a set threshold, the chip under test is a qualified chip; otherwise, it is an unqualified chip.

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