Chip, memory access method and device, consistency management module and computer equipment

Abstract

The embodiment of the invention provides a chip, a memory access method and device, a consistency management module and computer equipment, and the chip comprises an address transmission network which is used for routing a memory access address to the consistency management module; the network-on-chip is used for routing the memory access request of the CPU core to the consistency management module; the routing speed of the address transmission network is higher than that of the network-on-chip; the consistency management module is used for acquiring a predictive memory access request, and the predictive memory access request is generated based on the memory access address; transmitting the predictive memory access request to a memory control module, and obtaining predictive data prefetched from a memory by the memory control module based on the predictive memory access request; storing the prediction data and the corresponding memory access address; judging whether memory access data requested by the memory access request is prefetched or not; and if yes, taking the stored prediction data of the memory access address corresponding to the memory access request as memory access data, and feeding back the memory access data to the CPU core through the network-on-chip. According to the embodiment of the invention, the memory access delay of the CPU core can be reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the field of on-chip network technology, and specifically to a chip, a memory access method, an apparatus, a consistency management module, and a computer device. Background Art

[0002] Network on Chip (NoC) is a communication architecture used to connect multiple functional modules in chips such as SOC (System on Chip). That is, the functional modules in the chip can be interconnected through the network on chip.

[0003] The functional modules in the chip that access the on-chip network can be regarded as nodes of the on-chip network. For example, the CPU (Central Processing Unit) core and the memory control module in the chip can be used as nodes to access the on-chip network, so as to interact through the on-chip network to realize the memory access requirements of the CPU core (memory access requirements are the requirements to access the memory). In this context, the memory access latency of the CPU core is a key indicator for chip performance optimization. How to provide a technical solution to reduce the memory access latency of the CPU core has become a technical problem that technicians in this field urgently need to solve. Summary of the invention

[0004] In view of this, embodiments of the present application provide a chip, a memory access method, an apparatus, a consistency management module, and a computer device to reduce the memory access latency of the CPU core, thereby optimizing chip performance.

[0005] To achieve the above objectives, the embodiments of the present application provide the following technical solutions.

[0006] In a first aspect, an embodiment of the present application provides a chip, including:

[0007] An address transmission network is used to obtain a memory access address and route the memory access address to a consistency management module;

[0008] The on-chip network is used to route the memory access request of the CPU core to the consistency management module; wherein the routing speed of the address transmission network is faster than that of the on-chip network;

[0009] The consistency management module is used to:

[0010] Obtaining a predictive memory access request, the predictive memory access request is generated based on a memory access address output by an address transmission network; transmitting the predictive memory access request to a memory control module so that the memory control module pre-fetches predicted data from the memory based on the predictive memory access request; obtaining predicted data pre-fetched from the memory by the memory control module based on the predictive memory access request; saving the predicted data and the corresponding memory access address;

[0011] And, obtain the memory access request of the CPU core routed by the on-chip network, and determine whether the memory access data requested by the memory access request is pre-fetched; if so, use the saved prediction data of the memory access address corresponding to the memory access request as the memory access data of the memory access request, and feed back the memory access data of the memory access request to the CPU core through the on-chip network.

[0012] In a second aspect, an embodiment of the present application provides a memory access method, which is applied to a consistency management module, and the method includes:

[0013] Obtaining a predictive memory access request, the predictive memory access request is generated based on a memory access address output by an address transmission network; transmitting the predictive memory access request to a memory control module so that the memory control module pre-fetches predicted data from the memory based on the predictive memory access request; obtaining predicted data pre-fetched from the memory by the memory control module based on the predictive memory access request; saving the predicted data and the corresponding memory access address;

[0014] and obtaining a memory access request of a CPU core routed by the on-chip network, and determining whether the memory access data requested by the memory access request is pre-fetched; if so, using the saved prediction data of the memory access address corresponding to the memory access request as the memory access data of the memory access request, and feeding back the memory access data of the memory access request to the CPU core through the on-chip network;

[0015] Among them, the routing speed of the address transmission network is faster than that of the on-chip network.

[0016] In a third aspect, an embodiment of the present application provides a memory access device, which is applied to a consistency management module, and the device includes:

[0017] A prefetch processing logic unit is used to obtain a predictive memory access request, which is generated based on a memory access address output by an address transmission network; transmit the predictive memory access request to a memory control module so that the memory control module prefetches predicted data from the memory based on the predictive memory access request; obtain the predicted data prefetched from the memory by the memory control module based on the predictive memory access request; and save the predicted data and the corresponding memory access address;

[0018] A memory access request processing logic unit is used to obtain a memory access request of a CPU core routed by the on-chip network, and determine whether the memory access data requested by the memory access request is pre-fetched; if so, the saved prediction data of the memory access address corresponding to the memory access request is used as the memory access data of the memory access request, and the memory access data of the memory access request is fed back to the CPU core through the on-chip network;

[0019] Among them, the routing speed of the address transmission network is faster than that of the on-chip network.

[0020] In a fourth aspect, an embodiment of the present application provides a consistency management module, which is configured to execute the memory access method as described in the second aspect above, or the consistency management module is provided with a memory access device as described in the third aspect above.

[0021] In a fifth aspect, an embodiment of the present application provides a computer device, comprising the chip as described in the first aspect above.

[0022] In an embodiment of the present application, in addition to the on-chip network, the chip is also provided with an address transmission network, and the routing speed of the address transmission network is faster than that of the on-chip network, so that the address transmission network can be used to obtain the memory access address and route the memory access address to the consistency management module; the on-chip network can be used to route the memory access request of the CPU core to the consistency management module; the consistency management module can obtain the predictive memory access request, and the predictive memory access request is generated based on the memory access address output by the address transmission network; the predictive memory access request is transmitted to the memory control module, so that the memory control module pre-fetches the predicted data from the memory based on the predictive memory access request; thus, the consistency management module can obtain the predicted data pre-fetched from the memory by the memory control module based on the predictive memory access request, and save the predicted data and the corresponding memory access address; further, the consistency management module obtains the memory access request of the CPU core routed by the on-chip network. When requesting, since the embodiment of the present application can pre-fetch predicted data from the memory based on the predictive memory access request, and the routing speed of the address transmission network is faster than the on-chip network, when the memory access request routed by the on-chip network reaches the consistency management module, the memory access data requested by the memory access request may have been pre-fetched. Therefore, when the consistency management module obtains the memory access request routed by the on-chip network, it can determine whether the memory access data requested by the memory access request is pre-fetched; if the memory access data requested by the memory access request is pre-fetched, the consistency management module can use the saved predicted data of the memory access address corresponding to the memory access request as the memory access data of the memory access request, and feed back the memory access data of the memory access request to the CPU core through the on-chip network, thereby avoiding the process of accessing the memory based on the memory access request routed by the on-chip network, reducing the waiting time from the CPU core issuing the memory access request to obtaining the memory access data, and shortening the memory access delay of the CPU core.

[0023] It can be seen that in the embodiment of the present application, the routing speed of the address transmission network is faster than the on-chip network, so that the address transmission network can speed up the routing speed of the memory access address, support the embodiment of the present application to generate predictive memory access requests in advance and pre-fetch predicted data from the memory in advance, so that the consistency management module can save the predicted data pre-fetched from the memory and the corresponding memory access address; further, when the formal memory access request reaches the consistency management module through the on-chip network, if the consistency management module finds that the memory access data requested by the memory access request has been pre-fetched, the consistency management module can directly obtain the predicted data of the memory access address corresponding to the memory access request from the saved predicted data as the memory access data of the memory access request, thereby avoiding the delay of the consistency management module reading the memory access data from the memory after obtaining the memory access request, and shortening the memory access delay of the CPU core. Therefore, the chip provided in the embodiment of the present application adopts the architecture design of the on-chip network and the address transmission network, as well as the data pre-fetching control strategy of the consistency management module, which can process the memory access address routed by the address transmission network separately from the formal memory access request routed by the on-chip network, thereby optimizing the load of the on-chip network, shortening the memory access delay of the CPU core, and optimizing the chip performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

[0025] Figure 1A This is an example diagram of the chip architecture provided in an embodiment of the present application.

[0026] Figure 1B Another example diagram of the architecture of the chip provided in an embodiment of the present application.

[0027] Figure 2 This is another example diagram of the architecture of the chip provided in an embodiment of the present application.

[0028] Figure 3 This is an example diagram of the settings of the second address injection module.

[0029] Figure 4 A flowchart of a memory access method provided in an embodiment of the present application.

[0030] Figure 5 A block diagram of a memory access device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] To understand the chip architecture that uses on-chip networks, Figure 1A The following is an exemplary diagram showing the architecture of the chip provided in the embodiment of the present application, as shown in FIG. Figure 1A As shown, the architecture of the chip may include: an on-chip network 100 and multiple nodes. The on-chip network 100 is used to connect multiple functional modules in the chip, and the functional modules in the chip that are connected to the on-chip network are regarded as nodes of the on-chip network, that is, the functional modules in the chip that are connected to the on-chip network and communicate through the on-chip network are collectively referred to as nodes of the on-chip network.

[0033] For example, nodes of the network on chip include but are not limited to:

[0034] IP (Intellectual Property) cores, such as CPU (Central Processing Unit) cores, GPU (Graphics Processing Unit) cores, etc.

[0035] Memory control module (i.e., memory controller), which is responsible for managing access operations to memory such as DDR (Double Data Rate) and DRAM (Dynamic Random Access Memory). For example, the memory control module can process the read and write requests of the CPU core and perform memory scheduling. The memory can be located off-chip (i.e., outside the chip). It can be seen that the memory control module can communicate with the CPU core through the on-chip network to meet the memory access requirements of the CPU core.

[0036] IO (input and output) modules, such as network interfaces and USB (Universal Serial Bus) controllers, which exchange data with other nodes on the chip network through the chip network;

[0037] Accelerators, such as ISP (Image Signal Processor), encryption unit and other dedicated accelerators, which participate in the data processing tasks of the chip through the on-chip network;

[0038] The consistency management module, also known as the consistency root node, is used to manage cache consistency between multiple CPU cores. In a multi-core CPU (i.e., a CPU with multiple CPU cores), cache consistency means that the data copies of the same memory address in the independent caches of the multiple CPU cores should remain consistent. Specifically, the multiple CPU cores have their own independent caches (such as L1 caches), and the multiple CPU cores have a shared cache (such as L2 caches or L3 caches). When any CPU core modifies the data in the independent cache, the consistency management module can use the cache consistency protocol to update or mark the corresponding data in the independent caches of other CPU cores and the shared cache as invalid, thereby ensuring that the data in the shared cache is consistent with the data copies in the independent caches of each CPU core, avoiding errors caused by data inconsistency.

[0039] Taking the CPU core memory access scenario as an example, Figure 1A Based on the example chip architecture, Figure 1B Another example diagram of the architecture of the chip provided in the embodiment of the present application is shown exemplarily. Figure 1A and Figure 1B As shown, in the memory access scenario of the CPU core, the nodes accessing the on-chip network 100 involve the CPU core 110, the consistency management module 120, and the memory control module 130. The specific memory access process can be as follows:

[0040] If the CPU core 110 needs to access memory data, the memory access request of the CPU core 110 may be sent to the on-chip network 100;

[0041] The on-chip network 100 is responsible for routing memory access requests to the consistency management module 120;

[0042] When the memory access request reaches the consistency management module 120, the consistency management module 120 checks whether the memory access data required by the memory access request is in the independent cache of other CPU cores; if the consistency management module 120 confirms that the memory access data required by the memory access request is not saved by the independent cache of other CPU cores (that is, the memory access data required by the memory access request is not cached by other CPU cores), the consistency management module 120 confirms that the memory access data needs to be read from the memory, and thus passes the memory access request to the memory control module 130;

[0043] After receiving the memory access request, the memory control module 130 reads the memory access data from the memory based on the memory access request, and returns the memory access data to the CPU core through the consistency root node (needs to be routed through the on-chip network), or directly returns the memory access data to the CPU core (needs to be routed through the on-chip network);

[0044] Further, if the consistency management module 120 confirms that the memory access data required by the memory access request is stored in the independent cache of other CPU cores (that is, the memory access data required by the memory access request is cached by other CPU cores), the consistency management module 120 confirms that there is no need to read the memory access data from the memory, and can notify other CPU cores holding the memory access data to provide the memory access data to the CPU core that issued the memory access request.

[0045] It can be seen that when the CPU core accesses the memory, it needs to use the on-chip network to communicate with the consistency management module, memory control module and other nodes. Therefore, the on-chip routing delay (time delay of transmission signal) of the on-chip network has a crucial impact on the delay of the CPU core accessing the memory (i.e., memory access delay).

[0046] It should be noted that the on-chip network connects the functional modules in the chip through on-chip routing. The on-chip routing delay refers to the time required for the signal to be transmitted on the on-chip routing of the on-chip network. The memory access delay of the CPU core refers to the time delay between the CPU core issuing a memory access request and obtaining a response (for example, the waiting time between the CPU core issuing a memory access request and obtaining memory access data); since the CPU core needs to communicate with the consistency management module, memory control module and other nodes through the on-chip routing of the on-chip network, the on-chip routing delay of the on-chip network increases, and the memory access delay of the CPU core will also increase accordingly, that is, the on-chip routing delay of the on-chip network is one of the main factors leading to the increase in memory access delay.

[0047] However, as the progress of semiconductor technology slows down, the chip area gradually increases due to the maturity of the technology and the increase in the integration of complex functions. That is, the slowdown in semiconductor technology progress means that it is more difficult to reduce latency and increase bandwidth by shrinking the process nodes. At the same time, due to the increase in chip integrated functions and complexity, the chip area increases; and the increase in chip area leads to an increase in the on-chip routing delay of the on-chip network, that is, as the chip area increases, the signal needs to be transmitted over a longer distance, resulting in an increase in the on-chip routing delay.

[0048] It can be seen that on-chip routing delay is one of the main factors that lead to increased memory access delay, and on-chip routing delay is affected by factors such as increased chip area, high-frequency chip operation, and signal transmission distance.

[0049] Based on this, it is necessary to consider reducing the memory access latency of the CPU core to optimize chip performance.

[0050] One solution is to use high-level routing to reduce the transmission delay of on-chip signals when accessing memory (on-chip signals are signals of the on-chip network), wherein high-level routing has the characteristics of lower resistance and capacitance, which can reduce signal transmission time.

[0051] However, as an important resource of the chip, the use of high-level routing will occupy important resources of the chip, and as the chip frequency continues to increase, due to signal integrity and parasitic effects, the effect of reducing signal transmission delay brought by high-level routing will become limited.

[0052] It should be noted that the routing can correspond to the metal wires connecting various functional modules in the chip, and can be distributed at different levels of the chip. For example, there are multiple metal layers in the physical structure of the chip, and different routing can be arranged in each metal layer. Routing can be specifically divided into low-level routing and high-level routing. Low-level routing is used for short-distance, local connection between functional modules, and has relatively large resistance, while high-level routing is used for long-distance connection, has small resistance and capacitance, and is suitable for long-distance signal transmission.

[0053] Another solution is to reuse the on-chip network and introduce a prediction mechanism in the on-chip network to predict the possible memory access requests of the CPU core, so as to read the memory in advance based on the predicted memory access requests, so as to extract the prepared memory access data when the CPU core needs to access the memory (that is, when the CPU core actually issues a memory access request), thereby reducing the waiting time between the CPU core issuing a memory access request and obtaining the memory access data, and shortening the memory access delay.

[0054] However, this approach still requires the reuse of the existing on-chip network to transmit memory access requests and memory access data, does not change the network architecture, and cannot solve the signal transmission delay of the on-chip network itself; at the same time, the advance amount of the prediction mechanism is limited and does not increase with the increase of chip area and scale.

[0055] It should be noted that the lead time refers to the time span from prediction to the actual memory access of the CPU core; the effectiveness of the prediction mechanism depends on accurately predicting the memory access mode of the CPU core, that is, before the CPU core actually issues a memory access request, the future memory access requirements of the CPU core are predicted based on the memory access mode of the CPU core; and when the prediction is accurate, the lead time will also be subject to the physical limitations of the on-chip network and memory access speed. Specifically, the time range of the lead time must be before the CPU core actually issues a memory access request, but this time range is limited, that is, too early may cause data to be overwritten or invalid, and too late may not effectively reduce memory access latency, so the maximum value of the lead time is limited; based on this, as the chip area and scale increase, the corresponding increase in on-chip routing delay will lead to larger memory access latency, and with the limited lead time of the prediction mechanism, it is difficult to further reduce memory access latency.

[0056] Another solution is to set up an additional fast network to transmit memory page information so as to open the memory pages that the CPU core needs to access in advance, thereby reducing the page opening time when reading data from the memory, thereby reducing memory access latency.

[0057] However, the time for opening the memory page in advance in the above method is limited, that is, the time window for opening the memory page in advance is limited, and the memory page cannot be kept in the open state indefinitely, so it cannot be guaranteed that all memory accesses of the CPU core can be processed by opening the memory page in advance; at the same time, opening too many memory pages in advance will increase memory power consumption, especially when the memory page opened in advance is not finally accessed by the CPU core, the energy consumption of the memory will increase; and, since the number of memory pages that can be managed by the memory control module at one time is limited, even if there is an additional fast network, the memory control module will have a resource bottleneck when opening multiple memory pages at the same time. If more memory pages need to be opened at the same time, the memory may become overloaded, resulting in the effect of reducing the memory access delay is not obvious.

[0058] It should be noted that a memory page, such as a DDR page, refers to a group of continuous storage units in the memory (such as a row). When the memory page accesses data, the memory page needs to be opened (i.e. activated). Therefore, opening the memory page in advance can reduce the delay in memory access. That is, if the memory page where the data is located is in the open state, the read or write operation can be performed quickly.

[0059] Considering the defects of the above solutions, in order to reduce memory access delay, the embodiment of the present application adjusts the architecture of the chip. Specifically, on the basis of the on-chip network, the chip adds a set of address transmission networks independent of the on-chip network, which is dedicated to transmitting memory access addresses, especially memory access addresses that are sensitive to transmission delays; and the routing speed of the address transmission network is faster than the on-chip network, so that the embodiment of the present application can transmit the memory access address to the consistency management module in advance through the address transmission network, so that the consistency management module can pre-fetch the data required for the CPU core to access the memory in advance, thereby reducing the memory access delay of the CPU core.

[0060] That is to say, the embodiments of the present application can separate the memory access address transmission function of the address transmission network from the memory access request and memory access data transmission function of the on-chip network, and the routing speed of the address transmission network is faster than the on-chip network, thereby optimizing the network resource utilization. When the memory access request of the CPU core reaches the consistency management module, the consistency management module has pre-fetched the data required for the CPU core memory access based on the memory access address transmitted in advance by the address transmission network, thereby reducing the overall memory access delay of the CPU core.

[0061] As an optional implementation, Figure 2 Another exemplary architecture diagram of the chip provided in the embodiment of the present application is shown in combination with Figure 1B and Figure 2 As shown, in Figure 1B Based on the exemplary chip architecture, Figure 2The architecture of the exemplary chip may further include: an address transmission network 210 , which is a dedicated transmission network independent of the on-chip network 100 and is dedicated to transmitting memory access addresses, especially delay-sensitive memory access addresses.

[0062] As an optional implementation, the on-chip network 100 can be a transmission network that ensures data determinism and loss-free transmission. However, due to on-chip routing delays, higher network frequencies, network congestion, etc. of the on-chip network, the on-chip network may have large transmission delays. Therefore, the embodiment of the present application sets an address transmission network 210 independent of the on-chip network 100 in the chip, and the routing speed of the address transmission network 210 is faster than that of the on-chip network 100, so that the address transmission network 210 is used to specifically transmit memory access addresses, especially delay-sensitive memory access addresses, so that the memory access addresses can reach the consistency management module 120 through the address transmission network 210 ahead of the CPU core's memory access request, so that the consistency management module 120 can pre-fetch the data required for the CPU core memory access based on the memory access address that arrives in advance, thereby shortening the memory access delay.

[0063] As an optional implementation, the address transmission network 210 may have a routing function to ensure that the memory access address can be routed, so that the address transmission network 210 may be provided with a routing module to realize the routing function; at the same time, in order to ensure that the address transmission network 210 can transmit the memory access address to the consistency management module 120 as quickly as possible, the routing speed of the address transmission network 210 should be higher than the routing speed of the on-chip network 100; for example, the address transmission network is designed to have a routing function, and the cache forwarding function is canceled, that is, the address transmission network does not set a cache forwarding function (for example, the node that is not in the address transmission network caches the data packet), thereby avoiding the additional processing overhead when the data packet is transmitted between nodes. In other words, the memory access address can be transmitted and routed in the address transmission network in the form of a data packet, and the design of the address transmission network 210 without a cache forwarding function can ensure that the data packet of the memory access address can quickly pass through the address transmission network, reduce the intermediate residence time, reduce the transmission delay, and realize the special transmission of the memory access address based on the routing function.

[0064] Furthermore, the network frequency of the address transmission network 210 can be set to be lower than the network frequency of the on-chip network 100, that is, different from the high-frequency operation of the on-chip network 100, the address transmission network 210 is set to operate at a low frequency to reduce the capacitance effect on the routing and reduce the demand for Repeaters (repeaters), thereby reducing routing delays. In other words, the network frequency of the address transmission network is lower than the network frequency of the on-chip network, but the capacitance effect on the routing of the address transmission network is smaller than the capacitance effect on the routing of the on-chip network, and the number of Repeaters of the address transmission network is smaller than the number of Repeaters of the on-chip network, so that the address transmission network set to operate at a low frequency can reduce routing delays by reducing capacitance effects and reducing the demand for Repeaters.

[0065] It should be noted that the network frequency of the address transmission network or the on-chip network is the operating frequency, that is, the clock frequency, which indicates the number of data transmission operations performed per unit time (for example, per second). The network frequency is measured in megahertz (MHz) or gigahertz (GHz). Repeaters are used to enhance signals in the network. For example, in an on-chip network, signals need to be transmitted between multiple functional modules such as the CPU, memory control module, and IO module. Therefore, the on-chip network may cover the entire chip, which causes the signal to traverse a longer path. This requires the Repeater to enhance the signal in the path to prevent signal attenuation. Although Repeaters play a role in improving the quality of signal transmission, the use of Repeaters will bring certain delays and energy consumption.

[0066] It should be explained that although the address transmission network is set as a low-frequency network that runs at a low frequency, which is lower than the on-chip network that is set as a high-frequency network, the address transmission network can effectively reduce the transmission delay of the memory access address by reducing routing delays, canceling the cache forwarding function, and reducing the need for Repeaters, thereby achieving a routing speed of the address transmission network that is faster than the routing speed of the on-chip network.

[0067] It can be seen that in the embodiment of the present application, the on-chip network as a high-frequency network can transmit a large amount of data information, for example, the on-chip network is used to transmit memory access requests, memory access data (such as returning memory access data to the CPU core), etc., but the excessively high frequency of the on-chip network may bring about capacitance effects, signal integrity problems and higher power consumption, so the on-chip network needs to ensure the certainty and lossless transmission of data, and there is a large routing delay; and the address transmission network as a low-frequency network is dedicated to transmitting memory access addresses, so compared to the on-chip network, the information transmitted by the address transmission network is lightweight, and the address transmission network can be designed by reducing routing delays, reducing the use of Repeaters and cache-free forwarding to achieve accelerated transmission of memory access addresses. Therefore, in the embodiment of the present application, the address transmission network and the on-chip network have different divisions of labor and settings.

[0068] In a further optional implementation, the address transmission network can be synchronized using a transmission clock. For example, the address transmission network can be synchronized using a global transmission clock, that is, the sending end and the receiving end of the address transmission network can be synchronized according to the global transmission clock to reduce jitter, transmission delay and other problems caused by clock asynchrony. In other words, the global transmission clock synchronization mechanism can enable the sending end and the receiving end of the address transmission network to work based on the same clock signal, ensuring the accuracy of memory access address transmission and reducing jitter and delay caused by clock asynchrony.

[0069] In an optional implementation, the sending end of the address transmission network is a functional module in the chip that sends the memory access address to the address transmission network, such as a CPU core, a cache controller of LLC (Last Level Cache), or any node in the on-chip network that participates in the memory access request forwarding processing; the receiving end of the address transmission network is a functional module that receives the memory access address output by the address transmission network, such as a consistency management module, or a functional module that connects the consistency management module and the address transmission network (such as the request generation module described below).

[0070] In other possible optional implementations, the address transmission network may also adopt a clock-free transmission mechanism, that is, the address transmission network may not use a global transmission clock to synchronize the sender and the receiver, but instead complete the synchronization through a sampling mechanism at the sender and the receiver (that is, the starting point and the end) of the address transmission network; for example, the sender of the address transmission network sends the memory access address to the address transmission network at a certain data rate in the absence of a clock, and the receiver of the address transmission network obtains the memory access address transmitted from the address transmission network through a sampling mechanism, that is, the receiver samples the signal on the transmission line of the address transmission network to synchronize the correct memory access address.

[0071] In an optional implementation, the memory access addresses transmitted by the address transmission network can be divided into:

[0072] The memory access address predicted by the CPU core is referred to as the predicted memory access address. For example, the CPU core can set a prediction algorithm to predict the memory access address corresponding to the future memory access demand of the CPU core as the predicted memory access address, and transmit the predicted memory access address to the address transmission network; in this case, the sending end of the address transmission network can be the CPU core;

[0073] The memory access address of the memory access request issued by the CPU core is referred to as the formal memory access address. For example, the CPU core has a need to access data during operation. If the data that the CPU needs to access is not hit in the LLC, the LLC's cache controller can transmit the CPU core's memory access request to the consistency management module through the on-chip network; at this time, the on-chip interface of the LLC's cache controller (the interface between the LLC's cache controller and the on-chip network) can transmit the memory access address (i.e., the formal memory access address) in the CPU core's memory access request to the address transmission network, or any node in the on-chip network that participates in the memory access request forwarding processing can transmit the formal memory access address to the address transmission network; in this case, the sending end of the address transmission network can be the LLC's cache controller (specifically the on-chip interface therein), or any node in the on-chip network that participates in the memory access request forwarding processing.

[0074] That is to say, the embodiments of the present application support the use of an address transmission network to transmit predicted memory access addresses, so as to transmit the predicted memory access addresses corresponding to the predicted future memory access requirements of the CPU core to the consistency management module, thereby pre-fetching data for the future memory access requirements of the CPU core in advance; the embodiments of the present application also support the use of an address transmission network to transmit formal memory access addresses, so that after the CPU core issues a memory access request, the time when the formal memory access address is transmitted to the consistency management module through the address transmission network can be earlier than the time when the memory access request is transmitted to the consistency management module through the on-chip network, so that when the memory access request arrives at the consistency management module, the consistency management module has pre-fetched the memory access data based on the formal memory access address in advance.

[0075] In a further optional implementation, a plurality of address injection modules may be provided in the chip, and the address injection modules are used to inject memory access addresses into the address transmission network so that the address transmission network routes the memory access addresses to the consistency management module.

[0076] The memory access address based on the injection address transmission network is divided into predicted memory access address and formal memory access address. Figure 2 As shown, the address injection module can be divided into:

[0077] A first address injection module 220 for injecting a predicted memory access address into an address transmission network;

[0078] And, a second address injection module 230 for injecting the formal memory access address into the address transmission network.

[0079] That is to say, for the predicted memory access address, a first address injection module 220 connecting the CPU core and the address transmission network can be set in the chip to inject the predicted memory access address predicted by the CPU core (for example, the predicted memory access address predicted by the prediction algorithm of the CPU core) into the address transmission network; for example, the first address injection module can connect the CPU core and the address transmission network through wiring, so that the predicted memory access address predicted by the CPU core can be injected into the address transmission network through the connected first address injection module. In this case, the sending end of the address transmission network can be the CPU core, and the CPU core provides the predicted memory access address to the address transmission network through the first address injection module.

[0080] For the formal memory access address, multiple second address injection modules 230 can be set in the chip to connect the on-chip interface of the LLC cache controller with the address transmission network, and connect any node in the on-chip network that participates in the memory access request forwarding processing with the address transmission network.

[0081] In an optional implementation, an on-chip interface to the LLC cache controller, Figure 3 The following is an exemplary diagram showing the configuration of the second address injection module: Figure 3 As shown, the on-chip interface 311 of the LLC cache controller 310 is used to connect to the on-chip network 110, and can transmit the memory access request of the CPU core 110 to the on-chip network 110 when the LLC misses. In the embodiment of the present application, a second address injection module 230 connecting the on-chip interface 311 and the address transmission network 210 can be set. For example, the second address injection module 230 can connect the on-chip interface 311 and the address transmission network 210 through wiring, so that when the on-chip interface 311 transmits the memory access request to the on-chip network 110, the formal memory access address in the memory access request can be injected into the address transmission network 210 through the second address injection module 230. In this case, the sending end of the address transmission network can be the on-chip interface of the LLC cache controller, and the on-chip interface provides the formal memory access address to the address transmission network through the second address injection module.

[0082] In other optional implementations, after the memory access request of the CPU core is sent to the on-chip network, the on-chip network may need to use other nodes to forward the memory access request to the consistency management module. Therefore, there are other nodes involved in forwarding the memory access request on the routing path of the memory access request to the consistency management module. The embodiment of the present application can also support any node in the on-chip network that participates in the memory access request forwarding process to transmit the memory access address of the memory access request to the address transmission network; thus, the embodiment of the present application can be set to connect any node in the on-chip network that participates in the memory access request forwarding process and the second address injection module of the address transmission network. For example, the second address injection module can connect any node in the on-chip network that participates in the memory access request forwarding process and the address transmission network through routing, so that any node in the on-chip network that participates in the memory access request forwarding process can inject the formal memory access address in the memory access request forwarded into the address transmission network through the connected second address injection module. In this case, the sending end of the address transmission network can be any node in the on-chip network that participates in the memory access request forwarding process, and the arbitrary node provides the formal memory access address to the address transmission network through the second address injection module.

[0083] In an optional implementation, the address injection module (whether the first address injection module or the second address injection module) can be a hardware unit on the chip. On the one hand, the address injection module is connected to the sending end of the address transmission network (such as the on-chip interface of the CPU core, LLC's cache controller, or any node in the on-chip network that participates in the memory access request forwarding processing) through wiring (such as metal wires), and on the other hand, it accesses the address transmission network through wiring to provide the memory access address (predicted memory access address or formal memory access address) provided by the sending end of the address transmission network to the address transmission network for transmission routing.

[0084] As an optional implementation, Figure 4 An optional flowchart of the memory access method provided in the embodiment of the present application is shown as an example. Figure 4 The method flow may include the following steps.

[0085] In step S410, the address transmission network obtains a memory access address.

[0086] In an optional implementation, the memory access address obtained by the address transmission network can be a predicted memory access address. For example, the CPU core can determine the predicted memory access address, and the CPU core can transmit the predicted memory access address to the address transmission network (for example, the CPU core can inject the predicted memory access address into the address transmission network through a first address injection module), so that the address transmission network obtains the predicted memory access address.

[0087] Specifically, for the predicted memory access address, the predicted memory access address is not the memory access address in the memory access request issued by the CPU core, but the memory access address of the future memory access demand predicted by the CPU core based on the prediction algorithm or prediction strategy; for example, the CPU core can determine the predicted memory access address by analyzing the historical memory access pattern. For example, when the program running by the CPU core often accesses adjacent memory addresses, the CPU core can predict the memory address that may be accessed next time based on the memory addresses that have been accessed, as the predicted memory access address. For example, the CPU core can determine the predicted memory access address by predicting the instruction stream. For example, the CPU core can analyze the instructions to be executed and determine the memory addresses that may be accessed by the instructions to be executed as the predicted memory access addresses; specifically, when the CPU core supports prefetch instructions, the CPU core can determine the predicted memory access address in advance when executing prefetch instructions, wherein the prefetch instructions require the CPU core to load the data to be used from the memory to the cache in advance.

[0088] In an optional implementation, the memory access address obtained by the address transmission network can be a formal memory access address, such as the formal memory access address in a memory access request issued by the CPU core, which can be injected into the address transmission network (for example, the formal memory access address can be injected into the address transmission network through a second address injection module) so that the address transmission network obtains the formal memory access address.

[0089] For the formal memory access address, if the CPU core needs to access the data in the memory during operation, the memory access request of the CPU core can be sent to the on-chip network, and the formal memory access address in the memory access request can be injected into the address transmission network. For example, when the CPU core reads data in LLC (Last Level Cache), LLC misses (that is, the data that the CPU core needs to read is not in LLC), then the CPU core needs to access the data in the memory, so that the cache controller of LLC can send the memory access request of the CPU core to the on-chip network through the on-chip interface, and the formal memory access address in the memory access request can be injected into the address transmission network through the second address injection module. That is to say, in the above example, the address of the CPU core that the LLC misses can be regarded as a delay-sensitive memory access address, and the memory access request of the CPU core is routed to the consistency management module through the on-chip network, and the formal memory access address in the memory access request can be injected into the address transmission network. Since the routing speed of the address transmission network is faster than that of the on-chip network, the formal memory access address can reach the consistency management module before the memory access request through the address transmission network.

[0090] It should be noted that in modern processors, the cache is divided into multiple levels (such as L1 cache, L2 cache and L3 cache), and the cache capacity of each level gradually increases, while the speed gradually slows down; LLC is the last level cache of the CPU core, such as L3 cache; when the CPU core needs to access data, if the data does not hit in the L1 cache or L2 cache, it will continue to search the LLC. If the data still does not hit in the LLC, the CPU core needs to read the required data from the memory. At this time, the memory access request of the CPU core is an LLC miss read request, which contains the address of the data that the CPU core needs to read in the memory (that is, the formal memory access address); thus, the LLC miss read request can be transmitted to the on-chip network through the on-chip interface of the LLC cache controller, and the formal memory access address can be injected into the address transmission network through the second address injection module connected to the on-chip interface.

[0091] Regarding the formal memory access address, in other possible optional implementations, other nodes in the on-chip network that participate in forwarding and processing memory access requests can also inject the formal memory access address of the memory access request into the address transmission network so that the address transmission network obtains the memory access address of the memory access request. The relevant content can be referred to the description of the corresponding part of the previous text and will not be expanded here.

[0092] In step S411, the address transmission network routes the memory access address to the consistency management module.

[0093] After the address transmission network obtains the memory access address, the address transmission network routes the memory access address with the consistency management module as the routing destination; thus, the address transmission network can route the memory access address to the consistency management module based on the routing path to the consistency management module.

[0094] In an optional implementation, based on different injection positions of the memory access address into the address transmission network, the routing path of the address transmission network to route the memory access address to the consistency management module may be different; wherein, different injection positions of the memory access address into the address transmission network mean that the sending end of the address transmission network is different.

[0095] For example, taking the predicted memory access address as an example, the sending end of the address transmission network is the CPU core. The predicted memory access address is injected into the address transmission network through the first address injection module connecting the CPU core and the address transmission network. After the address transmission network obtains the predicted memory access address, it can route the predicted memory access address to the consistency management module based on the routing path from the first address injection module to the consistency management module.

[0096] For example, taking the formal memory access address and the sending end of the address transmission network as an example, the formal memory access address is injected into the address transmission network through the second address injection module connecting the on-chip interface and the address transmission network. After obtaining the formal memory access address, the address transmission network can route the formal memory access address to the consistency management module based on the routing path connecting the second address injection module of the on-chip interface to the consistency management module.

[0097] For example, taking the formal memory access address, and the sending end of the address transmission network is any node in the on-chip network that participates in forwarding and processing memory access requests, the formal memory access address is injected into the address transmission network through a second address injection module connecting the arbitrary node and the address transmission network. After obtaining the formal memory access address, the address transmission network can route the formal memory access address to the consistency management module based on the routing path connecting the second address injection module of the arbitrary node to the consistency management module.

[0098] In the routing path where the address transmission network routes the memory access address (whether it is the predicted memory access address or the formal memory access address) to the consistency management module, the address transmission network can quickly route the memory access address to the consistency management module due to the design of small routing delay of the address transmission network, small use of Repeater, and no cache forwarding.

[0099] In a further optional implementation, since the memory access request corresponding to the formal memory access is routed to the consistency management module through the on-chip network, the memory access address (whether it is a predicted memory access address or a formal memory access address) routed by the address transmission network to the consistency management module cannot be used as a formal memory access, that is, the memory access address (whether it is a predicted memory access address or a formal memory access address) routed by the address transmission network to the consistency management module is an address for reading the memory in advance, that is, an address for pre-fetching memory data in advance. Based on this, the memory access address (whether it is a predicted memory access address or a formal memory access address) routed by the address transmission network to the consistency management module can be used for predictive and advance memory reading, so that the embodiment of the present application can generate a predictive memory access request based on the memory access address (whether it is a predicted memory access address or a formal memory access address) output by the address transmission network, so as to use the predictive memory access request to pre-fetch memory data, and the predictive memory access request needs to be distinguished from the formal memory access request issued by the CPU core.

[0100] In a further optional implementation, the predictive memory access request may have a discardable and non-consistent property, that is, a request used as a predictive and proactive memory data prefetch. The purpose of the predictive memory access request is to enable the consistency management module to read the memory in advance to prefetch data that the CPU core may require, thereby shortening the memory access latency of the CPU core. Therefore, the predictive memory access request may be discarded and cache consistency may not be required (i.e., no complex cache consistency management mechanism is required).

[0101] Specifically, the CPU core's formal memory access request is non-droppable, deterministic, and needs to go through cache consistency management to avoid errors caused by data inconsistency; and different from the CPU core's formal memory access request, the role of the predictive memory access request is to initiate a memory read operation in advance to pre-fetch the data that the CPU core may need in advance, so the predictive memory access request is discardable, for example, the consistency management module can also not process the predictive memory access request and discard the predictive memory access request; at the same time, the predictive memory access request is non-consistent, that is, the predictive memory access request does not participate in cache consistency management, that is, the predictive memory access request does not change the state of the data and does not affect the data in other CPU cores or caches. This is because the predictive memory access request is only a read request to pre-fetch data from the memory in advance, and does not change the state of the data, nor does it affect the data in other CPU cores or caches. Furthermore, the data state in other CPU cores or caches may affect the predictive memory access request, for example, other CPU cores have modified the data requested by the predictive memory access request but have not yet written it back to the memory, which may affect the accuracy of the data requested by the predictive memory access request.

[0102] In a further optional implementation, in combination with Figure 2As shown, a request generation module 240 may also be provided in the chip to generate a predictive memory access request based on the predicted memory access address output by the address transmission network, and transmit the predictive memory access request to the consistency management module. Specifically, the request generation module 240 is located between the address transmission network 210 and the consistency management module 120, that is, the consistency management module 120 is connected to the address transmission network 210 through the request generation module 240. For example, the request generation module 240 is respectively connected to the address transmission network 210 and the consistency management module 120 through wiring, so that the request generation module 240 can connect the consistency management module 120 and the address transmission network 210; furthermore, when the address transmission network routes the memory access address (whether it is a predicted memory access address or a formal memory access address) with the consistency management module as the routing destination, the request generation module connecting the address transmission network and the consistency management module can obtain the memory access address output by the address transmission network; and, the request generation module can generate a predictive memory access request based on the memory access address output by the address transmission network, and transmit the predictive memory access request to the consistency management module, so that the consistency management module can pre-fetch the data corresponding to the memory access address from the memory in advance through the memory control module.

[0103] In other possible implementations, the embodiments of the present application may not set up a request generation module, but instead the address transmission network directly routes the memory access address (whether it is a predicted memory access address or a formal memory access address) to the consistency management module, so that the consistency management module can obtain the memory access address output by the address transmission network, and generate a predictive memory access request based on the memory access address output by the address transmission network; that is, the predictive memory access request can also be generated by the consistency management module based on the memory access address output by the address transmission network, and is not limited to generating predictive memory access requests by adding a request generation module.

[0104] It can be understood that the operation of reading memory is controlled by the memory control module, so the consistency management module needs to provide the predictive memory access request to the memory control module so that the memory control module controls the advance reading operation of the memory. Therefore, it is sufficient to generate the predictive memory access request before interacting with the memory control module. Therefore, the embodiment of the present application may not be limited to generating the predictive memory access request through the request generation module or generating the predictive memory access request through the consistency management module.

[0105] In a further optional implementation, when the consistency management module identifies the memory access address output by the address transmission network, it may be regarded as obtaining the memory access address output by the address transmission network, so that a predictive memory access request may be generated based on the memory access address output by the address transmission network. For example, the consistency management module may identify whether the memory access address comes from the address transmission network, so that when the memory access address is identified to come from the address transmission network, a predictive memory access request may be generated based on the memory access address output by the address transmission network.

[0106] For example, an embodiment of the present application can distinguish between information transmitted by an address transmission network and information transmitted by an on-chip network through a hardware port. For example, a consistency management module can connect the on-chip network and the address transmission network through different hardware ports, that is, the consistency management module can connect the consistency management module through a dedicated hardware port. Therefore, when the consistency management module detects a memory access address transmitted by a hardware port connected to the address transmission network, it can be regarded as identifying the memory access address output by the address transmission network, and then generating a predictive memory access request based on the memory access address output by the address transmission network.

[0107] For example, the address transmission network can transmit the memory access address in the form of a data packet, so that the data packet of the memory access address can carry a source identifier to indicate that the memory access address comes from the routing transmission of the address transmission network, thereby distinguishing it from the routing transmission of the on-chip network; for example, the header of the data packet of the memory access address routed by the address transmission network can be attached with a source identifier to indicate that the memory access address comes from the routing transmission of the address transmission network. Therefore, the consistency management module can identify the memory access address output by the address transmission network by identifying the source identifier attached to the header of the data packet, and then generate a predictive memory access request based on the memory access address output by the address transmission network.

[0108] As an optional implementation, in order to distinguish between the CPU core's formal memory access request and the predictive memory access request, the embodiment of the present application can distinguish the request type between the memory access request and the predictive memory access request through the request identifier. For example, the structure of the request can have a request identifier field to indicate the type of request, so that the embodiment of the present application can distinguish between the memory access request and the predictive memory access request through different values ​​of the request identifier field; further, when the request generation module or the consistency management module generates a predictive memory access request based on the memory access address, the value of the request identifier field in the predictive memory access request can be set to correspond to the predictive memory access request.

[0109] For example, if the value of the request identification field is a first value (such as 0), it indicates that the request is a memory access request, and if the value of the request identification field is a second value (such as 1), it indicates that the request is a predictive memory access request; thus, the value of the request identification field in the predictive memory access request can be set to the second value (such as 1). Taking the request identification field as a flag bit (Flag) as an example, different values ​​of the flag bit can indicate whether the request is a memory access request or a predictive memory access request; for example, if the value of the flag bit is a first value (such as 0), it is a memory access request, and if the value of the flag bit is a second value (such as 1), it is a predictive memory access request; thus, when the request generation module or the consistency management module generates a predictive memory access request based on the memory access address, it can set the value of the flag bit in the predictive memory access request to the second value (such as 1).

[0110] In step S412, the consistency management module obtains a predictive memory access request, where the predictive memory access request is generated based on a memory access address output by an address transmission network.

[0111] As described above, the predictive memory access request is used to pre-fetch data from the memory in advance, corresponding to the memory access address output by the address transmission network; in a possible implementation, the request generation module set in the chip can generate a predictive memory access request based on the memory access address output by the address transmission network (whether it is a predicted memory access address or a formal memory access address), and provide it to the consistency management module so that the consistency management module obtains the predictive memory access request; in a possible implementation, the consistency management module can directly obtain the memory access address output by the address transmission network (whether it is a predicted memory access address or a formal memory access address), and generate a predictive memory access request to obtain the predictive memory access request.

[0112] In step S413, the consistency management module detects whether the current state meets the processing conditions of the predictive memory access request, if not, executes step S414, and if so, executes step S415.

[0113] After obtaining the predictive memory access request, the consistency management module can determine whether the processing conditions of the predictive memory access request are met based on the current state of the consistency management module, thereby deciding whether to transmit the predictive memory access request to the memory control module for processing or to discard the predictive memory access request.

[0114] In an optional implementation, the current state may include the working state of the consistency management module, and the working state of the consistency management module is divided into an idle state and a busy state; wherein, if the consistency management module is in an idle state, it means that the consistency management module is not currently processing complex consistency operations or has not received formal memory access requests. At this time, the load of the consistency management module is light, and the current state is regarded as meeting the processing conditions of predictive memory access requests; if the consistency management module is in a busy state, it means that the consistency management module is currently processing formal memory access requests, or is performing complex cache consistency operations. At this time, the load of the consistency management module is high, and based on the discardable attribute of the predictive memory access request, it is regarded that the current state does not meet the processing conditions of the predictive memory access request, so that the consistency management module can discard the predictive memory access request.

[0115] In other optional implementations, the current state may include the data state of the predictive memory access request, that is, the state of the data requested by the predictive memory access request in the chip system. If the data state of the predictive memory access request is modified in the independent cache of other CPU cores, it indicates that the data requested by the predictive memory access request is modified by other CPU cores but has not been synchronized to the memory. At this time, the data requested by the predictive memory access request read from the memory may be outdated or even wrong. Therefore, the current state is deemed to not meet the processing conditions of the predictive memory access request, so that the consistency management module can discard the predictive memory access request; if the data state of the predictive memory access request is not cached (for example, the data requested by the predictive memory access request is not in the independent cache of other CPU cores), or it has not been modified in the independent cache of other CPU cores, then the data requested by the predictive memory access request read from the memory at this time is correct, so the current state is deemed to meet the processing conditions of the predictive memory access request.

[0116] It should be noted that the inconsistency property of predictive memory access requests means that the consistency management module does not need to perform the same cache consistency check on predictive memory access requests as it does on formal memory access requests. For example, the consistency management module does not need to notify the independent caches of other CPU cores to invalidate data, but it needs to perform basic checks and judgments on the data status of predictive memory access requests to avoid situations where the data requested by the predictive memory access request is outdated or even erroneous, thereby avoiding situations where the memory access data obtained by subsequent formal memory access requests is outdated or even erroneous.

[0117] In a further optional implementation, the embodiment of the present application can combine the working state of the consistency management module and the data state of the predictive memory access request to determine whether the current state meets the processing conditions of the predictive memory access request; for example, if the working state of the consistency management module is an idle state, and the data state of the predictive memory access request is not cached or has not been modified in the independent cache of other CPU cores, then the current state is deemed to meet the processing conditions of the predictive memory access request, and the execution step S415 can be entered to transmit the predictive memory access request to the memory control module; for example, if the working state of the consistency management module is a busy state, or the data state of the predictive memory access request is modified in the independent cache of other CPU cores, then the current state is deemed to not meet the processing conditions of the predictive memory access request, and the execution step S414 can be entered to discard the predictive memory access request.

[0118] In step S414 , the consistency management module discards the predictive memory access request.

[0119] In step S415 , the consistency management module transmits the predictive memory access request to the memory control module.

[0120] In other optional implementations, the embodiment of the present application may not set step S413, that is, after obtaining the predictive memory access request, the consistency management module can directly transmit the predictive memory access request to the memory control module. In other words, the method of detecting whether the current state (the working state of the consistency management module, the data state of the predictive memory access request, etc.) meets the processing conditions of the predictive memory access request can be used as an optional implementation method.

[0121] In step S416 , the memory control module pre-fetches predicted data from the memory based on the predictive memory access request.

[0122] The memory controller obtains the predictive memory access request transmitted by the consistency management module, and can perform a memory read operation based on the predictive memory access request. The memory read operation performed by the memory control module based on the predictive memory access request can be regarded as an operation of prefetching data from the memory. For ease of explanation, the data prefetched from the memory by the memory control module based on the predictive memory access request can be called predicted data.

[0123] In step S417 , the memory control module transmits the prediction data to the consistency management module.

[0124] After pre-fetching predicted data from the memory based on the predictive memory access request, the memory control module can feed back the predicted data to the consistency management module.

[0125] In step S418, the consistency management module saves the prediction data and the corresponding memory access address.

[0126] After obtaining the prediction data fed back by the memory control module, the consistency management module can save the prediction data and the corresponding memory access address. That is, the consistency management module can save the prediction data corresponding to the predictive memory access request and the memory access address corresponding to the predictive memory access request.

[0127] In an optional implementation, combined with Figure 2 As shown, a data pre-fetch cache 250 connected to the consistency management module 120 may be provided in the chip, so that the consistency management module can cache the predicted data and the corresponding memory access address in the data pre-fetch cache.

[0128] The consistency management module caches the memory access addresses of predictive memory access requests and the corresponding prediction data pre-fetched from the memory in the data pre-fetch cache in order to optimize subsequent formal memory access requests. That is, if a formal memory access request arrives at the consistency management module subsequently, and the memory access address of the formal memory access request is consistent with the memory access address cached in the data pre-fetch cache, the consistency management module can directly obtain the prediction data consistent with the memory access address of the memory access request from the data pre-fetch cache as the memory access data of the memory access request, without having to access the memory, thereby shortening the memory access delay.

[0129] In a further optional implementation, the management of the data prefetch cache determines whether the predicted data can be effectively cached and used for subsequent formal memory access requests, so that the embodiments of the present application can design the cache structure and data replacement strategy of the data prefetch cache.

[0130] In an optional implementation, the data replacement strategy of the data prefetch cache can be designed as a FIFO (First In First Out) replacement strategy, that is, the predicted data are cached in the order in which they enter the data prefetch cache, and the earliest predicted data entering is removed first when the cache space of the data prefetch cache is full.

[0131] In an optional implementation, the data replacement strategy of the data prefetch cache can also be designed to use other replacement strategies, not limited to FIFO, such as an LRU (Least Recently Used) replacement strategy, that is, the least recently used predicted data in the data prefetch cache is replaced and removed first.

[0132] It should be noted that the choice of data replacement strategy for the data prefetch cache depends on the design goals. If the predicted data in the data prefetch cache has a high usage frequency, replacement strategies such as LRU are more applicable; if the usage frequency of the predicted data in the data prefetch cache is relatively random, replacement strategies such as FIFO are more applicable.

[0133] In other optional implementations, the data pre-fetch cache can be merged with the system cache (eg, shared cache) of the chip, thereby reducing the use of hardware resources to optimize resource utilization. Of course, the embodiment of the present application can also support independent setting of the data pre-fetch cache.

[0134] In other optional implementations, the embodiments of the present application may not set up a data prefetch cache, but the consistency management module itself saves the predicted data and the corresponding memory access address. For example, the consistency management module may use a consistency directory to store the predicted data and the corresponding memory access address; wherein, the consistency directory is used for cache consistency management of the consistency management module, which is a management mechanism for cache consistency. For example, the consistency management module can use the consistency directory to record the data copies held by the CPU core or cache to achieve cache consistency management; the embodiments of the present application use the consistency directory to save the predicted data and the corresponding memory access address, so the existing resources of the consistency management module can be reused to achieve the preservation of the predicted data and the corresponding memory access address, and there is no need to set up a data prefetch cache to save the predicted data and the corresponding memory access address, which can optimize the hardware resources of the chip.

[0135] In step S419, the on-chip network routes the memory access request to the consistency management module.

[0136] The memory access request formally issued by the CPU core can be routed to the consistency management module through the on-chip network. For example, if the data that the CPU core needs to access is not hit in the LLC, the LLC cache controller can transmit the memory access request of the CPU core to the on-chip network, and then route it to the consistency management module through the on-chip network.

[0137] In step S420 , the consistency management module determines whether the memory access data requested by the memory access request is pre-fetched, and if so, executes step S421 , and if not, executes step S423 .

[0138] Since the embodiments of the present application can prefetch data from the memory based on predictive memory access requests, when the consistency management module obtains the memory access request of the CPU core routed by the on-chip network, the consistency management module does not directly transmit the memory access request to the memory control module for processing, but first determines whether the memory access data requested by the memory access request is prefetched, such as determining whether the memory access data requested by the memory access request has been prefetched, or determining whether the memory access data requested by the memory access request is being prefetched.

[0139] As an optional implementation, if the memory access data requested by the memory access request has been pre-fetched, the memory access address saved by the consistency management module corresponds to the memory access request, that is, the memory access address saved by the consistency management module is consistent with the memory access address carried by the memory access request, so that the consistency management module can judge whether the saved memory access address (such as the memory access address cached in the data pre-fetch cache) corresponds to the memory access request, that is, whether they are consistent, to determine whether the memory access data requested by the memory access request has been pre-fetched; if the memory access address saved by the consistency management module corresponds to the memory access request, it means that the memory access data requested by the memory access request has been pre-fetched, that is, the judgment result of step S420 is yes, so that the embodiment of the present application can enter S421, and then the consistency management module can use the predicted data of the memory access address corresponding to the memory access request as the memory access data of the memory access request, and feed it back to the CPU core through the on-chip network to avoid memory access based on the memory access request of the CPU core, thereby shortening the waiting time from the CPU core issuing a memory access request to obtaining the memory access data, and shortening the memory access delay.

[0140] As an optional implementation, the memory access data requested by the memory access request may be prefetched, that is, the consistency management module may have transmitted the predictive memory access request corresponding to the memory access address and the memory access request to the memory control module, but has not yet obtained the prediction data fed back by the memory control module. At this time, it is deemed that the memory access data requested by the memory access request is being prefetched, that is, the judgment result of step S420 is yes, so that the consistency management module can wait for the prediction data fed back by the memory control module in order to save the prediction data fed back by the memory control module and the corresponding memory access address; further, after the consistency management module saves the prediction data and the corresponding memory access address fed back by the memory control module, the consistency management module can use the saved prediction data of the memory access address corresponding to the memory access request as the memory access data of the memory access request, and feed it back to the CPU core through the on-chip network to avoid memory access based on the memory access request of the CPU core, thereby shortening the waiting time from the CPU core issuing the memory access request to obtaining the memory access data, and shortening the memory access delay.

[0141] Further, if the consistency management module determines that the memory access data requested by the memory access request is not prefetched, that is, the judgment result of step S420 is no, for example, the memory access data requested by the memory access request is not being prefetched, and the memory access address saved by the consistency management module does not correspond to the memory access request, then the consistency management module can enter S423 and transmit the memory access request to the memory control module for processing.

[0142] In a further optional implementation, since the memory access request issued by the CPU core needs to undergo cache consistency management, the consistency management module may perform a cache consistency check on the memory access request before executing step S420; for example, the consistency management module may check whether the memory access data required by the memory access request is in the independent cache of other CPU cores; if not, that is, the memory access data required by the memory access request is not saved by the independent cache of other CPU cores, the consistency management module enters step S420, that is, enters the step of determining whether the memory access data requested by the memory access request is prefetched; if yes, that is, the memory access data required by the memory access request is saved by the independent cache of other CPU cores, the consistency management module may notify other CPU cores holding the memory access data to provide the memory access data to the CPU core that issued the memory access request, and the consistency management module does not enter step S420 at this time.

[0143] In step S421, the consistency management module uses the saved prediction data of the memory access address corresponding to the memory access request as the memory access data of the memory access request.

[0144] In step S422, the consistency management module feeds back the memory access data of the memory access request to the CPU core via the on-chip network.

[0145] The subsequent process is the processing flow when the judgment result of step S420 is no.

[0146] In step S423, the consistency management module transmits the memory access request to the memory control module.

[0147] In step S424, the memory control module reads the memory access data of the memory access request from the memory based on the memory access request.

[0148] In step S425, the memory control module feeds back the memory access data of the memory access request to the consistency management module.

[0149] In step S426, the consistency management module feeds back the memory access data of the memory access request to the CPU core via the on-chip network.

[0150] That is to say, when a memory access request routed by the on-chip network reaches the consistency management module, the consistency management module will check whether there is a predictive memory access request with the same address, and pre-fetch the data in advance, which is specifically divided into pre-fetching completion and pre-fetching in progress; if so, the consistency management module can use the predicted data corresponding to the memory access address of the memory access request from the saved predicted data as the memory access data, and feed it back to the CPU core through the on-chip network, thereby skipping the process of accessing the memory based on the memory access request, reducing the waiting time from the CPU core issuing the memory access request to obtaining the memory access data, and shortening the memory access delay of the CPU core; if not, the consistency management module follows the processing flow of transmitting the memory access request to the memory control module, and feeds back the memory access data read by the memory control module based on the memory access request to the CPU core through the on-chip network.

[0151] In an embodiment of the present application, in addition to the on-chip network, the chip is also provided with an address transmission network, and the routing speed of the address transmission network is faster than that of the on-chip network, so that the address transmission network can be used to obtain the memory access address and route the memory access address to the consistency management module; the on-chip network can be used to route the memory access request of the CPU core to the consistency management module; the consistency management module can obtain the predictive memory access request, and the predictive memory access request is generated based on the memory access address output by the address transmission network; the predictive memory access request is transmitted to the memory control module, so that the memory control module pre-fetches the predicted data from the memory based on the predictive memory access request; thus, the consistency management module can obtain the predicted data pre-fetched from the memory by the memory control module based on the predictive memory access request, and save the predicted data and the corresponding memory access address; further, the consistency management module obtains the memory access request of the CPU core routed by the on-chip network. When requesting, since the embodiment of the present application can pre-fetch predicted data from the memory based on the predictive memory access request, and the routing speed of the address transmission network is faster than the on-chip network, when the memory access request routed by the on-chip network reaches the consistency management module, the memory access data requested by the memory access request may have been pre-fetched. Therefore, when the consistency management module obtains the memory access request routed by the on-chip network, it can determine whether the memory access data requested by the memory access request is pre-fetched; if the memory access data requested by the memory access request is pre-fetched, the consistency management module can use the saved predicted data of the memory access address corresponding to the memory access request as the memory access data of the memory access request, and feed back the memory access data of the memory access request to the CPU core through the on-chip network, thereby avoiding the process of accessing the memory based on the memory access request routed by the on-chip network, reducing the waiting time from the CPU core issuing the memory access request to obtaining the memory access data, and shortening the memory access delay of the CPU core.

[0152] It can be seen that in the embodiment of the present application, the routing speed of the address transmission network is faster than the on-chip network, so that the address transmission network can speed up the routing speed of the memory access address, support the embodiment of the present application to generate predictive memory access requests in advance and pre-fetch predicted data from the memory in advance, so that the consistency management module can save the predicted data pre-fetched from the memory and the corresponding memory access address; further, when the formal memory access request reaches the consistency management module through the on-chip network, if the consistency management module finds that the memory access data requested by the memory access request has been pre-fetched, the consistency management module can directly obtain the predicted data of the memory access address corresponding to the memory access request from the saved predicted data as the memory access data of the memory access request, thereby avoiding the delay of the consistency management module reading the memory access data from the memory after obtaining the memory access request, and shortening the memory access delay of the CPU core. Therefore, the chip provided in the embodiment of the present application adopts the architecture design of the on-chip network and the address transmission network, as well as the data pre-fetching control strategy of the consistency management module, which can process the memory access address routed by the address transmission network separately from the formal memory access request routed by the on-chip network, thereby optimizing the load of the on-chip network, shortening the memory access delay of the CPU core, and optimizing the chip performance.

[0153] Based on the contents described in the previous text, the memory access device provided in the embodiment of the present application is introduced below. The memory access device described below can be regarded as a logical functional unit required to be set by the consistency management module to implement the memory access method provided in the embodiment of the present application. The contents described below can be referenced in correspondence with the contents described above.

[0154] As an optional implementation, Figure 5 An optional block diagram of a memory access device provided in an embodiment of the present application is exemplarily shown. The memory access device can be applied to a consistency management module. Figure 5 , the memory access device may include:

[0155] The pre-fetch processing logic unit 510 is used to obtain a predictive memory access request, which is generated based on the memory access address output by the address transmission network; transmit the predictive memory access request to the memory control module so that the memory control module pre-fetches the predicted data from the memory based on the predictive memory access request; obtain the predicted data pre-fetched from the memory by the memory control module based on the predictive memory access request; save the predicted data and the corresponding memory access address;

[0156] The memory access request processing logic unit 520 is used to obtain the memory access request of the CPU core routed by the on-chip network, and determine whether the memory access data requested by the memory access request is pre-fetched; if so, the saved prediction data of the memory access address corresponding to the memory access request is used as the memory access data of the memory access request, and the memory access data of the memory access request is fed back to the CPU core through the on-chip network;

[0157] Among them, the routing speed of the address transmission network is faster than that of the on-chip network.

[0158] As an optional implementation, the memory access address output by the address transmission network includes a predicted memory access address, where the predicted memory access address is a memory access address of a future memory access demand predicted by the CPU core based on a prediction algorithm;

[0159] and / or,

[0160] The memory access address output by the address transmission network includes a formal memory access address, and the formal memory access address is the memory access address in the memory access request of the CPU core.

[0161] As an optional implementation, the pre-fetch processing logic unit 510 is used to obtain the predictive memory access request, including:

[0162] Obtaining a predictive memory access request transmitted by a request generation module;

[0163] Among them, the request generation module connects the consistency management module and the address transmission network in the chip, is used to obtain the memory access address output by the address transmission network, generate a predictive memory access request based on the memory access address output by the address transmission network, and transmit the predictive memory access request to the consistency management module.

[0164] As an optional implementation, the consistency management module connects the on-chip network and the address transmission network through different hardware ports.

[0165] As an optional implementation, the memory access request and the predictive memory access request have request identification fields with different values; wherein, if the value of the request identification field is a first value, it indicates that the request is a memory access request; if the value of the request identification field is a second value, it indicates that the request is a predictive memory access request.

[0166] As an optional implementation, the prefetch processing logic unit 510 is also used to detect whether the current state meets the processing conditions of the predictive memory access request after obtaining the predictive memory access request; if so, enter the step of transmitting the predictive memory access request to the memory control module; if not, discard the predictive memory access request; wherein the predictive memory access request has a discardable attribute.

[0167] In an optional implementation, the current state includes:

[0168] The working state of the consistency management module, wherein if the working state of the consistency management module is an idle state, the processing condition of the predictive memory access request is met, and if the working state of the consistency management module is a busy state, the processing condition of the predictive memory access request is not met;

[0169] and / or,

[0170] The data status of the predictive memory access request, wherein, if the data status of the predictive memory access request is not cached or has not been modified in the independent cache of other CPU cores, then the processing conditions of the predictive memory access request are met; if the data status of the predictive memory access request is modified in the independent cache of other CPU cores, then the processing conditions of the predictive memory access request are not met; wherein, the predictive memory access request does not participate in cache consistency management.

[0171] In an optional implementation, the memory access request processing logic unit 520 is configured to determine whether the memory access data requested by the memory access request is pre-fetched, including:

[0172] Determine whether the memory access data requested by the memory access request has been pre-fetched, wherein if the memory access data requested by the memory access request has been pre-fetched, the memory access address saved by the consistency management module corresponds to the memory access request;

[0173] or,

[0174] Determine whether the memory access data requested by the memory access request is being prefetched, wherein if the memory access data requested by the memory access request is being prefetched, the consistency management module has transmitted the predictive memory access request corresponding to the memory access address and the memory access request to the memory control module, but has not yet obtained the predictive data fed back by the memory control module;

[0175] In a further optional implementation, the memory access request processing logic unit 520 is also used to wait for the prediction data fed back by the memory control module if the memory access data requested by the memory access request is being prefetched, so as to save the prediction data fed back by the memory control module and the corresponding memory access address.

[0176] In a further optional implementation, the memory access request processing logic unit 520 is also used to transmit the memory access request to the memory control module if it is determined that the memory access data requested by the memory access request has not been prefetched; obtain the memory access data of the memory access request read from the memory by the memory control module based on the memory access request; and feed back the memory access data of the memory access request to the CPU core through the on-chip network.

[0177] In a further optional implementation, the memory access request processing logic unit 520 is also used to perform cache consistency management based on the memory access request after obtaining the memory access request of the CPU core routed by the on-chip network, so as to check whether the memory access data required by the memory access request is in the independent cache of other CPU cores; if not, entering the step of determining whether the memory access data requested by the memory access request is pre-fetched; if so, notifying other CPU cores holding the memory access data to provide the memory access data to the CPU core that issued the memory access request.

[0178] As an optional implementation, the pre-fetch processing logic unit 510 is used to store the predicted data and the corresponding memory access address, including:

[0179] In the data pre-fetch cache, the predicted data and the corresponding memory access address are cached;

[0180] Alternatively, the prediction data and the corresponding memory access address are stored in a consistency directory, wherein the consistency directory is used for cache consistency management of the consistency management module.

[0181] Furthermore, the embodiment of the present application also provides a consistency management module, which is configured to execute the process steps related to the consistency management module in the memory access method provided by the embodiment of the present application; for example, the consistency management module can be configured to execute the process steps related to the consistency management module in the memory access method provided by the embodiment of the present application by setting the memory access device provided by the embodiment of the present application. For example, in the chip design stage, the hardware logic of the logical function unit of the memory access device (such as the pre-fetch processing logic unit and the memory access request processing logic unit) can be designed in the consistency management module, so that through the hardware logic design of the consistency management module and the control of the software microcode, the consistency management module can execute the process steps related to the consistency management module in the memory access method provided by the embodiment of the present application.

[0182] In a further optional implementation, the embodiment of the present application further provides a computer device, such as a terminal device or a server device, which may include the chip provided by the embodiment of the present application. The relevant architecture and functions of the chip provided by the embodiment of the present application can be referred to the above description and will not be expanded here.

[0183] The above describes multiple implementation schemes provided by the embodiments of the present application. The various optional methods introduced in each implementation scheme can be combined and cross-referenced with each other without conflict, thereby extending a variety of possible implementation schemes, which can all be considered as implementation schemes disclosed and open in the embodiments of the present application.

[0184] Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims

1. A chip, characterized in that: include: An address transmission network is used to obtain a memory access address and route the memory access address to a consistency management module; The on-chip network is used to route the memory access request of the CPU core to the consistency management module; wherein the routing speed of the address transmission network is faster than that of the on-chip network; The consistency management module is used to: Obtaining a predictive memory access request, the predictive memory access request is generated based on a memory access address output by an address transmission network; transmitting the predictive memory access request to a memory control module so that the memory control module pre-fetches predicted data from the memory based on the predictive memory access request; obtaining predicted data pre-fetched from the memory by the memory control module based on the predictive memory access request; saving the predicted data and the corresponding memory access address; And, obtain the memory access request of the CPU core routed by the on-chip network, and determine whether the memory access data requested by the memory access request is pre-fetched; if so, use the saved prediction data of the memory access address corresponding to the memory access request as the memory access data of the memory access request, and feed back the memory access data of the memory access request to the CPU core through the on-chip network.

2. The chip according to claim 1, characterized in that: The chip further comprises: a plurality of address injection modules, wherein the address injection modules are used to inject memory access addresses into the address transmission network.

3. The chip according to claim 2, characterized in that: The memory access address includes a predicted memory access address, and the predicted memory access address is a memory access address of a future memory access demand predicted by the CPU core based on a prediction algorithm; the address injection module includes: a first address injection module; The first address injection module connects the CPU core and the address transmission network, and is used to inject the predicted memory access address predicted by the CPU core into the address transmission network.

4. The chip according to claim 2, characterized in that: The memory access address includes a formal memory access address, and the formal memory access address is a memory access address in a memory access request of a CPU core; the address injection module includes: a second address injection module; The second address injection module connects the on-chip interface of the cache controller of the LLC with the address transmission network, and is used to inject the memory access address in the memory access request transmitted by the on-chip interface into the address transmission network when the LCC misses, wherein the on-chip interface transmits the memory access request to the on-chip network; And / or, the second address injection module connects any node in the on-chip network that participates in the memory access request forwarding processing with the address transmission network, and is used to inject the memory access address in the memory access request forwarded by the arbitrary node into the address transmission network.

5. The chip according to claim 1, characterized in that: The chip also includes: a request generation module; The request generation module connects the consistency management module with the address transmission network, is used to obtain the memory access address output by the address transmission network, generate a predictive memory access request based on the memory access address output by the address transmission network, and transmit the predictive memory access request to the consistency management module; The consistency management module, used to obtain the predictive memory access request, includes: Acquire the predictive memory access request transmitted by the request generation module.

6. The chip according to claim 1, characterized in that: The consistency management module connects the on-chip network and the address transmission network through different hardware ports.

7. The chip according to claim 1, characterized in that: The memory access request and the predictive memory access request have request identification fields with different values; wherein, if the value of the request identification field is a first value, it indicates that the request is a memory access request; and if the value of the request identification field is a second value, it indicates that the request is a predictive memory access request.

8. The chip according to any one of claims 1 to 7, characterized in that: The consistency management module is also used for: After obtaining the predictive memory access request, check whether the current state meets the processing conditions of the predictive memory access request; if so, enter the step of transmitting the predictive memory access request to the memory control module; if not, discard the predictive memory access request; wherein the predictive memory access request has a discardable attribute.

9. The chip according to claim 8, characterized in that: The current status includes: The working state of the consistency management module, wherein if the working state of the consistency management module is an idle state, the processing condition of the predictive memory access request is met, and if the working state of the consistency management module is a busy state, the processing condition of the predictive memory access request is not met; and / or, The data status of the predictive memory access request, wherein, if the data status of the predictive memory access request is not cached or has not been modified in the independent cache of other CPU cores, then the processing conditions of the predictive memory access request are met; if the data status of the predictive memory access request is modified in the independent cache of other CPU cores, then the processing conditions of the predictive memory access request are not met; wherein, the predictive memory access request does not participate in cache consistency management.

10. The chip according to any one of claims 1 to 7, characterized in that: The consistency management module is used to determine whether the memory access data requested by the memory access request is pre-fetched, including: Determine whether the memory access data requested by the memory access request has been pre-fetched, wherein if the memory access data requested by the memory access request has been pre-fetched, the memory access address saved by the consistency management module corresponds to the memory access request; or, Determine whether the memory access data requested by the memory access request is being prefetched, wherein if the memory access data requested by the memory access request is being prefetched, the consistency management module has transmitted the predictive memory access request corresponding to the memory access address and the memory access request to the memory control module, but has not yet obtained the predictive data fed back by the memory control module; The consistency management module is also used to wait for the prediction data fed back by the memory control module if the memory access data requested by the memory access request is being pre-fetched, so as to save the prediction data fed back by the memory control module and the corresponding memory access address.

11. The chip according to claim 10, characterized in that: The consistency management module is also used to, if it is determined that the memory access data requested by the memory access request is not pre-fetched, transmit the memory access request to the memory control module; obtain the memory access data of the memory access request read from the memory by the memory control module based on the memory access request; and feed back the memory access data of the memory access request to the CPU core through the on-chip network.

12. The chip according to any one of claims 1 to 7, characterized in that: The consistency management module is also used for: After obtaining the memory access request of the CPU core routed by the on-chip network, cache consistency management is performed based on the memory access request to check whether the memory access data required by the memory access request is in the independent cache of other CPU cores; If not, then entering the step of determining whether the memory access data requested by the memory access request is pre-fetched; If so, the other CPU cores holding the memory access data are notified, and the memory access data is provided to the CPU core that issued the memory access request.

13. The chip according to any one of claims 1 to 7, characterized in that: The chip further includes: a data pre-fetch cache connected to the consistency management module; The consistency management module, used to store the prediction data and the corresponding memory access address, includes: In the data pre-fetch cache, the predicted data and the corresponding memory access address are cached; Wherein, the data replacement strategy of the data pre-fetch cache includes: FIFO replacement strategy, or LRU replacement strategy; The data pre-fetch cache is independently configured, or the data pre-fetch cache is combined with the system cache of the chip.

14. The chip according to any one of claims 1 to 7, characterized in that: The consistency management module, used to store the prediction data and the corresponding memory access address, includes: The prediction data and the corresponding memory access address are stored in the consistency directory, wherein the consistency directory is used for cache consistency management of the consistency management module.

15. The chip according to any one of claims 1 to 7, characterized in that: The network frequency of the address transmission network is lower than the network frequency of the on-chip network, the capacitance effect on the routing of the address transmission network is smaller than the capacitance effect on the routing of the on-chip network, and the number of repeaters in the address transmission network is smaller than the number of repeaters in the on-chip network; wherein the address transmission network is designed to have a routing function, and the cache forwarding function is canceled.

16. The chip according to any one of claims 1 to 7, characterized in that: The sending end and receiving end of the address transmission network are synchronized according to the global transmission clock; wherein, the sending end of the address transmission network is a functional module in the chip that sends the memory access address to the address transmission network, and the receiving end of the address transmission network is a functional module that receives the memory access address output by the address transmission network.

17. A memory access method, characterized in that: Applied to the consistency management module, the method comprises: Obtaining a predictive memory access request, the predictive memory access request is generated based on a memory access address output by an address transmission network; transmitting the predictive memory access request to a memory control module so that the memory control module pre-fetches predicted data from the memory based on the predictive memory access request; obtaining predicted data pre-fetched from the memory by the memory control module based on the predictive memory access request; saving the predicted data and the corresponding memory access address; and obtaining a memory access request of a CPU core routed by the on-chip network, and determining whether the memory access data requested by the memory access request is pre-fetched; if so, using the saved prediction data of the memory access address corresponding to the memory access request as the memory access data of the memory access request, and feeding back the memory access data of the memory access request to the CPU core through the on-chip network; Among them, the routing speed of the address transmission network is faster than that of the on-chip network.

18. The memory access method according to claim 17, characterized in that: The memory access address output by the address transmission network includes a predicted memory access address, where the predicted memory access address is a memory access address of a future memory access demand predicted by the CPU core based on a prediction algorithm; and / or, The memory access address output by the address transmission network includes a formal memory access address, and the formal memory access address is the memory access address in the memory access request of the CPU core.

19. The memory access method according to claim 17, characterized in that: The obtaining of the predictive memory access request comprises: Obtaining a predictive memory access request transmitted by a request generation module; Among them, the request generation module connects the consistency management module and the address transmission network in the chip, is used to obtain the memory access address output by the address transmission network, generate a predictive memory access request based on the memory access address output by the address transmission network, and transmit the predictive memory access request to the consistency management module.

20. The memory access method according to claim 17, characterized in that: The memory access request and the predictive memory access request have request identification fields with different values; wherein, if the value of the request identification field is a first value, it indicates that the request is a memory access request; and if the value of the request identification field is a second value, it indicates that the request is a predictive memory access request.

21. The memory access method according to any one of claims 17 to 19, characterized in that: Also includes: After obtaining the predictive memory access request, detecting whether the current state satisfies the processing condition of the predictive memory access request; If yes, then entering the step of transmitting the predictive memory access request to the memory control module; If not, the predictive memory access request is discarded; wherein the predictive memory access request has a discardable attribute.

22. The memory access method according to claim 21, characterized in that: The current status includes: The working state of the consistency management module, wherein if the working state of the consistency management module is an idle state, the processing condition of the predictive memory access request is met, and if the working state of the consistency management module is a busy state, the processing condition of the predictive memory access request is not met; and / or, The data status of the predictive memory access request, wherein, if the data status of the predictive memory access request is not cached or has not been modified in the independent cache of other CPU cores, then the processing conditions of the predictive memory access request are met; if the data status of the predictive memory access request is modified in the independent cache of other CPU cores, then the processing conditions of the predictive memory access request are not met; wherein, the predictive memory access request does not participate in cache consistency management.

23. The memory access method according to any one of claims 17 to 19, characterized in that: The determining whether the memory access data requested by the memory access request is pre-fetched comprises: Determine whether the memory access data requested by the memory access request has been pre-fetched, wherein if the memory access data requested by the memory access request has been pre-fetched, the memory access address saved by the consistency management module corresponds to the memory access request; or, Determine whether the memory access data requested by the memory access request is being prefetched, wherein if the memory access data requested by the memory access request is being prefetched, the consistency management module has transmitted the predictive memory access request corresponding to the memory access address and the memory access request to the memory control module, but has not yet obtained the predictive data fed back by the memory control module; The method further comprises: If the memory access data requested by the memory access request is being pre-fetched, the prediction data fed back by the memory control module is waited for, so as to save the prediction data fed back by the memory control module and the corresponding memory access address.

24. The memory access method according to claim 23, characterized in that: The stored prediction data and the corresponding memory access address include: In the data pre-fetch cache, the predicted data and the corresponding memory access address are cached; Alternatively, the prediction data and the corresponding memory access address are stored in a consistency directory, wherein the consistency directory is used for cache consistency management of the consistency management module.

25. A memory access device, characterized in that: Applied to a consistency management module, the device comprises: A prefetch processing logic unit is used to obtain a predictive memory access request, which is generated based on a memory access address output by an address transmission network; transmit the predictive memory access request to a memory control module so that the memory control module prefetches predicted data from the memory based on the predictive memory access request; obtain the predicted data prefetched from the memory by the memory control module based on the predictive memory access request; and save the predicted data and the corresponding memory access address; A memory access request processing logic unit is used to obtain a memory access request of a CPU core routed by the on-chip network, and determine whether the memory access data requested by the memory access request is pre-fetched; if so, the saved prediction data of the memory access address corresponding to the memory access request is used as the memory access data of the memory access request, and the memory access data of the memory access request is fed back to the CPU core through the on-chip network; Among them, the routing speed of the address transmission network is faster than that of the on-chip network.

26. A consistency management module, characterized in that: The consistency management module is configured to execute the memory access method according to any one of claims 17 to 24, or the consistency management module is provided with the memory access device according to claim 25.

27. A computer device, characterized in that: Comprising a chip as described in any one of claims 1-16.

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