FPGA (Field Programmable Gate Array) on-chip spectrum sensing data compression method and system

Abstract

The invention discloses an FPGA (Field Programmable Gate Array) on-chip spectrum sensing data compression method and system. The method comprises the following steps: acquiring spectrum sensing data acquired by a digital acquisition board; performing signal detection on the spectrum sensing data to obtain a long-segment sequence and writing the long-segment sequence into an FIFO cache; constructing a Hash dictionary according to the data read by the FIFO cache, and then performing preliminary compression on the data to obtain a preliminary compression result; constructing a Huffman tree according to the preliminary compression result, then performing secondary compression on the preliminary compression result to obtain a secondary compression result, and writing the secondary compression result into an FIFO cache; outputting a Gzip data stream according to a secondary compression result in the FIFO cache through a PCIE (Peripheral Component Interface Express) interface; according to the invention, high-efficiency spectrum sensing data compression is realized.

Description

Technical Field

[0001] The present invention relates to the field of spectrum sensing and data compression, and in particular to a spectrum sensing data compression method and system on an FPGA chip. Background Art

[0002] In the context of the information age represented by 5G, 6G, the Internet of Things, and integrated space-ground communications, various new types of intelligent equipment have been accessed in the fields of radar, communications, navigation, etc., and businesses are emerging in an endless stream, making the electromagnetic spectrum environment increasingly complex and available spectrum resources increasingly scarce.

[0003] Spectrum sensing obtains spectrum occupancy information in electromagnetic space by performing various detections and processing on signals in different domains. It is the leading means to resolve the sharp contradiction between the increasingly scarce spectrum resources and the insufficient utilization of the allocated spectrum resources.

[0004] In spectrum sensing systems, the performance indicators of ADC, FPGA, DSP and other devices required have been greatly improved with the development of integrated circuits. During long-term operation, spectrum sensing systems will generate massive amounts of electromagnetic spectrum data. The large amount of data to be transmitted makes it difficult to allocate hardware resources between sensors and data processing centers, store large-capacity data and transmit downlink data, which has a negative impact on the entire spectrum sensing system.

[0005] The Chinese invention application with application number 202311739105.4 discloses "An FPGA-based LZ4 compression and decompression system and medium", and its technical solution is: an FPGA-based LZ4 compression and decompression system and medium, including: an encoder unit and a decoder unit; the encoder unit includes: an input buffer, a forward buffer, a hash dictionary and an encoding circuit; the input buffer, which groups and caches the original data to be compressed; the forward buffer, which performs a sliding window traversal on the grouped string data; the hash dictionary, which determines whether the traversed data is the first-appearing string or a repeated string, stores the first-appearing string as a non-matching item in the dictionary and obtains the non-matching item information, and uses the repeated string as a matching item to obtain the matching item information; the encoding circuit, which outputs the non-matching item information and the matching item information as a compressed data frame according to the set compressed data frame format; the decoder unit, which decodes the compressed data frame according to the compressed data frame format to obtain the decompressed restored data. The compression rate, power consumption and processing speed of this technical solution need to be improved. Summary of the invention

[0006] In order to solve the technical problem of low compression efficiency in the existing spectrum sensing data compression technology, the present invention provides an FPGA on-chip spectrum sensing data compression method and system. The technical solution adopted by the present invention is:

[0007] A first aspect of the present invention provides a spectrum sensing data compression method on an FPGA chip, the method comprising:

[0008] Obtain spectrum sensing data collected by the digital acquisition board;

[0009] Performing signal detection on the spectrum sensing data to obtain a long segment sequence and writing the long segment sequence into a FIFO buffer;

[0010] A hash dictionary is constructed based on the data read from the FIFO buffer, and then the data is preliminarily compressed to obtain a preliminary compression result;

[0011] Constructing a Huffman tree according to the preliminary compression result, and then performing secondary compression on the preliminary compression result to obtain a secondary compression result and write it into a FIFO buffer;

[0012] The secondary compression result in the FIFO buffer is output as a Gzip data stream through the PCIE interface.

[0013] As a preferred solution, a hash dictionary is constructed based on the data read from the FIFO cache, and then the data is preliminarily compressed. The method for obtaining the preliminary compression result includes:

[0014] The data is continuously read out through the front-end FIFO and input into the LZ77 encoder, and the read data is divided into multiple data blocks to be compressed. Among them, the continuous read data with a length not exceeding a certain byte will be divided into one block to be compressed, otherwise it will be divided into multiple blocks to be compressed; at the same time, when the length of a continuous input is not less than a certain byte, the input segment will be compressed, otherwise it will be discarded;

[0015] Perform sliding window traversal on the data to be compressed, build a hash table matching search, and use the length and distance obtained by matching together with the remaining fields to form the preliminary compression result.

[0016] As a preferred solution, a hash dictionary is constructed based on the data read from the FIFO buffer, and then the data is preliminarily compressed. The method for obtaining the preliminary compression result also includes:

[0017] The data read from the FIFO buffer is delayed by a preset pipeline controller and input into a preset check word generator;

[0018] The check word generator calculates the CRC check code according to the data read from the FIFO buffer and the CRC code table;

[0019] The CRC check code ensures that low-confidence data error correction is completed when the compressed data is decompressed.

[0020] As a preferred solution, a method for constructing a Huffman tree according to the preliminary compression result, and then performing secondary compression on the preliminary compression result to obtain the secondary compression result and write it into the FIFO cache includes:

[0021] Converting the preliminary compression result into an interval code;

[0022] The remaining words and interval code streams are counted and counted through the counting register array;

[0023] Repeat the traversal of the count register array and find the two code elements with the smallest statistical counts during this traversal, merge the count values ​​and increase the tree depth count of the corresponding code elements;

[0024] Obtaining a codeword length column of the Hufman tree according to the tree depth count;

[0025] Traverse the tree depth register array and calculate the Hufman codeword and extended bit codeword corresponding to each interval code;

[0026] Perform Huffman encoding on the codeword length column and obtain its codeword length column; output the block header, each group of bit streams and their corresponding item numbers in Gzip format through the state machine control, and put the CRC check code at the end of Gzip for verification during decompression;

[0027] Write the Gzip data stream as the secondary compression result into the FIFO buffer.

[0028] As a preferred solution, the method of outputting the secondary compression result in the FIFO buffer to a Gzip data stream through a PCIE interface includes:

[0029] The computer sends a read request, and the data output module releases the read enable to the FIFO buffer; the Gzip data stream of the FIFO output buffer is transmitted to the computer through the PCIE interface; after reading a compressed package data, the data output module releases the PCIE interrupt signal to inform the computer to interrupt the operation and complete the reading of a compressed package data.

[0030] A second aspect of the present invention provides an FPGA on-chip spectrum sensing data compression system, including a spectrum sensing data acquisition module, a signal detection module, an LZ77 module, a Huffman encoder module, and a data output module integrated in the FPGA and connected in sequence;

[0031] The spectrum sensing data acquisition module is used to acquire spectrum sensing data collected by the digital acquisition board;

[0032] The signal detection module is used to perform signal detection on the spectrum sensing data to obtain a long segment sequence and write it into a FIFO buffer;

[0033] The LZ77 module is used to construct a hash dictionary based on the data read from the FIFO cache, and then perform preliminary compression on the data to obtain a preliminary compression result;

[0034] The Huffman encoder module is used to construct a Huffman tree according to the preliminary compression result, and then perform secondary compression on the preliminary compression result to obtain a secondary compression result and write it into the FIFO buffer;

[0035] The data output module is used to output the secondary compression result in the FIFO buffer as a Gzip data stream through the PCIE interface.

[0036] As a preferred solution, the FPGA uses AMD's Virtex Ultrascale+ device to transmit baseband signal data.

[0037] As a preferred solution, the LZ77 module uses the AXI4-Stream protocol as the input interface design, the input data bit width is 8 bits, and 1 byte of input data is processed per clock cycle.

[0038] A third aspect of the present invention provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the steps of the aforementioned on-chip spectrum sensing data compression method for FPGA.

[0039] A fourth aspect of the present invention provides a computer device, comprising a storage medium, a processor, and a computer program stored in the storage medium and executable by the processor, wherein the computer program, when executed by the processor, implements the steps of the aforementioned on-chip spectrum sensing data compression method for FPGA.

[0040] Compared with the prior art, the present invention has the following beneficial effects:

[0041] The present invention realizes hash dynamic dictionary compression on spectrum sensing data stream through LZ77 encoding module.

[0042] The present invention constructs a Huffman tree on the preliminary compression result through a multi-level state machine to obtain a standard Gzip data stream.

[0043] The spectrum sensing data compression system provided by the present invention can realize efficient lossless compression of collected broadband signals on FPGA, has a high compression rate, and is suitable for broadband spectrum sensing processes with high data volumes. The compression module implemented on FPGA by the present invention has the advantages of low power consumption and high processing speed, and can meet the needs of real-time signal processing. BRIEF DESCRIPTION OF THE DRAWINGS

[0044] Figure 1A flow chart of a spectrum sensing data compression method on an FPGA chip provided in this embodiment;

[0045] Figure 2 A schematic diagram of the structure of the LZ77 module provided in this embodiment;

[0046] Figure 3 A schematic diagram of the Huffman encoder module workflow provided in this embodiment;

[0047] Figure 4 This is a workflow diagram of the data output module provided in this embodiment. DETAILED DESCRIPTION

[0048] The accompanying drawings are only used for illustrative purposes and are not to be construed as limiting the present invention;

[0049] It should be clear that the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the embodiments of the present application.

[0050] The terms used in the embodiments of the present application are only for the purpose of describing specific embodiments, and are not intended to limit the embodiments of the present application. The singular forms of "a", "said" and "the" used in the embodiments of the present application and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings. It should also be understood that the term "and / or" used herein refers to and includes any or all possible combinations of one or more associated listed items.

[0051] When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. On the contrary, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the attached claims. In the description of the present application, it should be understood that the terms "first", "second", "third", etc. are only used to distinguish similar objects, and do not have to be used to describe a specific order or sequence, nor can they be understood as indicating or implying relative importance. For those of ordinary skill in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0052] In addition, in the description of this application, unless otherwise specified, "multiple" means two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. The character " / " generally indicates that the previous and next associated objects are in an "or" relationship. The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0053] The present invention is further described below in conjunction with the accompanying drawings and embodiments.

[0054] Example 1

[0055] Please refer to Figure 1 This embodiment provides a spectrum sensing data compression method on an FPGA chip, the method comprising:

[0056] Obtain spectrum sensing data collected by the digital acquisition board;

[0057] Performing signal detection on the spectrum sensing data to obtain a long segment sequence and writing the long segment sequence into a FIFO buffer;

[0058] Please refer to Figure 2 , build a hash dictionary based on the data read from the FIFO cache, and then perform preliminary compression on the data to obtain a preliminary compression result;

[0059] Please refer to Figure 3 , constructing a Huffman tree according to the preliminary compression result, and then performing secondary compression on the preliminary compression result to obtain a secondary compression result and write it into a FIFO cache;

[0060] Please refer to Figure 4 , the secondary compression result in the FIFO buffer is output as a Gzip data stream through the PCIE interface.

[0061] In a specific embodiment, a hash dictionary is constructed based on data read from the FIFO buffer, and then the data is preliminarily compressed to obtain a preliminary compression result, including:

[0062] The data is continuously read out through the front-end FIFO and input into the LZ77 encoder, and the read data is divided into multiple data blocks to be compressed. Among them, the continuous read data with a length not exceeding a certain byte will be divided into one block to be compressed, otherwise it will be divided into multiple blocks to be compressed; at the same time, when the length of a continuous input is not less than a certain byte, the input segment will be compressed, otherwise it will be discarded;

[0063] Perform sliding window traversal on the data to be compressed, build a hash table matching search, and use the length and distance obtained by matching together with the remaining fields to form the preliminary compression result.

[0064] In a specific embodiment, a hash dictionary is constructed based on data read from the FIFO buffer, and then the data is preliminarily compressed to obtain a preliminary compression result, and the method further includes:

[0065] The data read from the FIFO buffer is delayed by a preset pipeline controller and input into a preset check word generator;

[0066] The check word generator calculates the CRC check code according to the data read from the FIFO buffer and the CRC code table;

[0067] The CRC check code ensures that low-confidence data error correction is completed when the compressed data is decompressed.

[0068] In a specific embodiment, a method of constructing a Huffman tree according to the preliminary compression result, and then performing secondary compression on the preliminary compression result to obtain the secondary compression result and write it into the FIFO cache includes:

[0069] Converting the preliminary compression result into an interval code;

[0070] The remaining words and interval code streams are counted and counted through the counting register array;

[0071] Repeat the traversal of the count register array and find the two code elements with the smallest statistical counts during this traversal, merge the count values ​​and increase the tree depth count of the corresponding code elements;

[0072] Obtaining a codeword length column of the Hufman tree according to the tree depth count;

[0073] Traverse the tree depth register array and calculate the Hufman codeword and extended bit codeword corresponding to each interval code;

[0074] Perform Huffman encoding on the codeword length column and obtain its codeword length column; output the block header, each group of bit streams and their corresponding item numbers in Gzip format through the state machine control, and put the CRC check code at the end of Gzip for verification during decompression;

[0075] Write the Gzip data stream as the secondary compression result into the FIFO buffer.

[0076] In a specific embodiment, the method of outputting the secondary compression result in the FIFO buffer to a Gzip data stream through a PCIE interface includes:

[0077] The computer sends a read request, and the data output module releases the read enable to the FIFO buffer; the Gzip data stream of the FIFO output buffer is transmitted to the computer through the PCIE interface; after reading a compressed package data, the data output module releases the PCIE interrupt signal to inform the computer to interrupt the operation and complete the reading of a compressed package data.

[0078] Example 2

[0079] This embodiment provides an FPGA on-chip spectrum sensing data compression system, including a spectrum sensing data acquisition module, a signal detection module, an LZ77 module, a Huffman encoder module, and a data output module integrated in the FPGA and connected in sequence;

[0080] The spectrum sensing data acquisition module is used to acquire spectrum sensing data collected by the digital acquisition board;

[0081] The signal detection module is used to perform signal detection on the spectrum sensing data to obtain a long segment sequence and write it into a FIFO buffer;

[0082] The LZ77 module is used to construct a hash dictionary based on the data read from the FIFO cache, and then perform preliminary compression on the data to obtain a preliminary compression result;

[0083] Specifically, the search distance of the LZ77 module covers the entire block to be compressed. During the compression process, a sliding window is traversed on the data to be compressed, and a hash table matching search is constructed. The hash value is calculated using the three consecutive bytes starting from the first byte of the current lookahead buffer, and the hash value is used as the index of the pointer to record the position where the string appears, and the value of the lookahead buffer is stored in the hash table, which is the process of inserting the character into the dictionary. The same characters have the same hash value after being processed by the hash function. Therefore, while calculating the hash value of the string, the hash value will also be used to read the corresponding content of the hash table for matching. The pointer index is read out using the read hash value. If the pointer is not read empty in the hash table, matching begins until an unmatched field appears. The offset in the matching process is calculated by looking up the position value read out by the pointer of the buffer and the lookahead buffer to obtain the length (length) and distance (distance) of the match, which together with the remaining fields (literal) constitute the first-level compression result.

[0084] Since the hash value is calculated using the first three bytes in each cycle and pushed into the hash table, the string corresponding to the hash value will always be up to date, thereby achieving the function of finding the longest matching string in the hash table.

[0085] The Huffman encoder module is used to construct a Huffman tree according to the preliminary compression result, and then perform secondary compression on the preliminary compression result to obtain a secondary compression result and write it into the FIFO buffer;

[0086] Specifically, the Huffman tree is controlled by a state machine, and the states of the state machine are described as follows:

[0087] State 1, idle state, in which all ports are initialized, and when the Huffman coding enable is pulled high, coding begins. In addition, the register array counts the number of distance codes and length codes that appear in the code stream, and this counting function is not controlled by the state.

[0088] State 2, traversal search and sorting. In this state, the register array is traversed through the index counter to find the two code elements with the smallest current count value, that is, the least number of occurrences.

[0089] State 3, repeated traversal. In this state, the two smallest count values ​​are added and stored in an index register, and the other register is disabled. At the algorithm level, it is equivalent to merging two subtrees. At this time, the merge indication level is pulled high, and the Huffman tree depth count of the corresponding code element is increased on the next clock edge. At the same time, in order to complete the sorting of the code element count, it is necessary to traverse the same number of times as the number of code elements, and the state machine will return to state 2 and traverse again. If all traversals are completed, enter state 4.

[0090] State 4, Huffman codeword length counting. Traverse the tree depth register array and calculate the Huffman codeword length corresponding to each distance code and length code, which is the codeword length column that records the Huffman tree information.

[0091] State 5, calculate Huffman coding codewords. Use the counter to traverse the tree by depth, and calculate the area Huffman tree code and extended bit code corresponding to the distance code and length code.

[0092] The data output module is used to output the secondary compression result in the FIFO buffer as a Gzip data stream through the PCIE interface.

[0093] In a specific embodiment, the FPGA uses AMD's Virtex Ultrascale+ device to transmit baseband signal data.

[0094] In a specific embodiment, the LZ77 module uses the AXI4-Stream protocol as the input interface design, the input data width is 8 bits, and 1 byte of input data is processed per clock cycle.

[0095] It should be noted that, since all functions are implemented by FPGA devices, the flexibility and complexity of the design are much different from those based on general-purpose processors. Therefore, in order to implement the compression system of the present invention on FPGA, the present application rationally designs the various modules of the compression system, including functional division and logic resources. The input cache FIFO in the present application implements the cache of the front-stage input data of the compression module, and is ultimately implemented based on the RAM resources on the FPGA. At the same time, the pointer in the compression module is based on a counter, the hash function is based on shift, splicing and addition combinational logic, the hash table is based on a multidimensional register array, and the matching function is based on comparison judgment logic. The internal ports, functions and resources called by these modules can all be easily implemented by FPGA devices.

[0096] The present invention reasonably designs the logic functions and resource occupancy of each module in the compression system, so that each submodule can be supported by the characteristics of the FPGA device. The logic functions of each module are orderly, the resource occupancy and layout and wiring are reasonable, and the timing converges, so that the compression system of the present invention improves the operating speed of the entire system by effectively utilizing the FPGA under the premise of realizing the function.

[0097] Example 3

[0098] A computer-readable storage medium stores a computer program, which, when executed by a processor, implements the steps of an on-chip spectrum sensing data compression method for FPGA described in Example 1.

[0099] Example 4

[0100] A computer device includes a storage medium, a processor, and a computer program stored in the storage medium and executable by the processor. When the computer program is executed by the processor, the steps of the on-chip spectrum sensing data compression method of FPGA described in Example 1 are implemented.

[0101] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the embodiments here. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the claims of the present invention.

Claims

1. A spectrum sensing data compression method on an FPGA chip, characterized in that: The method comprises: Obtain spectrum sensing data collected by the digital acquisition board; Performing signal detection on the spectrum sensing data to obtain a long segment sequence and writing the long segment sequence into a FIFO buffer; A hash dictionary is constructed based on the data read from the FIFO buffer, and then the data is preliminarily compressed to obtain a preliminary compression result; Constructing a Huffman tree according to the preliminary compression result, and then performing secondary compression on the preliminary compression result to obtain a secondary compression result and write it into a FIFO buffer; The secondary compression result in the FIFO buffer is output as a Gzip data stream through the PCIE interface.

2. The spectrum sensing data compression method on an FPGA chip according to claim 1, characterized in that: A hash dictionary is constructed based on the data read from the FIFO buffer, and then the data is preliminarily compressed. Methods for obtaining a preliminary compression result include: The data is continuously read out through the front-end FIFO and input into the LZ77 encoder, and the read data is divided into multiple data blocks to be compressed. Among them, the continuous read data with a length not exceeding a certain byte will be divided into one block to be compressed, otherwise it will be divided into multiple blocks to be compressed; at the same time, when the length of a continuous input is not less than a certain byte, the input segment will be compressed, otherwise it will be discarded; Perform sliding window traversal on the data to be compressed, build a hash table matching search, and use the length and distance obtained by matching together with the remaining fields to form the preliminary compression result.

3. The spectrum sensing data compression method on an FPGA chip according to claim 2, characterized in that: A hash dictionary is constructed based on the data read from the FIFO buffer, and then the data is preliminarily compressed. The method for obtaining the preliminary compression result also includes: The data read from the FIFO buffer is delayed by a preset pipeline controller and input into a preset check word generator; The check word generator calculates the CRC check code according to the data read from the FIFO buffer and the CRC code table; The CRC check code ensures that low-confidence data error correction is completed when the compressed data is decompressed.

4. The spectrum sensing data compression method on an FPGA chip according to claim 1, characterized in that: The method of constructing a Huffman tree according to the preliminary compression result, and then performing secondary compression on the preliminary compression result to obtain the secondary compression result and write it into the FIFO cache comprises: Converting the preliminary compression result into an interval code; The remaining words and interval code streams are counted and counted through the counting register array; Repeat the traversal of the count register array and find the two code elements with the smallest statistical counts during this traversal, merge the count values ​​and increase the tree depth count of the corresponding code elements; Obtaining a codeword length column of the Hufman tree according to the tree depth count; Traverse the tree depth register array and calculate the Hufman codeword and extended bit codeword corresponding to each interval code; Perform Huffman encoding on the codeword length column and obtain its codeword length column; output the block header, each group of bit streams and their corresponding item numbers in Gzip format through the state machine control, and put the CRC check code at the end of Gzip for verification during decompression; Write the Gzip data stream as the secondary compression result into the FIFO buffer.

5. The spectrum sensing data compression method on an FPGA chip according to claim 1, characterized in that: The method of outputting the secondary compression result in the FIFO buffer to a Gzip data stream through a PCIE interface includes: The computer sends a read request, and the data output module releases the read enable to the FIFO buffer; the Gzip data stream of the FIFO output buffer is transmitted to the computer through the PCIE interface; after reading a compressed package data, the data output module releases the PCIE interrupt signal to inform the computer to interrupt the operation and complete the reading of a compressed package data.

6. An FPGA on-chip spectrum sensing data compression system, characterized in that: It includes a spectrum sensing data acquisition module, a signal detection module, an LZ77 module, a Huffman encoder module, and a data output module which are integrated in the FPGA and connected in sequence; The spectrum sensing data acquisition module is used to acquire spectrum sensing data collected by the digital acquisition board; The signal detection module is used to perform signal detection on the spectrum sensing data to obtain a long segment sequence and write it into a FIFO buffer; The LZ77 module is used to construct a hash dictionary based on the data read from the FIFO cache, and then perform preliminary compression on the data to obtain a preliminary compression result; The Huffman encoder module is used to construct a Huffman tree according to the preliminary compression result, and then perform secondary compression on the preliminary compression result to obtain a secondary compression result and write it into the FIFO buffer; The data output module is used to output the secondary compression result in the FIFO buffer as a Gzip data stream through the PCIE interface.

7. The spectrum sensing data compression system on an FPGA chip according to claim 6, characterized in that: The FPGA uses AMD's Virtex Ultrascale+ device to transmit baseband signal data.

8. The spectrum sensing data compression system on an FPGA chip according to claim 6, characterized in that: The LZ77 module uses the AXI4-Stream protocol as the input interface design, the input data width is 8 bits, and 1 byte of input data is processed per clock cycle.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the on-chip spectrum sensing data compression method of FPGA as claimed in any one of claims 1 to 5 are implemented.

10. A computer device, characterized in that: The invention comprises a storage medium, a processor and a computer program stored in the storage medium and executable by the processor, wherein when the computer program is executed by the processor, the steps of the on-chip spectrum sensing data compression method of an FPGA are implemented as described in any one of claims 1 to 5.

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