Display panel and display device

Abstract

The invention discloses a display panel and a display device. The display panel comprises a first display area, a second display area and a first non-display area. In the first direction, the first non-display area is located on at least one side of the first display area, the first display area and the second display area are arranged in the second direction, and the first direction intersects with the second direction; the display panel comprises at least one first signal line and at least one row of first pixels which are located in a first display area; the first signal lines extend along a first direction, and the first signal lines are connected with one row of first pixels; the at least one second signal line and the at least one row of second pixels are located in the second display area; the second signal lines extend along the first direction, and the second signal lines are connected with one row of second pixels; the number of the first pixels arranged in the first direction is smaller than that of the second pixels arranged in the first direction; at least one compensation capacitor is located in the first non-display area and connected with the first signal line. The brightness difference of the display panel can be improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the technical field of display, and in particular, to a display panel and a display device. Background Art

[0002] When the display panel is irregular in shape, the lengths of the signal lines corresponding to different pixels are different, so that different signal lines have different load values, resulting in different brightness of different pixels, which reduces the display effect of the display panel. Summary of the invention

[0003] The present invention provides a display panel and a display device to improve the brightness difference of the display panel and enhance the display effect of the display panel.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, comprising a first display area, a second display area and a first non-display area; along a first direction, the first non-display area is located on at least one side of the first display area, the first display area and the second display area are arranged along a second direction, and the first direction intersects the second direction; the display panel comprises:

[0005] At least one first signal line and at least one row of first pixels are located in the first display area; the first signal line extends along the first direction, and the first signal line is connected to a row of first pixels;

[0006] At least one second signal line and at least one row of second pixels are located in the second display area; the second signal line extends along the first direction, and the second signal line is connected to a row of second pixels; the number of the first pixels arranged along the first direction is less than the number of the second pixels arranged along the first direction;

[0007] At least one compensation capacitor is located in the first non-display area, and the compensation capacitor is connected to the first signal line.

[0008] Optionally, the display panel also includes a gate driving circuit; the gate driving circuit is arranged in the first non-display area, and the compensation capacitor is arranged on a side of the gate driving circuit close to the first display area; the gate driving circuit is connected to the first signal line to provide a scanning signal for the first signal line.

[0009] Optionally, the display panel also includes a substrate and a driving circuit layer, the driving circuit layer is arranged on the substrate, and the pixel circuit in the first pixel is located in the driving circuit layer; the driving circuit layer includes at least two conductive layers, and the compensation capacitor includes at least two plates, and the at least two plates of the compensation capacitor are respectively located in different conductive layers.

[0010] Optionally, the driving circuit layer includes a first conductive layer and a second conductive layer which are stacked, the first conductive layer is arranged on a side of the second conductive layer close to the substrate, the compensation capacitor includes a first electrode plate and a second electrode plate, the first electrode plate of the compensation capacitor is located in the first conductive layer, the second electrode plate of the compensation capacitor is located in the second conductive layer, and the orthographic projections of the first electrode plate of the compensation capacitor and the second electrode plate of the compensation capacitor on the substrate at least partially overlap; the first signal line is connected to the first electrode plate of the compensation capacitor;

[0011] Preferably, the second electrode plate of the compensation capacitor is connected to a signal with a constant potential;

[0012] Preferably, the second electrode plate of the compensation capacitor is connected to a power signal or an initialization signal;

[0013] Preferably, the second plates of the plurality of compensation capacitors are connected as one.

[0014] Optionally, the first signal line is located in the first conductive layer, the first signal line extends to the first non-display area, and the first signal line includes an overlapping portion at least partially overlapping with the second electrode plate of the compensation capacitor, and the overlapping portion of the first signal line is reused as the first electrode plate of the compensation capacitor;

[0015] Preferably, a width of the overlapping portion of the first signal line is greater than a width of the first signal line in the first display area.

[0016] Optionally, the driving circuit layer further includes a third conductive layer, and the third conductive layer is arranged on a side of the second conductive layer away from the first conductive layer;

[0017] The compensation capacitor further includes a third electrode plate, the third electrode plate of the compensation capacitor is located in the third conductive layer, the third electrode plate of the compensation capacitor is connected to the first electrode plate of the compensation capacitor, the first signal line extends to the first non-display area, and the first signal line includes an overlapping portion at least partially overlapping with the second electrode plate of the compensation capacitor, and the overlapping portion of the first signal line is reused as the third electrode plate of the compensation capacitor; preferably, the width of the overlapping portion of the first signal line is greater than the width of the first signal line in the first display area;

[0018] Preferably, the display panel further includes a light emitting control signal line, and the light emitting control signal line is located in the third conductive layer.

[0019] Optionally, the driving circuit layer includes a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer stacked in sequence, the compensation capacitor includes a first electrode plate and a second electrode plate, the first electrode plate of the compensation capacitor is located in the second conductive layer, the second electrode plate of the compensation capacitor is located in the third conductive layer, and the orthographic projections of the first electrode plate of the compensation capacitor and the second electrode plate of the compensation capacitor on the substrate at least partially overlap;

[0020] The compensation capacitor further includes a third electrode plate, the third electrode plate of the compensation capacitor is located on the fourth conductive layer, and the third electrode plate of the compensation capacitor is connected to the first electrode plate of the compensation capacitor;

[0021] The first signal line extends to the first non-display area, and the first signal line includes an overlapping portion at least partially overlapping with the second electrode plate of the compensation capacitor, and the overlapping portion of the first signal line is reused as the third electrode plate of the compensation capacitor;

[0022] Preferably, the width of the overlapping portion of the first signal line is greater than the width of the first signal line in the first display area;

[0023] Preferably, the second electrode plate of the compensation capacitor is used to access a signal with a constant potential;

[0024] Preferably, the second electrode plate of the compensation capacitor is used to access a power signal or an initialization signal;

[0025] Preferably, the display panel further comprises a light emitting control signal line, and the light emitting control signal line is located in the fourth conductive layer;

[0026] Preferably, the compensation capacitor further includes a fourth electrode plate, the fourth electrode plate of the compensation capacitor is connected to the second electrode plate of the compensation capacitor, and a vertical projection of the fourth electrode plate of the compensation capacitor on the substrate at least partially overlaps with a vertical projection of the first electrode plate on the substrate;

[0027] Preferably, the driving circuit layer further comprises a semiconductor layer, the semiconductor layer is arranged on a side of the first conductive layer close to the substrate, and the fourth electrode is located on the first conductive layer or the semiconductor layer.

[0028] Optionally, the display panel also includes a second non-display area and a third non-display area; along the first direction, the second non-display area is arranged on at least one side of the second display area; along the second direction, the third non-display area is arranged on a side of the first display area away from the second display area; the display panel includes a plurality of the compensation capacitors, at least one of the compensation capacitors is arranged in the second non-display area and / or the third non-display area.

[0029] Optionally, the display panel also includes a second non-display area and a plurality of cascaded gate drive circuits; along the first direction, the second non-display area is arranged on at least one side of the second display area; the gate drive circuit is arranged in the first non-display area and the second non-display area; the gate drive circuit includes a first capacitor and a first transistor; the first electrode of the first transistor is used to input a clock signal, the second electrode of the first transistor is connected to the first plate of the first capacitor, and the second electrode of the first transistor is connected to the first signal line or the second signal line, and the gate of the first transistor is connected to the second plate of the first capacitor; the capacitance value of the first capacitor connected to the first signal line is greater than the capacitance value of the first capacitor connected to the second signal line.

[0030] Optionally, the compensation capacitor includes the first capacitor.

[0031] Optionally, the gate driving circuit connected to the first signal line is a first gate driving circuit, and the gate driving circuit connected to the second signal line is a second gate driving circuit; along the first direction, the width of the first plate of the first capacitor in the first gate driving circuit is greater than the width of the first plate of the first capacitor in the second gate driving circuit; the width of the second plate of the first capacitor in the first gate driving circuit is greater than the width of the second plate of the first capacitor in the second gate driving circuit;

[0032] Preferably, the display panel also includes a substrate and a first conductive layer and a second conductive layer stacked on the substrate, the first conductive layer is arranged on a side of the second conductive layer close to the substrate; the first plate of the first capacitor is located in the second conductive layer, and the second plate of the first capacitor is located in the first conductive layer.

[0033] Optionally, along the second direction, the length of the first plate of the first capacitor in the first gate driving circuit is greater than the length of the first plate of the first capacitor in the second gate driving circuit, and the length of the second plate of the first capacitor in the first gate driving circuit is greater than the length of the second plate of the first capacitor in the second gate driving circuit;

[0034] Preferably, at least part of the plate of the first capacitor in the first gate driving circuit extends between adjacent first gate driving circuits, or extends between the first gate driving circuit and the second gate driving circuit;

[0035] Preferably, along the second direction, the distance between adjacent first gate driving circuits is greater than the distance between adjacent second gate driving circuits.

[0036] Optionally, the display panel further includes a third conductive layer, and the third conductive layer is arranged on a side of the second conductive layer away from the substrate; the compensation capacitor further includes a second capacitor; the first electrode plate of the first capacitor is reused as the first electrode plate of the second capacitor, and the second electrode plate of the second capacitor is located on the third conductive layer; the vertical projection of the second electrode plate of the second capacitor on the substrate overlaps with the vertical projection of the first electrode plate of the first capacitor on the substrate;

[0037] Preferably, a cascade signal line is also arranged between adjacent gate drive circuits, the cascade signal line is connected to the first plate of the first capacitor in the gate drive circuit of the previous level, and the cascade signal line is connected to the starting signal input terminal of the gate drive circuit of this level; the cascade signal line is located in the third conductive layer.

[0038] Optionally, the first display area includes a plurality of first signal lines, and the capacitance values ​​of the compensation capacitors connected to the first signal lines are equal; or, along the direction from the second display area to the first display area, the capacitance values ​​of the compensation capacitors connected to the first signal lines gradually decrease;

[0039] Preferably, along the direction from the second display area to the first display area, the ratio of the sum of the capacitance values ​​of the compensation capacitor corresponding to the first first signal line and the equivalent capacitance of the first pixel to the sum of the capacitance values ​​of the compensation capacitor corresponding to the last first signal line and the equivalent capacitance of the first pixel is less than or equal to 100%:40%.

[0040] Optionally, the first display area includes a first sub-area and a second sub-area arranged along the first direction, and the first non-display area is arranged on a side of the first sub-area away from the second sub-area, and / or a side of the second sub-area away from the first sub-area.

[0041] In a second aspect, an embodiment of the present invention further provides a display panel, comprising a first display area, a second display area and a first non-display area; along a first direction, the first non-display area is located on at least one side of the first display area, the first display area and the second display area are arranged along a second direction, and the first direction intersects with the second direction; the display panel comprises:

[0042] At least one first signal line and at least one row of first pixels are located in the first display area; the first signal line extends along the first direction, and the first signal line is connected to a row of first pixels;

[0043] At least one second signal line and at least one row of second pixels are located in the second display area; the second signal line extends along the first direction, and the second signal line is connected to a row of second pixels; the number of the first pixels arranged along the first direction is less than the number of the second pixels arranged along the first direction;

[0044] A plurality of cascaded gate driving circuits; the gate driving circuit is arranged in the first non-display area; the gate driving circuit includes a first capacitor; the first capacitor is connected to the first signal line or the second signal line; the capacitance value of the first capacitor connected to the first signal line is greater than the capacitance value of the first capacitor connected to the second signal line.

[0045] Optionally, the gate drive circuit also includes a first transistor; the first electrode of the first transistor is used to input a clock signal, the second electrode of the first transistor is connected to the first plate of the first capacitor, and the gate of the first transistor is connected to the second plate of the first capacitor.

[0046] In a third aspect, an embodiment of the present invention further provides a display device, comprising the display panel described in the first aspect and the second aspect.

[0047] The technical solution of the embodiment of the present invention can fully utilize the border area of ​​the display panel by setting a compensation capacitor in the first non-display area. At the same time, the load of the first signal line can be increased by the compensation capacitor, thereby reducing the load difference between the first signal line and the second signal line, thereby reducing the brightness difference between the first display area and the second display area, improving the brightness consistency between the first display area and the second display area, and thus improving the display effect of the display panel. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic diagram of the structure of a display panel provided by an embodiment of the present invention;

[0049] Figure 2 A schematic diagram of a partial structure of a display panel in a first non-display area provided by an embodiment of the present invention;

[0050] Figure 3 A schematic diagram of a partial structure of a display panel in a first non-display area provided by an embodiment of the present invention;

[0051] Figure 4 A schematic diagram of a partial cross-sectional structure of another display panel in a first non-display area provided by an embodiment of the present invention;

[0052] Figure 5 A schematic diagram of a partial cross-sectional structure of another display panel in a first non-display area provided by an embodiment of the present invention;

[0053] Figure 6 A schematic diagram of a partial cross-sectional structure of another display panel in a first non-display area provided by an embodiment of the present invention;

[0054] Figure 7 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0055] Figure 8 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0056] Fig. 9 A schematic diagram of the structure of a gate drive circuit provided by an embodiment of the present invention;

[0057] Fig.10 A schematic diagram of a partial structure of a first gate driving circuit provided by an embodiment of the present invention;

[0058] Fig.11 A partial structural diagram of a second gate driving circuit provided by an embodiment of the present invention;

[0059] Fig.12 A schematic structural diagram of another first gate driving circuit provided by an embodiment of the present invention;

[0060] Fig.13 A schematic diagram of a partial structure of another first gate driving circuit provided by an embodiment of the present invention;

[0061] Fig.14 A schematic diagram of a cross-sectional structure of a first capacitor provided by an embodiment of the present invention obtained by cutting along AA';

[0062] Fig.15 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention;

[0063] Fig.16 A schematic structural diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0064] The present invention will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the present invention, rather than to limit the present invention. It should also be noted that, for ease of description, only parts related to the present invention, rather than all structures, are shown in the accompanying drawings.

[0065] The display panel includes a plurality of pixels, each pixel includes a display element and a pixel circuit, and the pixel circuit is connected to the display element for driving the display element to display. A scanning signal line is provided on the display panel for providing a scanning signal for a row of pixels. When the display panel has an irregular display area, the number of pixels in at least two rows is different, and / or the length of at least two scanning signal lines is different, so that the load values ​​corresponding to different scanning signal lines are different. When the scanning signal line provides scanning signals for the pixels, the scanning signals received by the pixels in different rows are different, so that the pixels in different rows have brightness differences, which reduces the display effect of the display panel.

[0066] In view of the above technical problem, an embodiment of the present invention provides a display panel. Figure 1 FIG. 1 is a schematic diagram of a display panel provided by an embodiment of the present invention. Figure 1 As shown, the display panel includes a first display area AA1, a second display area AA2 and a first non-display area NAA1; along a first direction X, the first non-display area NAA1 is located on one side of the first display area AA1, and the first display area AA1 and the second display area AA2 are arranged along a second direction Y; the first direction X intersects the second direction Y; the display panel includes:

[0067] At least one first signal line S1 and at least one row of first pixels P1 are located in the first display area AA1; the first signal line S1 extends along the first direction X, and the first signal line S1 is connected to a row of first pixels P1;

[0068] At least one second signal line S2 and at least one row of second pixels P2 are located in the second display area AA2; the second signal line S2 is along the first direction X, and the second signal line S2 is connected to a row of second pixels P2; the number of first pixels P1 arranged along the first direction X is less than the number of second pixels P2 arranged along the first direction X;

[0069] At least one compensation capacitor C1 is located in the first non-display area NAA1 , and the compensation capacitor C1 is connected to the first signal line S1 .

[0070] Specifically, when the display panel has an irregular display area, the number of pixels in at least two rows is different. Figure 1exemplarily shows that the display panel has a notch, so that the first display area AA1 is divided into a first sub-area AA11 and a second sub-area AA12 arranged along the first direction X. The first pixel P1 can be distributed in the first sub-area AA11 and the second sub-area AA12. At this time, the number of pixels in a row in the first display area AA1 is the sum of the number of first pixels P1 in a row in the first sub-area AA11 and the number of first pixels P1 in a row in the second sub-area AA12. The first signal line S1 can be connected to a row of first pixels P1 in the first sub-area AA11 and a row of first pixels P1 in the second sub-area AA12 at the same time, and is used to provide a scan signal for a row of first pixels P1 in the first display area AA1. The second signal line S2 can be connected to a row of second pixels P2, and is used to provide a scan signal for a row of second pixels P2 in the second display area AA2. The second display area AA2 and the first display area AA1 are arranged along the second direction Y. When a gap is provided between the first sub-area AA11 and the second sub-area AA12, the length of the first display area AA1 along the first direction X that can be used to arrange the first pixel P1 is less than the length of the second display area AA2 along the first direction X that can be used to arrange the second pixel P2, so that the number of arranged first pixels P1 is less than the number of arranged second pixels P2, and the load corresponding to the first signal line S1 is less than the load of the second signal line S2. It should be noted that, in other embodiments, the display panel may further provide a hole area in the first display area AA1, and similarly, the number of arranged first pixels P1 along the first direction X may be less than the number of arranged second pixels P2, so that the load corresponding to the first signal line S1 is less than the load of the second signal line S2.

[0071] The display panel may include two first non-display areas NAA1, which are respectively arranged on a side of the first sub-area AA11 away from the second sub-area AA12 and a side of the second sub-area AA12 away from the first sub-area AA11. When the compensation capacitor C1 is arranged in the first non-display area NAA1, it is possible to avoid increasing the area requirement of the non-display area between the first sub-area AA11 and the second sub-area AA12, which is conducive to reducing the wiring space of the non-display area between the first sub-area AA11 and the second sub-area AA12, and realizing a narrow frame of the display panel at the irregular display area.

[0072] Moreover, the first non-display area NAA1 is located on the side of the first display area AA1 along the first direction X. When the non-display area of ​​the display panel includes an arc-shaped edge, the first non-display area NAA1 includes an arc-shaped non-display area. The first non-display area NAA1 is provided with a compensation capacitor C1, which can make full use of the border area of ​​the display panel. When the compensation capacitor C1 is connected to the first signal line S1, the compensation capacitor C1 can be used as a load of the first signal line S1, that is, the load of the first signal line S1 is increased by the compensation capacitor C1, so that the load difference between the first signal line S1 and the second signal line S2 can be reduced, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2 caused by the load difference between the first signal line S1 and the second signal line S2, improving the brightness consistency between the first display area AA1 and the second display area AA2, and thereby improving the display effect of the display panel. Exemplarily, the first signal line S1 may extend from the first non-display area NAA1 to the first display area AA1. In the first non-display area NAA1, the compensation capacitor C1 is directly connected to the first signal line S1 as a load of the first signal line S1, which can simplify the wiring of the display panel.

[0073] It should be noted that when the first display area AA1 includes multiple rows of first pixels P1, the display panel includes multiple first signal lines S1, each of which can be connected to a row of first pixels P1, and is used to provide a scanning signal for a row of first pixels P1. At this time, the first non-display area NAA1 is provided with multiple compensation capacitors C1, each of which is connected to a first signal line S1, and is used to increase the load of each first signal line S1, reduce the load difference between the first signal line S1 and the second signal line S2, and improve the display effect of the display panel.

[0074] The technical solution of this embodiment can fully utilize the border area of ​​the display panel by setting a compensation capacitor in the first non-display area. At the same time, the load of the first signal line can be increased by the compensation capacitor, thereby reducing the load difference between the first signal line and the second signal line, thereby reducing the brightness difference between the first display area and the second display area, improving the brightness consistency between the first display area and the second display area, and thus improving the display effect of the display panel.

[0075] Figure 2 A schematic diagram of a partial structure of a display panel in a first non-display area provided by an embodiment of the present invention. Figure 2 As shown, the display panel also includes a gate driving circuit GIP; the gate driving circuit GIP is arranged in the first non-display area NAA1, and the compensation capacitor C1 is arranged on the side of the gate driving circuit GIP close to the first display area AA1; the gate driving circuit GIP is connected to the first signal line S1, and is used to provide a scanning signal for the first signal line S1.

[0076] Specifically, the gate drive circuit GIP may include a scan drive circuit, which is disposed in the first non-display area NAA1 and connected to the first signal line S1, so that it can be connected to the pixel circuit through the first signal line S1, and is used to provide a scan signal for the pixel circuit. When the compensation capacitor C1 is disposed on a side of the gate drive circuit GIP close to the first display area AA1, it can be disposed on a path where the first signal line S1 is connected to the gate drive circuit GIP, thereby simplifying the connection between the compensation capacitor C1 and the first signal line S1, and simplifying the wiring design of the first non-display area NAA1.

[0077] In some embodiments, the display panel also includes a substrate and a driving circuit layer, the driving circuit layer is arranged on the substrate, and the pixel circuit in the first pixel is located in the driving circuit layer; the driving circuit layer includes at least two conductive layers, and the compensation capacitor includes at least two plates, and the at least two plates of the compensation capacitor are respectively located in different conductive layers.

[0078] Specifically, the driving circuit layer includes at least two conductive layers for forming a pixel circuit. Exemplarily, the pixel circuit includes a transistor and a storage capacitor, etc. When the transistor is a top-gate transistor, the conductive layer included in the driving circuit layer can be at least two layers of a semiconductor layer, a first metal layer, a second metal layer and a third metal layer stacked sequentially on the substrate. The semiconductor layer can form an active region and a channel region of the transistor, the first metal layer can form a gate of the transistor, the second metal layer can form a plate of the storage capacitor, and the third metal layer can form a source and drain of the transistor. The compensation capacitor includes a first plate and a second plate arranged in an overlapping manner, and the first plate and the second plate can be arranged in the same layer with different conductive layers, respectively, and the vertical projections of the first plate and the second plate on the plate overlap, and the insulating layer between the conductive layers is used as a dielectric layer of the compensation capacitor to form a compensation capacitor. At this time, it is possible to avoid setting an additional film layer when forming the compensation capacitor, and the manufacturing process of the display panel can be simplified. Exemplarily, the material of the two plates of the compensation capacitor can be the same as the material of the conductive layer arranged in the same layer. When manufacturing a display panel, a compensation capacitor can be formed simultaneously when a pixel circuit is formed on a patterned conductive layer, thereby avoiding the need to increase the manufacturing process of the display panel. For example, when the first electrode of the compensation capacitor is disposed on the same layer as the first metal layer, the first electrode of the compensation capacitor can be formed simultaneously when the gate of the transistor is patterned on the first metal layer. When the second electrode of the compensation capacitor is disposed on the same layer as the third metal layer, the second electrode of the compensation capacitor can be formed simultaneously when the source and drain of the transistor are patterned on the third metal layer.

[0079] Figure 3 A schematic diagram of a partial cross-sectional structure of a display panel in a first non-display area provided by an embodiment of the present invention. Figure 3As shown, the driving circuit layer includes a first conductive layer M1 and a second conductive layer M2 which are stacked, the first conductive layer M1 is arranged on a side of the second conductive layer M2 close to the substrate, the compensation capacitor C1 includes a first electrode plate C11 and a second electrode plate C12, the first electrode plate C11 of the compensation capacitor C1 is located in the first conductive layer M1, the second electrode plate C12 of the compensation capacitor C1 is located in the second conductive layer M2, and the orthographic projections of the first electrode plate C11 of the compensation capacitor C1 and the second electrode plate C12 of the compensation capacitor C1 on the substrate at least partially overlap; the first signal line S1 is connected to the first electrode plate C11 of the compensation capacitor C1.

[0080] Specifically, the first conductive layer M1 may be a first metal layer of a driving circuit layer, used to form a gate of a transistor. The second conductive layer M2 may be a second metal layer of a driving circuit layer, used to form a plate of a storage capacitor. By arranging the first plate C11 of the compensation capacitor C1 to be located in the first conductive layer M1, the space of the first conductive layer M1 can be fully utilized, which is conducive to arranging a large area of ​​the first plate C11, thereby facilitating increasing the capacitance value of the compensation capacitor C1, improving the compensation effect of the compensation capacitor, and further improving the brightness consistency between the first display area and the second display area.

[0081] In some embodiments, the second plate of the compensation capacitor is connected to a signal with a constant potential, which can prevent the potential of the second plate of the compensation capacitor from changing, thereby preventing the coupling effect of the compensation capacitor from affecting the scanning signal on the first signal S1.

[0082] In some embodiments, the second plate of the compensation capacitor is connected to a power signal or an initialization signal.

[0083] Specifically, the power signal may include a first power signal and a second power signal. The first power signal transmits a positive power signal to the pixel circuit, for example, +7V. The second power signal is input to the cathode of the display element, for example, -7V. The initialization signal is also a fixed potential, which is used to initialize the gate of the driving transistor in the pixel and the anode of the display element, for example, the initialization signal is 1-3V. By setting the second plate of the compensation capacitor to access the power signal or the initialization signal, not only can the influence of the compensation capacitor on the scanning signal be avoided, but also the additional setting of the signal transmission line can be avoided, which is conducive to simplifying the wiring design of the display panel and the manufacturing process of the display panel. In addition, the potential stability of the power signal is relatively good. When the power signal is connected to the second plate of the compensation capacitor, the potential stability of the second plate of the compensation capacitor can be improved, thereby reducing the influence of other signals on the scanning signal.

[0084] In addition, when the initialization signal is connected to the second electrode plate of the compensation capacitor, the capacitance value of the compensation capacitor can be used as the load of the initialization signal, thereby increasing the voltage-stabilizing capacitance of the initialization signal, improving the stability of the initialization signal, and being beneficial to improving the display effect of the display panel.

[0085] In some embodiments, continue to refer to Figure 2 and Figure 3 , the second plates C12 of the plurality of compensation capacitors C1 are connected as one.

[0086] Specifically, different first signal lines S1 are connected to different first plates C11 of compensation capacitors C1, so as to avoid display panel abnormalities caused by short circuits of different first signal lines S1. At the same time, the second plates C12 of multiple compensation capacitors C1 are connected as one, which can not only make full use of the space of the first non-display area NAA1 to arrange the second plates C12, and increase the capacitance value of the compensation capacitor C1 as much as possible, but also simplify the manufacturing process of the second plates C12 of multiple compensation capacitors C1.

[0087] In some embodiments, the second plates C12 of different compensation capacitors C1 can also be independent plates set in the same layer. In this case, different second plates C12 can be dispersedly set according to the pattern of the film layer where the second plates C12 are located, thereby avoiding the compensation capacitor C1 from occupying a relatively large space and improving the space utilization of the first non-display area NAA1.

[0088] Continue to refer Figure 2 and Figure 3 The first signal line S1 is located in the first conductive layer M1, the first signal line S1 extends to the first non-display area NAA1, and the first signal line S1 includes an overlapping portion S11 that at least partially overlaps with the second electrode C12 of the compensation capacitor C1, and the overlapping portion S11 of the first signal line S1 is reused as the first electrode C11 of the compensation capacitor C1.

[0089] Specifically, when the first signal line S1 is located in the first conductive layer M1, the overlapping portion S11 of the first signal line S1 can be reused as the first electrode C11 of the compensation capacitor C1, which not only avoids the need to additionally set the first electrode C11 of the compensation capacitor C1, but also avoids the need to connect the first electrode C11 to the first signal line S1, thereby simplifying the manufacturing process of the display panel. Furthermore, the space of the first conductive layer M1 in the first non-display area NAA1 can be fully utilized, which is beneficial to increasing the capacitance value of the compensation capacitor C1.

[0090] Continue to refer Figure 2 and Figure 3 , the width of the overlapping portion S11 of the first signal line S1 is greater than the width of the first signal line S1 in the first display area AA1.

[0091] Specifically, when the overlapping portion S11 of the first signal line S1 is reused as the first electrode plate C11 of the compensation capacitor C1, the width of the overlapping portion S11 can be increased, thereby increasing the area of ​​the first electrode plate C11 of the compensation capacitor C1, which is beneficial to increase the capacitance value of the compensation capacitor C1, thereby better compensating for the brightness abnormalities of the first display area AA1 and the second display area AA2, thereby improving the brightness consistency of the display panel.

[0092] Figure 4 A schematic diagram of a partial cross-sectional structure of another display panel in a first non-display area provided by an embodiment of the present invention. Figure 4 As shown, the driving circuit layer also includes a third conductive layer M3, which is arranged on a side of the second conductive layer M2 away from the first conductive layer M1; the compensation capacitor C1 also includes a third electrode plate C13, the third electrode plate C13 of the compensation capacitor C1 is located in the third conductive layer M3, the third electrode plate C13 of the compensation capacitor C1 is connected to the first electrode plate C11 of the compensation capacitor C1, the first signal line S1 extends to the first non-display area NAA1, and the first signal line S1 includes an overlapping portion S11 that at least partially overlaps with the second electrode plate C12 of the compensation capacitor C1, and the overlapping portion S11 of the first signal line S1 is reused as the third electrode plate C13 of the compensation capacitor C1.

[0093] Specifically, the third conductive layer M3 may be a third metal layer of the driving circuit layer, which is used to form the source and drain of the transistor in the pixel. The first signal line S1 may be arranged in the third conductive layer M3, and at this time, the first signal line S1 may be connected to the first electrode C11 of the first conductive layer M1 through a via, so that the compensation capacitor C1 may be used as the load of the first signal line S1, thereby increasing the load of the first signal line S1, reducing the load difference between the first signal line S1 and the second signal line S2, and further reducing the brightness difference between the first display area AA1 and the second display area AA2. When the overlapping portion S11 of the first signal line S1 is reused as the third electrode C13 of the compensation capacitor C1, the third electrode C13 of the compensation capacitor C1 may form a capacitor with the second electrode C12 of the compensation capacitor C1, and at the same time, the second electrode C12 of the compensation capacitor C1 forms a capacitor with the first electrode C11 of the compensation capacitor C1, thereby increasing the capacitance value of the compensation capacitor C1, better compensating for the brightness abnormality of the first display area AA1 and the second display area AA2, and improving the brightness consistency of the display panel.

[0094] Continue to refer Figure 4 The display panel further includes a light emitting control signal line EM, and the light emitting control signal line EM is located in the third conductive layer M3.

[0095] Specifically, the light control signal line EM is connected to the light control signal input terminal of the pixel circuit to provide the pixel circuit with a light control signal. The light control signal line EM is located in the third conductive layer M3, which is conducive to simplifying the wiring design of the display panel and avoiding intersection and short circuit of different signal lines.

[0096] It should be noted that the display panel may further include a power signal line VDD and an initialization signal line VREF. The power signal line VDD is used to provide a power signal to the pixel, and the initialization signal line VREF is used to provide an initialization signal to the pixel. Figure 4 exemplarily shows that the second plate C12 of the compensation capacitor C1 is connected to the power signal. At this time, the initialization signal line VREF may be located in the third conductive layer M3. In some embodiments, Figure 5 A schematic diagram of a partial cross-sectional structure of another display panel in a first non-display area provided by an embodiment of the present invention. Figure 5 As shown, the second plate C12 of the compensation capacitor C1 can also be connected to the initialization signal, that is, the second plate C12 of the compensation capacitor C1 is connected to the initialization signal line VREF, thereby increasing the capacitance on the transmission initialization signal line VREF, which can make the potential of the initialization signal on the initialization signal line VREF more stable, thereby improving the effect of pixel circuit initialization and enhancing display performance. It should be noted that the second plate C12 of the compensation capacitor C1 has a fixed potential, so the second plate C12 of the compensation capacitor C1 can also be reused as a shielding structure to avoid crosstalk problems between signal lines.

[0097] Figure 6 A schematic diagram of a partial cross-sectional structure of another display panel in a first non-display area provided by an embodiment of the present invention. Figure 6 As shown, the driving circuit layer includes a first conductive layer ( Figure 6 The compensation capacitor C1 includes a first electrode plate C11 and a second electrode plate C12, the first electrode plate C11 of the compensation capacitor C1 is located in the second conductive layer M2, the second electrode plate C12 of the compensation capacitor C1 is located in the third conductive layer M3, and the orthographic projections of the first electrode plate C11 of the compensation capacitor C1 and the second electrode plate C12 of the compensation capacitor C1 on the substrate at least partially overlap; the compensation capacitor C1 also includes a third electrode plate C13, the third electrode plate C13 of the compensation capacitor C1 is located in the fourth conductive layer M4, and the third electrode plate C13 of the compensation capacitor C1 is connected to the first electrode plate C11 of the compensation capacitor C1; the first signal line S1 extends to the first non-display area NAA1, and the first signal line S1 includes an overlapping portion S11 that at least partially overlaps with the second electrode plate C12 of the compensation capacitor C1, and the overlapping portion S11 of the first signal line S1 is reused as the third electrode plate C13 of the compensation capacitor C1.

[0098] Specifically, Figure 6 FIG. 2 shows another exemplary film layer arrangement of the electrode plate of the compensation capacitor C1. Figure 6 As shown, the first signal line S1 is located in the fourth conductive layer M4, and the first plate C11 of the compensation capacitor C1 is located in the second conductive layer M2 and is connected to the first signal line S1 through a via, so that the connection between the compensation capacitor C1 and the first signal line S1 can be realized, so that the compensation capacitor C1 serves as the load of the first signal line S1. The orthographic projections of the first plate C11 of the compensation capacitor C1 and the second plate C12 of the compensation capacitor C1 on the substrate at least partially overlap, so that the first plate C11 and the second plate C12 of the compensation capacitor C1 can form a capacitor. At the same time, the overlapping portion S11 of the first signal line S1 is reused as the third plate C13 of the compensation capacitor C1, so that the second plate C12 of the compensation capacitor C1 and the third plate C13 of the compensation capacitor C1 form a capacitor. Thereby, the capacitance value of the compensation capacitor C1 is increased, the brightness abnormality of the first display area AA1 and the second display area AA2 is better compensated, and the brightness consistency of the display panel is improved.

[0099] In some embodiments, the width of the overlapping portion S11 of the first signal line S1 is greater than the width of the first signal line S1 in the first display area AA.

[0100] Specifically, when the overlapping portion S11 of the first signal line S1 is reused as the third electrode plate C13 of the compensation capacitor C1, the width of the overlapping portion S11 can be increased, thereby increasing the area of ​​the third electrode plate C13 of the compensation capacitor C1, which is beneficial to increase the capacitance value of the compensation capacitor C1, thereby better compensating for the brightness abnormality of the first display area AA1 and the second display area AA2, and improving the brightness consistency of the display panel.

[0101] Preferably, the second plate of the compensation capacitor is used to access a signal with a constant potential, which can avoid the potential of the second plate of the compensation capacitor from changing, thereby avoiding the influence of the coupling effect of the compensation capacitor on the scanning signal on the first signal S1.

[0102] Preferably, the second electrode plate of the compensation capacitor is used to access the power signal or the initialization signal; this not only avoids the influence of the compensation capacitor on the scanning signal, but also avoids the need for additional signal transmission lines, which is beneficial to simplifying the wiring design of the display panel and the manufacturing process of the display panel.

[0103] Preferably, the display panel further comprises a light emitting control signal line, and the light emitting control signal line is located in the fourth conductive layer.

[0104] Continue to refer Figure 6The compensation capacitor C1 also includes a fourth plate C14, which is connected to the second plate C12 of the compensation capacitor C1, and a vertical projection of the fourth plate C14 of the compensation capacitor C1 on the substrate at least partially overlaps with a vertical projection of the first plate C11 on the substrate.

[0105] Specifically, the vertical projection of the fourth plate C14 of the compensation capacitor C1 on the substrate overlaps at least partially with the vertical projection of the first plate C11 on the substrate, so that a capacitor is formed between the fourth plate C14 of the compensation capacitor C1 and the first plate C11. At the same time, the first plate C11 of the compensation capacitor C1 is connected to the first signal line S1, so that the capacitor formed by the fourth plate C14 and the first plate C11 is connected to the first signal line S1, so that it can be used as a load of the first signal line S1, and is used to reduce the load difference between the first signal line S1 and the second signal line S2. At this time, the capacitance between the fourth plate C14 of the compensation capacitor C1 and the first plate C11 can increase the capacitance value of the compensation capacitor C1, and can reduce the load difference between the first signal line S1 and the second signal line S2 as much as possible. In addition, the fourth plate C14 of the compensation capacitor C1 is connected to the second plate C12 of the compensation capacitor C1. When the second plate C12 of the compensation capacitor C1 is connected to a signal of a constant potential, the fourth plate C14 of the compensation capacitor C1 is also connected to a signal of a constant potential, so that the capacitance between the fourth plate C14 of the compensation capacitor C1 and the first plate C11 serves as one of the parallel sub-capacitors of the supplementary capacitor. At the same time, the fourth plate C14 can also be reused as a shielding structure to prevent other signals from affecting the scanning signal provided by the first signal line S1, thereby improving the reliability of the display panel.

[0106] Continue to refer Figure 6 The driving circuit layer further includes a semiconductor layer M0, which is disposed on a side of the first conductive layer close to the substrate, and the fourth electrode C14 is located on the first conductive layer or the semiconductor layer M0.

[0107] Specifically, the semiconductor layer M0 can be used to form an active region of a transistor in a pixel. At this time, the active region overlaps with the first conductive layer to form a transistor. Figure 6 The fourth plate C14 is shown in the example in the semiconductor layer M0. At this time, the semiconductor layer M0 can be heavily doped to form the fourth plate C14 of the compensation capacitor C1, and at least partially overlap with the vertical projection of the first plate C11 on the substrate to increase the capacitance value of the compensation capacitor C1.

[0108] In some embodiments, the fourth electrode plate C14 can also be arranged to be located in the first conductive layer, and the first electrode plate C11 can be located in the second conductive layer M2, so that the vertical distance between the fourth electrode plate C14 and the first electrode plate C11 is the thickness of the insulating layer between the first conductive layer and the second conductive layer M2, that is, the vertical distance between the fourth electrode plate C14 and the first electrode plate C11 is relatively small, thereby further increasing the capacitance value of the capacitor formed by the first electrode plate C14 and the first electrode plate C11, and further increasing the capacitance value of the compensation capacitor C1, which is beneficial to further reduce the load difference between the first signal line S1 and the second signal line S2.

[0109] Figure 7 FIG. 1 is a schematic diagram of another display panel structure provided by an embodiment of the present invention. Figure 7 As shown, the display panel also includes a second non-display area NAA2 and a third non-display area NAA3; along the first direction X, the second non-display area NAA2 is arranged on at least one side of the second display area AA2; along the second direction Y, the third non-display area NAA3 is arranged on a side of the first display area AA1 away from the second display area AA2; when the display panel includes multiple compensation capacitors C1, at least one compensation capacitor C1 is arranged in the second non-display area NAA2 and / or the third non-display area NAA3.

[0110] Specifically, Figure 7 As shown, the second non-display area NAA2 may be the non-display area on the left and right sides of the second display area AA2. The second non-display area NAA2 may form non-display areas on the left and right sides of the display area with the first non-display area NAA1. The third non-display area NAA3 may include non-display areas on the upper and lower sides of the display area. When the first display area AA1 includes multiple rows of first pixels, corresponding to multiple first signal lines S1, the display panel needs to be provided with multiple compensation capacitors C1. At this time, at least one compensation capacitor C1 may be provided to extend from the first non-display area NAA1 to at least one of the non-display areas on both sides thereof, which is beneficial to increase the space for arranging the compensation capacitor C1, thereby facilitating increasing the capacitance value of the compensation capacitor C1, and further reducing the load difference between the first signal line S1 and the second signal line S2. For example, as Figure 7 As shown, when the first display area AA1 is disposed above the display area of ​​the display panel, the compensation capacitor C1 may extend to the third non-display area NAA3, ie, the upper frame of the display panel, to increase the arrangement space of the compensation capacitor C1.

[0111] In some embodiments, Figure 8 A schematic diagram of the structure of another display panel provided by an embodiment of the present invention, Fig. 9 FIG. 1 is a schematic diagram of a gate drive circuit provided by an embodiment of the present invention. Figure 8 and Fig. 9As shown, the display panel also includes a second non-display area NAA2 and a plurality of cascaded gate drive circuits GIP; along the first direction X, the second non-display area NAA2 is arranged on at least one side of the second display area AA2; the gate drive circuit GIP is arranged in the first non-display area NAA1 and the second non-display area NAA2; the gate drive circuit GIP includes a first capacitor Cs1 and a first transistor T1; the first electrode of the first transistor T1 is used to input the clock signal provided by the clock signal input terminal CLK2, the second electrode of the first transistor T1 is connected to the first electrode plate of the first capacitor Cs1, and the second electrode of the first transistor T1 is connected to the first signal line S1 or the second signal line S2, and the gate of the first transistor T1 is connected to the second electrode plate of the first capacitor Cs1; the capacitance value of the first capacitor Cs1 connected to the first signal line S1 is greater than the capacitance value of the first capacitor Cs1 connected to the second signal line S2.

[0112] Specifically, the output terminal GOUT of each gate driving circuit GIP in the cascaded gate driving circuit GIP can be connected to the first signal line S1 or the second signal line S2, and is used to provide a scanning signal for the first signal line S1 or the second signal line S2. The gate driving circuit GIP includes a first transistor T1. When the first transistor T1 is turned on, the first transistor T1 can output a clock signal provided by the clock signal input terminal CLK2 to the output terminal GOUT of the gate driving circuit GIP as a scanning signal. The first plate of the first capacitor Cs1 is connected to the output terminal GOUT of the gate driving circuit GIP, and is used to maintain the scanning signal output by the gate driving circuit GIP. At this time, the first plate of the first capacitor Cs1 is connected to the first signal line S1 or the second signal line S2, so that the first capacitor Cs1 serves as a load of the first signal line S1 or the second signal line S2. When the number of first pixels P1 arranged along the first direction X is less than the number of second pixels P2 arranged, the load of the first signal line S1 in the first display area AA1 is less than the load of the second signal line S2 in the second display area AA2. At this time, the capacitance value of the first capacitor Cs1 connected to the first signal line S1 is set to be greater than the capacitance value of the first capacitor Cs1 connected to the second signal line S2, so that the load of the first signal line S1 in the first non-display area NAA1 can be greater than the load of the second signal line S2 in the second non-display area NAA2, thereby reducing the load difference between the first signal line S1 and the second signal line S2 in the display area, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2 caused by the load difference between the first signal line S1 and the second signal line S2, improving the brightness consistency between the first display area AA1 and the second display area AA2, and thereby improving the display effect of the display panel.

[0113] Continue to refer Fig. 9The gate driving circuit GIP also includes a second transistor T2 and a potential maintaining capacitor Cs3, a first electrode of the second transistor T2 and a first electrode plate of the potential maintaining capacitor Cs3 are connected to the high voltage signal input terminal VGH, a gate of the second transistor T2 and a second electrode plate of the potential maintaining capacitor Cs3 are connected to the first node N1, and the second transistor T2 transmits the high voltage signal provided by the high voltage signal input terminal VGH to the output terminal GOUT when the potential of the first node N1 is at a low level. The gate drive circuit further includes a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7 and an eighth transistor T8, the gate of the third transistor T3 and the gate of the fifth transistor T5 are connected to the inverted clock signal input terminal CLK1, the first electrode of the third transistor T3 serves as the input terminal SIN of the gate drive circuit GIP, the first electrode of the fifth transistor T5 and the gate of the eighth transistor T8 are connected to the low voltage signal input terminal VGL, the second electrode of the third transistor T3 is connected to the gate of the fourth transistor T4, the second electrode of the sixth transistor T6 and the first electrode of the eighth transistor T8, the first electrode of the fourth transistor T4 and the gate of the sixth transistor T6 are connected to the clock signal input terminal CLK2, the second electrode of the fourth transistor T4 is connected to the second electrode of the fifth transistor T5, the gate of the seventh transistor T7 and the first node N1, the first electrode of the seventh transistor T7 is connected to the high voltage signal input terminal VGH, the second electrode of the seventh transistor T7 is connected to the first electrode of the sixth transistor, and the second electrode of the eighth transistor T8 is connected to the gate of the first transistor T1. The inverted clock signal provided by the inverted clock signal input terminal CLK1 is a clock signal with a potential opposite to that of the clock signal. The states of different transistors are controlled respectively by the inverted clock signal, the clock signal, the high voltage signal, the low voltage signal and the start signal inputted by the input terminal SIN of the gate drive circuit GIP, and the start signal inputted by the input terminal SIN of the gate drive circuit GIP can be shifted and outputted. When different gate drive circuits GIP are cascaded, a shifted output scanning signal can be provided for the first signal line S1 and the second signal line S2, so that the pixels in the first display area AA1 and the second display area AA2 can be driven row by row.

[0114] In some embodiments, the compensation capacitor C1 includes a first capacitor Cs1, so that the load difference between the first signal line S1 and the second signal line S2 can be directly compensated by adjusting the capacitance value of the first capacitor Cs1 in different gate drive circuits GIP, thereby avoiding the additional setting of the compensation capacitor C1 and simplifying the process difficulty of the display panel.

[0115] Fig.10 A partial structural diagram of a first gate driving circuit provided by an embodiment of the present invention, Fig.11 FIG. 1 is a partial structural diagram of a second gate drive circuit provided by an embodiment of the present invention. Figures 8 to 11As shown, the gate driving circuit GIP connected to the first signal line S1 is the first gate driving circuit GIP1, and the gate driving circuit GIP connected to the second signal line S2 is the second gate driving circuit GIP2; along the first direction X, the width d1 of the first plate of the first capacitor Cs1 in the first gate driving circuit GIP1 is greater than the width d2 of the first plate of the first capacitor Cs1 in the second gate driving circuit GIP2; the width d3 of the second plate of the first capacitor Cs1 in the first gate driving circuit GIP1 is greater than the width d4 of the second plate of the first capacitor Cs1 in the second gate driving circuit GIP2.

[0116] Specifically, Fig.10 and Fig.11 As shown, along the first direction X, the width d1 of the first plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the width d2 of the first plate of the first capacitor Cs1 in the second gate drive circuit GIP2, and at the same time, the width d3 of the second plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the width d4 of the second plate of the first capacitor Cs1 in the second gate drive circuit GIP2, so that the overlapping area of ​​the two plates of the first capacitor Cs1 in the first gate drive circuit GIP1 can be greater than the overlapping area of ​​the two plates of the first capacitor Cs1 in the second gate drive circuit GIP2, so that the capacitance value of the first capacitor Cs1 in the first gate drive circuit GIP1 can be greater than the capacitance value of the first capacitor Cs1 in the second gate drive circuit GIP2, which is used to compensate for the load difference between the first signal line S1 and the second signal line S2.

[0117] In some embodiments, the display panel also includes a substrate and a first conductive layer and a second conductive layer stacked on the substrate, the first conductive layer is arranged on a side of the second conductive layer close to the substrate; the first plate of the first capacitor is located in the second conductive layer, and the second plate of the first capacitor is located in the first conductive layer.

[0118] Specifically, the first conductive layer can form the gate of the first transistor and the second electrode of the first capacitor, and the second conductive layer can form the first electrode of the first capacitor and be connected to the second electrode of the first transistor through a via.

[0119] Continue to refer Fig.10 and Fig.11 Along the second direction Y, the length l1 of the first plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the length l2 of the first plate of the first capacitor Cs1 in the second gate drive circuit GIP2, and the length l3 of the second plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the length l4 of the second plate of the first capacitor Cs1 in the second gate drive circuit GIP2.

[0120] Specifically, along the second direction Y, the length l1 of the first plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the length l2 of the first plate of the first capacitor Cs1 in the second gate drive circuit GIP2, and the length l3 of the second plate of the first capacitor Cs1 in the first gate drive circuit GIP1 is greater than the length l4 of the second plate of the first capacitor Cs1 in the second gate drive circuit GIP2. Similarly, the overlapping area of ​​the two plates of the first capacitor Cs1 in the first gate drive circuit GIP1 can be greater than the overlapping area of ​​the two plates of the first capacitor Cs1 in the second gate drive circuit GIP2, so that the capacitance value of the first capacitor Cs1 in the first gate drive circuit GIP1 can be greater than the capacitance value of the first capacitor Cs1 in the second gate drive circuit GIP2, which is used to compensate for the load difference between the first signal line S1 and the second signal line S2.

[0121] Continue to refer Fig.10 At least part of the plate of the first capacitor Cs1 in the first gate driving circuit GIP1 extends between adjacent first gate driving circuits GIP1, or extends between the first gate driving circuit GIP1 and the second gate driving circuit GIP2.

[0122] Specifically, there is space between adjacent gate drive circuits GIP. Along the second direction Y, when the next-level gate drive circuit GIP of the first gate drive circuit GIP1 is the first gate drive circuit GIP1, the two plates of the first capacitor Cs1 in the first gate drive circuit GIP1 can be extended from one side of the first transistor T1 along the first direction X to between two adjacent first gate drive circuits GIP1, so that the two plates of the first capacitor Cs1 in the first gate drive circuit GIP1 can utilize the space between the adjacent first gate drive circuits GIP1, further increasing the capacitance value of the first capacitor Cs1 in the first gate drive circuit GIP1, further compensating for the load difference between the first signal line S1 and the second signal line S2, and at the same time improving the space utilization rate of the first non-display area NAA1. Similarly, along the second direction Y, when the next-level gate drive circuit GIP of the last first gate drive circuit GIP1 is the second gate drive circuit GIP2, the two plates of the first capacitor Cs1 in the last first gate drive circuit GIP1 can extend from one side of the first transistor T1 along the first direction X to between the last first gate drive circuit GIP1 and the first second gate drive circuit GIP2, and the capacitance value of the first capacitor Cs1 in the first gate drive circuit GIP1 can also be increased.

[0123] In some embodiments, continue to refer to Fig.10 and Fig.11, along the second direction Y, the distance d5 between adjacent first gate driving circuits GIP1 is greater than the distance d6 between adjacent second gate driving circuits GIP2. Exemplarily, the boundary of the semiconductor layer pattern in the gate driving circuit may be the boundary of the corresponding gate driving circuit.

[0124] Specifically, when the plate of the first capacitor Cs1 in the first gate drive circuit GIP1 extends between adjacent first gate drive circuits GIP1, or extends between the first gate drive circuit GIP1 and the second gate drive circuit GIP2, the distance d5 between adjacent first gate drive circuits GIP1 can be set to be greater than the distance d6 between adjacent second gate drive circuits GIP2, so that there is a larger space between adjacent first gate drive circuits GIP1 for setting the two plates of the first capacitor Cs1, thereby increasing the capacitance value of the first capacitor Cs1, and further compensating for the load difference between the first signal line S1 and the second signal line S2.

[0125] Fig.12 A schematic diagram of the structure of another first gate driving circuit provided by an embodiment of the present invention, Fig.13 A partial structural diagram of another first gate driving circuit provided by an embodiment of the present invention, Fig.14 A schematic diagram of a cross-sectional structure of a first capacitor provided by an embodiment of the present invention is obtained by cutting along AA'. Figure 12 to Figure 14 As shown, the display panel also includes a third conductive layer M3, which is arranged on a side of the second conductive layer M2 away from the substrate; the compensation capacitor C1 also includes a second capacitor Cs2; the first plate of the first capacitor Cs1 is reused as the first plate of the second capacitor Cs2, and the second plate of the second capacitor Cs2 is located in the third conductive layer M3; the vertical projection of the second plate of the second capacitor Cs2 on the substrate overlaps with the vertical projection of the first plate of the first capacitor Cs1 on the substrate.

[0126] Specifically, the third conductive layer M3 may be a third metal layer of the driving circuit layer, which is used to form the source and drain of the transistor in the pixel. The second plate of the second capacitor Cs2 is located in the third conductive layer M3, and the vertical projection of the second plate of the second capacitor Cs2 on the substrate overlaps with the vertical projection of the first plate of the first capacitor Cs1 on the substrate, so that the first plate of the first capacitor Cs1 and the second plate of the second capacitor Cs2 in the first gate driving circuit GIP1 can form the second capacitor Cs2. At this time, the first capacitor Cs1 and the second capacitor Cs2 are both connected to the output terminal GOUT of the first gate driving circuit GIP1, so that the load of the first signal line S1 can be further increased, and the load difference between the first signal line S1 and the second signal line S2 can be better compensated, thereby improving the brightness consistency of the display panel.

[0127] The display panel may further include a fixed potential signal line for providing a fixed potential signal. The second electrode of the second capacitor Cs2 is connected to the fixed potential signal line to avoid the influence of the second capacitor Cs2 on the scanning signal. Fig.12 As shown, the fixed potential signal line may include a power signal line VDD, and the power signal line VDD may be set in the third conductive layer M3. At this time, the second plate of the second capacitor Cs2 may be set to be connected to the power signal line VDD, so that the second plate of the second capacitor Cs1 has a fixed potential, thereby avoiding the influence of the first capacitor Cs2 on the scanning signal.

[0128] Continue to refer Fig.13 A cascade signal line ST is also provided between adjacent gate drive circuits GIP. The cascade signal line ST is connected to the first plate of the first capacitor Cs1 in the previous gate drive circuit GIP, and the cascade signal line ST is connected to the start signal input terminal SIN of the current gate drive circuit GIP; the cascade signal line ST is located in the third conductive layer M3.

[0129] Specifically, the cascade signal line ST is connected between the output terminal GOUT of the previous gate driving circuit GIP and the start signal input terminal SIN of the current gate driving circuit GIP, so that the scanning signal output by the previous gate driving circuit GIP is used as the start signal of the current gate driving circuit GIP, and the shift output of the scanning signals corresponding to different rows of pixels can be realized. The cascade signal line ST does not overlap with the second plate of the second capacitor Cs2, so as to avoid short circuit between the cascade signal line ST and the second plate of the second capacitor Cs2.

[0130] In some embodiments, Figure 7 As shown, when the first display area AA1 includes a plurality of first signal lines S1 , the capacitance values ​​of the compensation capacitors C1 correspondingly connected to the first signal lines S1 are equal.

[0131] Specifically, when the display panel is provided with a plurality of compensation capacitors C1, the capacitance value of each compensation capacitor C1 can be equal, so that the load corresponding to each first signal line S1 is equal, and the brightness difference of the first display area AA1 is reduced. At the same time, the load difference between different first signal lines S1 and second signal lines S2 can be reduced synchronously, and the brightness difference between the first display area AA1 and the second display area AA2 can be reduced, thereby improving the display effect of the display panel. Exemplarily, the capacitance value of each compensation capacitor C1 can be a capacitance value corresponding to the load difference between the first signal line S1 and the second signal line S2, so that after the first signal line S1 is connected to the compensation capacitor C1, the load difference between the first signal line S1 and the second signal line S2 tends to 0, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2, thereby improving the display effect of the display panel.

[0132] In some embodiments, Fig.15FIG. 1 is a schematic diagram of another display panel structure provided by an embodiment of the present invention. Fig.15 As shown, it is also possible to arrange multiple first signal lines S1 so that along the direction Y pointing from the second display area AA2 to the first display area AA1 , the capacitance value of the compensation capacitor C1 connected to the first signal line S1 gradually decreases.

[0133] Specifically, Fig.15 As shown, along the direction Y from the second display area AA2 to the first display area AA1, the area of ​​the compensation capacitor C1 connected to the first signal line S1 is gradually reduced, so that the capacitance value of the compensation capacitor C1 connected to the first signal line S1 is gradually reduced, so that the display brightness of the first display area AA1 is gradually reduced from the edge close to the second display area AA2, thereby improving the brightness difference between the first display area AA1 and the second display area AA2 within the visible range of the human eye. Moreover, along the direction from the second display area AA2 to the first display area AA1, the capacitance value of the compensation capacitor C1 connected to the first signal line S1 can be gradually reduced, so that the space required for the compensation capacitor C1 can be gradually reduced, which is conducive to realizing a narrow frame of the display panel.

[0134] In some embodiments, along the direction Y pointing from the second display area AA2 to the first display area AA1, the ratio of the sum of the capacitance values ​​of the compensation capacitor C1 connected to the first first signal line S1 and the equivalent capacitance of the first pixel P1 to the sum of the capacitance values ​​of the compensation capacitor C1 connected to the last first signal line S1 and the equivalent capacitance of the first pixel P1 is less than or equal to 100%:40%.

[0135] Specifically, the total load of the first signal line S1 includes the sum of the capacitance values ​​of the compensation capacitor C1 and the equivalent capacitance of the first pixel P1. Along the direction Y from the second display area AA2 to the first display area AA1, the ratio of the sum of the capacitance values ​​of the compensation capacitor C1 and the equivalent capacitance of the first pixel P1 connected to the first first signal line S1 and the sum of the capacitance values ​​of the compensation capacitor C1 and the equivalent capacitance of the first pixel P1 connected to the last first signal line S1 is less than or equal to 100%:40%, so that the load of the first signal line S1 adjacent to the second signal line S2 tends to be equal to the load of the second signal line S2, and the load of the first signal line S1 gradually decreases along the direction from the second display area AA2 to the first display area AA1, so that the brightness of the display panel can be gradually reduced from the first row of the first pixel P1 along the direction from the second display area AA2 to the first display area AA1, and the brightness difference between the first display area AA1 and the second display area AA2 can be improved within the visible range of human eyes.

[0136] In some embodiments, Figure 8As shown, the first display area AA1 includes a first sub-area AA11 and a second sub-area AA12 arranged along a first direction X, and the first non-display area NAA1 is arranged on a side of the first sub-area AA11 away from the second sub-area AA12, and / or a side of the second sub-area AA12 away from the first sub-area AA11.

[0137] Specifically, when the compensation capacitor C1 is set in the first non-display area NAA1, the compensation capacitor C1 can be set in the conventional non-display area on the left and right sides of the display panel, avoiding the need to additionally set the compensation capacitor C1 in the non-display area between the first sub-area AA11 and the second sub-area AA12, which is beneficial to reducing the wiring space of the non-display area between the first sub-area AA11 and the second sub-area AA12, and realizing a narrow frame of the display panel in the irregular display area. When the non-display area of ​​the display panel includes an arc-shaped edge, the first non-display area NAA1 includes an arc-shaped non-display area. The compensation capacitor C1 is set in the first non-display area NAA1, and the frame area of ​​the display panel can be fully utilized.

[0138] The embodiment of the present invention further provides a display panel. Figure 8 As shown, the display panel includes a first display area AA1, a second display area AA2 and a first non-display area NAA1; along a first direction X, the first non-display area NAA1 is located on at least one side of the first display area AA1, the first display area AA1 and the second display area AA2 are arranged along a second direction Y, and the first direction X intersects the second direction Y; the display panel includes:

[0139] At least one first signal line S1 and at least one row of first pixels P1 are located in the first display area AA1; the first signal line S1 extends along the first direction X, and the first signal line S1 is connected to a row of first pixels P1;

[0140] At least one second signal line S2 and at least one row of second pixels P2 are located in the second display area AA2; the second signal line S2 extends along the first direction X, and the second signal line S2 is connected to a row of second pixels P2; the number of first pixels P1 arranged along the first direction X is less than the number of second pixels P2 arranged along the first direction X;

[0141] A plurality of cascaded gate driving circuits GIP; the gate driving circuit GIP is arranged in the first non-display area NAA1; the gate driving circuit GIP includes a first capacitor Cs1; the first capacitor Cs1 is connected to the first signal line S1 or the second signal line S2; the capacitance value of the first capacitor Cs1 connected to the first signal line S1 is greater than the capacitance value of the first capacitor Cs1 connected to the second signal line S2.

[0142] Specifically, when the number of first pixels P1 arranged along the first direction X is less than the number of second pixels P2 arranged along the first direction X, the load of the first signal line S1 in the first display area AA1 is less than the load of the second signal line S2 in the second display area AA2. At this time, the capacitance value of the first capacitor Cs1 connected to the first signal line S1 is set to be greater than the capacitance value of the first capacitor Cs1 connected to the second signal line S2, so that the load of the first signal line S1 in the first non-display area NAA1 is greater than the load of the second signal line S2 in the second non-display area NAA2, thereby reducing the load difference between the first signal line S1 and the second signal line S2 in the display area, thereby reducing the brightness difference between the first display area AA1 and the second display area AA2 caused by the load difference between the first signal line S1 and the second signal line S2, improving the brightness consistency between the first display area AA1 and the second display area AA2, and thereby improving the display effect of the display panel.

[0143] In some embodiments, Fig. 9 As shown, the gate driving circuit GIP also includes a first transistor T1; the first electrode of the first transistor T1 is used to input the clock signal CLK2, the second electrode of the first transistor T1 is connected to the first plate of the first capacitor Cs1, and the gate of the first transistor T1 is connected to the second plate of the first capacitor Cs1.

[0144] Specifically, the second electrode of the first transistor T1 is connected to the first electrode plate of the first capacitor Cs1, and is connected to the first signal line S1 or the second signal line S2 as the output terminal GOUT of the gate drive circuit GIP, so that the first capacitor Cs1 serves as the load of the first signal line S1 or the second signal line S2, so that the load of the first signal line S1 or the second signal line S2 can be adjusted by adjusting the capacitance value of the first capacitor Cs1.

[0145] An embodiment of the present invention further provides a display device. Fig.16 FIG. 1 is a schematic diagram of a display device provided by an embodiment of the present invention. Fig.16 As shown, the display device 100 includes the display panel 10 provided by any embodiment of the present invention. Since the display device 100 includes the display panel 10 provided by any embodiment of the present invention, it has the same beneficial effects as the display panel 10 provided by any embodiment of the present invention, and will not be repeated here. The display device 100 can be, for example, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a smart wearable device, an information inquiry machine in a public place hall, and any other product or component with a display function.

[0146] Note that the above are only preferred embodiments of the present invention and the technical principles used. Those skilled in the art will understand that the present invention is not limited to the specific embodiments described herein, and that various obvious changes, readjustments and substitutions can be made by those skilled in the art without departing from the scope of protection of the present invention. Therefore, although the present invention has been described in more detail through the above embodiments, the present invention is not limited to the above embodiments, and may include more other equivalent embodiments without departing from the concept of the present invention, and the scope of the present invention is determined by the scope of the appended claims.

Claims

1. A display panel, characterized in that: The display panel comprises a first display area, a second display area and a first non-display area; along a first direction, the first non-display area is located at least on one side of the first display area, the first display area and the second display area are arranged along a second direction, and the first direction intersects with the second direction; the display panel comprises: At least one first signal line and at least one row of first pixels are located in the first display area; the first signal line extends along the first direction, and the first signal line is connected to a row of first pixels; At least one second signal line and at least one row of second pixels are located in the second display area; the second signal line extends along the first direction, and the second signal line is connected to a row of second pixels; the number of the first pixels arranged along the first direction is less than the number of the second pixels arranged along the first direction; At least one compensation capacitor is located in the first non-display area, and the compensation capacitor is connected to the first signal line.

2. The display panel according to claim 1, characterized in that: It also includes a gate driving circuit; the gate driving circuit is arranged in the first non-display area, and the compensation capacitor is arranged on a side of the gate driving circuit close to the first display area; the gate driving circuit is connected to the first signal line to provide a scanning signal for the first signal line.

3. The display panel according to claim 2, characterized in that: The display panel also includes a substrate and a driving circuit layer, the driving circuit layer is arranged on the substrate, and the pixel circuit in the first pixel is located in the driving circuit layer; the driving circuit layer includes at least two conductive layers, and the compensation capacitor includes at least two plates, and the at least two plates of the compensation capacitor are respectively located in different conductive layers.

4. The display panel according to claim 3, characterized in that: The driving circuit layer comprises a first conductive layer and a second conductive layer which are stacked, the first conductive layer being arranged on a side of the second conductive layer close to the substrate, the compensation capacitor comprising a first electrode plate and a second electrode plate, the first electrode plate of the compensation capacitor being located on the first conductive layer, the second electrode plate of the compensation capacitor being located on the second conductive layer, and the orthographic projections of the first electrode plate of the compensation capacitor and the second electrode plate of the compensation capacitor on the substrate at least partially overlap; the first signal line is connected to the first electrode plate of the compensation capacitor; Preferably, the second electrode plate of the compensation capacitor is connected to a signal with a constant potential; Preferably, the second electrode plate of the compensation capacitor is connected to a power signal or an initialization signal; Preferably, the second plates of the plurality of compensation capacitors are connected as one.

5. The display panel according to claim 4, characterized in that: The first signal line is located in the first conductive layer, the first signal line extends to the first non-display area, and the first signal line includes an overlapping portion at least partially overlapping with the second electrode plate of the compensation capacitor, and the overlapping portion of the first signal line is reused as the first electrode plate of the compensation capacitor; Preferably, a width of the overlapping portion of the first signal line is greater than a width of the first signal line in the first display area.

6. The display panel according to claim 4, characterized in that: The driving circuit layer further comprises a third conductive layer, and the third conductive layer is arranged on a side of the second conductive layer away from the first conductive layer; The compensation capacitor further includes a third electrode plate, the third electrode plate of the compensation capacitor is located in the third conductive layer, the third electrode plate of the compensation capacitor is connected to the first electrode plate of the compensation capacitor, the first signal line extends to the first non-display area, and the first signal line includes an overlapping portion at least partially overlapping with the second electrode plate of the compensation capacitor, and the overlapping portion of the first signal line is reused as the third electrode plate of the compensation capacitor; Preferably, the width of the overlapping portion of the first signal line is greater than the width of the first signal line in the first display area; Preferably, the display panel further includes a light emitting control signal line, and the light emitting control signal line is located in the third conductive layer.

7. The display panel according to claim 3, characterized in that: The driving circuit layer comprises a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer which are stacked in sequence, the compensation capacitor comprises a first electrode plate and a second electrode plate, the first electrode plate of the compensation capacitor is located in the second conductive layer, the second electrode plate of the compensation capacitor is located in the third conductive layer, and the orthographic projections of the first electrode plate of the compensation capacitor and the second electrode plate of the compensation capacitor on the substrate at least partially overlap; The compensation capacitor further includes a third electrode plate, the third electrode plate of the compensation capacitor is located on the fourth conductive layer, and the third electrode plate of the compensation capacitor is connected to the first electrode plate of the compensation capacitor; The first signal line extends to the first non-display area, and the first signal line includes an overlapping portion at least partially overlapping with the second electrode plate of the compensation capacitor, and the overlapping portion of the first signal line is reused as the third electrode plate of the compensation capacitor; Preferably, the width of the overlapping portion of the first signal line is greater than the width of the first signal line in the first display area; Preferably, the second electrode plate of the compensation capacitor is used to access a signal with a constant potential; Preferably, the second electrode plate of the compensation capacitor is used to access a power signal or an initialization signal; Preferably, the display panel further comprises a light emitting control signal line, and the light emitting control signal line is located in the fourth conductive layer; Preferably, the compensation capacitor further includes a fourth electrode plate, the fourth electrode plate of the compensation capacitor is connected to the second electrode plate of the compensation capacitor, and a vertical projection of the fourth electrode plate of the compensation capacitor on the substrate at least partially overlaps with a vertical projection of the first electrode plate on the substrate; Preferably, the driving circuit layer further comprises a semiconductor layer, the semiconductor layer is arranged on a side of the first conductive layer close to the substrate, and the fourth electrode is located on the first conductive layer or the semiconductor layer.

8. The display panel according to any one of claims 2 to 7, characterized in that: It also includes a second non-display area and a third non-display area; along the first direction, the second non-display area is arranged on at least one side of the second display area; along the second direction, the third non-display area is arranged on a side of the first display area away from the second display area; the display panel includes a plurality of the compensation capacitors, at least one of which is arranged in the second non-display area and / or the third non-display area.

9. The display panel according to claim 1, characterized in that: It also includes a second non-display area and multiple cascaded gate drive circuits; along the first direction, the second non-display area is arranged on at least one side of the second display area; the gate drive circuit is arranged in the first non-display area and the second non-display area; the gate drive circuit includes a first capacitor and a first transistor; the first electrode of the first transistor is used to input a clock signal, the second electrode of the first transistor is connected to the first electrode plate of the first capacitor, and the second electrode of the first transistor is connected to the first signal line or the second signal line, and the gate of the first transistor is connected to the second electrode plate of the first capacitor; the capacitance value of the first capacitor connected to the first signal line is greater than the capacitance value of the first capacitor connected to the second signal line.

10. The display panel according to claim 9, characterized in that: The compensation capacitor includes the first capacitor.

11. The display panel according to claim 9, characterized in that: The gate driving circuit connected to the first signal line is a first gate driving circuit, and the gate driving circuit connected to the second signal line is a second gate driving circuit; along the first direction, the width of the first plate of the first capacitor in the first gate driving circuit is greater than the width of the first plate of the first capacitor in the second gate driving circuit, and the width of the second plate of the first capacitor in the first gate driving circuit is greater than the width of the second plate of the first capacitor in the second gate driving circuit; Preferably, the display panel also includes a substrate and a first conductive layer and a second conductive layer stacked on the substrate, the first conductive layer is arranged on a side of the second conductive layer close to the substrate; the first plate of the first capacitor is located in the second conductive layer, and the second plate of the first capacitor is located in the first conductive layer.

12. The display panel according to claim 11, characterized in that: Along the second direction, the length of the first plate of the first capacitor in the first gate driving circuit is greater than the length of the first plate of the first capacitor in the second gate driving circuit, and the length of the second plate of the first capacitor in the first gate driving circuit is greater than the length of the second plate of the first capacitor in the second gate driving circuit; Preferably, at least part of the plate of the first capacitor in the first gate driving circuit extends between adjacent first gate driving circuits, or extends between the first gate driving circuit and the second gate driving circuit; Preferably, along the second direction, the distance between adjacent first gate driving circuits is greater than the distance between adjacent second gate driving circuits.

13. The display panel according to claim 11 or 12, characterized in that: It also includes a third conductive layer, which is arranged on a side of the second conductive layer away from the substrate; the compensation capacitor also includes a second capacitor; the first electrode plate of the first capacitor is reused as the first electrode plate of the second capacitor, and the second electrode plate of the second capacitor is located on the third conductive layer; the vertical projection of the second electrode plate of the second capacitor on the substrate overlaps with the vertical projection of the first electrode plate of the first capacitor on the substrate; Preferably, a cascade signal line is also arranged between adjacent gate drive circuits, the cascade signal line is connected to the first plate of the first capacitor in the gate drive circuit of the previous level, and the cascade signal line is connected to the starting signal input terminal of the gate drive circuit of this level; the cascade signal line is located in the third conductive layer.

14. The display panel according to claim 1, characterized in that: The first display area includes a plurality of the first signal lines, and the capacitance values ​​of the compensation capacitors connected to the first signal lines are equal; or, along the direction from the second display area to the first display area, the capacitance values ​​of the compensation capacitors connected to the first signal lines gradually decrease; Preferably, along the direction from the second display area to the first display area, the ratio of the sum of the capacitance values ​​of the compensation capacitor corresponding to the first first signal line and the equivalent capacitance of the first pixel to the sum of the capacitance values ​​of the compensation capacitor corresponding to the last first signal line and the equivalent capacitance of the first pixel is less than or equal to 100%:40%.

15. The display panel according to claim 1, characterized in that: The first display area includes a first sub-area and a second sub-area arranged along the first direction, and the first non-display area is arranged on a side of the first sub-area away from the second sub-area and / or a side of the second sub-area away from the first sub-area.

16. A display panel, characterized in that: The display panel comprises a first display area, a second display area and a first non-display area; along a first direction, the first non-display area is located at least on one side of the first display area, the first display area and the second display area are arranged along a second direction, and the first direction intersects with the second direction; the display panel comprises: At least one first signal line and at least one row of first pixels are located in the first display area; the first signal line extends along the first direction, and the first signal line is connected to a row of first pixels; At least one second signal line and at least one row of second pixels are located in the second display area; the second signal line extends along the first direction, and the second signal line is connected to a row of second pixels; the number of the first pixels arranged along the first direction is less than the number of the second pixels arranged along the first direction; A plurality of cascaded gate driving circuits; the gate driving circuit is arranged in the first non-display area; the gate driving circuit includes a first capacitor; the first capacitor is connected to the first signal line or the second signal line; the capacitance value of the first capacitor connected to the first signal line is greater than the capacitance value of the first capacitor connected to the second signal line.

17. The display panel according to claim 16, characterized in that: The gate drive circuit also includes a first transistor; the first electrode of the first transistor is used to input a clock signal, the second electrode of the first transistor is connected to the first plate of the first capacitor, and the gate of the first transistor is connected to the second plate of the first capacitor.

18. A display device, characterized in that: A display panel comprising any one of claims 1-17.

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