Resolution system suitable for split type round inductosyn
By designing a solution system including front-release module, excitation module, solution module, power module and software algorithm module, the problem of traditional split circular induction synchronizer lacking a high-precision angle decoding system is solved, and high-precision angle signal decoding and automatic zeroing are realized, improving the overall accuracy and reliability of the system.
Patent Information
- Application Number
- CN202411676117.1
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-22
- Publication Date
- 2025-03-04
AI Technical Summary
Traditional split circular induction synchronizers lack a supporting high-precision angle decoding system, resulting in reduced overall accuracy of the angle measurement system, structural interference, power supply mismatch, interface incompatibility and other problems, affecting the product market competitiveness.
A solution system including a front-discharge module, an excitation module, a solution module, a power supply module and a software algorithm module is designed. The amplification, filtering, decoding and automatic zeroing of the angle signal is achieved using a differential input amplification circuit, an active bandpass filtering circuit, an AD conversion circuit, a temperature compensation circuit, an FPGA and a DSP data processing circuit.
Through adaptive amplitude modulation, phase adjustment and other algorithms, the decoding accuracy of SIN and COS signals is improved, and the difference is controlled within 10mV, which improves the overall accuracy and reliability of the system.
Smart Images
Figure CN119555119A_ABST
Abstract
Description
Technical Field
[0001] The invention relates to the technical field of angle measurement system equipment, and in particular to a solution system suitable for a split-type circular induction synchronizer. Background Art
[0002] In the angle measurement system, the induction synchronizer is not only resistant to harsh environments, but also has a series of advantages such as high measurement accuracy, long life, low cost, easy installation, fast running speed, stable and reliable, etc. Therefore, the application fields of the induction synchronizer are spread across aerospace, aviation, machinery manufacturing, precision instruments, metrology and other departments.
[0003] Traditional split circular induction synchronizers do not have a matching angle decoding system. When customers configure them, problems such as structural interference, power supply mismatch, interface incompatibility, and the installation of low-precision angle measurement decoding circuits may occur, resulting in reduced overall accuracy of the angle measurement system or even unusability, which reduces the market competitiveness of the product. Such behavior will only increase product costs and extend the R&D period, which is extremely unfavorable for product market development. Therefore, designing a high-precision solution system is extremely important for the development of split circular induction synchronizers. Summary of the invention
[0004] In view of the above technical problems, the present invention provides a solution system suitable for a split circular induction synchronizer, comprising a preamplifier module, an excitation module, a solution module, a power supply module, and a software algorithm module. The preamplifier module is composed of a preamplifier board and a corresponding wiring harness, and includes a differential input amplifier circuit and a second-order active bandpass filter circuit for outputting an amplified angle signal; the excitation module includes a two-stage second-order active filter circuit and a power amplifier circuit; the solution module includes a second-order active bandpass filter circuit, an AD conversion circuit, a temperature compensation circuit, a synchronizer auxiliary installation indicator circuit, an FPGA, a DSP data processing circuit and a power supply module; the power supply module provides power support for the entire system, the synchronizer auxiliary installation indicator circuit assists the synchronizer installation, the temperature compensation circuit realizes the reading and compensation of temperature data, the excitation circuit converts the 10KHZ square wave signal output by the FPGA into a sinusoidal signal of the same frequency and outputs it to the synchronizer excitation coil through the preamplifier board after power amplification, the FPGA completes the reading and processing of the synchronizer angle, and the DSP data processing circuit connects to the FPGA through a high-speed EMIF interface, completes the interaction of angle data and sends the angle position data to the upper computer through the interface.
[0005] Furthermore, the software algorithm module is used to perform algorithmic processing on data, including decoding algorithm, amplitude automatic zeroing algorithm, phase automatic zeroing algorithm, zero bias automatic adjustment algorithm and communication protocol matching algorithm. The software algorithm module makes a judgment on the algorithm to be implemented based on the input algorithm data type and the algorithm identifier used.
[0006] Furthermore, the FPGA is used to complete the reading of the synchronizer angle and RDC control, interrupt signal generation, synchronization signal angle processing, communication with the DSP, and DSP clock and reset signal supply.
[0007] Furthermore, the DSP data processing circuit uses an external independent RC reset circuit to construct an EMIF channel, and the EMIF channel includes a 16-bit data line for transmitting data; an 8-bit address line for addressing; a read signal line for instructing the DSP to read data; a write signal line for instructing the DSP to write data; a chip select signal line for selecting a connected FPGA; an interrupt signal line for processing an interrupt request; the EMIF channel is used for high-speed data communication between the DSP and the FPGA; and the data transmission rate of the EMIF channel is adjusted according to a predefined parameter configuration.
[0008] Furthermore, the amplitude automatic zeroing algorithm is used to monitor and adjust the signal amplitude, including the signal amplitude attenuation caused by the aging of the synchronizer excitation coil and the signal amplitude fluctuation caused by the ambient temperature change.
[0009] Furthermore, the phase automatic zeroing algorithm is used to monitor and correct the signal phase, including the relative displacement change between the synchronizer and the readout device and the clock synchronization error caused by the fluctuation of the system power supply.
[0010] Furthermore, the zero bias automatic adjustment algorithm is automatically executed when the system is started or reset, and is used to eliminate the zero position deviation caused by the mechanical installation error of the synchronizer and the zero point drift after the system runs for a long time.
[0011] Furthermore, the communication protocol matching algorithm is used for automatic identification and configuration of multiple communication protocols and error detection and correction during data transmission.
[0012] Compared with the prior art, the present invention has the following beneficial effects: the present invention provides algorithms such as adaptive amplitude modulation and phase adjustment, which can reduce the difference between the amplitudes of the SIN and COS two-phase signals and control the difference within 10mV, thereby improving the system decoding accuracy by one order of magnitude; the small signal is input through a circular induction synchronizer for isolation, noise reduction and amplification processing, thereby filtering out clutter interference; the present invention is characterized by modular design, which has higher reliability and programmability. BRIEF DESCRIPTION OF THE DRAWINGS
[0013] Figure 1 It is a schematic diagram of the system block diagram of the present invention.
[0014] Figure 2 It is a schematic diagram of an electrical system block diagram of an embodiment of the present invention.
[0015] Figure 3 This is a block diagram of an automatic amplitude adjustment algorithm according to an embodiment of the present invention; Figure 4 This is a block diagram of an automatic phase adjustment algorithm according to an embodiment of the present invention; Figure 5 This is a block diagram of an automatic zero bias adjustment algorithm according to an embodiment of the present invention; DETAILED DESCRIPTION
[0016] Example: Figure 1 As shown, a solution system suitable for split circular induction synchronizer includes a preamplifier module, an excitation module, a solution module, a power module, and a software algorithm module. The preamplifier module is composed of a preamplifier board and a corresponding wiring harness, including a differential input amplifier circuit and a second-order active bandpass filter circuit for outputting an amplified angle signal; the excitation module includes a two-stage second-order active filter circuit and a power amplifier circuit; the solution module includes a second-order active bandpass filter circuit, an AD conversion circuit, a temperature compensation circuit, a synchronizer auxiliary installation indicator circuit, an FPGA, a DSP data processing circuit, and a power supply module; the power supply module provides power support for the entire system, the synchronizer auxiliary installation indicator circuit assists the synchronizer installation, the temperature compensation circuit realizes the reading and compensation of temperature data, the excitation circuit converts the 10KHZ square wave signal output by the FPGA into a sinusoidal signal of the same frequency and outputs it to the synchronizer excitation coil through the preamplifier board after power amplification, the FPGA completes the reading and processing of the synchronizer angle, and the DSP data processing circuit connects to the FPGA through a high-speed EMIF interface to complete the interaction of angle data and send the angle position data to the upper computer through the interface.
[0017] In this embodiment, Figure 2 As shown in the figure, the angle measurement circuit supports the synchronizer angle measurement element to process the angle measurement input signal, and then controls the AD conversion through FPGA. The converted 16-bit digital quantity is directly transmitted to the lower 14 bits of the 16-bit data line of the DSP's EMIF bus. Finally, the DSP reads the synchronizer COS and SIN two-phase AD conversion values and performs angle resolution. The synchronizer COS and SIN two-phase signals pass through a potentiometer, and the amplification factor can be manually adjusted. Then, the synchronizer output signal is filtered through an active second-order bandpass filter. After filtering, it is sent to the AD converter AD7606 for AD conversion. The conversion result is sent to the DSP processor for angle resolution. The DSP is expanded with an EEPROM to store configuration information and parameters. In the design, the DSP uses an external independent resistor-capacitor reset circuit, an external 30M passive crystal oscillator as the clock input, and communicates with the FPGA through a high-speed EMIF interface to complete data interaction with the FPGA. The EMIF channel is formed using 16-bit data lines, 8-bit address lines, and read, write, chip select and interrupt signal lines. The interrupt is provided by the FPGA, and the data refresh rate is 100us.
[0018] The software algorithm module is used to perform algorithmic processing on data, including decoding algorithm, amplitude automatic zeroing algorithm, phase automatic zeroing algorithm, zero bias automatic adjustment algorithm and communication protocol matching algorithm. The software algorithm module makes a judgment on the algorithm to be implemented based on the input algorithm data type and the algorithm identifier used.
[0019] FPGA is used to complete the synchronizer angle reading and RDC control, interrupt signal generation, synchronization signal angle processing, communication with DSP, DSP clock and reset signal supply. The DSP data processing circuit uses an external independent resistor-capacitor reset circuit to build an EMIF channel. The EMIF channel includes 16-bit data lines for data transmission; 8-bit address lines for addressing; read signal lines for instructing DSP to read data; write signal lines for instructing DSP to write data; chip select signal lines for selecting the connected FPGA; interrupt signal lines for processing interrupt requests; EMIF channel for high-speed data communication between DSP and FPGA; the data transmission rate of the EMIF channel is adjusted according to the predefined parameter configuration.
[0020] In this embodiment, Figure 3 When the system shown is powered on, the software collects and calculates the amplitude of the SIN and COS two-phase signals of each axis of the turntable in real time and calculates the peak value. The difference between the two-phase peak values can be used to calculate the difference coefficient P, and after multiple iterations of calculation and averaging, a stable and reasonable P value can be obtained. The software can reduce the difference in the amplitude of the SIN and COS two-phase signals through the P value and control the difference within 10mV. The amplitude automatic zeroing algorithm is used to monitor and adjust the signal amplitude, including the signal amplitude attenuation caused by the aging of the synchronizer excitation coil and the signal amplitude fluctuation caused by the ambient temperature change.
[0021] like Figure 4 As shown in the figure, when the system is powered on, the data D is automatically increased by 1 in each sampling cycle and the AD sampling value is saved. The software calculates the maximum value (peak value) of the AD sampling value in real time and records the D value at this time. The software can obtain a stable and reliable D value through repeated operations. The phase automatic zeroing algorithm is used to monitor and correct the signal phase, including the relative displacement change between the synchronizer and the readout device and the clock synchronization error caused by the system power supply fluctuation.
[0022] like Figure 5 As shown in the figure, when the system is powered on, the turntable can be controlled to move automatically and the zero offset value can be automatically calculated. When the zero offset needs to be corrected and compensated, the software will automatically correct and store it without manual intervention. The zero offset automatic adjustment algorithm is automatically executed when the system is started or reset, and is used to eliminate the zero position deviation caused by the mechanical installation error of the synchronizer and the zero point drift after the system has been running for a long time. The communication protocol matching algorithm is used for automatic identification and configuration of multiple communication protocols and error detection and correction during data transmission.
Claims
1. A solution system for a split-type circular induction synchronizer, comprising a preamplifier module, an excitation module, a solution module, a power module, and a software algorithm module, characterized in that: The preamplifier module is composed of a preamplifier board and a corresponding wiring harness, including a differential input amplifier circuit and a second-order active bandpass filter circuit, which is used to output the amplified angle signal; the excitation module includes a two-stage second-order active filter circuit and a power amplifier circuit; the solution module includes a second-order active bandpass filter circuit, an AD conversion circuit, a temperature compensation circuit, a synchronizer auxiliary installation indicator circuit, an FPGA, a DSP data processing circuit and a power supply module; the power supply module provides power support for the entire system, the synchronizer auxiliary installation indicator circuit assists the synchronizer installation, the temperature compensation circuit realizes the reading and compensation of temperature data, the excitation circuit converts the 10KHZ square wave signal output by the FPGA into a sinusoidal signal of the same frequency and outputs it to the synchronizer excitation coil through the preamplifier board after power amplification, the FPGA completes the reading and processing of the synchronizer angle, and the DSP data processing circuit connects to the FPGA through a high-speed EMIF interface, completes the interaction of angle data and sends the angle position data to the host computer through the interface.
2. A solution system for a split-type circular induction synchronizer according to claim 1, characterized in that: The software algorithm module is used to perform algorithmic processing on data, including decoding algorithm, amplitude automatic zeroing algorithm, phase automatic zeroing algorithm, zero bias automatic adjustment algorithm and communication protocol matching algorithm. The software algorithm module determines the implementation algorithm according to the input algorithm data type and the algorithm identifier used.
3. A solution system for a split-type circular induction synchronizer according to claim 1, characterized in that: The FPGA is used to complete the reading of the synchronizer angle and RDC control, interrupt signal generation, synchronization signal angle processing, communication with the DSP, and DSP clock and reset signal supply.
4. A solution system for a split-type circular induction synchronizer according to claim 1, characterized in that: The DSP data processing circuit uses an external independent RC reset circuit to construct an EMIF channel, and the EMIF channel includes a 16-bit data line for transmitting data; an 8-bit address line for addressing; a read signal line for instructing the DSP to read data; a write signal line for instructing the DSP to write data; a chip select signal line for selecting a connected FPGA; an interrupt signal line for processing an interrupt request; the EMIF channel is used for high-speed data communication between the DSP and the FPGA; and the data transmission rate of the EMIF channel is adjusted according to a predefined parameter configuration.
5. A solution system for a split-type circular induction synchronizer according to claim 2, characterized in that: The amplitude automatic zeroing algorithm is used to monitor and adjust the signal amplitude, including the signal amplitude attenuation caused by the aging of the synchronizer excitation coil and the signal amplitude fluctuation caused by the ambient temperature change.
6. A solution system for a split-type circular induction synchronizer according to claim 2, characterized in that: The phase automatic zeroing algorithm is used to monitor and correct the signal phase, including the relative displacement change between the synchronizer and the readout device and the clock synchronization error caused by the fluctuation of the system power supply.
7. A solution system for a split-type circular induction synchronizer according to claim 2, characterized in that: The zero bias automatic adjustment algorithm is automatically executed when the system is started or reset, and is used to eliminate the zero position deviation caused by the mechanical installation error of the synchronizer and the zero point drift after the system runs for a long time.
8. The solving system for split-type circular induction synchronizer according to claim 2, characterized in that: The communication protocol matching algorithm is used for automatic identification and configuration of multiple communication protocols and error detection and correction during data transmission.