High-resolution path delay test system and method for FPGA (Field Programmable Gate Array)

Abstract

The invention belongs to the technical field of integrated circuit testing, particularly relates to a high-resolution path delay testing system and method for an FPGA (Field Programmable Gate Array), and aims to solve the problem that delay faults are difficult to efficiently detect with high resolution by the existing testing method. According to the invention, a clock input module generates working and clock references and sends the working and clock references to a clock delay module and an output acquisition module respectively; the clock delay module receives a work clock, an initial tap is set to be 0, a delay clock is generated to the test vector generation module, and the test vector generation module generates a test excitation signal to drive a module to be tested accordingly. An output signal returns to the output acquisition module, and the circuit function is evaluated by comparing a reference clock. The sequence detection module monitors the number of taps of the clock delay module, and if the number does not reach a threshold value, the number of taps is circularly increased and the test process is repeated; and if the standard is reached, stopping the test. According to the invention, the test cost is reduced, the product reliability and quality assurance are enhanced, and the method has wide applicability and flexibility.

Description

Background Art

[0002] With the development of integrated circuits, FPGAs are becoming larger and larger, with higher speeds, more complex logic, and more and more important reliability issues. The need for FPGA testing has become particularly urgent, and its testing technology has also received extensive attention and research. Programmable interconnect resources are an important part of FPGAs. In FPGA devices, array-type programmable logic units are connected to form a whole through programmable interconnect resources. FPGAs can achieve specific functions required by different designers by connecting logic units to achieve different functions in a user-defined manner through programmable interconnect resources.

[0003] There are many programmable switches on the chip designed based on FPGA, and the delay of the whole chip is mainly determined by the number and stability of these programmable switches. To ensure that every switch and connection on the chip is free of faults, a very effective test method is needed to test the possible faults on the chip, solve the problem of signal transmission quality deterioration caused by the accumulation of small delays in the transmission path of the logic gates when the number of logic gates of FPGA increases exponentially, and study the delay test method with higher test resolution to ensure the timing and reliability of FPGA in use.

[0004] Based on this, the present invention proposes a high-resolution path delay test system and method for FPGA. Summary of the invention

[0005] In order to solve the above-mentioned problems in the prior art, namely, as the scale and complexity of FPGA increase, the accumulation of tiny delays in the logic gate transmission path affects the transmission quality of the signal, and the existing testing methods are difficult to detect these delay faults efficiently and with high resolution, the present invention provides a high-resolution path delay testing system and method for FPGA.

[0006] In a first aspect of the present invention, a high-resolution path delay test system for FPGA is proposed, comprising a clock input module, a clock delay module, a test vector generation module, a module to be tested, an output acquisition module and a sequence detection module;

[0007] The clock input module is used to generate the working clock and reference clock required by the system, input the working clock to the clock delay module, and input the reference clock to the output acquisition module;

[0008] The clock delay module is used to obtain a working clock and generate a delayed clock, and input the delayed clock into a test vector generation module, and the test vector generation module outputs a test stimulus signal to the module under test based on the delayed clock; wherein the initial tap of the clock delay module is 0;

[0009] All paths to be tested in the module to be tested are driven by the test excitation signal, and the output signals of all paths are transmitted to the output acquisition module, and the output acquisition module determines whether there is a fault in the circuit to be tested by judging the logical relationship between the reference clock and the output signal;

[0010] The sequence detection module is used to check whether the number of taps in the clock delay module reaches a preset threshold. If not, it jumps to the clock input module and increases the number of taps in the clock delay module by one; if it reaches the threshold, the test ends.

[0011] In some preferred embodiments, the frequencies of the working clock and the reference clock generated by the clock input module are provided by an external clock source, and the working clock and the reference clock are the same;

[0012] The working clock is used to drive each module in the system to operate according to the required timing;

[0013] The reference clock provides a time reference signal for the system.

[0014] In some preferred embodiments, the clock delay module includes an IDELAY2 module and an IDELAYCTRL module;

[0015] The IDELAY2 module is composed of a tapped delay line and is used for delaying the input signal. The IDELAYCTRL module is used for calibrating and controlling the IDELAY2 module.

[0016] In some preferred implementations, a trigger is provided inside the module to be tested and a plurality of paths to be tested are provided, and the trigger receives a test stimulus signal and stimulates the plurality of paths to be tested.

[0017] In some preferred embodiments, the test vector generation module is constructed based on a basic logic unit CLB, and constructs test vectors for multiple paths to be tested by programming and configuring the CLB to form a test stimulus signal to stimulate the module to be tested.

[0018] In some preferred implementations, the output acquisition module acquires and analyzes output signals of multiple paths to be tested based on an output response analyzer to determine whether there is a logic fault in the logic transition of the paths to be tested.

[0019] In some preferred implementations, the output acquisition module is driven by the working clock to simultaneously detect the logic levels and changes of multiple output signals.

[0020] In some preferred embodiments, the sequence detection module uses a weighted judgment method for critical paths to determine whether the number of taps in the clock delay module reaches a preset threshold.

[0021] In some preferred implementations, the delay size is changed by changing the tap value set inside the IDELAY2 module, and the delay size of each tap is set based on the working clock provided by the input clock module.

[0022] Another aspect of the present invention provides a high-resolution path delay test method for FPGA. Based on the high-resolution path delay test system for FPGA described in the first aspect, the method comprises the following steps:

[0023] Step S1: Generate a working clock and a reference clock based on the clock input module design;

[0024] Step S2: setting the initial tap in the clock delay module to 0, using the working clock to drive the clock delay module design, and generating a delayed clock;

[0025] Step S3: Generate a test stimulus signal based on a test vector generation module;

[0026] Step S4: the module to be tested obtains a test excitation signal and drives all paths to be tested to obtain an output signal;

[0027] Step S5: the output acquisition module acquires and analyzes the logical relationship of the output signals of the multiple paths to be tested to determine whether there is a fault in the circuit to be tested;

[0028] Step S6: The sequence detection module judges the current tap value. If it has not been reached, it jumps to step S1 and increases the number of taps in step S2 by one; if it has been reached, the test ends and the test results of different tap numbers are recorded.

[0029] Beneficial effects of the present invention:

[0030] Ultra-high-resolution delay measurement: By precisely controlling and adjusting the tap positions in the IDELAY2 module, a measurement resolution of up to 78 picoseconds (ps) is achieved. This greatly improves the detection accuracy of the delay characteristics of the signal transmission path inside the FPGA, helping to discover tiny delay differences and potential faults.

[0031] Reduced testing costs: This approach does not rely on automated test equipment and reduces reliance on external expensive test equipment, which significantly reduces testing costs and complexity, allowing more development stages and product batches to be fully tested.

[0032] Wide applicability and flexibility: This method can be easily migrated to FPGA products of different models and sizes to perform internal path delay testing. Because it fully utilizes the resources and characteristics of FPGA itself, it has high flexibility and wide applicability and is not limited to a specific type of ATE or external conditions.

[0033] Enhanced product reliability and quality assurance: Through more efficient and high-resolution testing methods, delay issues that may affect performance and reliability can be identified early in product development, and measures can be taken to optimize the design and improve the quality and reliability of the final product. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0035] Figure 1 It is a schematic diagram of the connection relationship between modules in a high-resolution path delay test system for FPGA of the present invention;

[0036] Figure 2 It is a structural schematic diagram of an IDELAY2 module in a high-resolution path delay test system for FPGA of the present invention;

[0037] Figure 3 The present invention discloses an output signal simulation diagram of a module to be tested in a high-resolution path delay test system for FPGA. DETAILED DESCRIPTION

[0038] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0039] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0040] like Figure 1-3 As shown, the present invention provides a high-resolution path delay test system for FPGA, including a clock input module, a clock delay module, a test vector generation module, a module to be tested, an output acquisition module and a sequence detection module;

[0041] The clock input module is used to generate the working clock and reference clock required by the system, input the working clock to the clock delay module, and input the reference clock to the output acquisition module;

[0042] The clock delay module is used to obtain a working clock and generate a delayed clock, and input the delayed clock into a test vector generation module, and the test vector generation module outputs a test stimulus signal to the module under test based on the delayed clock; wherein the initial tap of the clock delay module is 0;

[0043] All paths to be tested in the module to be tested are driven by the test excitation signal, and the output signals of all paths are transmitted to the output acquisition module, and the output acquisition module determines whether there is a fault in the circuit to be tested by judging the logical relationship between the reference clock and the output signal;

[0044] The sequence detection module is used to check whether the number of taps in the clock delay module reaches a preset threshold. If not, it jumps to the clock input module and increases the number of taps in the clock delay module by one; if it reaches the threshold, the test ends.

[0045] In order to more clearly describe the high-resolution path delay test system for FPGA of the present invention, the following is combined with Figure 1 Each module in the embodiment of the present invention is described in detail as follows:

[0046] The clock input module is used to generate the working clock and reference clock required by the system, input the working clock to the clock delay module, and input the reference clock to the output acquisition module;

[0047] In the present invention, the frequencies of the working clock and the reference clock generated by the clock input module are provided by an external clock source, and the working clock and the reference clock are the same, both of which are 200Mhz;

[0048] The working clock is used to drive each module inside the system to run according to the required timing; the reference clock provides a standard and accurate time reference signal for the system, and the clock module is connected to other modules of the system through a specific clock circuit.

[0049] The clock delay module is used to obtain a working clock and generate a delayed clock, and input the delayed clock into a test vector generation module, and the test vector generation module outputs a test stimulus signal to the module under test based on the delayed clock; wherein the initial tap of the clock delay module is 0;

[0050] See also Figure 2 , in the present invention, the clock delay module includes an IDELAY2 module and an IDELAYCTRL module;

[0051] The IDELAY2 module is composed of a tapped delay line and is used for delaying the input signal. The IDELAYCTRL module is used for calibrating and controlling the IDELAY2 module.

[0052] Clock delay module design, through which hierarchical delay of the clock is realized, which mainly includes IDELAY2 module and IDELAYCTRL module. The IDELAY2 module is designed with tap delay line, which can realize accurate and configurable delay processing of input signals. The IDELAYCTRL module can realize calibration control of related adjustable delay modules such as the IDELAY2 module. The precise hierarchical delay of the input clock can be finally realized through the coordinated configuration of the IDELAY2 module and the IDELAYCTRL module.

[0053] Specifically, the clock delay module includes the IDELAY2 module and the IDELAYCTRL module, and it is necessary to reasonably configure the IDELAY2 module and the IDELAYCTRL module to ensure that the IDELAY2 module sets a suitable delay for the signal of the data line. The IDELAYCTRL needs to work based on the reference clock to ensure that the functions involving delay adjustment of the entire system under different conditions are reliable and stable.

[0054] The IDELAY2 module is a dedicated delay unit with 31 levels. The delay size can be changed by changing the tap value set inside IDELAY2. The delay size of each tap is related to the working clock provided by the input clock module. When the clock input is 200MHZ, the number of taps is 78ps.

[0055] The IDELAYCTRL module is an input delay control, which calibrates the delay tap of the IDELAY2 module, reduces the influence of the processing process, voltage, and temperature, and ensures that the functions of the entire system involving delay adjustment under different conditions are reliable and stable. The IDELAYCTRL module in one clock region can simultaneously supply multiple IDELAY2 modules.

[0056] The clock delay module is used to obtain a working clock and generate a delayed clock, and input the delayed clock into a test vector generation module, and the test vector generation module outputs a test stimulus signal to the module under test based on the delayed clock; wherein the initial tap of the clock delay module is 0;

[0057] In the present invention, the test vector generation module generates the test vector for delay test based on the internal structure of FPGA. The linear feedback shift register is used in the module to realize the jump of transmission logic on the path to be tested and realize the design generation of test stimulus through the test vector generation module.

[0058] The test vector generation module is composed of a basic logic unit CLB. By programming and configuring the CLB, test vectors for multiple paths to be tested are constructed to form test stimulus signals that stimulate the modules to be tested. Specifically, by programming and configuring the CLB, internal components are used to construct test vectors for multiple paths to be tested to form input stimulus for the modules to be tested.

[0059] Among them, CLB stands for Configurable Logic Block, which means a configurable logic module.

[0060] All paths to be tested in the module to be tested are driven by the test excitation signal, and the output signals of all paths are transmitted to the output acquisition module, and the output acquisition module determines whether there is a fault in the circuit to be tested by judging the logical relationship between the reference clock and the output signal;

[0061] In the present invention, a trigger is provided inside the module to be tested and there are multiple paths to be tested, and the trigger receives a test excitation signal and excites the multiple paths to be tested;

[0062] The paths to be tested are grouped and designed inside the module to be tested. The paths to be tested are grouped and planned, and the paths in different groups are tested in parallel to achieve logical jumps of multiple paths to be tested. Multiple paths to be tested can improve test efficiency and test coverage.

[0063] The test path grouping design refers to identifying multiple test paths to be tested, grouping and planning the multiple test paths according to the logic flipping conditions of the test paths, forming combinational logic jumps of the multiple test paths, testing the paths in different groups in parallel, and checking the delay faults in these paths with the least test configuration.

[0064] The delayed clock tclk in the present invention enters the test vector generation module to control the test vector generator (TPG) circuit. The initial tap is set to 0 inside the IDELAY2 module. Each additional tap causes the rising edge or falling edge of the TPG output signal ts to be delayed by one tap.

[0065] The output acquisition module collects and analyzes the output signals of multiple paths to be tested based on the output response analyzer to determine whether there is a logic fault in the logic jump of the path to be tested. The output acquisition module is driven by the working clock and simultaneously detects the logic levels and changes of multiple output signals, such as Figure 3 shown.

[0066] The sequence detection module is used to check whether the number of taps in the clock delay module reaches a preset threshold. If not, it jumps to the clock input module and increases the number of taps in the clock delay module by one; if it reaches the threshold, it stops clock generation and the test ends.

[0067] The sequence detection module detects the delay level to judge the test process, which is a weighted judgment method for critical paths. It is implemented through the IOB structure inside the FPGA, controls the IDELAY2 delay level in the clock delay module to increase, traverses the test conditions of the path to be tested under different IDELAY2 delay levels, and realizes the judgment of the entire test process.

[0068] The preset threshold is preferably 31 in this embodiment.

[0069] IOB in the present invention stands for Input / Output Block, which means an input / output module.

[0070] It should be noted that the high-resolution path delay test system for FPGA provided in the above embodiment is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiment can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not regarded as improper limitations of the present invention.

[0071] The second embodiment of the present invention, based on the high-resolution path delay test system for FPGA in the first embodiment, proposes a high-resolution path delay test method for FPGA.

[0072] The method of the present invention is described in detail by taking the XC7K325T FPGA test as an example. The XC7K325T FPGA has rich internal resource modules including IOB, CLB, PLL, etc., and contains a dedicated delay unit IDELAY2 module, which has 31 levels of delay settings. The distinguishable delay time of each level of delay is provided by a dedicated IDELAYCTRL module. The IDELAYCTRL module in a clock area can provide multiple IDELAY2 modules at the same time. Select the clock source set to 200MHZ clock for output.

[0073] The method includes:

[0074] Step S1: Based on the clock input module, a signal source provides a 200 MHZ single-ended clock as the FPGA to generate a working clock clk and a reference clock clk_copy;

[0075] Step S2: setting the initial tap in the clock delay module to 0, using the working clock to drive the clock delay module design, and generating a delayed clock; Among them, the clock delay module design is driven by the 200MHZ working clock. The IDELAY2 module is as follows: Figure 2 As shown, the control signals CE, INC, and RST pins of the IDELAY2 module and the IDELAYCTRL module are set, the initial tap inside the IDELAY2 module is set to 0, the IDELAYCTRL module calibrates and controls the IDELAY2 module, and the multi-stage tap delay line design is realized by successively accumulating the tap number of the IDELAY2 module, so that accurate and configurable delay processing of the input signal can be realized. Since the IDELAY2 module has 31 tap levels, the delay setting from 0ps (the tap number is 0) to 2.418ns (the tap number is 31) can be realized;

[0076] Step S3: Generate a test stimulus signal based on a test vector generation module;

[0077] The test vector generation module is designed by using the CLB inside the FPGA to generate the test vector for delay test, and the linear feedback shift register is connected in series step by step to form the input logic flip circuit of the path to be tested;

[0078] Step S4: the module to be tested obtains a test excitation signal and drives all paths to be tested to obtain an output signal;

[0079] The modules to be tested are driven by triggers, and the paths to be tested are grouped according to the trigger nodes. The paths to be tested that terminate at the same trigger are grouped together, and the paths in different groups are tested in parallel to achieve logic jumps of multiple paths to be tested.

[0080] Step S5: the output acquisition module acquires and analyzes the logical relationship of the output signals of the multiple paths to be tested to determine whether there is a fault in the circuit to be tested;

[0081] The output acquisition module collects and analyzes the output signals of multiple paths to be tested. The output response analyzer is connected to the module to be tested through the acquisition circuit to collect the outputs of multiple paths to be tested, and judge whether there is a logic fault in the logic jump of the path to be tested. The test simulation is as follows: Figure 3 shown.

[0082] Step S6: The sequence detection module judges the current tap value. If it has not been reached, it jumps to step S1 and increases the number of taps in step S2 by one; if it has been reached, the test ends and the test results of different tap numbers are recorded.

[0083] The sequence detection module judges the current tap value of the IDELAY2 module. If the tap number has not reached 31, repeat all the above steps, adding one to the tap number set in the IDELAY2 module in step S2 each time until the tap number reaches 31. The test cycle is completely completed and the test results of different tap numbers are recorded.

[0084] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art can understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the scope of protection of the present invention.

[0085] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the method described above can refer to the corresponding process in the aforementioned system embodiment, and will not be repeated here.

[0086] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.

[0087] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.

[0088] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A high-resolution path delay test system for FPGA, characterized in that: It includes a clock input module, a clock delay module, a test vector generation module, a module to be tested, an output acquisition module and a sequence detection module; The clock input module is used to generate the working clock and reference clock required by the system, input the working clock to the clock delay module, and input the reference clock to the output acquisition module; The clock delay module is used to obtain a working clock and generate a delayed clock, and input the delayed clock into a test vector generation module, and the test vector generation module outputs a test stimulus signal to the module under test based on the delayed clock; wherein the initial tap of the clock delay module is 0; All paths to be tested in the module to be tested are driven by the test excitation signal, and the output signals of all paths are transmitted to the output acquisition module, and the output acquisition module determines whether there is a fault in the circuit to be tested by judging the logical relationship between the reference clock and the output signal; The sequence detection module is used to check whether the number of taps in the clock delay module reaches a preset threshold. If not, it jumps to the clock input module and increases the number of taps in the clock delay module by one; if it reaches the threshold, the test ends.

2. A high-resolution path delay test system for FPGA according to claim 1, characterized in that: The frequencies of the working clock and the reference clock generated by the clock input module are provided by an external clock source, and the working clock and the reference clock are the same; The working clock is used to drive each module in the system to operate according to the required timing; The reference clock provides a time reference signal for the system.

3. A high-resolution path delay test system for FPGA according to claim 1, characterized in that: The clock delay module includes an IDELAY2 module and an IDELAYCTRL module; The IDELAY2 module is composed of a tapped delay line and is used for delaying the input signal. The IDELAYCTRL module is used for calibrating and controlling the IDELAY2 module.

4. A high-resolution path delay test system for FPGA according to claim 1, characterized in that: A trigger and a plurality of paths to be tested are arranged inside the module to be tested. The trigger receives a test excitation signal and excites the plurality of paths to be tested.

5. A high-resolution path delay test system for FPGA according to claim 4, characterized in that: The test vector generation module is constructed based on a basic logic unit CLB, and constructs test vectors for multiple paths to be tested by programming and configuring the CLB to form a test stimulus signal to stimulate the module to be tested.

6. A high-resolution path delay test system for FPGA according to claim 4, characterized in that: The output acquisition module acquires and analyzes the output signals of the plurality of paths to be tested based on the output response analyzer, and determines whether there is a logic fault in the logic transition of the paths to be tested.

7. A high-resolution path delay test system for FPGA according to claim 6, characterized in that: The output acquisition module is driven by the working clock to simultaneously detect the logic levels and changes of multiple output signals.

8. A high-resolution path delay test system for FPGA according to claim 1, characterized in that: The sequence detection module uses a weighted judgment method for critical paths to determine whether the number of taps in the clock delay module has reached a preset threshold.

9. A high-resolution path delay test system for FPGA according to claim 3, characterized in that: The delay size is changed by changing the tap value set inside the IDELAY2 module, and the delay size of each tap is set based on the working clock provided by the input clock module.

10. A high-resolution path delay test method for FPGA, based on a high-resolution path delay test system for FPGA according to any one of claims 1 to 9, characterized in that: The method comprises the following steps: Step S1: Generate a working clock and a reference clock based on the clock input module design; Step S2: setting the initial tap in the clock delay module to 0, using the working clock to drive the clock delay module design, and generating a delayed clock; Step S3: Generate a test stimulus signal based on a test vector generation module; Step S4: the module to be tested obtains a test excitation signal and drives all paths to be tested to obtain an output signal; Step S5: the output acquisition module acquires and analyzes the logical relationship of the output signals of the multiple paths to be tested to determine whether there is a fault in the circuit to be tested; Step S6: The sequence detection module determines the current tap value. If it has not been reached, it jumps to step S1 and increases the number of taps in step S2 by one. If it is reached, the test ends and the test results of different tap numbers are recorded.

Images