Compiling method and device of compiler and related equipment

Abstract

The invention provides a compiling method and device of a compiler and related equipment, and relates to the technical field of communication algorithms, the method comprises the steps that a data directed acyclic graph of a to-be-compiled program is acquired, and the data directed acyclic graph comprises a plurality of source nodes of the to-be-compiled program and execution relation nodes among the source nodes; the execution relation nodes between the source nodes are expanded into instruction nodes, and an instruction directed acyclic graph corresponding to the data directed acyclic graph is generated; based on an instruction directed acyclic graph corresponding to the data directed acyclic graph, a target domain language instruction of the to-be-compiled program is generated through the scheduling operation, and the target domain language instruction comprises an execution mode of the to-be-compiled program; and executing the target domain language instruction in the running environment of the target domain language. The target domain language instruction of the to-be-compiled program is generated through the scheduling operation, the execution mode of the to-be-compiled program is optimized, and the compiling efficiency is improved.

Description

Background Art

[0002] In machine learning, the memory capacity and computing power of the Graphic Processing Unit (GPU) can no longer meet the existing large model training. Therefore, the model parameters need to be distributed on multiple GPUs for model training and model inference. As the scale of the model grows, the proportion of communication cost in the total GPU execution time increases. Custom collection algorithms optimized for specific network topologies and application-specific communication patterns can alleviate this bottleneck and help these applications scale. However, implementing correct and efficient custom algorithms is challenging.

[0003] The communication kernel in machine learning workloads supports collective communication operations of the Multi Point Interface (MPI), such as global reduction operations (AllReduce), all collection operations (AllGather), and all-to-all operations (AllToAll). These collective operations use various communication algorithms to collaboratively exchange data between GPUs. Vendor libraries (vendors responsible for providing communication devices and services) such as the NVIDIA Collective Communications Library (NCCL) and the Radeon Collective Communications Library (RCCL) provide high-performance implementations of some standard algorithms, namely ring and tree. Although these custom algorithms tailored to the underlying interconnect topology and input size have achieved remarkable results, they do not implement low-level optimizations such as pipeline parallelization and inter-process communication that help maximize performance.

[0004] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0005] The present disclosure provides a compilation method, apparatus and related equipment of a compiler, which at least to a certain extent overcome the problem in the related art that the communication cost accounts for too high a proportion of the GPU execution time.

[0006] Other features and advantages of the present disclosure will become apparent from the following detailed description, or may be learned in part by the practice of the present disclosure.

[0007] According to one aspect of the present disclosure, a compilation method of a compiler is provided, comprising: obtaining a data directed acyclic graph of a program to be compiled, the data directed acyclic graph comprising a plurality of source nodes of the program to be compiled and execution relationship nodes between the source nodes; expanding the execution relationship nodes between each source node into instruction nodes, and generating an instruction directed acyclic graph corresponding to the data directed acyclic graph; generating target domain language instructions of the program to be compiled through a scheduling operation based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, wherein the target domain language instructions include an execution mode of the program to be compiled; and executing the target domain language instructions in a running environment of the target domain language.

[0008] In some exemplary embodiments of the present disclosure, based on the aforementioned scheme, based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, after generating the target domain language instructions of the program to be compiled through a scheduling operation, the method also includes: combining the instruction directed acyclic graph corresponding to the data directed acyclic graph with the basic instructions in the program to be compiled to obtain fused instructions for the scheduling operation.

[0009] In some exemplary embodiments of the present disclosure, based on the aforementioned scheme, if the data operation is a remote operation, the instruction directed acyclic graph corresponding to the data directed acyclic graph is combined with the basic instructions in the program to be compiled to obtain a fusion instruction for scheduling the operation, including: expanding the remote copy instruction into sending and receiving instructions to form a first fusion instruction; expanding the remote summary instruction into sending data instructions and receiving summary copy instructions to form a second fusion instruction.

[0010] In some exemplary embodiments of the present disclosure, based on the aforementioned scheme, the edges between the execution relationship nodes between each source node are dependency relationships between operations generated by data movement and reuse buffer indexing.

[0011] In some exemplary embodiments of the present disclosure, based on the aforementioned scheme, based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, target domain language instructions of the program to be compiled are generated through a scheduling operation, including: assigning each instruction directed acyclic graph to a thread block for execution, and assigning each communication edge to a channel representing a data transmission connection, wherein the thread block establishes two unidirectional connections with a sending peer and a receiving peer for sending and receiving data blocks; and the channel is used to identify a sending path.

[0012] In some exemplary embodiments of the present disclosure, based on the aforementioned solution, the factors considered in the scheduling operation include at least one of the following: data dependency, processor characteristics, and data processing capabilities of target hardware.

[0013] According to another aspect of the present disclosure, a compilation device of a compiler is also provided, including: a data directed acyclic graph acquisition module, used to acquire a data directed acyclic graph of a program to be compiled, the data directed acyclic graph including multiple source nodes of the program to be compiled and execution relationship nodes between each source node; an instruction directed acyclic graph generation module, used to expand the execution relationship nodes between each source node into an instruction node, and generate an instruction directed acyclic graph corresponding to the data directed acyclic graph; a target domain language instruction generation module, used to generate target domain language instructions of the program to be compiled through a scheduling operation based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, wherein the target domain language instructions include an execution mode of the program to be compiled; and a program execution module, used to execute the target domain language instructions in a running environment of the target domain language.

[0014] According to another aspect of the present disclosure, an electronic device is provided, comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the compilation method of any one of the above compilers by executing the executable instructions.

[0015] According to another aspect of the present disclosure, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the compiling method of any one of the above compilers is implemented.

[0016] According to another aspect of the present disclosure, a computer program product is provided, including: a computer program or instructions, wherein when the computer program or instructions are executed by a processor, the compiling method of any one of the above compilers is implemented.

[0017] A compilation method, apparatus and related equipment of a compiler provided in an embodiment of the present invention can generate an execution mode of a program to be compiled included in the target domain language instructions in the running environment of the target domain language based on a data directed acyclic graph and an instruction directed acyclic graph by using a target domain language to compile a program for model training communication, complete the compilation of the program to be compiled, and generate the target domain language instructions of the program to be compiled through a scheduling operation, which can not only improve the compilation efficiency and reduce the time for generating intermediate representations, but also the target domain language instructions can further optimize the execution mode of the program to be compiled and improve the running performance of the program.

[0018] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The accompanying drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification are used to explain the principles of the present disclosure. Obviously, the accompanying drawings described below are only some embodiments of the present disclosure, and for ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without creative work.

[0020] Figure 1 A schematic diagram showing an exemplary application system architecture of a compiling method of a compiler in an embodiment of the present disclosure;

[0021] Figure 2 A schematic diagram of a compiling method of a compiler in an embodiment of the present disclosure is shown;

[0022] Figure 3 A schematic diagram of a compiler compilation process in an embodiment of the present disclosure is shown;

[0023] Figure 4 A schematic diagram of a compile operation structure in an embodiment of the present disclosure is shown;

[0024] Figure 5 A schematic diagram of a compilation process of a domain-specific language compiler in an embodiment of the present disclosure is shown;

[0025] Figure 6 A schematic diagram of a compiling device of a compiler in an embodiment of the present disclosure is shown;

[0026] Figure 7 A schematic diagram of an electronic device showing a compiling method using a compiler in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0027] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that the disclosure will be more comprehensive and complete and to fully convey the concepts of the example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

[0028] In addition, the described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be adopted. In other cases, known methods, devices, implementations or operations are not shown or described in detail to avoid blurring the various aspects of the present disclosure.

[0029] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0030] Figure 1 FIG. 1 shows an exemplary application system architecture diagram to which the compilation method of the compiler in the embodiment of the present disclosure can be applied. Figure 1 As shown, the system architecture may include a terminal device 101 , a network 102 and a server 103 .

[0031] The network 102 is a medium for providing a communication link between the terminal device 101 and the server 103, and can be a wired network or a wireless network.

[0032] Optionally, the wireless network or wired network described above uses standard communication technology and / or protocol. The network is usually the Internet, but it can also be any network, including but not limited to a local area network (LAN), a metropolitan area network (MAN), a wide area network (WAN), a mobile, wired or wireless network, a dedicated network or any combination of a virtual private network). In some embodiments, technologies and / or formats including Hyper Text Mark-up Language (HTML), Extensible Markup Language (XML), etc. are used to represent data exchanged through the network. In addition, conventional encryption technologies such as Secure Socket Layer (SSL), Transport Layer Security (TLS), Virtual Private Network (VPN), Internet Protocol Security (IPsec) can also be used to encrypt all or some links. In other embodiments, customized and / or dedicated data communication technologies can also be used to replace or supplement the above data communication technologies.

[0033] The terminal device 101 can be various electronic devices, including but not limited to smart phones, tablet computers, laptop computers, desktop computers, wearable devices, augmented reality devices, virtual reality devices, etc.

[0034] Optionally, the client of the application installed in different terminal devices 101 is the same, or the client of the same type of application based on different operating systems. Based on the different terminal platforms, the specific form of the client of the application can also be different, for example, the application client can be a mobile client, a PC client, etc.

[0035] The server 103 may be a server that provides various services, such as a background management server that provides support for the device operated by the user using the terminal device 301. The background management server may analyze and process the received request and other data, and feed back the processing results to the terminal device.

[0036] Optionally, the server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The terminal can be a smart phone, tablet computer, laptop computer, desktop computer, smart speaker, smart watch, etc., but is not limited to this. The terminal and the server can be directly or indirectly connected via wired or wireless communication, which is not limited in this application.

[0037] Those skilled in the art will know that Figure 1 The number of terminal devices, networks and servers in the embodiment is only for illustration, and any number of terminal devices, networks and servers may be provided according to actual needs, and the embodiments of the present disclosure do not limit this.

[0038] Under the above system architecture, an embodiment of the present disclosure provides a compiler compiling method, which can be executed by any electronic device with computing and processing capabilities.

[0039] In some embodiments, the compilation method of the compiler provided in the embodiments of the present disclosure may be executed by a terminal device of the above-mentioned system architecture; in other embodiments, the compilation method of the compiler provided in the embodiments of the present disclosure may be executed by a server in the above-mentioned system architecture; in other embodiments, the compilation method of the compiler provided in the embodiments of the present disclosure may be implemented by a terminal device and a server in the above-mentioned system architecture through interaction.

[0040] First of all, in response to the above-mentioned problems, a compilation method that can be applied to but is not limited to compilers is provided in the embodiments of the present disclosure, and can also be applied to any electronic device with a compilation function. Compared with the problem in the related art that the communication cost accounts for too high a proportion of the GPU execution time, the embodiments of the present disclosure generate target domain language instructions of the program to be compiled through scheduling operations, which not only improves the compilation efficiency and reduces the time for generating intermediate representations, but also optimizes the execution method of the program to be compiled through the target domain language instructions generated by the data directed acyclic graph and the instruction directed acyclic graph, thereby improving the running performance of the program.

[0041] Figure 2 A schematic diagram of a compiling method of a compiler in an embodiment of the present disclosure is shown, and the method comprises the following steps:

[0042] S202, obtaining a data directed acyclic graph of the program to be compiled, where the data directed acyclic graph includes a plurality of source nodes of the program to be compiled and execution relationship nodes between the source nodes.

[0043] It should be noted that the data directed acyclic graph in the embodiment of the present disclosure is obtained by parsing the source code of the program to be compiled, converting the source code into an abstract syntax tree, traversing the abstract syntax tree, adding nodes and edges, and finally obtaining the data directed acyclic graph, wherein the nodes in the data directed acyclic graph also include execution relationship nodes between each source node in the program to be compiled, for example, the copy and aggregation operation between each node is also a node, and the edges between the nodes are the dependencies between the operations generated by data movement and reuse buffer indexes, wherein the data directed acyclic graph records a dynamic global view and naturally exposes the parallelism of the program to be compiled.

[0044] S204, expanding the execution relationship nodes between each source node into instruction nodes, and generating an instruction directed acyclic graph corresponding to the data directed acyclic graph.

[0045] It should be noted that the instruction node in the embodiment of the present disclosure corresponds to a specific instruction or operation. For example, the program to be compiled contains source node A and source node B, and the execution relationship node between source node A and source node B is to summarize this operation. Then the instruction node is an instruction to summarize source node A and source node B. The embodiment of the present disclosure generates an instruction directed acyclic graph corresponding to the data directed acyclic graph based on the instruction node, which can provide more precise control and optimization opportunities for subsequent operations of the program to be compiled.

[0046] S206 , generating target domain language instructions of the program to be compiled through a scheduling operation based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, wherein the target domain language instructions include an execution mode of the program to be compiled.

[0047] It should be noted that the scheduling operation in the embodiment of the present disclosure refers to the compiler determining the execution order and time of each instruction in the program to be compiled according to certain strategies and algorithms. The goal of scheduling is to optimize the execution efficiency of the program, reduce the execution time, improve resource utilization, and ensure the correctness and consistency of the program. The scheduling strategy may include determining the execution order according to the priority of the instruction; or allocating a fixed time slice to each instruction and executing them in turn; or giving priority to the execution of the instruction with the shortest estimated execution time; or determining the execution order according to the dependency between instructions; or allocating parallel executed instructions to different processors or threads.

[0048] S208, executing the target domain language instruction in the target domain language running environment.

[0049] The compilation method of the compiler provided in the embodiment of the present disclosure, first, obtains a data directed acyclic graph of the program to be compiled including multiple source nodes of the program to be compiled and the execution relationship nodes between each source node; secondly, expands the execution relationship nodes between each source node into an instruction node, and generates an instruction directed acyclic graph corresponding to the data directed acyclic graph; then, based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, generates the program to be compiled including the target domain language instructions of the execution mode of the program to be compiled through a scheduling operation; finally, executes the target domain language instructions in the operating environment of the target domain language. Compared with the problem that the communication cost accounts for too high a proportion of the GPU execution time in the related art, the embodiment of the present disclosure generates the target domain language instructions of the program to be compiled through a scheduling operation, which can not only improve the compilation efficiency and reduce the time of generating the intermediate representation, but also the target domain language instructions further optimize the execution mode of the program to be compiled and improve the running performance of the program.

[0050] In some embodiments, after the target domain language instructions of the program to be compiled are generated by the scheduling operation based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, the compilation method of the compiler in the embodiment of the present disclosure further includes: combining the instruction directed acyclic graph corresponding to the data directed acyclic graph with the basic instructions in the program to be compiled to obtain a fusion instruction for the scheduling operation. Figure 3 As shown, specifically, the embodiment of the present disclosure combines the instruction directed acyclic graph with the basic instructions in the program to be compiled to obtain fused instructions, and the fused instructions can reduce the number of instructions and improve the execution efficiency of the instructions. The fused instructions transmit intermediate variables through GPU registers, which can optimize global memory access and significantly improve the performance and efficiency of the program.

[0051] In some embodiments, the basic instructions of the program to be compiled in the embodiments of the present disclosure include: a send data instruction (Send), a receive data instruction (Recv), a summarize data instruction (Reduce) and a copy data instruction (Copy).

[0052] In some embodiments, if the data operation of the disclosed embodiment is a remote operation, the instruction directed acyclic graph corresponding to the data directed acyclic graph is combined with the basic instructions in the program to be compiled to obtain a fused instruction for scheduling the operation, including: expanding the remote copy instruction into a send and receive instruction to form a first fused instruction; expanding the remote summary instruction into a send data instruction and a receive summary copy instruction to form a second fused instruction. Specifically, according to whether the data operation is local or remote, the compiler of the disclosed embodiment expands the data operation in different ways. For example, the first fused instruction is a send and receive instruction (Rcs, Rcr), and the second fused instruction is a send and receive summary copy instruction (Rrcs, Rrcr). The disclosed embodiment reduces the number of instructions by fusing instructions, reduces instruction decoding overhead and instruction cache pressure, improves instruction execution efficiency, reduces memory access, reduces memory bandwidth occupancy and latency, and generates more concise and efficient code, which is also easy for subsequent operators to understand and maintain.

[0053] In some embodiments, Figure 3 As shown, the embodiment of the present disclosure generates target domain language instructions of the program to be compiled through scheduling operations based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, including: assigning each instruction directed acyclic graph to a thread block for execution, assigning each communication edge to a channel representing a data transmission connection, wherein the thread block establishes two unidirectional connections with the sending peer and the receiving peer for sending and receiving data blocks; the channel is used to identify the sending path.

[0054] In some embodiments, the factors considered in the scheduling operation in the embodiments of the present disclosure include at least one of the following: data dependencies, processor characteristics, and data processing capabilities of the target hardware. Specifically, the embodiments of the present disclosure determine the execution order and time of instructions through scheduling operations to optimize the execution efficiency, resource management, and correctness of the program to be compiled. By constructing a directed acyclic graph (DAG) of instructions, selecting a suitable scheduling strategy, and executing tasks in sequence, the performance and reliability of the program can be significantly improved.

[0055] In some embodiments, the target domain language instructions in the embodiments of the present disclosure may be specific domain language instructions. The embodiments of the present disclosure set the specific domain language instructions as IR, which is represented as a tree data structure. A set is divided into separate GPU programs, which are further divided into thread blocks containing sequential instruction lists. These instructions will be executed sequentially. The thread blocks can establish two unidirectional connections with the sending peer and the receiving peer for sending and receiving data blocks. The GPU can establish multiple redundant connections with the same GPU. These connections are identified by channels. Channels are similar to labels in MPI and are used to identify sending paths.

[0056] In some embodiments, Figure 4 As shown, the compilation method of the compiler in the embodiment of the present disclosure specifically includes three parts: domain-specific language compilation 401; domain-specific language program scheduling 402; and domain-specific language runtime environment 403. Specifically, the domain-specific language in the embodiment of the present disclosure is a block-oriented language used to specify block routing through a GPU. The language is embedded in Python as a traceable digital subscriber line (DSL) with a fluent application programming interface (Application Programming Interface). The compiler interprets the sequentially executed program as a data DAG, which records the dynamic global view and naturally exposes the parallelism of the program. The compiler expands each block operation node into an instruction node to generate an instruction DAG that records the global instruction view. After generating the instruction DAG, the compiler performs a series of hole optimizations to merge consecutive basic instructions into fused instructions. After the compiled program is converted into an instruction DAG, the compiler generates a domain-specific language instruction (IR) through a scheduling process. The domain-specific language instruction (IR) outlines how the program is executed. At a high level, this involves assigning each instruction to a thread block for execution and assigning each communication edge to a channel representing a data transmission connection. The domain-specific language runtime executes the program by directly interpreting the domain-specific language instruction (IR). The runtime is an extension of NCCL and inherits the infrastructure connected in various interconnection modes. The runtime dynamically selects the correct algorithm to call based on a user-configurable size range. If the correct algorithm does not exist, the built-in algorithm of NCCL will be selected.

[0057] In some embodiments, the compilation process of the domain-specific language compiler in the embodiments of the present disclosure is as follows: Figure 5 As shown, the compiler reduces the domain-specific language to an intermediate representation called domain-specific language (IR), which is directly interpreted by the domain-specific language runtime environment. The compiler tracks the program to capture block dependencies and performs multiple optimizations such as aggregation, instruction fusion, and parallelization; the compiler uses domain-specific language instructions to schedule the program onto thread blocks so that users can control optimization and scheduling choices; the compiler ensures that distributed execution correctly implements the block-based semantics of the input program while ensuring the absence of deadlocks and data competition; the domain-specific language runtime environment executes domain-specific language instructions (IR) as a single Compute Unified Device Architecture (CUDA) core and performs additional optimizations such as pipelining to improve the utilization of thread blocks and links.

[0058] In some embodiments, the difference between the embodiments of the present disclosure and the related art is that: the embodiments of the present disclosure provide a program compilation method for large model training communication using a specific domain language, the compiler divides the GPU memory into data block buffers representing continuous element spans, and uses preconditions to determine the initial state of the input buffer, uses postconditions to set the expected state of the output buffer, generates an instruction DAG based on the data DAG, and describes the execution task process from a global view; in addition, under the premise that the embodiment of the present disclosure no longer affects the scheduling process of native large model communication instructions, in order to cooperate with the compilation method of the compiler in the embodiment of the present disclosure, two modifications are made to the scheduling of target domain language instructions: scheduling instructions in specific domain language instructions are provided, and program optimization is achieved by balancing parallelization and occupancy constraints; when giving the instruction DAG and scheduling operations of the program, the compiler abides by the rule that each thread block can have at most one sending end and one receiving end, and allocates an instruction node to each thread block.

[0059] Based on the same inventive concept, the present disclosure also provides a compiler compiling device, such as the following embodiment. Since the principle of solving the problem in the device embodiment is similar to that in the above method embodiment, the implementation of the device embodiment can refer to the implementation of the above method embodiment, and the repeated parts will not be repeated.

[0060] Figure 6 A schematic diagram of a compiling device of a compiler in an embodiment of the present disclosure is shown. Figure 6 As shown, the device comprises:

[0061] A data directed acyclic graph acquisition module 601 is used to acquire a data directed acyclic graph of the program to be compiled, wherein the data directed acyclic graph includes a plurality of source nodes of the program to be compiled and execution relationship nodes between the source nodes;

[0062] An instruction directed acyclic graph generating module 602 is used to expand the execution relationship nodes between each source node into instruction nodes, and generate an instruction directed acyclic graph corresponding to the data directed acyclic graph;

[0063] A target domain language instruction generation module 603 is used to generate target domain language instructions of the program to be compiled through a scheduling operation based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, wherein the target domain language instructions include an execution mode of the program to be compiled;

[0064] The program execution module 604 is used to execute target domain language instructions in the target domain language running environment.

[0065] A compilation device of a compiler provided in an embodiment of the present disclosure obtains a data directed acyclic graph of a program to be compiled including multiple source nodes of the program to be compiled and execution relationship nodes between each source node through a data directed acyclic graph acquisition module; through an instruction directed acyclic graph generation module, the execution relationship nodes between each source node are expanded into instruction nodes, and an instruction directed acyclic graph corresponding to the data directed acyclic graph is generated; through a target domain language instruction generation module, based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, a target domain language instruction of the execution mode of the program to be compiled including the program to be compiled is generated through a scheduling operation; through a program execution module, the target domain language instruction is executed in the operating environment of the target domain language. Compared with the problem that the communication cost accounts for too high a proportion of the GPU execution time in the related art, the embodiment of the present disclosure generates the target domain language instruction of the program to be compiled through a scheduling operation, which can not only improve the compilation efficiency and reduce the time of generating the intermediate representation, but also the target domain language instruction further optimizes the execution mode of the program to be compiled and improves the running performance of the program.

[0066] In some embodiments, the compilation device of the compiler in the embodiments of the present disclosure also includes: a fusion instruction module, which is used to generate target domain language instructions of the program to be compiled through scheduling operations based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, and then combine the instruction directed acyclic graph corresponding to the data directed acyclic graph with the basic instructions in the program to be compiled to obtain fusion instructions for scheduling operations.

[0067] In some embodiments, if the data operation in the disclosed embodiment is a remote operation, the fusion instruction module is also used to expand the remote copy instruction into send and receive instructions to form a first fusion instruction; and expand the remote summary instruction into a send data instruction and a receive summary copy instruction to form a second fusion instruction.

[0068] In some embodiments, the edges between the execution relationship nodes between each source node in the embodiments of the present disclosure are dependency relationships between operations generated by data movement and reuse buffer indexes.

[0069] In some embodiments, the target domain language instruction generation module in the embodiments of the present disclosure is also used to assign each instruction directed acyclic graph to a thread block for execution, and assign each communication edge to a channel representing a data transmission connection, wherein the thread block establishes two unidirectional connections with the sending peer and the receiving peer for sending and receiving data blocks; the channel is used to identify the sending path.

[0070] In some embodiments, the factors considered in the scheduling operation in the embodiments of the present disclosure include at least one of the following: data dependency, processor characteristics, and data processing capabilities of target hardware.

[0071] Those skilled in the art will appreciate that various aspects of the present disclosure may be implemented as systems, methods or program products. Therefore, various aspects of the present disclosure may be specifically implemented in the following forms, namely: complete hardware implementation, complete software implementation (including firmware, microcode, etc.), or a combination of hardware and software, which may be collectively referred to herein as "circuits", "modules" or "systems".

[0072] Based on the same inventive concept, an electronic device is also provided in an embodiment of the present disclosure, the electronic device comprising: a processor; and a memory for storing executable instructions of the processor; wherein the processor is configured to execute the compilation method of any of the above compilers by executing the executable instructions. Since the principle of solving the problem in the electronic device embodiment is similar to that in the above method embodiment, the implementation of the electronic device embodiment can refer to the implementation of the above method embodiment, and the repeated parts will not be repeated.

[0073] Refer to the following Figure 7 An electronic device 700 according to this embodiment of the present disclosure is described. Figure 7 The electronic device 700 shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present disclosure.

[0074] like Figure 7 As shown, the electronic device 700 is in the form of a general computing device. The components of the electronic device 700 may include but are not limited to: at least one processing unit 701, at least one storage unit 702, and a bus 703 connecting different system components (including the storage unit 702 and the processing unit 701).

[0075] The storage unit stores program codes, which can be executed by the processing unit 701, so that the processing unit 701 executes the steps described in the above “exemplary method” section of this specification according to various exemplary embodiments of the present disclosure.

[0076] In some embodiments, when the electronic device is used to control the compilation method of the compiler disclosed above, for example, the processing unit 701 may perform the following steps of the above method embodiment:

[0077] Obtain a data directed acyclic graph of a program to be compiled, the data directed acyclic graph including multiple source nodes of the program to be compiled and execution relationship nodes between each source node; expand the execution relationship nodes between each source node into instruction nodes, and generate an instruction directed acyclic graph corresponding to the data directed acyclic graph; based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, generate target domain language instructions of the program to be compiled through a scheduling operation, wherein the target domain language instructions include an execution mode of the program to be compiled; and execute the target domain language instructions in a running environment of the target domain language.

[0078] The storage unit 702 may include a readable medium in the form of a volatile storage unit, such as a random access storage unit (RAM) 7021 and / or a cache storage unit 7022 , and may further include a read-only storage unit (ROM) 7023 .

[0079] The storage unit 702 may also include a program / utility 7024 having a set (at least one) of program modules 7025, such program modules 7025 including but not limited to: an operating system, one or more application programs, other program modules, and program data, each of which or some combination may include an implementation of a network environment.

[0080] Bus 703 may represent one or more of several types of bus structures, including a memory unit bus or memory unit controller, a peripheral bus, an accelerated graphics port, a processing unit, or a local bus using any of a variety of bus architectures.

[0081] The electronic device 700 may also communicate with one or more external devices 704 (e.g., keyboards, pointing devices, Bluetooth devices, etc.), may also communicate with one or more devices that enable a user to interact with the electronic device 700, and / or may communicate with any device that enables the electronic device 700 to communicate with one or more other computing devices (e.g., routers, modems, etc.). This communication may be performed through an input / output (I / O) interface 705. In addition, the electronic device 700 may also communicate with one or more networks (e.g., local area networks (LANs), wide area networks (WANs), and / or public networks, such as the Internet) through a network adapter 706. As shown, the network adapter 706 communicates with other modules of the electronic device 700 through a bus 703. It should be understood that, although not shown in the figure, other hardware and / or software modules may be used in conjunction with the electronic device 700, including but not limited to: microcode, device drivers, redundant processing units, external disk drive arrays, RAID systems, tape drives, and data backup storage systems, etc.

[0082] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a terminal device, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0083] Based on the same inventive concept, a computer-readable storage medium is also provided in the embodiment of the present disclosure, on which a computer program is stored, and when the computer program is executed by a processor, the compilation method of the compiler of any one of the above items is implemented. Since the principle of solving the problem in the embodiment of the computer-readable storage medium is similar to that in the embodiment of the method, the implementation of the embodiment of the computer-readable storage medium can refer to the implementation of the embodiment of the method, and the repeated parts will not be repeated.

[0084] More specific examples of computer-readable storage media in the present disclosure may include, but are not limited to, an electrical connection having one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0085] In the present disclosure, a computer readable storage medium may include a data signal propagated in baseband or as part of a carrier wave, wherein a readable program code is carried. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A readable signal medium may also be any readable medium other than a readable storage medium, which may send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device.

[0086] Alternatively, the program code contained on the computer-readable storage medium may be transmitted using any appropriate medium, including but not limited to wireless, wired, optical cable, RF, etc., or any suitable combination of the foregoing.

[0087] In a specific implementation, the program code for performing the operations of the present disclosure may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as Java, C++, etc., and conventional procedural programming languages ​​such as "C" or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, as a separate software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device may be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computing device (e.g., using an Internet service provider to connect through the Internet).

[0088] Based on the same inventive concept, a computer program product is also provided in the embodiment of the present disclosure, including a computer program product, including: a computer program or an instruction, and a compiling method of a compiler that implements any one of the above method embodiments when the computer program or the instruction is executed by a processor. Since the principle of solving the problem in the computer program product embodiment is similar to that in the above method embodiment, the implementation of the computer program product embodiment can refer to the implementation of the above method embodiment, and the repeated parts will not be repeated.

[0089] It should be noted that, although several modules or units of the device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present disclosure, the features and functions of two or more modules or units described above can be embodied in one module or unit. On the contrary, the features and functions of one module or unit described above can be further divided into multiple modules or units to be embodied.

[0090] In addition, although the steps of the method in the present disclosure are described in a specific order in the drawings, this does not require or imply that the steps must be performed in this specific order, or that all the steps shown must be performed to achieve the desired results. Additionally or alternatively, some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps, etc.

[0091] Through the description of the above implementation, it is easy for those skilled in the art to understand that the example implementation described here can be implemented by software, or by software combined with necessary hardware. Therefore, the technical solution according to the implementation of the present disclosure can be embodied in the form of a software product, which can be stored in a non-volatile storage medium (which can be a CD-ROM, a USB flash drive, a mobile hard disk, etc.) or on a network, including several instructions to enable a computing device (which can be a personal computer, a server, a mobile terminal, or a network device, etc.) to execute the method according to the implementation of the present disclosure.

[0092] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure, which follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are intended to be exemplary only, and the true scope and spirit of the present disclosure are indicated by the appended claims.

Claims

1. A compiling method of a compiler, characterized in that: include: Obtaining a data directed acyclic graph of the program to be compiled, wherein the data directed acyclic graph includes a plurality of source nodes of the program to be compiled and execution relationship nodes between the source nodes; Expanding the execution relationship nodes between each source node into instruction nodes, and generating an instruction directed acyclic graph corresponding to the data directed acyclic graph; Based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, generating target domain language instructions of the program to be compiled through a scheduling operation, wherein the target domain language instructions include an execution mode of the program to be compiled; The target domain language instructions are executed in a target domain language runtime environment.

2. The compiling method of the compiler according to claim 1, characterized in that: After generating the target domain language instructions of the program to be compiled through a scheduling operation based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, the method further includes: The instruction directed acyclic graph corresponding to the data directed acyclic graph is combined with basic instructions in the program to be compiled to obtain fused instructions for scheduling operations.

3. The compiling method of the compiler according to claim 2, characterized in that: If the data operation is a remote operation, the instruction directed acyclic graph corresponding to the data directed acyclic graph is combined with the basic instructions in the program to be compiled to obtain a fused instruction for scheduling the operation, including: Extending the remote copy instruction into a sending and receiving instruction to form a first fusion instruction; The remote summary instruction is expanded into a send data instruction and a receive summary copy instruction to form a second fusion instruction.

4. The compiling method of the compiler according to claim 1, characterized in that: The edges between each source node are the dependencies between operations resulting from data movement and reuse buffer indexing.

5. The compiling method of the compiler according to claim 1, characterized in that: Based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, generating target domain language instructions of the program to be compiled through a scheduling operation, including: Each instruction directed acyclic graph is assigned to a thread block for execution, and each communication edge is assigned to a channel representing a data transmission connection, wherein the thread block establishes two unidirectional connections with a sending peer and a receiving peer for sending and receiving data blocks; and the channel is used to identify a sending path.

6. The compiling method of the compiler according to claim 1, characterized in that: The factors considered in the scheduling operation include at least one of the following: data dependency, processor characteristics, and data processing capability of target hardware.

7. A compiling device of a compiler, characterized in that: include: A data directed acyclic graph acquisition module, used to acquire a data directed acyclic graph of the program to be compiled, wherein the data directed acyclic graph includes a plurality of source nodes of the program to be compiled and execution relationship nodes between the source nodes; An instruction directed acyclic graph generation module, used for expanding the execution relationship nodes between each source node into instruction nodes, and generating an instruction directed acyclic graph corresponding to the data directed acyclic graph; A target domain language instruction generation module, used to generate target domain language instructions of the program to be compiled through a scheduling operation based on the instruction directed acyclic graph corresponding to the data directed acyclic graph, wherein the target domain language instructions include an execution mode of the program to be compiled; The program execution module is used to execute the target domain language instructions in the target domain language running environment.

8. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the compiling method of the compiler according to any one of claims 1 to 6 by executing the executable instructions.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the compiling method of the compiler according to any one of claims 1 to 6 is implemented.

10. A computer program product comprising: A computer program or instruction, characterized in that when the computer program or instruction is executed by a processor, it implements the compiling method of the compiler according to any one of claims 1 to 6.

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