Method and device for clearing cache data page

Abstract

The embodiment of the invention provides a cache data page clearing method and device.The method comprises the steps that under the condition that a first cache data page of a solid state disk is accessed, a visible second cache data page of the first cache data page is determined in a pre-created visible graph, the visible graph comprises the address of each cache data page of the solid state disk, the number of access times in a preset duration, and the visibility between the cache data pages; adjusting the levels of the first cache data page and the second cache data page; and under the condition that the third cache data page with the lowest level exists in the solid state disk, clearing the third cache data page. Through the method and the device, the problem of low universality caused by the fact that a cache scheme cannot cover all scenes with expected input / output in related technologies is solved, and the effect of improving the universality of the cache scheme is achieved.

Description

Technical Field

[0001] The embodiments of the present application relate to the computer field, and in particular, to a method and device for clearing cache data pages. Background Art

[0002] Solid State Disk (SSD) is a storage device based on NAND Flash Memory (NAND Flash), which is widely used in embedded systems, personal computers and high-performance platforms. SSD has the advantages of small size, high performance, random access and low energy consumption, making it one of the main storage devices. In addition to the NAND flash array that permanently stores data, SSDs usually have faster but smaller Dynamic Random Access Memory (DRAM) as a cache for input / output (I / O) operations, which is used to store logical-physical address mapping data structures and temporarily cache the contents of overwrite or write requests.

[0003] Since the DRAM cache capacity of SSDs is limited, cache management schemes must effectively manage cache space to ensure high performance and longevity. When the cache space is full, some cached data must be taken out and refreshed to the underlying flash array to make room for new data. Therefore, the design and implementation of cache management schemes can significantly affect the input / output (I / O) performance of SSDs. Some existing cache management algorithms may have problems such as inefficiency, frequent data refreshes, and write amplification, resulting in performance degradation and shortened flash life.

[0004] There is currently no effective solution to the above problems. Summary of the invention

[0005] The embodiments of the present application provide a method and device for clearing cache data pages, so as to at least solve the problem that the cache solution in the related art cannot cover all scenarios with expected input / output, resulting in low versatility.

[0006] According to one embodiment of the present application, a method for clearing cache data pages is provided, comprising: when a first cache data page of the solid-state drive is accessed, determining a second cache data page that is visible to the first cache data page in a pre-created visible graph, wherein the visible graph includes: the addresses of each cache data page of the solid-state drive and the number of accesses within a preset time length, and the visibility between each cache data page; adjusting the levels of the first cache data page and the second cache data page; and when there is a third cache data page of the lowest level on the solid-state drive, clearing the third cache data page.

[0007] In an exemplary embodiment, the levels of the first cache data page and the second cache data page are adjusted, including: recording the first cache data page at the top of a first-level list, wherein the first-level list is used to record high-level cache data pages; and recording the second cache data page in a list of a corresponding level according to the number of accesses to the second cache data page.

[0008] In an exemplary embodiment, according to the access count of the second cache data page, the second cache data page is recorded in a list of a corresponding level, including: when the access count of the second cache data page is greater than or equal to a preset threshold, the second cache data page is recorded at the first position of the second level list, otherwise, the second cache data page is recorded at the first position of the third level list; wherein the level of the first level list is greater than that of the second level list, the level of the second level list is greater than that of the third level list, the third cache data page is recorded in a fourth level list, and the level of the third level list is greater than that of the fourth level list.

[0009] In an exemplary embodiment, when there is a third cache data page of the lowest level in the solid-state hard disk, the third cache data page is cleared, including: when there is an idle channel in the solid-state hard disk and the number of the idle channels is N, determining the number M of the third cache data pages in the fourth-level list, wherein N and M are integers greater than 0; when M is less than or equal to N, clearing M of the third cache data pages; when M is greater than N, clearing the last N of the third cache data pages in the fourth-level list.

[0010] In an exemplary embodiment, before determining in a pre-created visible graph a second cache data page that is visible to the first cache data page, the method further includes: creating the visible graph based on the addresses of each cache data page of the solid-state drive and the number of accesses within a preset time length, wherein the horizontal axis of the visible graph is the address of each cache data page, the vertical axis of the visible graph is the number of accesses to each cache data page within the preset time length, and the visible graph also includes connecting lines, through which the visible cache data pages are connected.

[0011] In an exemplary embodiment, the method further includes: determining that the i-th cache data page and the j-th cache data page are visible when the i-th cache data page and the j-th cache data page of the solid state drive meet the following conditions:

[0012]

[0013] in, is the address of the i-th cache data page, is the number of accesses to the i-th cache data page, is the address of the jth cache data page, is the number of accesses to the j-th cache data page, is the address of the kth cache data page, is the access count of the kth cache data page, the access address of the kth cache data page is between the address of the ith cache data page and the address of the jth cache data page, wherein i, j, and k are integers.

[0014] In an exemplary embodiment, the method further includes: creating a relationship matrix of each of the cache data pages based on the visible graph, wherein the relationship matrix represents the relationship between each of the cache data pages and other cache data pages through a character string, including: creating a relationship matrix of the sth cache data page in the following manner, s is an integer: using a first character string to represent a cache data page that is not adjacent to the address of the sth cache data page and whose access frequency is higher than a first frequency threshold, using a second character string to represent a cache data page that is adjacent to the address of the sth cache data page and whose access frequency is lower than a second frequency threshold, using a third character string to represent a cache data page that is adjacent to the address of the sth cache data page and whose access frequency is higher than the first frequency threshold, and using a fourth character string to represent other cache data pages, and the address difference between the address of the sth cache data page and the address of the adjacent cache data page is greater than or equal to a preset value.

[0015] In an exemplary embodiment, after recording the first cache data page in the first level list, the method further includes: when the number of cache data pages in the first level list is greater than or equal to a first quantity threshold, moving the cache data page at the end of the first level list to the second level list; after recording the second cache data page at the first position in the second level list, the method further includes: when the number of cache data pages in the second level list is greater than or equal to a second quantity threshold, moving the cache data page at the end of the second level list to the third level list; after recording the second cache data page at the first position in the third level list, the method further includes: when the number of cache data pages in the third level list is greater than or equal to a third quantity threshold, moving the cache data page at the end of the third level list to the fourth level list.

[0016] According to another embodiment of the present application, a device for clearing cache data pages is provided, including: a determination module, used to determine, in a pre-created visible graph, a second cache data page that is visible to a first cache data page of the solid-state drive when the first cache data page is accessed, wherein the visible graph includes: the addresses of each cache data page of the solid-state drive and the number of accesses within a preset time period, and the visibility between each cache data page; an adjustment module, used to adjust the levels of the first cache data page and the second cache data page; and a clearing module, used to clear the third cache data page of the lowest level when there is a third cache data page of the solid-state drive.

[0017] According to another embodiment of the present application, a computer-readable storage medium is provided, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when run.

[0018] According to another embodiment of the present application, an electronic device is provided, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0019] Through the present application, when the first cache data page of the solid state drive is accessed, the second cache data page visible to the first cache data page is determined in a pre-created visible graph, wherein the visible graph includes: the address of each cache data page of the solid state drive and the number of accesses within a preset time length, and the visibility between each cache data page; the level of the first cache data page and the second cache data page is adjusted; when the third cache data page of the lowest level exists in the solid state drive, the third cache data page is cleared. Therefore, the problem that the cache solution in the related art cannot cover all scenarios with expected input / output, resulting in low versatility, can be solved, thereby achieving the effect of improving the versatility of the cache solution. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 It is a hardware structure block diagram of a terminal device or a computer device of a method for clearing cache data pages according to an embodiment of the present application;

[0021] Figure 2 is a flowchart of a method for clearing cache data pages according to an embodiment of the present application;

[0022] Figure 3 is a visible graph of access frequencies of four cache data pages according to an embodiment of the present invention;

[0023] Figure 4 is a node transmission diagram of a four-layer list according to an embodiment of the present invention;

[0024] Figure 5 is a batch adjustment flow chart according to an embodiment of the present invention;

[0025] Figure 6 is a flow chart of batch eviction according to an embodiment of the present invention;

[0026] Figure 7 is a whole flow chart according to an embodiment of the present invention;

[0027] Figure 8 It is a structural block diagram of a device for clearing cache data pages according to an embodiment of the present application. DETAILED DESCRIPTION

[0028] The embodiments of the present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0029] It should be noted that the terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence.

[0030] The definitions of abbreviations involved in the embodiments of the present invention are as follows:

[0031] 1. SSD (Solid State Disk): Solid-state drive. A solid-state drive is a data storage device based on non-volatile flash memory. Compared with traditional mechanical hard drives, it has faster read and write speeds, lower energy consumption, and higher shock and drop resistance.

[0032] 2. FTL (Flash Translation Layer): Flash Translation Layer. Flash Translation Layer is an important component in SSDs, responsible for converting logical addresses into physical addresses, managing bad blocks, load balancing and other functions to ensure the normal operation of SSDs.

[0033] 3. DRAM (Dynamic Random Access Memory): Dynamic random access memory is a semiconductor memory used to temporarily store data and programs. It is usually used for the main memory of a computer and has the characteristics of fast read and write speed and volatility.

[0034] 4. LRU (Least Recently Used): Least Recently Used. LRU is a cache algorithm that eliminates data that has not been accessed for the longest time based on the time when the data was most recently accessed, in order to improve cache hit rate and performance.

[0035] 5. LFU (Least Frequently Used): Least Frequently Used. LFU is a cache algorithm that eliminates the least frequently accessed data based on the frequency of data access, in order to retain frequently accessed data and improve cache hit rate and performance.

[0036] 6. Visible graph. A visible graph is a chart used to display specific data or information, usually in a graphical form so that users can quickly understand and analyze the data. In this embodiment, in order to construct and record scalar observations The visible graph associated with a univariate time series of , treating the series as points A two-dimensional set of As defined by the following formula, when All time points , when the convexity condition is met:

[0037]

[0038] This can be are considered as interconnected connected vertices of the visible graph.

[0039] 7. Four-level lists: including hit list, hot list, adjacent list, and eviction list. These lists help manage cached data pages of different visible graph types, where each node in the list corresponds to a cached data page. After that, the hot cached data is identified with its neighboring data and nearby (hot) data and saved in the SSD cache. Finally, by referring to the connectivity in the visible graph of the cache page, the cache frees up cache space in a round of clearing based on batch processing.

[0040] The technical background involved in the embodiments of the present invention is as follows:

[0041] Solid State Disk (SSD) based on NAND Flash Memory (NAND Flash) is gradually becoming the main storage device for embedded systems, personal computers and high-performance platforms due to its small size, high performance, random access and low energy consumption. In addition to the NAND flash array that permanently stores data, SSD devices usually have a faster but smaller amount of Dynamic Random Access Memory (DRAM) as a cache for input / output (I / O) operations.

[0042] In general, the DRAM cache of SSD is not only used to save the logical-physical address mapping data structure, but also to temporarily cache the content of overwrite or write requests. In this way, the content of the write request can be quickly confirmed after being cached. Therefore, it can greatly reduce the number of refresh operations on the underlying flash array, thereby improving the I / O performance and life of the SSD. If the cache space is full, the cache management scheme must take out some cached data and refresh them to the underlying flash array to make room for new data. Therefore, due to the limited cache capacity of SSD, cache management can significantly affect I / O performance. We know that locality of reference describes the ability to predict future accesses from past accesses and is the basis of cache management. There are two main types of locality: temporal and spatial. Temporal locality refers to repeated accesses to the same data, and spatial locality refers to adjacent accesses to nearby data within a short period of time.

[0043] The method for clearing cache data pages provided in the embodiments of the present application can be executed in a terminal device or a computer device or a similar computing device. Taking running on a terminal device or a computer device as an example, Figure 1 1 is a hardware structure block diagram of a terminal device or a computer device for a method of clearing cache data pages according to an embodiment of the present application. Figure 1 As shown, the terminal device or computer device may include one or more ( Figure 1Only one is shown in the figure) a processor 102 (the processor 102 may include but is not limited to a processing device such as a microprocessor MCU or a programmable logic device FPGA) and a memory 104 for storing data, wherein the above terminal device or computer device may also include a transmission device 106 and an input / output device 108 for communication functions. It can be understood by those skilled in the art that Figure 1 The structure shown is only for illustration and does not limit the structure of the above terminal device or computer device. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations are shown.

[0044] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the method for clearing cache data pages in the embodiment of the present application. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories can be connected to the terminal device or computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0045] The transmission device 106 is used to receive or send data via a network. The specific example of the above network may include a wireless network provided by a communication provider of a terminal device or a computer device. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0046] In this embodiment, a method for clearing cache data pages is provided. Figure 2 is a flow chart of a method for clearing cache data pages according to an embodiment of the present application, such as Figure 2 As shown, the process includes the following steps:

[0047] Step S202, when a first cache data page of the solid state drive is accessed, determining a second cache data page visible to the first cache data page in a pre-created visibility graph, wherein the visibility graph includes: addresses of each cache data page of the solid state drive and the number of accesses within a preset time length, and visibility between each cache data page;

[0048] Figure 3 It is a visible graph of the access frequency of four cache data pages according to an embodiment of the present invention. In this embodiment, the visible graph is created according to the address of each cache data page of the solid state drive and the number of accesses within a preset time length, wherein the horizontal axis of the visible graph is the address of each cache data page, the vertical axis of the visible graph is the number of accesses of each cache data page within the preset time length, and the visible graph also includes connecting lines, and the visible cache data pages are connected by the connecting lines.

[0049] The embodiment of the present invention uses the visible graph technology to unify the time and space positions of all cached data pages. Specifically, the logical page address sequence of the cached data page can be converted into a connection graph, in which each node represents a cached data page, and the value of the node is set to the number of accesses to the cached data page in the previous time window. If visibility exists, two nodes in the visible graph are connected by an edge, indicating that it does not highly intersect with any intermediate data.

[0050] like Figure 3 As shown, the horizontal axis of the visible graph is the address of each cache data page, and the vertical axis of the visible graph is the number of accesses to each cache data page within a preset time. The preset time can be determined according to actual conditions. If the access frequency is high, the preset time can be set shorter; if the access frequency is low, the preset time can be set longer. The visible cache data pages are connected by connecting lines. Figure 3 As shown in the figure, the access count sequence of four cache data pages is shown. Given a specific node (e.g. Figure 3 2), three types of connected (visible) nodes are defined: adjacent (nearest neighbor) with high access frequency (e.g., node 1), adjacent with low access frequency (e.g., node 3), and non-adjacent with high access frequency (e.g., node 4). In this embodiment, an adjacent node is defined as a node whose logical page number difference from a given node is no more than 4.

[0051] Specifically, when the following conditions are met between the i-th cache data page and the j-th cache data page of the solid state drive, it is determined that the i-th cache data page and the j-th cache data page are visible:

[0052]

[0053] in, is the address of the i-th cache data page, is the number of accesses to the i-th cache data page, is the address of the jth cache data page, is the number of accesses to the j-th cache data page, is the address of the kth cache data page, is the access count of the kth cache data page, the access address of the kth cache data page is between the address of the ith cache data page and the address of the jth cache data page, wherein i, j, and k are integers.

[0054] The above conditions have more stringent requirements on visibility, resulting in more accurate list classification, especially more accurate adjacent lists and hot lists.

[0055] Optionally, refreshing the visible graph of cached data pages helps to dynamically manage cache. To this end, the visible graph is refreshed by taking into account changes in visibility conditions in the graph. The number of connections of cached pages is reflected in the number of edges in the visible graph. The maximum number of connections for n nodes in the visible graph conforms to the following formula:

[0056]

[0057] Because the cache is constantly updated as pages are cleared, the number of cached pages in the original visible graph keeps decreasing.

[0058] When the number of cache pages (i.e. nodes used to build the visible graph) is reduced to When , it indicates that a considerable number of cache nodes have been evicted since the last visible graph generation, and a new round of reconstruction must be triggered. Reconstructing the visible graph more frequently can directly improve cache management, but this will bring more overhead, thus affecting I / O processing.

[0059] In an exemplary embodiment, a relationship matrix of each cache data page is created according to the visible graph, wherein the relationship matrix represents the relationship between each cache data page and other cache data pages through a character string, including: creating a relationship matrix of the s-th cache data page in the following manner, s is an integer: a first character string represents a cache data page that is not adjacent to the address of the s-th cache data page and has an access frequency higher than a first frequency threshold, a second character string represents a cache data page that is adjacent to the address of the s-th cache data page and has an access frequency lower than a second frequency threshold, a third character string represents a cache data page that is adjacent to the address of the s-th cache data page and has an access frequency higher than the first frequency threshold, and a fourth character string represents other cache data pages, and the address difference between the address of the s-th cache data page and the address of the adjacent cache data page is greater than or equal to a preset value.

[0060] In this embodiment, the visibility graph is stored in the form of a matrix. The matrix describes the connection between cache data pages. The binary element represents the corresponding visibility between two nodes in the visibility graph.

[0061]

[0062] For example, the first character string is 11, indicating a cache data page that is not adjacent to the address of the s-th cache data page and whose access frequency is higher than the first frequency threshold, the second character string is 10, indicating a cache data page that is adjacent to the address of the s-th cache data page and whose access frequency is lower than the second frequency threshold, the third character string is 01, indicating a cache data page that is adjacent to the address of the s-th cache data page and whose access frequency is higher than the first frequency threshold, and the fourth character string is 00, indicating that the address difference between the address of the s-th cache data page and the address of the adjacent cache data page is greater than or equal to a preset value.

[0063] The first frequency threshold and the second frequency threshold represent the number of times the cache data page is accessed within a certain period of time, and the first frequency threshold is greater than the second frequency threshold. In this embodiment, the adjacent node is defined as a node whose logical page number difference with the given node does not exceed 4. Therefore, the address difference is greater than or equal to the preset value. The preset value can be set to 4, or it can be adjusted according to actual conditions.

[0064] With the above relationship matrix, when a cached data page is accessed, the matrix can be checked to locate its visible nodes and adjust them accordingly. More specifically, we treat spatial locality and temporal locality as two-dimensional data and integrate them using a visibility graph. In other words, adjacent nodes can see each other in the visibility graph, reflecting the spatial locality of reference. The current node can see other nodes with high access frequency, solving the temporal locality of reference.

[0065] Specifically, when a first cache data page of the solid state drive is accessed, a second cache data page visible to the first cache data page is determined in a pre-created visibility map.

[0066] When the first cache data page is accessed, a second cache data page visible to the first cache data page may be determined through the visibility graph or the relationship matrix, such as Figure 3 If cache data page 1 is accessed, cache data page 2, cache data page 3, and cache data page 4 that are visible to the cache data page can be determined through the visibility graph.

[0067] Step S204, adjusting the levels of the first cache data page and the second cache data page;

[0068] Specifically, the first cache data page is recorded at the top of a first-level list, wherein the first-level list is used to record high-level cache data pages; according to the number of accesses to the second cache data page, the second cache data page is recorded in a list of a corresponding level.

[0069] In this embodiment, in order to manage the data pages in the cache, four levels of lists are maintained: an eviction list, an adjacent list, a hot list, and a hit list. The first level list is a hit list, which is used to record the highest level of cache data pages. When a cache data page is accessed, it is recorded at the top of the first level list, and the cache data pages visible to the accessed cache data page are adjusted accordingly according to their access times and recorded in the corresponding level list.

[0070] Specifically, when the access times of the second cache data page is greater than or equal to a preset threshold, the second cache data page is recorded at the first place in the second level list; otherwise, the second cache data page is recorded at the first place in the third level list; wherein, the level of the first level list is greater than that of the second level list, the level of the second level list is greater than that of the third level list, the third cache data page is recorded in the fourth level list, and the level of the third level list is greater than that of the fourth level list.

[0071] The above-mentioned preset threshold can be set according to the actual access frequency. If the access frequency is high, the above-mentioned preset threshold can be set higher; if the access frequency is low, the above-mentioned access threshold can be set lower. The above-mentioned second-level list is a hot list, and the above-mentioned third-level list is an adjacent list. The above-mentioned fourth-level list is an eviction list. If the number of accesses to the above-mentioned second cache data page is greater than or equal to the preset threshold, the above-mentioned second cache data page is recorded at the first place in the above-mentioned second-level list. If the number of accesses to the above-mentioned second cache data page is less than the preset threshold, the above-mentioned second cache data page is recorded at the first place in the above-mentioned third-level list. The above-mentioned third cache data page is the lowest-level cache data page, so it is recorded in the above-mentioned fourth-level list. Among them, the number of accesses to the cache data pages recorded in the first-level list, the second-level list, the third-level list and the fourth-level list gradually decrease.

[0072] For example, in the initialization phase (i.e., all lists are empty), all nodes of cached data pages are linked to the eviction list in a Least Recently Used (LRU) manner. Once a given cached data page is accessed again, a promotion batch adjustment is performed to move the nodes of the accessed cached data page and its visible (cached) data pages to a higher-level list. The cached data page will be evicted if and only if its corresponding node is at the end of the eviction list to make room for new data. Figure 4 is a node transmission diagram of a four-level list according to an embodiment of the present invention. When a cached data page is accessed, the corresponding node is moved to the head of the hit list, and the related nodes visible in the visible graph are adjusted. High-frequency visible access nodes are moved to the hot list, and other adjacent nodes are moved to the adjacent list. In addition, when the low-level list becomes empty, all nodes of a specific list are downgraded to the adjacent low-level list.

[0073] like Figure 4 As shown, cached data pages in the hot list can be recorded in the hit list because they are accessed; cached data pages in the adjacent list can be recorded in the hit list because they are accessed, or they can be recorded in the hot list according to high access frequency; cached data pages in the eviction list can be recorded in the hit list because they are accessed, or they can be recorded in the hot list according to high access frequency, or they can be recorded in the adjacent list because of low access frequency.

[0074] Optionally, after recording the first cache data page in the first level list, the method further includes: when the number of cache data pages in the first level list is greater than or equal to a first quantity threshold, moving the cache data page at the end of the first level list to the second level list; after recording the second cache data page at the first position in the second level list, the method further includes: when the number of cache data pages in the second level list is greater than or equal to a second quantity threshold, moving the cache data page at the end of the second level list to the third level list; after recording the second cache data page at the first position in the third level list, the method further includes: when the number of cache data pages in the third level list is greater than or equal to a third quantity threshold, moving the cache data page at the end of the third level list to the fourth level list.

[0075] The first quantity threshold is the maximum number of cache data pages that the first-level list can store. When the number of cache data pages in the first-level list is greater than the first quantity threshold, the cache data page at the end of the first-level list is moved to the second-level list; the second quantity threshold is the maximum number of cache data pages that the second-level list can store. When the number of cache data pages in the second-level list is greater than the second quantity threshold, the cache data page at the end of the second-level list is moved to the third-level list; the third quantity threshold is the maximum number of cache data pages that the third-level list can store. When the number of cache data pages in the third-level list is greater than the third quantity threshold, the cache data page at the end of the third-level list is moved to the fourth-level list.

[0076] Figure 5 is a batch adjustment flow chart according to an embodiment of the present invention, which shows that the nodes in the list are adjusted in batches when the corresponding data page is hit. It moves the hit node to the hit list of level 3, and moves the related visible nodes to the hot list and the adjacent list accordingly. Figure 5 As shown, the process includes the following steps:

[0077] S501, obtaining the list level of the cache data page;

[0078] S502, determine whether the number of accesses to the cached data page is greater than or equal to a preset threshold, if yes, jump to S503, if no, jump to S504;

[0079] S503, recording the cached data page in a hot list;

[0080] S504, recording the cached data page in an adjacent list;

[0081] Through the above operations, the cache data pages can be dynamically adjusted according to the changes in the access frequency of the cache data pages, thereby improving the cache hit rate.

[0082] Step S206: when there is a third cache data page of the lowest level in the solid state drive, clear the third cache data page.

[0083] The third cache data page is a cache data page of the lowest level and is recorded in the lowest level eviction list. When the solid state drive has the cache data page of the lowest level, the third cache data page is cleared.

[0084] Specifically, when there are idle channels in the solid-state hard disk and the number of the idle channels is N, determine the number M of the third cache data pages in the fourth-level list, where N and M are integers greater than 0; when M is less than or equal to N, clear M of the third cache data pages; when M is greater than N, clear the last N of the third cache data pages in the fourth-level list.

[0085] In this embodiment, the evicted data pages are flushed to the flash memory cells of the SSD channel to make cache space for new data. In order to maximize the refresh parallelism on the SSD channel, it supports clearing cached data pages in batches by referencing visibility connections. When selecting the tail node of the eviction list to be popped, it also selects related nodes in the eviction list that are visible from the tail node and have a smaller number of accesses. Then, all selected data pages are cleared. In addition, we limit the size of the batch refresh request to be less than the number of free channels of the SSD. Therefore, the popped pages can be refreshed into the SSD channels in parallel without exacerbating I / O congestion on the SSD channels.

[0086] Therefore, in order to avoid I / O congestion, this embodiment limits the number of batch evictions to be less than the number of idle SSD channels at the current point. When the number of third cache data pages in the fourth-level list is less than or equal to the number of idle channels, the number of third cache data pages in the fourth-level list is cleared based on the number of third cache data pages in the fourth-level list, that is, all third cache data pages in the fourth-level list can be cleared; when the number of third cache data pages in the fourth-level list is greater than the number of idle channels, the number of third cache data pages in the fourth-level list is cleared based on the number of idle channels.

[0087] Figure 6 is a batch expulsion flow chart according to an embodiment of the present invention, such as Figure 6 As shown, the process includes:

[0088] S601, obtaining a page address set of visible graph nodes;

[0089] S602, obtaining the original list level of the address and the address and level of the visible graph type;

[0090] S603, determine whether the Level is the lowest, if so, jump to S604;

[0091] S604, determine whether the number of cached data pages in the eviction list is less than the number of free channels, if yes, jump to S605, if no, jump to S606;

[0092] S605, clear all cached data pages in the eviction list;

[0093] S606, clearing the cache data page with the last idle channel number in the eviction list.

[0094] Through the above steps, the problem in the related art that the cache solution cannot cover all scenarios with expected input / output, resulting in low versatility, is solved, and the versatility of the cache solution is improved.

[0095] Figure 7 is a whole flow chart according to an embodiment of the present invention, such as Figure 7 As shown, the process includes the following steps:

[0096] S701, the visible graph unifies temporal locality and spatial locality;

[0097] S702, batch cache data page upgrade and downgrade adjustment;

[0098] S703, obtaining a page address set of visible graph nodes;

[0099] S704, adaptively refresh the visible graph of the cached data page;

[0100] S705, batch evict pages.

[0101] The embodiment of the present invention adopts the improved visible graph technology to unify the temporal locality and spatial locality of references in SSD cache management. Then, four levels of lists are used, which correspond to the four connection situations of nodes in the visible graph of cache data pages, so as to manage pages in different ways. At the same time, a batch-based cache data page promotion and demotion adjustment method is proposed. The hit pages, their adjacent pages and their (nearby) frequently accessed pages are batch-promoted to the high-level list, and the cold data pages are demoted to the low-level list until they are evicted from the cache. Then, the visible graph of adaptively refreshed cache data pages is introduced to provide real-time and effective information for cache management. The number of evicted data pages that are members of the visible graph of the previous round is observed, and if the number exceeds a predefined threshold, a new generation round is triggered. Finally, a batch-based recycling method is designed to obtain more cache space in the next round. It not only pops up the selected nodes in the eviction list, but also pops up some related data pages that are visible to the selected nodes and have a low access frequency. The cache management scheme proposed in the embodiment of the present invention can further improve the cache usage efficiency and reduce the I / O latency of SSD devices.

[0102] The basic idea of ​​the embodiment of the present invention is to use the improved visible graph technology to unify the time and spatial location of I / O access references to guide the cache management in the SSD. Specifically, the embodiment of the present invention proposes to adaptively generate a visible graph of cache data pages, and then support batch adjustment of adjacent or nearby (hot) cache data pages based on the connection conditions in the visible graph. In addition, the cached data pages are evicted in batches with reference to the connection conditions to maximize the internal refresh parallelism of the SSD device without exacerbating I / O congestion. In this way, compared with the most advanced cache management scheme for SSDs, the present invention can improve cache hit rates, reduce I / O latency, and extend the service life of SSDs.

[0103] The key points of the embodiments of the present invention are as follows:

[0104] The present invention proposes an SSD cache management scheme based on an improved visible graph. It unifies the temporal and spatial locations of references, and supports batch adjustment of adjacent or nearby hot cache data by referencing the connections in the visible graph of all cache data pages. In particular, it can guide cache management in a timely manner by reconstructing the visible graph of adaptively refreshed cache data pages according to the visible graph. In addition, by using the visible graph, cold data can be cleared from the cache in batches, thereby maximizing the internal refresh parallelism of the SSD device. Compared with the most advanced SSD cache management scheme, the cache hit rate can be significantly improved, and then I / O latency can be reduced and the SSD service life can be extended.

[0105] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of the present application, or the part that contributes to the prior art, can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, disk, CD), and includes a number of instructions for a terminal device (which can be a mobile phone, computer, server, or network device, etc.) to execute the methods described in each embodiment of the present application.

[0106] In this embodiment, a device for clearing cache data pages is also provided, which is used to implement the above embodiments and preferred implementations, and will not be repeated here. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0107] Figure 8is a structural block diagram of a device for clearing cache data pages according to an embodiment of the present application, such as Figure 8 As shown, the device includes a determination module 802, which is used to determine, in a pre-created visible graph, a second cache data page that is visible to the first cache data page of the solid-state drive when the first cache data page is accessed, wherein the visible graph includes: the addresses of each cache data page of the solid-state drive and the number of accesses within a preset time length, and the visibility between each cache data page; the adjustment module 804 adjusts the levels of the first cache data page and the second cache data page; the clearing module 806 clears the third cache data page when there is a third cache data page of the lowest level in the solid-state drive.

[0108] In an exemplary embodiment, the above-mentioned device is also used to record the first cache data page at the top of a first-level list, wherein the first-level list is used to record high-level cache data pages; according to the number of accesses to the second cache data page, the second cache data page is recorded in a list of a corresponding level.

[0109] In an exemplary embodiment, the above-mentioned device is also used to record the second cache data page at the first place in the second level list when the access number of the second cache data page is greater than or equal to a preset threshold, otherwise, record the second cache data page at the first place in the third level list; wherein the level of the first level list is greater than that of the second level list, the level of the second level list is greater than that of the third level list, the third cache data page is recorded in the fourth level list, and the level of the third level list is greater than that of the fourth level list.

[0110] In an exemplary embodiment, the above-mentioned device is also used to determine the number M of the third cache data pages in the fourth-level list when there are idle channels in the solid-state hard disk and the number of the idle channels is N, wherein N and M are integers greater than 0; when M is less than or equal to N, clear M of the third cache data pages; when M is greater than N, clear the last N of the third cache data pages in the fourth-level list.

[0111] In an exemplary embodiment, the above-mentioned device is also used to create the visible graph based on the addresses of each cache data page of the solid-state hard disk and the number of accesses within a preset time length, wherein the horizontal axis of the visible graph is the address of each cache data page, the vertical axis of the visible graph is the number of accesses of each cache data page within the preset time length, and the visible graph also includes connecting lines, and the visible cache data pages are connected by the connecting lines.

[0112] In an exemplary embodiment, the apparatus is further configured to determine that the i-th cache data page and the j-th cache data page are visible when the i-th cache data page and the j-th cache data page of the solid state drive meet the following conditions:

[0113]

[0114] in, is the address of the i-th cache data page, is the number of accesses to the i-th cache data page, is the address of the jth cache data page, is the number of accesses to the j-th cache data page, is the address of the kth cache data page, is the access count of the kth cache data page, the access address of the kth cache data page is between the address of the ith cache data page and the address of the jth cache data page, wherein i, j, and k are integers.

[0115] In an exemplary embodiment, the above-mentioned device is also used to create a relationship matrix of the sth cache data page in the following manner, where s is an integer: a first character string represents a cache data page that is not adjacent to the address of the sth cache data page and has an access frequency higher than a first frequency threshold, a second character string represents a cache data page that is adjacent to the address of the sth cache data page and has an access frequency lower than a second frequency threshold, a third character string represents a cache data page that is adjacent to the address of the sth cache data page and has an access frequency higher than the first frequency threshold, and a fourth character string represents other cache data pages, and the address difference between the address of the sth cache data page and the address of the adjacent cache data page is greater than or equal to a preset value.

[0116] In an exemplary embodiment, the above-mentioned device is also used to record the first cache data page in the first level list after the method further includes: when the number of cache data pages in the first level list is greater than or equal to a first quantity threshold, move the cache data page at the end of the first level list to the second level list; after recording the second cache data page at the first position of the second level list, the method further includes: when the number of cache data pages in the second level list is greater than or equal to a second quantity threshold, move the cache data page at the end of the second level list to the third level list; after recording the second cache data page at the first position of the third level list, the method further includes: when the number of cache data pages in the third level list is greater than or equal to a third quantity threshold, move the cache data page at the end of the third level list to the fourth level list.

[0117] It should be noted that the above modules can be implemented by software or hardware. For the latter, it can be implemented in the following ways, but not limited to: the above modules are all located in the same processor; or the above modules are located in different processors in any combination.

[0118] An embodiment of the present application further provides a computer-readable storage medium, in which a computer program is stored, wherein the computer program is configured to execute the steps of any of the above method embodiments when running.

[0119] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk or an optical disk.

[0120] An embodiment of the present application further provides an electronic device, including a memory and a processor, wherein a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0121] In an exemplary embodiment, the electronic device may further include a transmission device and an input / output device, wherein the transmission device is connected to the processor, and the input / output device is connected to the processor.

[0122] For specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary implementation modes, and this embodiment will not be described in detail herein.

[0123] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general computing device, they can be concentrated on a single computing device, or distributed on a network composed of multiple computing devices, they can be implemented by a program code executable by a computing device, so that they can be stored in a storage device and executed by the computing device, and in some cases, the steps shown or described can be executed in a different order from that herein, or they can be made into individual integrated circuit modules, or multiple modules or steps therein can be made into a single integrated circuit module for implementation. Thus, the present application is not limited to any specific combination of hardware and software.

[0124] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A method for clearing cache data pages, characterized in that: Applied to solid state drives, including: In the case where a first cache data page of the solid state drive is accessed, determining a second cache data page visible to the first cache data page in a pre-created visibility map, wherein the visibility map includes: addresses of each cache data page of the solid state drive and the number of accesses within a preset time length, and visibility between each cache data page; Adjusting the levels of the first cache data page and the second cache data page; In the case that the solid state drive has a third cache data page of the lowest level, the third cache data page is cleared.

2. The method according to claim 1, characterized in that The levels of the first cache data page and the second cache data page are adjusted, including: Recording the first cache data page at the top of a first level list, wherein the first level list is used to record high-level cache data pages; According to the number of accesses to the second cache data page, the second cache data page is recorded in a list of a corresponding level.

3. The method according to claim 2, characterized in that According to the number of accesses to the second cache data page, recording the second cache data page in a list of a corresponding level includes: If the number of accesses to the second cache data page is greater than or equal to a preset threshold, the second cache data page is recorded at the first position in the second level list; otherwise, the second cache data page is recorded at the first position in the third level list; Among them, the level of the first level list is greater than that of the second level list, the level of the second level list is greater than that of the third level list, the third cache data page is recorded in the fourth level list, and the level of the third level list is greater than that of the fourth level list.

4. The method according to claim 3, characterized in that In a case where the solid state drive has a third cache data page of the lowest level, clearing the third cache data page includes: In the case where there are idle channels in the solid state drive and the number of the idle channels is N, determining the number M of the third cache data pages in the fourth level list, where N and M are integers greater than 0; When M is less than or equal to N, clear M third cache data pages; When M is greater than N, the last N third cache data pages in the fourth level list are cleared.

5. The method according to claim 1, characterized in that Before determining in a pre-created visibility map a second cache data page visible to the first cache data page, the method further includes: The visible graph is created based on the addresses of each cache data page of the solid state drive and the number of accesses within a preset time period, wherein the horizontal axis of the visible graph is the address of each cache data page, the vertical axis of the visible graph is the number of accesses of each cache data page within the preset time period, and the visible graph also includes connecting lines, and the visible cache data pages are connected by the connecting lines.

6. The method according to claim 5, characterized in that The method further comprises: When the following conditions are met between the i-th cache data page and the j-th cache data page of the solid state drive, it is determined that the i-th cache data page and the j-th cache data page are visible: ； in, is the address of the i-th cache data page, is the number of accesses to the i-th cache data page, is the address of the jth cache data page, is the number of accesses to the j-th cache data page, is the address of the kth cache data page, is the access count of the kth cache data page, the access address of the kth cache data page is between the address of the ith cache data page and the address of the jth cache data page, wherein i, j, and k are integers.

7. The method according to claim 5, characterized in that The method further comprises: A relationship matrix of each cache data page is created according to the visible graph, wherein the relationship matrix represents the relationship between each cache data page and other cache data pages through a character string, including: Create the relationship matrix for the sth cache data page in the following way, where s is an integer: The first character string represents a cache data page that is not adjacent to the address of the sth cache data page and has an access frequency higher than a first frequency threshold, the second character string represents a cache data page that is adjacent to the address of the sth cache data page and has an access frequency lower than a second frequency threshold, the third character string represents a cache data page that is adjacent to the address of the sth cache data page and has an access frequency higher than the first frequency threshold, and the fourth character string represents other cache data pages, and the address difference between the address of the sth cache data page and the address of the adjacent cache data page is greater than or equal to a preset value.

8. The method according to claim 3, characterized in that After recording the first cache data page in the first level list, the method further includes: if the number of cache data pages in the first level list is greater than or equal to a first number threshold, moving the cache data page at the end of the first level list to the second level list; After recording the second cache data page at the first position in the second level list, the method further includes: if the number of cache data pages in the second level list is greater than or equal to a second number threshold, moving the cache data page at the end of the second level list to the third level list; After recording the second cache data page at the first position of the third-level class list, the method further includes: when the number of cache data pages in the third-level list is greater than or equal to a third quantity threshold, moving the cache data page at the end of the third-level list to the fourth-level list.

9. A device for clearing cache data pages, characterized in that: include: A determination module, configured to determine, in a pre-created visibility graph, a second cache data page visible to a first cache data page of the solid state drive when the first cache data page is accessed, wherein the visibility graph includes: addresses of each cache data page of the solid state drive and the number of accesses within a preset time period, and visibility between each cache data page; An adjustment module, configured to adjust the levels of the first cache data page and the second cache data page; The clearing module is used to clear the third cache data page when there is a third cache data page of the lowest level in the solid state drive.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 1 to 8 when executed by a processor.

11. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 1 to 8 are implemented.

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