Open-winding dual three-level ANPC inverter, fault-tolerant control method and neutral-point potential balance control strategy under fault-tolerant control

Abstract

The invention discloses an open-winding dual three-level ANPC inverter with fault-tolerant capability and a fault-tolerant control method capable of simplifying the modulation process of the two three-level inverters, an inverter topological structure comprises a first inverter and a second inverter, the first inverter and the second inverter are both active midpoint clamping three levels, and the first inverter and the second inverter are connected with each other. One side of the load is connected with a direct current side capacitor midpoint of the first inverter through three bidirectional thyristors, and the other side of the load is connected with a direct current side capacitor midpoint of the second inverter through three bidirectional thyristors. A carrier pulse width modulation method of superposing zero sequence components is adopted, and sector judgment and basic vector action time calculation are not needed, so that the modulation process is greatly simplified, and the calculation amount is reduced; and the adopted neutral-point potential voltage-sharing strategy can balance the capacitor voltage in an inverter fault-tolerant mode.

Description

Technical Field

[0001] The present invention belongs to the technical field of power electronics and electric drive, and in particular relates to an open-winding dual three-level ANPC inverter, a fault-tolerant control method and a midpoint potential balance control strategy under fault-tolerant control. Background Art

[0002] In new energy vehicles, photovoltaic power generation or high-power occasions, open-winding double-ended cascade inverters are widely used. There are two main types of open-winding dual inverter structures: independent DC bus structure and common DC bus structure. For the common DC bus structure, the two inverters are directly connected, and there is an inherent zero-sequence loop in the system, which generates zero-sequence circulating current, which will cause large power loss and torque pulsation of the load motor. The independent DC bus structure naturally suppresses the zero-sequence current because the two DC power supplies are independent of each other. However, for some extreme working occasions, the system may have fault conditions, and the fault-tolerant control technology of the open-winding dual inverter is extremely important. The modulation process of the traditional three-level in normal working occasions and fault-tolerant control generally adopts the SVPWM method, which requires reading the sector and calculating the vector action time. Compared with the carrier-based pulse width modulation method based on superimposed zero-sequence components, it has the disadvantages of large calculation amount and complex algorithm. In addition, when the three-level inverter is in normal operation, the midpoint voltage can be balanced by adjusting the action time of the two redundant small vectors. However, in the fault-tolerant mode, the lack of redundant small vectors is not conducive to the balance of the midpoint potential. Summary of the invention

[0003] The purpose of the present invention is to address the deficiencies of the above-mentioned technologies and to provide an open-winding dual three-level ANPC inverter with fault tolerance, a fault-tolerant control method that can simplify the modulation process of two three-level inverters, and a midpoint potential balance control strategy in the fault-tolerant control mode of the three-level inverter.

[0004] To achieve the above-mentioned object, the present invention provides an open-winding dual three-level ANPC inverter, wherein the inverter topology structure includes a first inverter and a second inverter, wherein the first inverter and the second inverter are both active midpoint embedded three-level inverters, wherein one side of the load is connected to the midpoint of the DC side capacitor of the first inverter through three bidirectional thyristors, and the other side of the load is connected to the midpoint of the DC side capacitor of the second inverter through three bidirectional thyristors.

[0005] Further, one side of the load is connected to the midpoint of the DC side capacitor of the first inverter through three bidirectional thyristors, and the other side of the load is connected to the midpoint of the DC side capacitor of the second inverter through three bidirectional thyristors. Specifically:

[0006] The bidirectional thyristor SSR1 is connected to the load side of the a1-phase bridge arm at the midpoint o1 of the DC-side capacitor of the first inverter. The bidirectional thyristor SSR2 is connected to the load side of the b1-phase bridge arm at the midpoint o1 of the DC-side capacitor of the first inverter. The bidirectional thyristor SSR3 is connected to the load side of the c1-phase bridge arm at the midpoint o1 of the DC-side capacitor of the first inverter. The bidirectional thyristor SSR6 is connected to the load side of the a2-phase bridge arm at the midpoint o2 of the DC-side capacitor of the second inverter. The bidirectional thyristor SSR5 is connected to the load side of the b2-phase bridge arm at the midpoint o2 of the DC-side capacitor of the second inverter. The bidirectional thyristor SSR4 is connected to the load side of the c2-phase bridge arm at the midpoint o2 of the DC-side capacitor of the second inverter.

[0007] A fault-tolerant control method for the open-winding dual three-level ANPC inverter described above is also provided. When any phase bridge arm of the first inverter or the second inverter fails, the corresponding bidirectional thyristor of the faulty phase bridge arm is turned on to connect the midpoint of the DC-side capacitor to the load, completing topological reconstruction to achieve fault-tolerant control. The fault-tolerant control method of the first inverter is as follows:

[0008] 1) Obtain the modulation ratio m of the first inverter during normal operation. When 0 < m < 0.5, execute step 2). When 0.5 < m < 1, reduce m to 0 - 0.5 and then execute step 2).

[0009] 2) Select the modulation wave of the faulty phase bridge arm and obtain the superimposed zero-sequence component of the modulation wave.

[0010] The zero-sequence component u of the modulation wave 0x = -u x where u x is the modulation wave of the faulty phase bridge arm, and x is a, b, or c.

[0011] 3) Superimpose the zero-sequence component of the modulation wave to obtain a new three-phase modulation wave.

[0012] Superimpose the zero-sequence component of the modulation wave onto the original three-phase modulation wave of the faulty inverter to obtain a new three-phase modulation wave, that is

[0013]

[0014] The fault-tolerant control method of the second inverter is the same as that of the first inverter.

[0015] Furthermore, when any phase bridge arm of the first inverter and the second inverter fails, turn on the corresponding bidirectional thyristor of the faulty phase bridge arm of the first inverter to connect the midpoint of the DC-side capacitor to the load, and at the same time turn on the corresponding bidirectional thyristor of the faulty phase bridge arm of the second inverter to connect the midpoint of the DC-side capacitor to the load, completing topological reconstruction to achieve fault-tolerant control. The fault-tolerant control method of the first inverter is as follows:

[0016] 1) Obtain the modulation ratio m when the first inverter is operating normally. When 0 < m < 0.5, execute step 2); when 0.5 < m < 1, reduce m to 0 - 0.5 and then execute step 2);

[0017] 2) Select the modulation wave of the faulty phase leg and obtain the superimposed zero - sequence component of the modulation wave;

[0018] The zero - sequence component of the modulation wave u 0x =-u x ,u x is the modulation wave of the faulty phase leg, and x is a, b, or c;

[0019] 3) Superimpose the zero - sequence component of the modulation wave to obtain a new three - phase modulation wave;

[0020] Superimpose the zero - sequence component of the modulation wave onto the original three - phase modulation wave of the faulty inverter to obtain a new three - phase modulation wave, that is

[0021]

[0022] Similarly, the fault - tolerant control method of the second inverter is the same as that of the first inverter, and the fault - tolerant control of the second inverter and the first inverter is carried out simultaneously.

[0023] A neutral - point potential balance control strategy under the above - mentioned fault - tolerant control is also provided. The neutral - point potential balance control strategy under the fault - tolerant control of the first inverter is specifically as follows:

[0024] When x is a, under fault - tolerant control, the phase of the a - phase leg will be clamped to the 0 state; under ideal conditions, the charge change Q0 caused by the three - phase current within a carrier period is:

[0025]

[0026] In the formula, Q0 is the charge caused by the three - phase current within a carrier period, i a 、i b 、i c are the three - phase currents after fault - tolerance of the first inverter, T s is the time of a carrier period, u a1 '、u b1 '、u c1 ' are the three - phase modulation waves after amplitude - limiting the first inverter after introducing the charge;

[0027] When the voltage - equalizing strategy is adopted, if the reference voltage is in the first, second, fourth, and fifth sectors of the first inverter, then translate the modulation wave of the c - phase; let u b1 ' = u b ', formula (2) can be obtained:

[0028]

[0029] Among them, sign() is the rounding function;

[0030] The amount of charge Q caused by the DC side capacitance deviation c It is expressed by formula (4):

[0031]

[0032] Where, C is the DC side capacitance, U dc1 is the capacitor voltage on the DC side, U d c2 is the capacitor voltage on the DC side;

[0033] Let Q C =Q0, that is, formula (3) can be obtained as formula (5):

[0034]

[0035] The maximum translation value △u of the given limited modulation wave is:

[0036] △u=|U dc1 -U dc2 |·0.02 (6)

[0037] So when the c-phase shift modulation wave u c1 'When, u c1 The range of the initial translation that needs to satisfy equation (7) is:

[0038] [u c '-△u,u c '+△u] (7)

[0039] If the reference voltage is in the third and sixth sectors of the first inverter, the modulation wave of phase b is shifted, and u c1 '=u c ', i.e. u b1 'Calculation and u c1 ' is calculated the same as above. At the same time, when the b-phase shift modulation wave u b1 'When, u b1 'The range of the initial translation must satisfy equation (7);

[0040] When x is b or c, the midpoint potential balance control strategy of the first inverter under fault-tolerant control is the same as the midpoint potential balance control strategy of phase a under fault-tolerant control, which will not be described in detail here;

[0041] Furthermore, the midpoint potential balance control strategy under the fault-tolerant control of the second inverter is the same as the midpoint potential balance control strategy under the fault-tolerant control of the first inverter.

[0042] Furthermore, the modulation wave shifted in different sectors under the a-phase fault-tolerant control needs to meet the range of Table 1:

[0043] Table 1

[0044] Sector Modulation wave selection Minimum translation Maximum translation value 1 <![CDATA[u c1 ']]> -1 <![CDATA[u b1 ']]> 2 <![CDATA[u c1 ']]> <![CDATA[u b1 '-1]]> 0 3 <![CDATA[u b1 ']]> <![CDATA[u c1 ']]> 1 4 <![CDATA[u c1 ']]> <![CDATA[u b1 ']]> 1 5 <![CDATA[u c1 ']]> 0 <![CDATA[u b1 '+1]]> 6 <![CDATA[u b1 ']]> -1 <![CDATA[u c1 ']]>

[0045] The modulation wave shifted in different sectors under the fault-tolerant control of phase b must meet the range of Table 2:

[0046] Table 2

[0047] Sector Modulation wave selection Minimum translation Maximum translation value 1 <![CDATA[u a1 ']]> 0 <![CDATA[u c1 '+1]]> 2 <![CDATA[u c1 ']]> -1 <![CDATA[u a1 ']]> 3 <![CDATA[u a1 ']]> -1 <![CDATA[u c1 ']]> 4 <![CDATA[u a1 ']]> <![CDATA[u c1 '-1]]> 0 5 <![CDATA[u c1 ']]> <![CDATA[u a1 ']]> 1 6 <![CDATA[u a1 ']]> <![CDATA[u c1 ']]> 1

[0048] The modulation wave shifted in different sectors under the c-phase fault-tolerant control must meet the range of Table 3:

[0049] Table 3

[0050] Sector Modulation wave selection Minimum translation Maximum translation value 1 <![CDATA[u a1 ']]> <![CDATA[u b1 ']]> 1 2 <![CDATA[u b1 ']]> <![CDATA[u a1 ']]> 1 3 <![CDATA[u b1 ']]> 0 <![CDATA[u a1 '+1]]> 4 <![CDATA[u a1 ']]> -1 <![CDATA[u b1 ']]> 5 <![CDATA[u b1 ']]> -1 <![CDATA[u a1 ']]> 6 <![CDATA[u b1 ']]> <![CDATA[u a1 '-1]]> 0

[0051] Furthermore, the midpoint potential balance control strategy under the fault-tolerant control of the second inverter is the same as the midpoint potential balance control strategy under the fault-tolerant control of the first inverter, and the midpoint potential balance control strategy under the fault-tolerant control of the second inverter is carried out simultaneously with the midpoint potential balance control strategy under the fault-tolerant control of the first inverter.

[0052] Compared with the prior art, the beneficial effects of the present invention are as follows: the present invention adopts a carrier pulse width modulation method with a superimposed zero-sequence component, which does not require sector judgment and calculation of the basic vector action time, greatly simplifies the modulation process and reduces the amount of calculation; and the midpoint potential equalization strategy adopted can balance the capacitor voltage in the inverter fault tolerance mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] Figure 1 This is a topological structure diagram of an open-winding dual three-level ANPC inverter of the present invention;

[0054] Figure 2 It is a schematic diagram of the fault-tolerant structure of the open-winding dual inverter of the present invention under the condition of a1 bridge arm fault;

[0055] Figure 3 It is a schematic diagram of the spatial voltage vector of the three-level inverter under the fault tolerance of the a1 phase bridge arm;

[0056] Figure 4 It is a schematic diagram of the space voltage vector of the open-winding dual inverter under the fault tolerance of the a1 phase bridge arm;

[0057] Figure 5 is the modulation waveform injected by the zero-sequence component;

[0058] Figure 6This is the simulation diagram of the fault-tolerant control of phase a1 when m=0.4;

[0059] Figure 7 It is the simulation diagram of fault-tolerant control of phase a1 when m=0.8 is reduced to m=0.4;

[0060] Figure 8 It is the open-circuit fault-tolerant topology of phase a of the three-level ANPC inverter;

[0061] Fig. 9 is a diagram of the effect of the moving modulated wave on the basic vector;

[0062] Fig.10 YesS a4 Simulation diagram of fault-tolerant control and voltage-sharing strategy (m>0.5, derating operation) under open circuit, m=0.8, PF=0.8. DETAILED DESCRIPTION

[0063] like Figure 1 The open-winding dual three-level ANPC inverter with fault tolerance is shown, and the inverter topology includes a first inverter and a second inverter. The first inverter and the second inverter are both active midpoint embedded three-level. One side of the load is connected to the midpoint of the DC side capacitor of the first inverter through three bidirectional thyristors, and the other side of the load is connected to the midpoint of the DC side capacitor of the second inverter through three bidirectional thyristors. That is, the bidirectional thyristor SSR1 connects the midpoint o1 of the DC side capacitor of the first inverter and the load side of the a1 phase bridge arm, the bidirectional thyristor SSR2 connects the midpoint o1 of the DC side capacitor of the first inverter and the load side of the b1 phase bridge arm, and the bidirectional thyristor SSR3 connects the midpoint o1 of the DC side capacitor of the first inverter and the load side of the c1 phase bridge arm; the bidirectional thyristor SSR6 connects the midpoint o2 of the DC side capacitor of the second inverter and the load side of the a2 phase bridge arm, the bidirectional thyristor SSR5 connects the midpoint o2 of the DC side capacitor of the second inverter and the load side of the b2 phase bridge arm, and the bidirectional thyristor SSR4 connects the midpoint o2 of the DC side capacitor of the second inverter and the load side of the c2 phase bridge arm. When the first inverter and the inverter are working normally, the six bidirectional thyristors are in the disconnected state; when an open circuit fault occurs in a phase bridge arm of the first inverter and / or the second inverter, the corresponding bidirectional thyristor is turned on so that the load of this phase is connected to the midpoint of the DC side capacitor to achieve fault-tolerant control. At this time, the bridge arm of this phase is embedded in the 0 level, and the three-level inverter is in a two-phase controllable state.

[0064] For different single-bridge-arm open-circuit faults, different fault-tolerant methods are corresponding, where the single-bridge-arm open circuit includes the single-bridge-arm open-circuit fault of a single inverter and the single-bridge-arm open-circuit fault of two inverters. The open circuit of a single inverter includes six types of faults: the a1-bridge-arm fault, b1-bridge-arm fault, c1-bridge-arm fault in the first inverter, and the a2-bridge-arm fault, b2-bridge-arm fault, c2-bridge-arm fault in the second inverter; the single-bridge-arm open-circuit faults of two inverters include nine types: a1a2-bridge-arm fault, b1b2-bridge-arm fault, c1c2-bridge-arm fault, a1b2-bridge-arm fault, a1c2-bridge-arm fault, b1a2-bridge-arm fault, b1c2-bridge-arm fault, c1a2-bridge-arm fault, c1b2-bridge-arm fault.

[0065] For the above six single-bridge-arm faults, when a fault occurs in the a1 phase, the a1 bridge arm is open-circuited. By turning on SSR1 to connect the left end of the a-phase load to the midpoint of the DC-side capacitor of the first inverter, at this time, the a1 bridge arm is clamped at the 0-level state. The first inverter has two remaining controllable bridge arms. The first inverter can choose whether to adjust the modulation ratio for fault-tolerant control under different modulation ratios.

[0066] That is, when any phase bridge arm of the first inverter or the second inverter fails, turn on the corresponding bidirectional thyristor of the faulty phase bridge arm to connect the midpoint of the DC-side capacitor to the load, complete the topology reconstruction to achieve fault-tolerant control; the fault-tolerant control method of the first inverter is specifically as follows:

[0067] 1) Obtain the modulation ratio m of the first inverter during normal operation. When 0 < m < 0.5, execute step 2); when 0.5 < m < 1, reduce m to 0 - 0.5 and then execute step 2);

[0068] 2) Select the modulation wave of the faulty phase bridge arm and obtain the superimposed modulation wave zero-sequence component;

[0069] The modulation wave zero-sequence component u 0x =-u x ,u x is the modulation wave of the faulty phase bridge arm, and x is a, b, or c;

[0070] 3) Superimpose the modulation wave zero-sequence component to obtain a new three-phase modulation wave;

[0071] Superimpose the modulation wave zero-sequence component on the original three-phase modulation wave of the faulty inverter to obtain a new three-phase modulation wave, that is

[0072]

[0073] The fault-tolerant control method of the second inverter is the same as that of the first inverter.

[0074] For the nine types of two-leg faults, when the a1c2 leg fails, the a1c2-phase leg is open. By turning on SSR1 to connect the left end of the a-phase load to the midpoint of the DC-link capacitor of the first inverter, and turning on SSR4 to connect the right end of the c-phase load to the midpoint of the DC-link capacitor of the second inverter, the a1c2-phase leg is clamped at the 0-level state at this time. Both the first inverter and the second inverter have two controllable legs remaining. The two inverters can choose whether to adjust the modulation ratio for fault-tolerant control under different modulation ratios.

[0075] That is, when any phase leg of the first inverter and the second inverter fails, turn on the corresponding bidirectional thyristor of the faulty phase leg of the first inverter to connect the midpoint of the DC-link capacitor to the load, and at the same time turn on the corresponding bidirectional thyristor of the faulty phase leg of the second inverter to connect the midpoint of the DC-link capacitor to the load, and complete the topology reconfiguration to achieve fault-tolerant control; the specific method of fault-tolerant control of the first inverter is as follows:

[0076] 1) Obtain the modulation ratio m when the first inverter is operating normally. When 0 < m < 0.5, execute step 2); when 0.5 < m < 1, reduce m to 0 - 0.5 and then execute step 2);

[0077] 2) Select the modulation wave of the faulty phase leg and obtain the superimposed zero-sequence component of the modulation wave;

[0078] The zero-sequence component u of the modulation wave 0x =-u x where u x is the modulation wave of the faulty phase leg, and x is a, b, or c;

[0079] 3) Superimpose the zero-sequence component of the modulation wave to obtain a new three-phase modulation wave;

[0080] Superimpose the zero-sequence component of the modulation wave onto the original three-phase modulation wave of the faulty inverter to obtain a new three-phase modulation wave, that is

[0081]

[0082] Similarly, the fault-tolerant control method of the second inverter is the same as that of the first inverter, and the fault-tolerant control of the second inverter is carried out simultaneously with that of the first inverter.

[0083] When the system operates in the fault-tolerant control mode, the present invention also proposes a neutral-point potential balance control strategy under the fault-tolerant control mode of a three-level inverter; that is, the neutral-point potential balance control strategy under the fault-tolerant control of the first inverter is specifically as follows:

[0084] In general carrier modulation, the duty ratio of the 0 level of each phase is related to the value of its modulation wave. It can be obtained that the time for the a-phase to output the 0 level within a carrier period is:

[0085] Ta0 =d a0 ·T s =(1-|u a '|)·T s (8)

[0086] Where, T a0 is the time that phase a outputs 0 level in one carrier cycle, d a0 is the duty cycle of the a-phase output 0 level within one carrier cycle, T s is the time of one carrier cycle.

[0087] When x is a, under fault-tolerant control, the phase of the a-phase bridge arm will be clamped to the 0 state; under ideal conditions, the charge change Q0 caused by the three-phase current in one carrier cycle is:

[0088]

[0089] Where Q0 is the charge caused by the three-phase current in one carrier cycle, i a 、i b 、i c is the three-phase current after fault tolerance of the first inverter, T s is the time of one carrier cycle, u a1 '、u b1 '、u c1 ' is a three-phase modulation wave for limiting the amplitude of the first inverter after the charge is introduced;

[0090] When the voltage balancing strategy is adopted, if the reference voltage is in the first, second, fourth and fifth sectors of the first inverter, the modulation wave of phase c is shifted; let u b1 '=u b ', formula (2) can be obtained:

[0091]

[0092] Among them, sign() is the rounding function; when u c '>0, sign(u c ')=1; when u c '<0, sign(u c ')=-1; when u c '=0,sign(u c ')=0, then equation (5) does not exist, let u c1 '=u c '; and the modulated wave does not change its sign during its movement, so sign(u c ')=sign(u c1 ').

[0093] The amount of charge Q caused by the DC side capacitance deviation c It is expressed by formula (4):

[0094]

[0095] Where, C is the DC side capacitance, U dc1 is the capacitor voltage on the DC side, U d c2 is the capacitor voltage on the DC side;

[0096] Let Q C =Q0, that is, formula (3) can be obtained as formula (5):

[0097]

[0098] The maximum translation value △u of the given limited modulation wave is:

[0099] △u=|U dc1 -U dc2 |·0.02 (6)

[0100] So when the c-phase shift modulation wave u c1 'When, u c1 The range of the initial translation that needs to satisfy equation (7) is:

[0101]

[0102] If the reference voltage is in the third and sixth sectors of the first inverter, the modulation wave of phase b is shifted, and u c1 '=u c ', i.e. u b1 'Calculation and u c1 ' is calculated the same as above. At the same time, when the b-phase shift modulation wave u b1 'When, u b1 'The range of the initial translation must satisfy equation (7);

[0103] When x is b or c, the midpoint potential balance control strategy of the first inverter under fault-tolerant control is the same as the midpoint potential balance control strategy of phase a under fault-tolerant control, which will not be repeated here.

[0104] In addition, the range of modulation wave translation will also be affected by the sector. When in different sectors, the value of the modulation wave will be limited, and at this time, the modulation wave needs to be limited again.

[0105] The details are as follows:

[0106] The modulation wave shifted in different sectors under phase a fault tolerant control must meet the range of Table 1:

[0107] Table 1

[0108] Sector Modulation wave selection Minimum translation Maximum translation value 1 <![CDATA[u c1 ']]> -1 <![CDATA[u b1 ']]> 2 <![CDATA[u c1 ']]> <![CDATA[u b1 '-1]]> 0 3 <![CDATA[u b1 ']]> <![CDATA[u c1 ']]> 1 4 <![CDATA[u c1 ']]> <![CDATA[u b1 ']]> 1 5 <![CDATA[u c1 ']]> 0 <![CDATA[u b1 '+1]]> 6 <![CDATA[u b1 ']]> -1 <![CDATA[u c1 ']]>

[0109] The modulation wave shifted in different sectors under the fault-tolerant control of phase b must meet the range of Table 2:

[0110] Table 2

[0111]

[0112]

[0113] The modulation wave shifted in different sectors under the c-phase fault-tolerant control must meet the range of Table 3:

[0114] Table 3

[0115] Sector Modulation wave selection Minimum translation Maximum translation value 1 <![CDATA[u a1 ']]> <![CDATA[u b1 ']]> 1 2 <![CDATA[u b1 ']]> <![CDATA[u a1 ']]> 1 3 <![CDATA[u b1 ']]> 0 <![CDATA[u a1 '+1]]> 4 <![CDATA[u a1 ']]> -1 <![CDATA[u b1 ']]> 5 <![CDATA[u b1 ']]> -1 <![CDATA[u a1 ']]> 6 <![CDATA[u b1 ']]> <![CDATA[u a1 '-1]]> 0

[0116] The midpoint potential balance control strategy under the fault-tolerant control of the second inverter is the same as the midpoint potential balance control strategy under the fault-tolerant control of the first inverter. When the first inverter and the second inverter are simultaneously under fault-tolerant control, the midpoint potential balance control strategy under the fault-tolerant control of the second inverter is performed simultaneously with the midpoint potential balance control strategy under the fault-tolerant control of the first inverter.

[0117] The technical solution of the present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

[0118] like Figure 2 The figure shows the fault-tolerant control schematic diagram after the system topology is reconstructed when an open-circuit fault occurs in the a1 phase bridge arm. When the a1 phase bridge arm is open-circuited, the a1 phase bridge arm is isolated, and SSR1 is turned on to connect the left side of the a phase load to the midpoint of the DC side capacitor of the first inverter.

[0119] like Figure 3 The figure shows the schematic diagram of the voltage vector of the fault tolerance space of the first inverter in the case of a1 phase bridge arm fault. At this time, the voltage vector is reduced from 27 vectors in normal operation to 9 vectors. In the traditional three-level fault tolerance control method, a zero vector and six small vectors in the figure are often used to synthesize the reference voltage. The carrier PWM method based on zero-sequence component injection in the present invention does not require sector judgment and vector action time calculation. The calculation amount is reduced and the modulation process is greatly simplified.

[0120] like Figure 4 The fault-tolerant spatial voltage vector diagram of the open-winding dual inverter under the a1 phase bridge arm fault. The radius of the maximum modulation space of the spatial voltage vector diagram is The DC voltage utilization is 75% under normal operating conditions.

[0121] like Figure 5The modulation waveform of the zero-sequence component injected when phase a is faulty is shown. At this time, the modulation wave of the original three-phase modulation wave is 0.5. After the zero-sequence component is superimposed, the modulation wave of phase a becomes 0.

[0122] The open-winding dual inverter fault-tolerant control strategy of the present invention is verified in MATLAB / Simulink.

[0123] like Figure 6 As shown in the simulation diagram from normal operation state to fault state and then to fault-tolerant control state when m=0.4 when the a1 phase bridge arm fails, the simulation duration is set to 0.15s, of which 0-0.05s is the normal operation mode, 0.05-0.1s is the fault mode, and 0.1-0.15s is the fault-tolerant control mode. In the normal operation mode, the three phases operate symmetrically. It can be seen from the figure that in the a1 fault mode, only phases b and c are left in the system, and the current of phase a is 0. When m=0.4, when m<0.5, there is no derating operation, and fault-tolerant control can restore the system to normal operation.

[0124] like Figure 7 As shown in the simulation diagram, when m=0.8 under the fault of phase a1 bridge arm and m is reduced to 0.4 during fault-tolerant control, the system goes from normal operation to fault state and then to fault-tolerant control state. At this time, the system can achieve three-phase symmetrical operation, and as analyzed in the previous article, the voltage utilization rate is 3 / 4 of that in normal operation, and the current amplitude is reduced from 20 to 15, which is also reduced to 75% of normal operation.

[0125] like Figure 8 The figure shows the fault-tolerant control schematic diagram after the system topology is reconstructed when the system works in the single inverter power supply mode and an open circuit fault occurs in the a-phase bridge arm. When the a-phase bridge arm is open, the turned-on thyristor connects the left side of the a-phase load to the midpoint of the DC side capacitor of the first inverter.

[0126] like Fig. 9 The figure shows the influence of the moving modulation wave on the basic vector. dc1 -U dc2 >0, in order to balance the midpoint potential, it is necessary to reduce U dc1 Or increase U dc2 , when a small vector needs to adjust the action time, and the midpoint current i m >0, its effect on the midpoint voltage is to increase U dc1 And reduce U dc2 , so at this time it is necessary to reduce the action time of the small vector; when i m <0, the action time of the small vector needs to be increased. dc1 -U dc2 <0, in order to balance the midpoint potential, it is necessary to increase U dc1 Or reduce U dc2, when the midpoint current i generated by the small vector that needs to adjust the action time m >0, it is necessary to increase the action time of the small vector; when i m <0, the action time of the small vector needs to be reduced.

[0127] Table 1 is the vector sequence of each sector after phase a fault tolerance

[0128] Sector Vector Sequence 1 OOO-OON-ONN-ONN-OON-OOO 2 OPO-OOO-OON-OON-OOO-OPO 3 OPP-OPO-OOO-OOO-OPO-OPP 4 OPP-OOP-OOO-OOO-OOP-OPP 5 OOP-OOO-ONO-ONO-OOO-OOP 6 OOO-ONO-ONN-ONN-ONO-OOO

[0129] In a small sector, the reference voltage is synthesized by a zero vector and two small vectors. Taking sector 2 as an example, Figure 9 It can be seen that when the b-phase modulation wave is moved upward, the action time of the small vector OPO can be increased, and the action time of the zero vector OOO can be reduced; when the C-phase modulation wave is moved upward, the action time of the small vector OON can be reduced, and the action time of the zero vector OOO can be increased. In addition to changing the action time of the small vector to be adjusted, the moving modulation wave will also affect the action time of another vector. The midpoint current generated by the zero vector is 0, which has no effect on the midpoint voltage. Based on this principle, the small vector whose action time needs to be adjusted is selected. It can be obtained that the small vectors selected in the six sectors are: OON, OON, OPO, OOP, ONO and ONO.

[0130] from Fig. 9 It can be seen that moving the modulation wave upward in the second sector will reduce the OON action time, while moving the modulation wave downward will increase the OON action time. The same can be seen in other sectors: moving the modulation wave upward in the first and sixth sectors will reduce the small vector action time, while moving the modulation wave downward will increase the small vector action time; moving the modulation wave upward in the third, fourth and fifth sectors will increase the small vector action time, while moving the modulation wave downward will reduce the small vector action time.

[0131] In addition, the figure shows the movable range of the modulation wave in the second sector. When the reference voltage is in the second sector, the equilibrium midpoint potential needs to translate the c-phase modulation wave. In order to ensure that the original vector order is not changed, it cannot be greater than 0 when moving upward and cannot be less than u when moving downward. b1 '-1. So its translation range is [u b1 '-1,0].

[0132] Fig.10 Medium S a4 Open circuit, m = 0.8, PF = 0.8 under fault tolerance control and voltage balancing strategy (m> 0.5, derating operation) simulation diagram, it can be seen that in S a4 or S a1 and S a3When a fault occurs and the fault-tolerant strategy is not used, the output state of phase a voltage is abnormal, and the three-phase current amplitude and phase are distorted, causing the midpoint voltage to be unbalanced. When the fault-tolerant strategy is adopted, but the midpoint potential balance strategy is not adopted, the current can reach a three-phase balanced state, but the capacitor voltage remains in an unbalanced state after the fault state diverges and cannot converge. When the midpoint potential balance strategy is adopted in the fault-tolerant control state, the capacitor voltage gradually converges.

Claims

1. An open-winding dual three-level ANPC inverter, characterized in that: The inverter topology includes a first inverter and a second inverter. Both the first inverter and the second inverter are active neutral point clamped three-level inverters. One side of the load is connected to the midpoint of the DC side capacitor of the first inverter through three bidirectional thyristors, and the other side of the load is connected to the midpoint of the DC side capacitor of the second inverter through three bidirectional thyristors.

2. The open-winding dual three-level ANPC inverter according to claim 1, characterized in that: The connection of one side of the load to the midpoint of the DC side capacitor of the first inverter through three bidirectional thyristors and the connection of the other side of the load to the midpoint of the DC side capacitor of the second inverter through three bidirectional thyristors are specifically as follows: The bidirectional thyristor SSR1 connects the midpoint o1 of the DC side capacitor of the first inverter to the load side of the a1-phase bridge arm. The bidirectional thyristor SSR2 connects the midpoint o1 of the DC side capacitor of the first inverter to the load side of the b1-phase bridge arm. The bidirectional thyristor SSR3 connects the midpoint o1 of the DC side capacitor of the first inverter to the load side of the c1-phase bridge arm. The bidirectional thyristor SSR6 connects the midpoint o2 of the DC side capacitor of the second inverter to the load side of the a2-phase bridge arm. The bidirectional thyristor SSR5 connects the midpoint o2 of the DC side capacitor of the second inverter to the load side of the b2-phase bridge arm. The bidirectional thyristor SSR4 connects the midpoint o2 of the DC side capacitor of the second inverter to the load side of the c2-phase bridge arm.

3. A fault-tolerant control method for an open-winding dual three-level ANPC inverter as described in claim 1. When any phase bridge arm of the first inverter or the second inverter fails, the corresponding bidirectional thyristor of the faulty phase bridge arm is turned on to connect the midpoint of the DC side capacitor to the load, completing topology reconfiguration to achieve fault-tolerant control. It is characterized in that: The fault-tolerant control method of the first inverter is specifically as follows: 1) Obtain the modulation ratio m of the first inverter during normal operation. When 0 < m < 0.5, execute step 2); when 0.5 < m < 1, reduce m to 0 - 0.5 and then execute step 2); 2) Select the modulation wave of the faulty phase bridge arm and obtain the superimposed zero-sequence component of the modulation wave; Modulation wave zero sequence component u 0x =-u x ,u x is the modulation wave of the fault phase bridge arm, x is a, b or c; 3) Superimpose the zero-sequence component of the modulation wave to obtain a new three-phase modulation wave; Superimpose the zero-sequence component of the modulation wave onto the original three-phase modulation wave of the faulty inverter to obtain a new three-phase modulation wave, that is The fault-tolerant control method of the second inverter is the same as that of the first inverter.

4. According to the fault-tolerant control method of the open-winding dual three-level ANPC inverter described in claim 3, when any phase bridge arm of the first inverter and the second inverter fails, turn on the corresponding bidirectional thyristor of the faulty phase bridge arm of the first inverter to connect the midpoint of the DC side capacitor to the load, and at the same time turn on the corresponding bidirectional thyristor of the faulty phase bridge arm of the second inverter to connect the midpoint of the DC side capacitor to the load, completing topology reconfiguration to achieve fault-tolerant control. It is characterized in that: The fault-tolerant control method of the first inverter is specifically as follows: 1) Obtain the modulation ratio m of the first inverter during normal operation. When 0 < m < 0.5, execute step 2); when 0.5 < m < 1, reduce m to 0 - 0.5 and then execute step 2); 2) Select the modulation wave of the faulty phase bridge arm and obtain the superimposed zero-sequence component of the modulation wave; Modulation wave zero sequence component u 0x =-u x ,u x is the modulation wave of the fault phase bridge arm, x is a, b or c; 3) Superimpose the zero-sequence component of the modulation wave to obtain a new three-phase modulation wave; The zero-sequence component of the modulation wave is superimposed on the original three-phase modulation wave of the faulty inverter to obtain a new three-phase modulation wave, that is, Similarly, the fault-tolerant control method of the second inverter is the same as the fault-tolerant control method of the first inverter, and the fault-tolerant control of the second inverter is performed simultaneously with the fault-tolerant control of the first inverter.

5. A midpoint potential balance control strategy under fault-tolerant control as claimed in claim 3, characterized in that: The midpoint potential balance control strategy under the fault-tolerant control of the first inverter is specifically as follows: When x is a, under fault-tolerant control, the phase of the a-phase bridge arm will be clamped to the 0 state; under ideal conditions, the charge change Q0 caused by the three-phase current in one carrier cycle is: Where Q0 is the charge caused by the three-phase current in one carrier cycle, i a 、i b 、i c is the three-phase current after fault tolerance of the first inverter, T s is the time of one carrier cycle, u a1 '、u b1 '、u c1 ' is a three-phase modulation wave for limiting the amplitude of the first inverter after the charge is introduced; When the voltage balancing strategy is adopted, if the reference voltage is in the first, second, fourth and fifth sectors of the first inverter, the modulation wave of the c phase is shifted; Let u b1 '=u b ', formula (2) can be obtained: Among them, sign() is the rounding function; The amount of charge Q caused by the DC side capacitance deviation c It is expressed by formula (4): Where, C is the DC side capacitance, U dc1 is the capacitor voltage on the DC side, U dc2 is the capacitor voltage on the DC side; Let Q C =Q0, that is, formula (3) can be obtained as formula (5): The maximum translation value △u of the given limited modulation wave is: △u=|U dc1 -IN dc2 |·0.02 (6) So when the c-phase shift modulation wave u c1 'When, u c1 The range of the initial translation that needs to satisfy equation (7) is: [in c '-△u,u c '+△u](7) If the reference voltage is in the third and sixth sectors of the first inverter, the modulation wave of phase b is shifted, and u c1 '=u c ', i.e. u b1 'Calculation and u c1 ' is calculated the same as above. At the same time, when the b-phase shift modulation wave u b1 'When, u b1 'The range of the initial translation must satisfy equation (7); When x is b or c, the midpoint potential balance control strategy of the first inverter under fault-tolerant control is the same as the midpoint potential balance control strategy of phase a under fault-tolerant control, which will not be described in detail here; Furthermore, the midpoint potential balance control strategy under the fault-tolerant control of the second inverter is the same as the midpoint potential balance control strategy under the fault-tolerant control of the first inverter.

6. The midpoint potential balance control strategy under fault-tolerant control according to claim 5 is characterized in that: The modulation wave shifted in different sectors under the a-phase fault-tolerant control needs to meet the range of Table 1: Table 1 The modulation wave shifted in different sectors under the fault-tolerant control of phase b must meet the range of Table 2: Table 2 The modulation wave shifted in different sectors under the c-phase fault-tolerant control must meet the range of Table 3: Table 3 。 7. The midpoint potential balance control strategy under fault-tolerant control according to claim 5 is characterized in that: The midpoint potential balance control strategy under the fault-tolerant control of the second inverter is the same as the midpoint potential balance control strategy under the fault-tolerant control of the first inverter, and the midpoint potential balance control strategy under the fault-tolerant control of the second inverter is carried out simultaneously with the midpoint potential balance control strategy under the fault-tolerant control of the first inverter.

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