High-speed low-power-consumption comparator of SAR ADC

Abstract

The invention discloses a high-speed low-power-consumption comparator of an SAR ADC, and relates to the technical field of analog or digital-analog hybrid integrated circuits. The comparator comprises a pre-amplification stage and a latch stage, an enable signal cp end of the pre-amplification stage is connected with an enable signal Ki, a positive input end of the pre-amplification stage is connected with a differential input positive end signal vp, a negative input end of the pre-amplification stage is connected with a differential input negative end signal vn, a positive output end vop is connected with a positive input end of the latch stage through a switch K1, and a negative output end von is connected with a positive input end of the latch stage through a switch K2. The switch K1 and the switch K2 are both controlled by an enable signal Ki; a differential input positive end signal vp is connected with the positive input end of the latch stage through a switch K3, a differential input negative end signal vn is connected with the positive input end of the latch stage through a switch K4, and the switch K3 and the switch K4 are both controlled by an inversion signal Kim of an enable signal Ki. According to the scheme, the gain and the bandwidth of the pre-amplification stage are improved, so that the speed and the precision of the pre-amplification stage are improved at the same time.

Description

Technical Field

[0001] The present application relates to the technical field of analog or digital-analog hybrid integrated circuits, and in particular to a high-speed and low-power comparator for a SAR ADC. Background Art

[0002] In recent years, with the further improvement of the performance indicators of analog-to-digital converters, especially with the continuous development of integrated circuit process technology, the research on high-speed and low-power SAR structure ADC has become more and more in-depth. With the continuous evolution of integrated circuit manufacturing technology, the requirements for the power consumption and speed of comparators are getting higher and higher. Therefore, the high-speed and low-power technology of SAR ADC has become a hot topic in the current research of analog-to-digital converters.

[0003] The following introduces the basic working principle of the traditional SAR ADC structure and the existing technology of the comparator. Figure 1 As shown, the SAR ADC is mainly composed of a sampling switch S, a comparator, a capacitor array and a SAR logic. When the SAR ADC is in the sampling phase, the switch S is turned on, and the positive and negative input terminals of the comparator are connected to the differential signal sources VIP and VIN respectively, and the differential input positive signals vp and vn are sampled onto the plates of the capacitor array. After the sampling is completed, the sampling switch S is disconnected, and the SAR ADC enters the successive approximation phase. At this time, the comparator compares the differential input positive signals vp and vn successively, and the comparison results are used to switch the capacitor array through the SAR logic to generate a new residual voltage and, thereby completing a successive approximation process. After the SAR ADC performs n successive approximations according to the above process, an n-bit digital code is generated, and the process of converting the analog signal into a digital signal is finally completed. n is a natural number greater than 0, indicating the number of successive approximations.

[0004] As the main analog device in the above structure, the performance of the comparator directly affects the performance of the entire SAR ADC. The schematic diagram of the traditional comparator structure in SAR ADC is as follows: Figure 2 As shown, it includes a pre-amplifier stage and a latch stage. The differential input positive end signals vp and vn are input to the pre-amplifier stage. Ki is the enable signal of the pre-amplifier stage. The output of the pre-amplifier stage enters the latch stage for further amplification and latching. Finally, the output of the latch stage controls the SAR logic. The schematic diagram of the traditional pre-amplifier stage is shown in Figure 3As shown, IB is a tail current source, the differential input tubes are NMOS tubes M1 and M2, the source stages of the NMOS tubes M1 and M2 are both connected to one end of the current source IB, the other end of the current source IB is grounded, the gate stages of the NMOS tubes M1 and M2 are respectively connected to the differential input positive terminal signals vp and vn, the drains of the NMOS tubes M1 and M2 are respectively connected to the drains of the PMOS tubes M3 and M4, the PMOS tubes M3 and M4 are load tubes, and the drains of the PMOS tubes M3 and M4 are respectively connected to their own gates, and the source stages of the PMOS tubes M3 and M4 are both connected to the power supply vdd.

[0005] Assuming that the above pre-amplifier stage is completely symmetrical, the absolute value of the gain A of the above pre-amplifier stage can be expressed as:

[0006]

[0007] Among them, g m1 and g m3 They are Figure 3 The transconductance of NMOS tube M1 and PMOS tube M3 in the equation (1) shows that due to g m1 and g m3 At the same order of magnitude, the absolute value of the gain of the traditional pre-amplifier stage is relatively small, so the accuracy is poor. If you want to increase the gain, you can increase the output impedance of the pre-amplifier stage, but as the output impedance increases, the bandwidth of the pre-amplifier stage decreases rapidly, which significantly affects the speed of the entire comparator. On the other hand, the working mode of the traditional comparator is solidified. During the entire successive approximation process, the pre-amplifier stage is always in working state, so that the speed of the comparator does not reach the optimal level. Due to the static current of the pre-amplifier stage, the comparator also always has static power consumption.

[0008] In view of this, a high-speed and low-power comparator for SAR ADC is urgently needed. Summary of the invention

[0009] In view of the shortcomings of the prior art described above, the present application proposes a high-speed, low-power comparator for SAR ADC, which solves the problem of static power consumption of the pre-amplifier stage in the entire successive approximation process in the prior art; on the other hand, it solves the problem of the contradiction between the gain and bandwidth of the pre-amplifier stage in the prior art.

[0010] In order to achieve the above-mentioned purpose, this application specifically adopts the following technical solutions:

[0011] A high-speed, low-power comparator for a SAR ADC, the comparator comprising a pre-amplification stage and a latch stage,

[0012] The enable signal cp of the pre-amplifier stage is connected to the enable signal Ki, the positive input terminal is connected to the differential input positive terminal signal vp, the negative input terminal is connected to the differential input negative terminal signal vn, the positive output terminal vop is connected to the positive input terminal of the latch stage through the switch K1, and the negative output terminal von is connected to the positive input terminal of the latch stage through the switch K2, and the switches K1 and K2 are both controlled by the enable signal Ki;

[0013] At the same time, the differential input positive end signal vp is connected to the positive input end of the latch stage through the switch K3, and the differential input negative end signal vn is connected to the positive input end of the latch stage through the switch K4. The switches K3 and K4 are both controlled by the inverted signal Kim of the enable signal Ki.

[0014] As an optional technical solution, i in the enable signal Ki is 1, 2, ..., n-1, n; n is a natural number greater than 0. When i is n, it means that in the design of an n-bit SAR ADC, the latch stage uses n flip-flops DFF.

[0015] As an optional technical solution, the signal input terminal D of the first trigger DFF is connected to the power supply vdd, the enable signal terminal CP is connected to the clock signal clk, and the reset terminal R is connected to the sampling control signal S.

[0016] When the sampling control signal S is at a high level, the output terminal Q of the trigger DFF is forced to reset to 0. When the sampling control signal S is at a low level, the trigger DFF exits the reset state. The output terminal Q of the trigger DFF follows the clock signal clk, and the value of the output terminal Q is output as the enable signal K1 and passed to the input terminal D of the next trigger.

[0017] Until the last flip-flop DFF outputs the enable signal Kn.

[0018] As an optional technical solution, the output terminal Q of the trigger DFF is forced to be reset to 0, specifically:

[0019] When the SAR ADC is in the sampling phase, S=1, the output enable signals Ki of the n D flip-flops DFF are reset to 0.

[0020] As an optional technical solution, when the sampling control signal S is at a low level, the trigger DFF exits the reset state, specifically:

[0021] When the SAR ADC is in the successive approximation phase, S=0, and the output enable signals Ki of the n D flip-flops DFF are sequentially pulled high from 0 to 1 following the rising edge of the clock signal clk.

[0022] As an optional technical solution, the pre-amplification stage includes a tail current source IB, and the tail current source IB is controlled by an enable signal Ki.

[0023] When the enable signal Ki is 0, the tail current source IB is not enabled, and the pre-amplification stage has no static power consumption;

[0024] When the enable signal Ki is 1, the tail current source IB is enabled, one end of the tail current source IB is grounded, and the other end is simultaneously connected to the source of the differential input NMOS tubes M1 and M2 of the pre-amplifier stage;

[0025] The gates of the NMOS tubes M1 and M2 are connected to the differential input positive terminal signals vp and vn respectively, the drains of the NMOS tubes M1 and M2 are connected to the drains of the PMOS tubes M3 and M4 respectively, the drains of the PMOS tubes M3 and M4 are connected to their own gates respectively, and the sources of the PMOS tubes M3 and M4 are connected to the power supply vdd.

[0026] As an optional technical solution, it also includes NMOS tubes M5 and M6, both of which have drains connected to the power supply vdd, the source of the NMOS tube M5 is simultaneously connected to the drain of the NMOS tube M1 and the drain of the PMOS tube M3, the gate of the NMOS tube M5 is connected to the differential input negative terminal signal vn, the source of the NMOS tube M6 is simultaneously connected to the drain of the NMOS tube M2 and the drain of the PMOS tube M4, and the gate of the NMOS tube M6 is connected to the differential input positive terminal signal vp.

[0027] As an optional technical solution, the PMOS tubes M3 and M4 are load tubes.

[0028] As an optional technical solution, the enable signal cp of the latch stage is connected to the clock signal clk.

[0029] The beneficial effects of this application include:

[0030] Compared with the traditional method of always using the cascade of the pre-amplifier stage and the latch stage in the process of successive approximation, a flexible configuration method of the pre-amplifier stage and the latch stage is proposed. When the successive approximation is in the first few cycles, the comparator working mode is set to connect the input signal directly to the latch stage, and the latch stage is used to directly compare the comparator input signal, and the pre-amplifier stage is disabled, thereby reducing the static power consumption of the comparator. When the successive approximation is in the last few cycles, the comparator working mode is set to amplify the input signal through the pre-amplifier stage before entering the latch stage. Through the above configuration, the speed and power consumption of the comparator are optimized;

[0031] Compared with the traditional method of increasing the gain of the preamplifier stage by increasing the output impedance of the preamplifier stage, a method of increasing the equivalent span of the preamplifier stage is proposed, which simultaneously improves the gain and bandwidth of the preamplifier stage, thereby simultaneously improving the speed and accuracy of the preamplifier stage.

[0032] Other beneficial effects or advantages of the present application will be described in detail in conjunction with the specific structure in the specific implementation manner. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings required for use in the embodiments or the prior art descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative labor. In addition, it should be understood that the proportional relationship of the various components in the drawings of this specification does not represent the proportional relationship in the actual material selection and design, which is only a schematic diagram of the structure or position, where:

[0034] Figure 1 SAR ADC structure diagram

[0035] Figure 2 Schematic diagram of the traditional comparator structure in SAR ADC

[0036] Figure 3 Traditional pre-amplification stage structure

[0037] Figure 4 Schematic diagram of the change in speed of the pre-amplifier stage and the latch stage with the input signal amplitude comparison

[0038] Figure 5 Schematic diagram of successive approximation of SAR ADC comparator input

[0039] Figure 6 The pre-amplification stage principle diagram (a) and half-side small signal equivalent circuit (b) proposed by the present invention

[0040] Figure 7 The configurable low power amplifier structure proposed by the present invention

[0041] Figure 8 Comparator control signal generation circuit DETAILED DESCRIPTION

[0042] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0043] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0044] In the description of this application, it should be noted that the terms used, such as "top" and "bottom", refer to the part of this application that is close to the top when in use as the top, and the part that is close to the bottom as the bottom; the terms used, such as "first" and "second", are only used to distinguish expressions, and do not indicate or imply that they have a difference in importance or order; the terms used, such as "inside" and "outside", refer to the inside and outside of a specific contour. The use of the above terms is only to facilitate a clear and simple description of the technical solution of this application, and cannot be understood as a limitation on this application.

[0045] Embodiment 1:

[0046] The invention discloses a high-speed and low-power comparator of a SAR ADC. The comparator comprises a preamplifier stage and a latch stage. An enable signal cp of the preamplifier stage is connected to an enable signal Ki, a positive input terminal is connected to a differential input positive terminal signal vp, a negative input terminal is connected to a differential input negative terminal signal vn, a positive output terminal vop is connected to the positive input terminal of the latch stage through a switch K1, a negative output terminal von is connected to the positive input terminal of the latch stage through a switch K2, and both the switches K1 and K2 are controlled by the enable signal Ki; meanwhile, the differential input positive terminal signal vp is connected to the positive input terminal of the latch stage through a switch K3, and the differential input negative terminal signal vn is connected to the positive input terminal of the latch stage through a switch K4, and both the switches K3 and K4 are controlled by an inverted signal Kim of the enable signal Ki.

[0047] In order to facilitate understanding of the improvement of this solution, the prior art is briefly described first:

[0048] The schematic diagram of the change of the pre-amplifier stage and the latch stage with the input signal amplitude comparison speed is as follows Figure 4 As shown by Figure 4 It can be seen that when the input signal amplitude is relatively small, the comparison speed of the pre-amplifier stage structure is faster; when the input signal amplitude is relatively large, the comparison speed of the latch stage structure is faster. Figure 5 As shown by Figure 5 It can be seen that in the first few cycles of successive approximation, the difference between the comparator differential input signals vp and vn is large, and in the last few cycles of successive approximation, the comparator differential input positive signal vp and the differential input negative signal vn gradually approach each other, and the difference is small.

[0049] Based on the above rules, different comparator working modes can be selected according to different successive approximation time periods, so as to achieve fast comparison of comparator input signals while consuming the lowest power. At the same time, in different modes, unnecessary working modules are turned off to reduce the static power consumption of the comparator.

[0050] Therefore, the present invention proposes a high-speed and low-power comparator for SAR ADC, such as Figure 7 As shown:

[0051] In the enable signal Ki, i=1, 2, ..., n-1, n; n is a natural number greater than 0. When i is n, it means that in the design of an n-bit SAR ADC, the latch stage uses n flip-flops DFF.

[0052] The signal input terminal D of the first trigger DFF is connected to the power supply vdd, the enable signal terminal CP is connected to the clock signal clk, and the reset terminal R is connected to the sampling control signal S.

[0053] When the sampling control signal S is at a high level, the output terminal Q of the trigger DFF is forced to reset to 0. When the sampling control signal S is at a low level, the trigger DFF exits the reset state. The output terminal Q of the trigger DFF follows the clock signal clk, and the value of the output terminal Q is output as the enable signal K1 and passed to the input terminal D of the next trigger.

[0054] Until the last flip-flop DFF outputs the enable signal Kn.

[0055] The output terminal Q of the flip-flop DFF is forced to be reset to 0. Specifically, when the SAR ADC is in the sampling phase, S=1, and the output enable signals Ki of the n D flip-flops DFF are reset to 0.

[0056] When the sampling control signal S is at a low level, the trigger DFF exits the reset state. Specifically, when the SAR ADC is in the successive approximation phase, S=0, and the output enable signals Ki of the n D flip-flops DFF are sequentially pulled high from 0 to 1 following the rising edge of the clock signal clk.

[0057] According to the actual situation, one of the signals Ki (i = 1, 2, ..., n-1, n) and its inverted signal Kim (i = 1, 2, ..., n-1, n) can be selected to control Figure 7 There are 4 switches between the pre-amplifier stage and the latch stage.

[0058] Furthermore, its working principle is:

[0059] When the SAR ADC is in the first few successive approximation cycles, due to the large difference between the comparator differential input positive terminal signal vp and the differential input negative terminal signal vn, Figure 4 It can be seen that the comparison speed of the latch stage is faster than that of the pre-amplifier stage. The comparator differential input positive terminal signal vp and the differential input negative terminal signal vn can be directly used as the input signal of the latch stage. At this time, select Figure 8 The corresponding enable signal Ki (i = 1, 2, ..., n-1, n) is 0, so that the control Figure 7 The switch in is disconnected;

[0060] At the same time, the enable signal Kim (i = 1, 2, ..., n-1, n) is 1, making the controlled Figure 7 The middle switch is turned on, so that the comparator differential input signal is directly input to the latch stage.

[0061] By enabling the signal Ki (i=1,2,…,n-1,n), Figure 6 The tail current source IB of the preamplifier stage in (a) is not enabled, so that the preamplifier stage has no static power consumption, which reduces the static power consumption of the entire comparator. As the successive approximation process continues, the difference between the positive terminal signal vp of the comparator differential input and the negative terminal signal vn of the differential input gradually decreases, and the comparison speed of the latch stage for the small signal differential voltage gradually becomes slower than that of the preamplifier stage.

[0062] at this time, Figure 8 The corresponding enable signal Ki (i=1,2,…,n-1,n) changes from 0 to 1, making it control Figure 7 The switch in is turned on and the preamplifier stage is enabled. The inverting signal Kim (i=1,2,…,n-1,n) changes from 1 to 0, making the one it controls Figure 7 The middle switch is disconnected, so that the differential input signal of the comparator is first input to the pre-amplifier stage, amplified by the pre-amplifier stage, and then input to the latch stage.

[0063] As an optional technical solution, the pre-amplifier stage includes a tail current source IB, which is controlled by an enable signal Ki. When the enable signal Ki is 0, the tail current source IB is not enabled, and the pre-amplifier stage has no static power consumption; when the enable signal Ki is 1, the tail current source IB is enabled, one end of the tail current source IB is grounded, and the other end is simultaneously connected to the source of the differential input NMOS tubes M1 and M2 of the pre-amplifier stage; the gates of the NMOS tubes M1 and M2 are respectively connected to the differential input positive terminal signals vp and vn, the drains of the NMOS tubes M1 and M2 are respectively connected to the drains of the PMOS tubes M3 and M4, the drains of the PMOS tubes M3 and M4 are respectively connected to their own gates, and the sources of the PMOS tubes M3 and M4 are both connected to the power supply vdd.

[0064] It also includes NMOS tubes M5 and M6, both drains of which are connected to the power supply vdd, the source of the NMOS tube M5 is simultaneously connected to the drain of the NMOS tube M1 and the drain of the PMOS tube M3, the gate of the NMOS tube M5 is connected to the differential input negative terminal signal vn, the source of the NMOS tube M6 is simultaneously connected to the drain of the NMOS tube M2 and the drain of the PMOS tube M4, the gate of the NMOS tube M6 is connected to the differential input positive terminal signal vp, and the PMOS tubes M3 and M4 are load tubes.

[0065] Furthermore, the half-side small signal equivalent circuit of the preamplifier stage is as follows Figure 6 As shown in (b), the working principle of the pre-amplification stage is:

[0066] Assuming that all MOS tubes work in the saturation region, o1 , r o3 and r o6 are the small signal output impedances of the MOS tubes M1, M3 and M6 working in the saturation region, g m1 and g m3 are the transconductance of NMOS tube M1 and PMOS tube M3, respectively. m6 is the transconductance of the PMOS tube, vp and vn are the positive and negative input signals of the pre-amplifier stage respectively. xp and v xn for Figure 6 (b) The small signal voltage of the corresponding node.

[0067] Since MOS tubes M1, M3 and M6 work in the saturation region, their small signal impedance r o1 , r o3 and r o6 Therefore, the current flowing through the pre-amplifier output node v xn The current at Figure 6 (b) is composed of three voltage-controlled current sources. o1 , r o3 and r o6 In the case of a small signal current, Kirchhoff's current law shows that in this half-side equivalent circuit, the output node v xn The node current equation at can be expressed as:

[0068] g m1 vp-g m3 v xn =g m6 (vp-v xn ) (2)

[0069] Similarly, if we change the other half of the equivalent circuit, v xn The corresponding node is named v xp, and assuming that the circuit is completely symmetrical, then in the other half of the equivalent circuit, the output node v xp The node current equation at can be expressed as:

[0070] g m1 vn-g m3 v xp =g m6 (vn-v xp ) (3)

[0071] Solving the above two equations (2) and (3) together, the absolute value of the gain A of the preamplifier stage can be expressed as:

[0072]

[0073] It can be seen from formula (4) that the pre-amplifier stage structure proposed in the present invention has a significantly reduced denominator and a significantly increased numerator compared to the traditional pre-amplifier stage structure, thereby significantly improving the gain. At the same time, the gain improvement method is not achieved by increasing the output impedance of the pre-amplifier stage, but by increasing the equivalent span of the pre-amplifier stage, which means that the pre-amplifier stage structure proposed in the present invention simultaneously improves the gain and bandwidth of the pre-amplifier stage, and significantly improves the accuracy and speed of the pre-amplifier stage.

[0074] Finally, it should be understood that the embodiments described in this specification are only used to illustrate the principles of the embodiments of this specification. Other variations may also fall within the scope of this specification. Therefore, as an example and not a limitation, alternative configurations of the embodiments of this specification may be considered consistent with the teachings of this specification. Accordingly, the embodiments of this specification are not limited to the embodiments explicitly introduced and described in this specification.

Claims

1. A high-speed, low-power comparator for a SAR ADC, characterized in that: The comparator comprises a pre-amplification stage and a latch stage, The enable signal cp of the pre-amplifier stage is connected to the enable signal Ki, the positive input terminal is connected to the differential input positive terminal signal vp, the negative input terminal is connected to the differential input negative terminal signal vn, the positive output terminal vop is connected to the positive input terminal of the latch stage through the switch K1, and the negative output terminal von is connected to the positive input terminal of the latch stage through the switch K2, and the switches K1 and K2 are both controlled by the enable signal Ki; At the same time, the differential input positive end signal vp is connected to the positive input end of the latch stage through the switch K3, and the differential input negative end signal vn is connected to the positive input end of the latch stage through the switch K4. The switches K3 and K4 are both controlled by the inverted signal Kim of the enable signal Ki.

2. A high-speed, low-power comparator for a SAR ADC as claimed in claim 1, characterized in that: In the enable signal Ki, i=1, 2, ..., n-1, n; n is a natural number greater than 0. When i is n, it means that in the design of an n-bit SAR ADC, the latch stage uses n flip-flops DFF.

3. The high-speed, low-power comparator for a SAR ADC as claimed in claim 2, characterized in that: The signal input terminal D of the first trigger DFF is connected to the power supply vdd, the enable signal terminal CP is connected to the clock signal clk, and the reset terminal R is connected to the sampling control signal S. When the sampling control signal S is at a high level, the output terminal Q of the trigger DFF is forced to reset to 0. When the sampling control signal S is at a low level, the trigger DFF exits the reset state. The output terminal Q of the trigger DFF follows the clock signal clk, and the value of the output terminal Q is output as the enable signal K1 and passed to the input terminal D of the next trigger. Until the last flip-flop DFF outputs the enable signal Kn.

4. The high-speed, low-power comparator for a SAR ADC as claimed in claim 3, characterized in that: The output terminal Q of the flip-flop DFF is forced to reset to 0, specifically: When the SAR ADC is in the sampling phase, S=1, the output enable signals Ki of the n D flip-flops DFF are reset to 0.

5. The high-speed, low-power comparator for SAR ADC according to claim 3, characterized in that: When the sampling control signal S is at a low level, the trigger DFF exits the reset state, specifically: When the SAR ADC is in the successive approximation phase, S=0, and the output enable signals Ki of the n D flip-flops DFF are sequentially pulled high from 0 to 1 following the rising edge of the clock signal clk.

6. The high-speed, low-power comparator for a SAR ADC as claimed in claim 1, characterized in that: The pre-amplification stage includes a tail current source IB, which is controlled by an enable signal Ki. When the enable signal Ki is 0, the tail current source IB is not enabled, and the pre-amplification stage has no static power consumption; When the enable signal Ki is 1, the tail current source IB is enabled, one end of the tail current source IB is grounded, and the other end is simultaneously connected to the source of the differential input NMOS tubes M1 and M2 of the pre-amplifier stage; The gates of the NMOS tubes M1 and M2 are connected to the differential input positive terminal signals vp and vn respectively, the drains of the NMOS tubes M1 and M2 are connected to the drains of the PMOS tubes M3 and M4 respectively, the drains of the PMOS tubes M3 and M4 are connected to their own gates respectively, and the sources of the PMOS tubes M3 and M4 are connected to the power supply vdd.

7. A high-speed, low-power comparator for a SAR ADC as claimed in claim 6, characterized in that: It also includes NMOS tubes M5 and M6, both drains of which are connected to the power supply vdd, the source of the NMOS tube M5 is connected to the drain of the NMOS tube M1 and the drain of the PMOS tube M3, the gate of the NMOS tube M5 is connected to the differential input negative terminal signal vn, the source of the NMOS tube M6 is connected to the drain of the NMOS tube M2 and the drain of the PMOS tube M4, and the gate of the NMOS tube M6 is connected to the differential input positive terminal signal vp.

8. The high-speed, low-power comparator for SAR ADC according to claim 6, characterized in that: The PMOS tubes M3 and M4 are load tubes.

9. A high-speed, low-power comparator for a SAR ADC as claimed in any one of claims 1 to 8, characterized in that: The enable signal cp of the latch stage is connected to the clock signal clk.

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