SJ-MOSFET device and manufacturing method thereof

Abstract

The invention discloses an SJ-MOSFET device. The SJ-MOSFET device comprises a first conductive type substrate; a first conductive type epitaxial layer; a source region; a body region; a second conductive type doped column; the trench gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region; and the trench pseudo gate is arranged on the side surface of the second conductive type doped column and penetrates through the source region and the body region. On the other hand, the invention discloses a manufacturing method. According to the invention, the grid electrode and the grid electrode groove are arranged on the side surface of the doped column, and a part of the grid electrode groove is arranged in the doped column, so that the area of the grid electrode groove occupying the MESA is small, and the grid electrode groove is arranged towards the interior of the doped column, so that the cell size and the pitch between two source electrode contact holes can be reduced to the greatest extent, and the performance of the MESA is improved. And meanwhile, no JFET resistor exists, so that the optimization of the on-resistance is realized.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductors, and in particular relates to a SJ-MOSFET device and a manufacturing method thereof. Background Art

[0002] At present, in semiconductor device technology, SJ-MOSFET device (Super Junction Trench Mosfet) technology is widely used, especially in the field of medium and high voltage switching converters. Compared with the traditional voltage-withstand structure, the super structure forms alternating P-type and N-type regions in the drift region of the conventional device. It can make the resistivity of the drift region lower without compromising the voltage-withstand capability of the device. Therefore, the device can also achieve a lower on-resistance and reduce the power consumption of the system. Therefore, it is widely used in high-voltage and high-frequency switching power supply circuits.

[0003] The current SJ MOSFET devices all have the gate in the middle of two Pillars, one gate controls two channels, and the source contact hole is punched on the Pillar. The surge capability needs to be improved, and the dynamic parameter matching application adjustment freedom is not high. Summary of the invention

[0004] In view of this, in order to solve the problem of the background technology, the present invention provides a SJ-MOSFET device, comprising:

[0005] a first conductive type substrate;

[0006] A first conductivity type epitaxial layer, wherein the first conductivity type epitaxial layer is disposed on a first conductivity type substrate;

[0007] A source region, wherein the source region is disposed on an upper surface of the first conductivity type epitaxial layer;

[0008] a body region, the body region being arranged below the source region;

[0009] A second conductive type doped column, wherein the second conductive type doped column is disposed in the first conductive type epitaxial layer and runs through the source region and the body region;

[0010] A trench gate, which is arranged on a side of the second conductive type doped column and penetrates the source region and the body region;

[0011] A trench dummy gate is disposed on a side of the second conductive type doped column and penetrates the source region and the body region.

[0012] Preferably, it also includes a dielectric layer and a metal layer,

[0013] The dielectric layer is arranged above the first conductive type epitaxial layer, the metal layer is arranged above the dielectric layer, contact holes are opened on the dielectric layer, and the metal layer is electrically connected to the source region and the second conductive type doped column through the corresponding contact holes respectively;

[0014] The depth of the contact hole extends to a depth corresponding to the body region.

[0015] Preferably, the trench dummy gate is electrically connected to the metal layer through a contact hole;

[0016] The metal layer is electrically connected to the source electrode, or the metal layer is electrically connected to the gate electrode.

[0017] Another aspect of the present invention discloses a method for manufacturing a SJ-MOSFET device, comprising the following steps:

[0018] providing a substrate, and disposing an epitaxial layer on the substrate;

[0019] forming a second conductivity type doped column in the epitaxial layer;

[0020] Performing ion implantation on the upper surface of the epitaxial layer to form a body region;

[0021] Etching the side of the second conductive type doped column to form a second trench;

[0022] forming a trench gate and / or a trench dummy gate in the second trench;

[0023] A source region is formed on the upper surface of the body region:

[0024] forming a dielectric layer above the epitaxial layer;

[0025] forming a contact hole on the dielectric layer, wherein the contact hole penetrates the source region and extends to the body region;

[0026] forming a CT region at the bottom of the contact hole by ion implantation and annealing;

[0027] Deposition is performed on the dielectric layer to form a metal layer.

[0028] Preferably, forming a second conductivity type doped column in the epitaxial layer comprises:

[0029] forming a second conductivity type doped column in the epitaxial layer by a multi-layer epitaxial implantation process, wherein the multi-layer epitaxial implantation process includes epitaxial growth, photolithography and ion implantation;

[0030] or,

[0031] Etching is performed on the epitaxial layer and the barrier layer to form a first trench, and then a second conductive type doped column is formed in the first trench by a single epitaxial layer implantation process.

[0032] Preferably, after forming the second trench, the method further comprises the step of: growing a sacrificial oxide layer on the second trench and removing the layer.

[0033] Preferably, after forming the second trench, a HDP process is performed on the second trench to fill the second trench and then etch back to form a thick oxide layer at the bottom of the second trench.

[0034] Preferably, forming a trench gate and / or a trench dummy gate in the second trench comprises: generating a gate oxide layer in the second trench and then filling it to form gate polysilicon.

[0035] Preferably, the trench dummy gate is electrically connected to the metal layer through a contact hole.

[0036] The beneficial effects of the present invention are:

[0037] (1) The present invention arranges the gate and the gate trench on the side of the doped column, and a part of the gate trench is arranged inside the doped column, so that the gate trench occupies less area of ​​the MESA, and the gate trench is arranged further inside the doped column, which can minimize the distance between the two source contact holes and thus reduce the cell size (pitch). At the same time, there is no JFET resistance, and the on-resistance is optimized.

[0038] (2) In the present invention, contact holes are provided on both the second conductive type doped column and the MESA region. The contact holes are electrically connected to the source, so that there are two source contact holes in one cell, which greatly improves the surge capability of the device.

[0039] (3) The present invention can adjust the effect of input capacitance Ciss according to actual scenarios. The device itself can adjust the input capacitance Ciss by adjusting the number of gates, and Cgs (i.e., the capacitance before GS) is proportional to the number of gates. Therefore, when Cgs needs to be reduced, the trench pseudo-gate 8 can be electrically connected to the source.

[0040] (4) Each channel of the present invention is independently controlled by a gate, and different Ciss and Cgs can be easily adjusted for different applications with a high degree of freedom, which reduces the ringing generated during the switching process and greatly reduces the EMI risk.

[0041] (5) Although the present invention changes the internal structure of the device, the present invention does not increase the layout and process costs of the device in terms of the manufacturing method. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0043] Figures 1 to 9 Schematic diagram of a flow chart of an embodiment of the present invention. DETAILED DESCRIPTION

[0044] The core of the present invention is to provide a SJ-MOSFET device and a method for manufacturing the same. The present invention sets the gate and the gate groove on the side of the doped column, and a part of the gate groove is set inside the doped column, so that the gate groove occupies less area of ​​the MESA, and the gate groove is set further inside the doped column, which can minimize the cell size and the pitch between the two source contact holes, and at the same time, there is no JFET resistance, so the on-resistance is optimized. At the same time, the source contact holes are increased, and the surge capacity is improved. In addition, the present invention also provides a method for adjusting the ratio of the gate capacitance, adjusting the design matching according to the application, reducing the ringing generated during the switching process, and greatly reducing the EMI risk.

[0045] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0046] Embodiment 1

[0047] Figures 1 to 9 A method for manufacturing a SJ-MOSFET device provided in this embodiment is shown, comprising the following steps:

[0048] S1: Figure 1 As shown, a substrate 1 is prepared, and an epitaxial layer 2 is formed on the substrate 1 .

[0049] S2: Figure 2 As shown, a first trench 4 is formed on the epitaxial layer 2 (left), and then a second conductive type doped column 4 - 1 is formed in the first trench 4 by a single-layer epitaxial layer implantation process (right).

[0050] S3: Figure 3 As shown, ion implantation is performed on the upper surface of the epitaxial layer 2 and then diffusion is performed to form a body region 5.

[0051] S4: Figure 4 As shown, etching is performed on the side of the second conductive type doped column 4 - 1 to form a second trench 6 .

[0052] S5: Figure 5 As shown, a trench gate 7 and / or a trench dummy gate 8 is formed in the second trench 6; preferably, a gate oxide layer is first formed in the second trench 6, and then filled to form gate polysilicon, and finally the trench gate 7 and / or the trench dummy gate 8 is formed.

[0053] S6: Figure 6 As shown, a source region 9 is formed on the upper surface of the body region 5 ; preferably, ion implantation is performed on the upper surface of the body region 5 , and then annealing is performed to form the source region 9 .

[0054] S7: Figure 7 As shown, a dielectric layer 10 is formed on the epitaxial layer 2. Preferably, the dielectric layer 10 is formed by oxide deposition.

[0055] S8: Figure 8 As shown, a contact hole 11 is formed on the dielectric layer 10, and the contact hole 11 extends through the source region to the body region; preferably, etching is performed from the dielectric layer 10, and the etching depth extends to the depth corresponding to the body region, and the contact holes 11 are respectively arranged at positions corresponding to the trench pseudo gate 8 and the second conductive type doped column 4-1, and a contact hole 11 is also arranged between the two second conductive type doped columns 4-1, so that the trench pseudo gate 8 and the second conductive type doped column 4-1 can be electrically connected to the source region 9, and then the CT region is formed at the bottom of the contact hole 11 The portion that contacts the body region is ion implanted and annealed.

[0056] S9: Fig. 9 As shown, deposition is performed on the dielectric layer 10 to form a metal layer 12 , and the metal layer 12 is also deposited downward at the contact hole 11 , so that the trench dummy gate 8 and the second conductive type doped column 4 - 1 are electrically connected to the metal layer 12 respectively.

[0057] In a preferred embodiment, in step S2, the second conductive type doped column 4-1 may be formed in the epitaxial layer 2 by a multi-layer epitaxial implantation process, wherein the multi-layer epitaxial implantation process includes epitaxial growth, photolithography and ion implantation.

[0058] In a preferred embodiment, after forming the second trench 6 in step S4, the step of: growing and removing a sacrificial oxide layer on the second trench 6 is further included. Preferably, a thick oxide structure (TBO) is then formed at the bottom of the second trench 6. One implementation method may be to perform HDP process filling and etching back to form a thick oxide layer at the bottom of the second trench 6, which improves the withstand voltage, reduces the Cgd capacitance, and helps optimize the device manufacturing process.

[0059] Embodiment 2

[0060] like Fig. 9 As shown, this embodiment discloses a SJ-MOSFET device, including:

[0061] A substrate 1 of a first conductivity type;

[0062] An epitaxial layer 2 of a first conductivity type, wherein the epitaxial layer 2 of the first conductivity type is disposed on a substrate 1 of the first conductivity type;

[0063] A source region 9, which is arranged on the upper surface of the epitaxial layer 2 of the first conductivity type;

[0064] A body region 7, wherein the body region 7 is arranged below the source region 9;

[0065] A second conductive type doped column 4 - 1 , which is disposed in the first conductive type epitaxial layer 2 and penetrates the source region 9 and the body region 7 ;

[0066] A trench gate 7, which is disposed on a side of the second conductive type doped column 4-1 and extends through the source region to the body region;

[0067] A trench dummy gate 8, which is disposed on the side of the second conductive type doped column 4-1 and extends through the source region to the body region;

[0068] A dielectric layer 10 and a metal layer 12, wherein the dielectric layer 10 is disposed above the epitaxial layer 2 of the first conductivity type, and the metal layer 12 is disposed above the dielectric layer 10, and the metal layer 12 is electrically connected to the epitaxial layer 2 of the first conductivity type through a contact hole 11, and the contact hole 11 penetrates the dielectric layer 10 and the source region 9 and extends to a depth corresponding to the body region 7;

[0069] The trench dummy gate 8 is electrically connected to the metal layer 12 through the contact hole 11 .

[0070] It should be noted that the name of the trench dummy gate 8 is to distinguish it from the trench gate 7, but the trench dummy gate 8 can actually also play the role of the trench gate 7, because the trench dummy gate 8 of the embodiment of the present invention is electrically connected to the metal layer 12 through the contact hole 11, but in reality there are multiple areas in the metal layer 12 of the SJ-MOSFET device (including metal areas that can be interconnected and metal areas that are not interconnected), and the metal layer 12 can choose to be electrically connected to the gate or to the source. When electrically connected to the source, the trench dummy gate 8 plays the role of a dummy gate, and when electrically connected to the gate, the role of the trench dummy gate 8 is consistent with that of the trench gate 7.

[0071] The gate and gate trench of the embodiment of the present invention are arranged on the side of the doped column, and a part of the gate trench is arranged inside the doped column, so that the gate trench occupies less area of ​​​​MESA, and the gate trench is arranged further inside the doped column, which can minimize the cell size and the pitch between the two source contact holes. At the same time, there is no JFET resistance, and the on-resistance is optimized.

[0072] The embodiment of the present invention can adjust the effect of input capacitance Ciss according to the actual scenario. The device itself can adjust the input capacitance Ciss by adjusting the number of gates, and Cgs (i.e., the capacitance before GS) is proportional to the number of gates. Therefore, when Cgs needs to be reduced, the trench pseudo gate 8 is electrically connected to the source.

[0073] In some actual non-high-frequency usage scenarios, the smaller the input capacitance Ciss, the better. However, the input capacitance Ciss of the SJ-MOSFET device disclosed in the embodiment of the present invention is only slightly larger than that of the conventional SJ-MOSFET device. However, the increase in the input capacitance Ciss will reduce the transconductance and reduce the ringing generated during the switching process of the device, thereby reducing the risk of EMI.

[0074] If the working scenario requires high-frequency application, the capacitance ratio can be adjusted directly by adjusting the number or connection relationship of the trench pseudo-gates 8. For example, in a scenario with a small Cgs, the trench pseudo-gate 8 can be connected to the source to reduce the number of working gates of the device.

[0075] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0076] The above description of the disclosed embodiments enables one skilled in the art to implement or use the present invention. Various modifications to these embodiments will be apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present invention. Therefore, the present invention will not be limited to the embodiments shown herein, but rather to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A SJ-MOSFET device, characterized in that: include: a first conductive type substrate; A first conductivity type epitaxial layer, wherein the first conductivity type epitaxial layer is disposed on a first conductivity type substrate; A source region, wherein the source region is disposed on an upper surface of the first conductivity type epitaxial layer; a body region, the body region being arranged below the source region; A second conductive type doped column, wherein the second conductive type doped column is disposed in the first conductive type epitaxial layer and runs through the source region and the body region; A trench gate, which is arranged on a side of the second conductive type doped column and penetrates the source region and the body region; A trench dummy gate is disposed on a side of the second conductive type doped column and penetrates the source region and the body region.

2. The SJ-MOSFET device according to claim 1, characterized in that: It also includes a dielectric layer and a metal layer. The dielectric layer is arranged above the first conductive type epitaxial layer, the metal layer is arranged above the dielectric layer, contact holes are opened on the dielectric layer, and the metal layer is electrically connected to the source region and the second conductive type doped column through the corresponding contact holes respectively; The depth of the contact hole extends to a depth corresponding to the body region.

3. The SJ-MOSFET device according to claim 2, characterized in that: The trench dummy gate is electrically connected to the metal layer through a contact hole; The metal layer is electrically connected to the source electrode, or the metal layer is electrically connected to the gate electrode.

4. A method for manufacturing a SJ-MOSFET device, characterized in that: The steps include: providing a substrate, and disposing an epitaxial layer on the substrate; forming a second conductivity type doped column in the epitaxial layer; Performing ion implantation on the upper surface of the epitaxial layer to form a body region; Etching the side of the second conductive type doped column to form a second trench; forming a trench gate and / or a trench dummy gate in the second trench; A source region is formed on the upper surface of the body region: forming a dielectric layer above the epitaxial layer; forming a contact hole on the dielectric layer, wherein the contact hole penetrates the source region and extends to the body region; forming a CT region at the bottom of the contact hole by ion implantation and annealing; Deposition is performed on the dielectric layer to form a metal layer.

5. The manufacturing method according to claim 4, characterized in that: Forming a second conductive type doped column in the epitaxial layer, comprising: forming a second conductivity type doped column in the epitaxial layer by a multi-layer epitaxial implantation process, wherein the multi-layer epitaxial implantation process includes epitaxial growth, photolithography and ion implantation; or, Etching is performed on the epitaxial layer and the barrier layer to form a first trench, and then a second conductive type doped column is formed in the first trench by a single epitaxial layer implantation process.

6. The method according to claim 4, characterized in that: After forming the second trench, the method further includes the steps of: growing a sacrificial oxide layer on the second trench and removing the layer.

7. The method according to claim 4, characterized in that: After forming the second trench, a HDP process is performed on the second trench to fill and then etch back to form a thick oxide layer at the bottom of the second trench.

8. The manufacturing method according to claim 4, characterized in that: Forming a trench gate and / or a trench dummy gate in the second trench includes: generating a gate oxide layer in the second trench, and then filling it to form gate polysilicon.

9. The manufacturing method according to claim 4, characterized in that: The trench dummy gate is electrically connected to the metal layer through a contact hole.

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