Semiconductor device and method for manufacturing semiconductor device

Abstract

The embodiment of the invention discloses a semiconductor device and a manufacturing method of the semiconductor device. The semiconductor device includes: a semiconductor layer; the drain well region is located on the semiconductor layer; the drain region is located in the drain well region; the first source well region and the second source well region are located on the two sides of the drain region respectively; the first source region is located in the first source well region; the second source region is located in the second source well region; the first source well contact region is located in the first source region and extends to the first source well region; the second source well contact region is located in the second source region and extends to the second source well region; the first gate unit extends from the first source well region to the drain region; the second gate unit extends from the second source well region to the drain region; a first part of the first source electrode is in ohmic contact with the first source region, and a second part is in ohmic contact with the first source trap contact region; the first part of the second source electrode is in ohmic contact with the second source region, and the second part is in ohmic contact with the second source trap contact region. According to the semiconductor device, the source electrode is in contact with the source region and the source well contact region at the same time, so that the working performance is improved.

Description

Technical Field

[0001] The present application relates to the semiconductor field, and in particular to a semiconductor device and a method for manufacturing the semiconductor device. Background Art

[0002] In power management technology, MOS tubes controlled by protection circuits are usually connected in series in the loop for charge and discharge protection. In order to meet the charging speed requirements when the power is charged, the on-resistance of the MOS tube needs to be as small as possible. The methods of reducing the on-resistance in the prior art include reducing the cell size, reducing the chip thickness and increasing the substrate concentration. However, smaller cell size and thinner chips mean reduced mechanical strength, which increases the risk of damage to the switch tube during manufacturing and use. Secondly, although a high-concentration substrate can reduce the on-resistance, it may also lead to an increase in leakage current, thereby affecting the energy efficiency and stability of the MOS tube. Summary of the invention

[0003] The present application provides a semiconductor device and a method for manufacturing the semiconductor device, aiming to solve the problem in the prior art that reducing the on-resistance of a MOS tube may lead to performance degradation in other aspects.

[0004] The present application provides a semiconductor device, comprising: a semiconductor layer, having a first doping type; a drain well region, having a second doping type, located in the semiconductor layer; a drain region, having the second doping type, located in the drain well region; a first source well region and a second source well region, having the first doping type, respectively located on both sides of the drain region; a first source region, having the second doping type, located in the first source well region; a second source region, having the second doping type, located in the second source well region; a first source well contact region, having the first doping type, located in the first source region and extending to the first source well region; a second source well contact region, having the first doping type, located in the second source region and extending to the second source well region; a first gate unit, located on the semiconductor layer, extending from the first source well region to the drain region The semiconductor layer is provided with a first gate unit, the first gate unit being arranged on the semiconductor layer and extending from the second source well region to the drain region, covering a portion of the second source well region and a portion of the drain region; the ... second gate unit, the first gate unit being arranged on the semiconductor layer and extending from the second source well region to the drain region, covering a portion of the second source well region and a portion of the drain region; the

[0005] The present application provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor layer of a first doping type; forming a drain well region with a second doping type in the semiconductor layer; forming a drain region of the second doping type in the drain well region; forming a first source well region and a second source well region of the first doping type symmetrically arranged on both sides of the drain region; forming a first gate unit and a second gate unit; using ion implantation to simultaneously form a first source region and a second source region, wherein the first source region is in the first source well region and the second source region is in the second source well region; forming a first source opening region and a second source opening region, wherein the first source opening region leaks out a portion of the first source well contact region and a portion of the first source region, and the second source opening region leaks out a portion of the second source well contact region and a portion of the second source region; and using the first doping type ion implantation to form a first source well contact region and a second source well contact region in the first source region and the second source region.

[0006] The present application provides a method for manufacturing a semiconductor device, comprising: providing a semiconductor layer of a first doping type; forming a drain well region of a second doping type in the semiconductor layer; forming a drain region of the second doping type in the drain well region; forming a first source well region and a second source well region of the first doping type symmetrically arranged on both sides of the drain region; forming a first gate unit and a second gate unit; using ion implantation to simultaneously form a first source region and a second source region, wherein the first source region is in the first source well region, and the second source region is in the second source well region; using a first doping type ion implantation according to a source well contact region mask to form a first source well contact region and a second source well contact region in the first source region and the second source region; and forming a first source opening region and a second source opening region according to an opening region mask, wherein the first source opening region leaks a portion of the first source region and a portion or all of the first source well contact region, and the second source opening region leaks a portion of the second source region and a portion or all of the second source well contact region.

[0007] Through one or more of the above-mentioned embodiments in the present application, at least the following technical effects can be achieved: the present application provides a semiconductor MOS device in which a source electrode is in contact with both a source region and a source well contact region. The larger area contact between the source electrode and the source region can reduce the MOS resistance. At the same time, the source electrode of the semiconductor device is in contact with the source well contact region, thereby avoiding the situation in the prior art where the source electrode and the source cannot effectively contact each other, thereby resulting in a parasitic diode and the MOS tube cannot work normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The technical solution and other beneficial effects of the present application will be made apparent by describing in detail the specific implementation methods of the present application in conjunction with the accompanying drawings.

[0009] Figure 1 A schematic diagram of the circuit structure of an existing battery protection system is shown;

[0010] Figure 2A top view of a semiconductor device according to an embodiment of the present application is shown;

[0011] Figure 3 Shows Figure 2 A cross-sectional view of the semiconductor device along the AA' direction in the example shown;

[0012] Figure 4 Shows Figure 2 A cross-sectional view of the semiconductor device along the BB' direction in the example shown;

[0013] Figure 5 A schematic diagram of a semiconductor layer according to an embodiment of the present application is shown;

[0014] Figure 6 A schematic diagram showing a drain well region after being formed according to an embodiment of the present application is shown;

[0015] Figure 7 A schematic diagram showing a process after forming an isolation region according to an embodiment of the present application is shown;

[0016] Figure 8 A schematic diagram showing the formation of a drain region, a first source well region, and a second source well region according to an embodiment of the present application is shown;

[0017] Fig. 9 A schematic diagram showing the formation of a first dielectric layer and a polysilicon layer according to an embodiment of the present application is shown;

[0018] Fig.10 A schematic diagram showing the formation of a first gate unit, a second gate unit, a first source region and a second source region according to an embodiment of the present application is shown;

[0019] Fig.11 The diagram shows the process of forming the second dielectric layer according to an embodiment of the present application. Fig.10 Schematic diagram of the structure shown in;

[0020] Fig.12 A schematic diagram showing a first source well contact region and a second source well contact region after forming according to an embodiment of the present application;

[0021] Fig.13 A schematic diagram of an overlay of an opening area mask and a source well contact area mask according to an embodiment of the present application is shown.

[0022] The meanings of the reference numerals are as follows:

[0023] 201 Semiconductor layer

[0024] 202 first dielectric layer

[0025] 203 Drain well region

[0026] 204a first source well region

[0027] 204b second source well region

[0028] 205 Quarantine

[0029] 206 Polysilicon layer

[0030] 2061 First Gate Unit

[0031] 2062 Second gate unit

[0032] 207a The first source region

[0033] 207b Second source region

[0034] 208 Leakage Area

[0035] 209 Second dielectric layer

[0036] 210a First source opening area

[0037] 210b Second source opening area

[0038] 211a First source well contact region

[0039] 211b Second source well contact region

[0040] 212a First source electrode

[0041] 212b second source electrode

[0042] 213 Electrostatic Withstand Voltage Area

[0043] 303 Electrostatic Protection Area Mask

[0044] 304a first N-type doping region

[0045] 304b second N-type doping region

[0046] 305 First protective contact window

[0047] 306 Second protective contact window

[0048] 307 First electrostatic protection electrode

[0049] 308 second electrostatic protection electrode

[0050] 401 First Opening

[0051] 402 Second Opening

[0052] 403 The Third Opening

[0053] 404 The Fourth Opening

[0054] 405 The Fifth Opening

[0055] 501 Opening Area Mask

[0056] 502 Source well contact area mask DETAILED DESCRIPTION

[0057] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0058] In the description of the present application, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on the present application. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present application, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0059] In the description of the present application, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or can communicate with each other; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances. In this embodiment, the simulated display screen touch unit is connected to the head tracking unit to obtain the movement path of the sensing cursor in the display device.

[0060] In the present application, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may include that the first and second features are in direct contact, or may include that the first and second features are not in direct contact but are in contact through another feature between them. Moreover, a first feature being "above", "above" and "above" a second feature includes that the first feature is directly above and obliquely above the second feature, or simply indicates that the first feature is higher in level than the second feature. A first feature being "below", "below" and "below" a second feature includes that the first feature is directly below and obliquely below the second feature, or simply indicates that the first feature is lower in level than the second feature.

[0061] The disclosure below provides many different embodiments or examples to realize the different structures of the present application. In order to simplify the disclosure of the present application, the parts and settings of specific examples are described below. Of course, they are only examples, and the purpose is not to limit the present application. In addition, the present application can repeat reference numbers and / or reference letters in different examples, and this repetition is for the purpose of simplification and clarity, which itself does not indicate the relationship between the various embodiments and / or settings discussed. In addition, the various specific processes and material examples provided by the present application, but those of ordinary skill in the art can appreciate the application of other processes and / or the use of other materials.

[0062] To facilitate understanding of the semiconductor device in the embodiment of the present application, the application scenario of the semiconductor device provided by the embodiment of the present application is first explained. The semiconductor device provided by the embodiment of the present application can be applied to the battery management and charging protection system of portable electronic devices such as smart phones, smart watches, and tablet computers, or can also be applied to different scenarios such as protecting current conversion systems and power ICs. Figure 1 In the power protection circuit shown, the power protection chip mainly monitors and controls the charging and discharging state of the battery to prevent abnormal conditions such as overcharging, overdischarging and overcurrent. The battery 1 supplies power to the external circuit 4, and the power protection chip is arranged between the battery 1 and the external circuit 4. The power protection chip has a first input terminal and a second input terminal for providing a control signal to control the conduction of the two MOS tube structures 3.

[0063] Figure 2 A top view of a semiconductor device according to an embodiment of the present application is shown. The semiconductor device includes a device area and an electrostatic protection area. The device area and the electrostatic protection area are schematically divided according to the functions of the semiconductor structure formed on each part of the substrate. In practical applications, the semiconductor device can be formed on a complete substrate. The substrate can be a single crystal silicon substrate or an epitaxial substrate. The substrate material can be: silicon, germanium, silicon carbide, gallium arsenide, gallium phosphide, and can be a compound semiconductor, an alloy semiconductor, etc., or a combination of the above materials. Figure 2In the illustrated embodiment, for ease of understanding, the first source electrode 212a and the first source well contact region 211a and the first source region 207a directly contacting the first source electrode 212a are illustrated, wherein the first source well contact regions 211a are arranged at intervals in the first source region 207a along the long side direction of the first source electrode 212a. Figure 2 In the embodiment, a portion of the first source region 207a and a portion of the first source well contact region 211a are in direct contact with the first source electrode 212a and form an effective ohmic contact. Figure 2 The area ratio and shape of the first source well contact region 211a and the first source region 207a are only schematically expressed, and do not represent the area ratio and shape of the first source well contact region 211a and the first source region 207a in actual applications.

[0064] Figure 3 Shows Figure 2 A cross-sectional view of a semiconductor device along the A-A' direction. Figure 4 Shown along Figure 2 A cross-sectional view of a semiconductor device in the BB' direction. Figure 2-4 In the embodiment shown, the semiconductor device uses a single crystal silicon substrate, which includes:

[0065] The semiconductor layer 201 has a first doping type;

[0066] The drain well region 203 has a second doping type and is located in the semiconductor layer 201;

[0067] The drain region 208 has a second doping type and is located in the drain well region 203;

[0068] The first source well region 204a and the second source well region 204b have a first doping type and are respectively located on both sides of the drain region 208;

[0069] A first source region 207a, having a second doping type, located in the first source well region 204a;

[0070] The second source region 207b has a second doping type and is located in the second source well region 204b;

[0071] The first source well contact region 211 a , having the first doping type, is located in the first source region 207 a and extends to the first source well region 204 a .

[0072] The second source well contact region 211 b , having the first doping type, is located in the second source region 207 b and extends to the second source well region 204 b .

[0073] A first gate unit 2061 is located on the semiconductor layer 201, extends from the first source well region 204a to the drain region 208, and covers a portion of the first source well region 204a and a portion of the drain region 208;

[0074] A second gate unit 2062 is located on the semiconductor layer 201, extends from the second source well region 204b to the drain region 208, and covers a portion of the second source well region 204b and a portion of the drain region 208;

[0075] A first source electrode 212a having a first portion and a second portion, wherein the first portion of the first source electrode 212a is located above the first source region 207a to form an ohmic contact with the first source region 207a, and the second portion of the first source electrode 212a is located above the first source well contact region 211a to form an ohmic contact with the first source well contact region 211a; and

[0076] The second source electrode 212b has a first part and a second part. The first part of the second source electrode 212b is located above the second source region 207b to form an ohmic contact with the second source region 207b. The second part of the second source electrode 212b is located above the second source well contact region 211b to form an ohmic contact with the second source well contact region 211b.

[0077] exist Figure 3-4 In the embodiment shown, the semiconductor device further includes an isolation region 205, and the isolation region 205 is located above the drain region 208. The first gate unit 2061 and the second gate unit 2062 also cover a portion of the isolation region 205. It should be noted that Figure 3 In the illustrated embodiment, the isolation region 205 can improve the drain electric field distribution of the first field effect transistor M1 and the second field effect transistor M2 , but in some embodiments, the semiconductor device may not include the isolation region 205 .

[0078] exist Figure 3-4 In the illustrated embodiment, the semiconductor device includes two metal oxide semiconductor field effect transistors (FETs) with a common drain, which are named as a first FET M1 and a second FET M2 for ease of understanding. The first FET M1 and the second FET M2 have a common drain (not shown in the figure, hereinafter referred to as a common drain) on the isolation region 205, and the first FET M1 and the second FET M2 are symmetrically arranged along the center line of the isolation region 205.

[0079] The first source region 207a serves as the source of the first field effect transistor M1, and the first gate unit 2061 serves as the gate of the first field effect transistor M1. The first gate unit 2061 receives a control signal and controls the on and off of the first field effect transistor M1 based on the control signal. The first source region 207a is disposed on the upper surface of the first source well region 204a, and one surface of the first source region 207a is exposed outside the first source well region 204a, and the surface serves as a connection surface of the first source region 207a, and is used to connect other metal layers or interconnect metals (not shown in the figure).

[0080] exist Figure 3 In the embodiment shown, a first source well contact region 211a is provided on the surface of the first source region 207a, and is connected to the first source electrode 212a through the first source well contact region 211a; a second source well contact region 211b is provided on the surface of the second source region 207b, and is connected to the second source electrode 212b through the second source well contact region 211b; the ion implantation dose of the first source well contact region 211a is greater than the ion implantation dose of the first source region 207a, and the ion implantation dose of the second source well contact region 211b is greater than the ion implantation dose of the second source region 207b. In the embodiment of the present application, the electrical connection between the first source region 207a and the first source electrode 212a is improved by increasing the area of ​​ohmic contact between the first source region 207a and the first source electrode 212a. Similarly, the electrical connection between the second source region 207b and the second source electrode 212b is improved by increasing the area of ​​ohmic contact between the second source region 207b and the second source electrode 212b.

[0081] The second field effect transistor M2 is completely symmetrical with the first field effect transistor M1 and has the same structure and working principle. The second field effect transistor M2 can be understood by referring to the principle description of the first field effect transistor M1, and the structure and principle of the second field effect transistor M2 will not be described in detail here.

[0082] exist Figure 2 In the illustrated embodiment, the first source well region 204a, the drain region 208 and the second source well region 204b are arranged in sequence along the short side direction of the first source electrode, the number of first source well contact regions 211a is N, and the N first source well contact regions 211a are arranged at intervals in the first source region 207a along the long side direction of the first source electrode, where N is a positive integer ≥1.

[0083] In some embodiments, in the short side direction of the first source electrode, the width of the first source well contact region 211a may be less than or equal to the width of the first source region 207a ( Figure 22 shows a case where the width of the first source well contact region 211a is smaller than the width of the first source region 207a. It should be noted that in some embodiments, the width of the first source well contact region 211a may be equal to the width of the first source region 207a. Similarly, the width of the second source well contact region 211b may be equal to or smaller than the width of the second source region 207b.

[0084] exist Figure 3-4 In the illustrated embodiment, the first gate unit 2061 includes a first portion and a second portion, wherein the first portion is formed using the first dielectric layer 202 on the semiconductor layer 201, and the second portion is formed using the polysilicon layer 206 on the first dielectric layer 202. The second gate unit 2062 includes a first portion and a second portion, wherein the first portion is formed using the first dielectric layer 202 on the semiconductor layer 201, and the second portion is formed using the polysilicon layer 206 on the first dielectric layer 202, wherein the polysilicon layer 206 has a first doping type. The first dielectric layer 202 is used as a gate oxide layer to isolate the polysilicon layer 206 from the semiconductor layer 201.

[0085] exist Figure 2-4 In the illustrated embodiment, the first source electrode 212a penetrates the second dielectric layer 209, is located above the first source well contact region 211a and is electrically connected to the first source well contact region 211a, and the first source electrode 212a is also located above the first source region 207a and is electrically connected to the first source region 207a. The second source electrode 212b penetrates the second dielectric layer 209, is located above the second source well contact region 211b and is electrically connected to the second source well contact region 211b, and the second source electrode 212b is also located above the second source region 207b and is electrically connected to the second source region 207b. The first source electrode 212a includes a first source metal filled in the first source opening region 210a, wherein the first source opening region 210a and the first source well contact region 211a are formed according to different mask plates. The first source opening region 210a is first formed by photolithography according to the opening region mask plate, and then the first source well contact region 211a is formed by ion implantation according to the source well contact region mask plate. The second source electrode 212b includes a second source metal filled in the second source opening region 210b, wherein the second source opening region 210b and the second source well contact region 211b are formed according to different masks. The second source opening region 210b is first formed by photolithography according to the opening region mask, and then the second source well contact region 211b is formed by ion implantation according to the source well contact region mask.

[0086] like Figure 2-4 As shown, a semiconductor device provided by the present application also includes an electrostatic protection device, and the electrostatic protection device includes:

[0087] A first dielectric layer 202 is disposed on the semiconductor layer 201;

[0088] A polysilicon layer 206 is disposed on the first dielectric layer 202;

[0089] The polysilicon layer 206 includes a first N-type doping region 304a and a second N-type doping region 304b, wherein a P-type doping region is located between the first N-type doping region 304a and the second N-type doping region 304b. Figure 2-4 In the embodiment shown, the first N-type doping region 304a, the P-type doping region 206 between the first N-type doping region 304a and the second N-type doping region 304b, and the second N-type doping region 304b form an NPN structure for electrostatically protecting the gate of the first transistor M1. It should be noted that Figure 2-4 The NPN structure shown is only an example. In some embodiments, there may be multiple N-type doping regions and multiple P-type doping regions to form an NPNPN structure or an NPNPNPN structure, etc. according to the withstand voltage requirements of the application.

[0090] exist Figure 2-4 In the illustrated embodiment, the P-type doping region 206, the first gate unit 2061, and the second gate unit 2062 are formed simultaneously. The first N-type doping region 304a, the second N-type doping region 304b, the first source region 207a, and the second source region 207b are formed simultaneously using the same mask.

[0091] exist Figure 2-4 In the illustrated embodiment, the semiconductor device further includes a first electrostatic protection electrode 307 and a second electrostatic protection electrode 308, wherein the first electrostatic protection electrode 307 penetrates the second dielectric layer 209, is located above the first N-type doping region 304a and is electrically connected to the first N-type doping region 304a. The second electrostatic protection electrode 308 penetrates the second dielectric layer 209, is located above the second N-type doping region 304b and is electrically connected to the second N-type doping region 304b. The first electrostatic protection electrode 307 is electrically connected to the first gate unit 2061, and the second electrostatic protection electrode 308 is electrically connected to the first source electrode 212a, providing electrostatic protection for the first field effect transistor M1. The connection direction of the electrostatic protection electrode is not limited. For example, the first electrostatic protection electrode 307 can be electrically connected to the first source electrode 212a, and the second electrostatic protection electrode 308 can be electrically connected to the first gate unit 2061.

[0092] In some embodiments, the semiconductor device may further include a third electrostatic protection electrode and a fourth electrostatic protection electrode, which are electrically connected to the second source electrode 212b and the second gate unit 2062 respectively to provide electrostatic protection for the second field effect transistor M2.

[0093] exist Figure 2-4 In the illustrated embodiment, the square resistance of the first doping type semiconductor layer 201 is 5-30 Ohm / sq.

[0094] exist Figure 2-4 In the illustrated embodiment, the first doping type is P-type doping, and the second doping type is N-type doping.

[0095] exist Figure 2-4 In the illustrated embodiment, the semiconductor device further includes an electrostatic withstand voltage region 213 , which is formed simultaneously with the isolation region 205 using the same process to increase the isolation capability between the drain well region 203 and the P-type doped region 206 .

[0096] In some embodiments, the isolation region 205 and the electrostatic withstand voltage region 213 are manufactured using a STI process or a LOCOS process. For example, the isolation region 205 may be formed by forming a trench on the surface of the semiconductor layer 201 and filling the trench with silicon oxide material.

[0097] In an embodiment of the present application, a laterally diffused metal oxide semiconductor is provided, and a common drain design is adopted between two field effect transistors, which saves chip area, allows more MOS devices to be accommodated per unit chip area, and reduces the on-resistance per unit area, thereby improving chip performance. At the same time, since the cross-sectional area of ​​the source electrode is much larger than the source well contact area, the source electrode is in contact with the source area and the source well contact area at the same time, and the large area contact between the source electrode and the source area can reduce the resistance of the MOS device, and since the contact area between the source electrode and the source well contact area of ​​the MOS device is large, the problem of parasitic diode caused by the source area and the source well contact area not being short-circuited in the prior art is avoided. Similarly, in the electrostatic protection device, the contact area between the first N-type doped region and the second N-type doped region and the electrostatic protection electrode is also large, and its ohmic contact effect is better.

[0098] The present application also provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a device area and an electrostatic protection area, and the manufacturing method includes steps S101 to S109.

[0099] Step S101: providing a semiconductor layer 201 of a first doping type.

[0100] Step S102 : forming a drain well region 203 having a second doping type in the semiconductor layer 201 .

[0101] Step S103 : forming a drain region 208 of a second doping type in the drain well region 203 .

[0102] Step S104 : forming a first source well region 204 a and a second source well region 204 b of the first doping type symmetrically disposed on both sides of the drain region 208 .

[0103] Step S105 : forming a first gate unit 2061 and a second gate unit 2062 .

[0104] Step S106: ion implantation is used to simultaneously form a first source region 207a and a second source region 207b, wherein the first source region 207a is in the first source well region 204a, and the second source region 207b is in the second source well region 204b.

[0105] Step S107: forming a first source opening region 210a and a second source opening region 210b according to the opening region mask, wherein the first source opening region 210a leaks a portion of the first source region 207a, and the second source opening region 210b leaks a portion of the second source region 207b.

[0106] Step S108: Implanting first doping type ions into the first source region 207a and the second source region 207b according to the source well contact region mask to form a first source well contact region 211a and a second source well contact region 211b.

[0107] Please refer to the following Figures 5 to 12 , a method for manufacturing a semiconductor integrated circuit is described by taking an embodiment in which the first doping type is P-type doping and the second doping type is N-type doping.

[0108] Figure 5 A schematic diagram of a semiconductor layer 201 according to an embodiment of the present application is shown. In some embodiments, the semiconductor layer 201 is doped by an ion implantation process to form a P-type doped semiconductor layer 201 .

[0109] Figure 6 FIG. 2 is a schematic diagram showing a drain well region 203 formed according to an embodiment of the present application. A portion of the semiconductor layer 201 is doped by an ion implantation process to form the drain well region 203. The drain well region 203 is doped with a different doping type from the semiconductor layer 201. In some embodiments, the N-type ion implantation dose of the drain well region 203 is 1e 12 ~5e 13 / cm 3 , the doping concentration of the drain well region 203 is greater than the doping concentration of other parts of the semiconductor layer 201. In one embodiment, the drain well region 203 can be formed by an epitaxial process.

[0110] Figure 7 The schematic diagram of forming the isolation region 205 and the electrostatic withstand voltage region 213 according to an embodiment of the present application is shown. The isolation region 205 and the electrostatic withstand voltage region 213 are formed by an STI process or a LOCOS process, and the material of the isolation region 205 is silicon oxide. It should be noted that the process flow of forming the isolation region 205 can be omitted in some embodiments.

[0111] Figure 8A schematic diagram is shown after forming the drain region 208, the first source well region 204a and the second source well region 204b according to an embodiment of the present application. Since the isolation region 205 is relatively thin, an N-type doped drain region 208 can be formed around the isolation region 205 by an ion implantation process. At the same time, a P-type doped first source well region 204a and a second source well region 204b are formed on both sides of the isolation region 205 (drain region 208) by ion implantation. The two are symmetrical to each other and are spaced apart from the drain region 208.

[0112] Fig. 9 A schematic diagram after forming a first dielectric layer 202 and a polysilicon layer 206 according to an embodiment of the present application is shown. After the polysilicon layer 206 is formed, the polysilicon layer 206 is doped to obtain a P-type doped polysilicon layer 206, which is used to form a first gate unit 2061 and a second gate unit 2062 and a P-type doped region.

[0113] Fig.10 A schematic diagram after forming the first gate unit 2061, the second gate unit 2062, the first source region 207a, and the second source region 207b according to an embodiment of the present application is shown. After removing a portion of the first dielectric layer 202 and the polysilicon layer 206, a first opening 401 exposing the first source well region 204a, a second opening 402 exposing the drain region 208, and a third opening 403 exposing the second source well region 204b are formed. The dielectric layer and the first doped type polysilicon layer 206 between the first opening 401 and the second opening 402 are configured as the first gate unit 2061, and the dielectric layer and the first doped type polysilicon layer 206 between the second opening 402 and the third opening 403 are configured as the second gate unit 2062. Ion implantation is performed through the first opening 401 to form the N-type doped first source region 207a, and ion implantation is performed through the third opening 403 to form the N-type doped second source region 207b. In one embodiment, the N-type ion implantation dosage of the first source region 207a and the second source region 207b is 1e 15 / cm 2 While forming the N-type doped first source region 207a and the second source region 207b by ion implantation, N-type ions are implanted into the polysilicon layer 206 to form the first N-type doped region 304a and the second N-type doped region 304b.

[0114] Fig.11 The second dielectric layer 209 is formed according to an embodiment of the present application. Fig.10 The second dielectric layer 209 completely covers the surface of the semiconductor layer 201 , the first gate unit 2061 and the second gate unit 2062 .

[0115] Fig.12A schematic diagram of forming a first source well contact region 211a and a second source well contact region 211b according to an embodiment of the present application is shown. First, a first source opening region 210a exposing a portion of the first source region 207a and a second source opening region 210b exposing a portion of the second source region 207b are formed in the second dielectric layer 209.

[0116] Fig.13 The schematic diagram of the superposition of the opening area mask 501 and the source well contact area mask 502 according to the embodiment of the present application is shown. In one embodiment, the first source opening area 210a, the second source opening area 210b, the first protection contact window 305 and the second protection contact window 306 are first formed according to the opening area mask 501, wherein the first source opening area 210a leaks a part of the first source area 207a, and the second source opening area 210b leaks a part of the second source area 207b. Then, according to the source well contact area mask 502, the first doping type ion implantation is used to form the first source area and the second source area. In one embodiment, according to the source well contact area mask 502, ion implantation is performed through the first source opening area 210a to form the first source well contact area 211a, and ion implantation is performed through the second source opening area 210b to form the second source well contact area 211b.

[0117] In some embodiments, the P-type ion implantation dosage for forming the first source well contact region 211a and the second source well contact region 211b is 1e 15 / cm 2 -1e 16 / cm 2 Between orders of magnitude.

[0118] In some embodiments, the width ratio of the first source opening region 210a to the first source region 207a is in the range of 0.1:1 to 1:1. The first source well contact region 211a formed by the contact window with this width ratio can enable good contact performance and current transmission efficiency between the first source region 207a and the source electrode, and the second source well contact region 211b is similar, which will not be described in detail here.

[0119] After forming a first source well contact region 211a of the first doping type through the first source opening region 210a and forming a second source well contact region 211b of the first doping type through the second source opening region 210b, the method further includes filling the first source opening region 210a with a first source metal to form a first source electrode 212a, and filling the second source opening region 210b with a second source metal to form a second source electrode 212b. Figure 2-4 A schematic diagram is shown after forming the first source electrode 212 a and the second source electrode 212 b according to an embodiment of the present application.

[0120] Regarding the manufacture of the electrostatic protection device, after step 105 , the manufacturing method of the semiconductor device further includes: forming an electrostatic protection zone mask 303 on the surface of the polysilicon layer 206 in the electrostatic protection zone, removing a portion of the electrostatic protection zone mask 303 , and forming a fourth opening 404 and a fifth opening 405 .

[0121] Fig.10 A schematic diagram is shown after a portion of the electrostatic protection zone mask 303 is removed according to an embodiment of the present application. After a portion of the electrostatic protection zone mask 303 is removed to form a fourth opening 404 and a fifth opening 405, while forming a first source region 207a and a second source region 207b by ion implantation, ion implantation is performed through the fourth opening 404 to form a first N-type doping region 304a, and ion implantation is performed through the fifth opening 405 to form a second N-type doping region 304b. The first N-type doping region 304a and the second N-type doping region 304b are N-type doped. The N-type ion implantation dose of the first N-type doping region 304a and the second N-type doping region 304b is 1e 15 / cm 2 After forming the first N-type doping region 304a and the second N-type doping region 304b, all the electrostatic protection area masks 303 are removed.

[0122] Fig.11 FIG. 2 shows a schematic diagram after forming the second dielectric layer 209 according to an embodiment of the present application. Fig.12 A schematic diagram after forming the first protection contact window 305 and the second protection contact window 306 according to an embodiment of the present application is shown, and the first protection contact window 305 exposing the first N-type doping region 304a and the second protection contact window 306 exposing the second N-type doping region 304b are formed by using the second dielectric layer 209. In some embodiments, in the first direction, the ratio of the width of the first protection contact window 305 to the width of the first N-type doping region 304a is in the range of 0.2:1 to 1:1, and a suitable width ratio can improve the protection effect and reliability of the device. Figure 3-4A schematic diagram after forming the first electrostatic protection electrode 307 and the second electrostatic protection electrode 308 according to an embodiment of the present application is shown. The first protection contact window 305 is filled with a metal material to form the first electrostatic protection electrode 307, and the second protection contact window 306 is filled with a metal material to form the second electrostatic protection electrode 308. It should be noted that, in one embodiment, while forming the source well contact region mask 502, an electrostatic protection region mask that masks the first protection contact window 305 and the second protection contact window 306 is simultaneously formed in the electrostatic protection region, so when the first source well contact region 211a and the second source well contact region 211b are formed by ion implantation, the first N-type doping region 304a and the second N-type doping region 304b exposed through the first protection contact window 305 and the second protection contact window 306 are not affected by P-type doping.

[0123] The present application also provides a method for manufacturing a semiconductor device, wherein the semiconductor device includes a device area and an electrostatic protection area, and the manufacturing method includes steps S201 to S209.

[0124] Step S201: providing a semiconductor layer of a first doping type;

[0125] Step S202: forming a drain well region having a second doping type in the semiconductor layer;

[0126] Step S203: forming a drain region of a second doping type in the drain well region;

[0127] Step S204: forming a first source well region and a second source well region of a first doping type symmetrically arranged on both sides of the drain region;

[0128] Step S205: forming a first gate unit and a second gate unit;

[0129] Step S206: forming a first source region and a second source region simultaneously by ion implantation, wherein the first source region is in the first source well region, and the second source region is in the second source well region;

[0130] Step S207: implanting first doping type ions into the first source region and the second source region according to the source well contact region mask to form a first source well contact region and a second source well contact region; and

[0131] Step S208: forming a first source opening area and a second source opening area according to the opening area mask, wherein the first source opening area leaks a portion of the first source area and a portion or all of the first source well contact area, and the second source opening area leaks a portion of the second source area and a portion or all of the second source well contact area.

[0132] In one embodiment, the first source well contact region further extends to the first source well region, and the second source well contact region further extends to the second source well region.

[0133] The above embodiment can be applied to a power protection system, such as Figure 1 As shown, the power protection system includes an input positive terminal B+, an input negative terminal B-, an output positive terminal P+, an output negative terminal P-, a first resistor R1, a first capacitor C1, a power protection chip 2 and the above-mentioned semiconductor device 3.

[0134] The input positive terminal B+ is coupled to the positive terminal of the power supply, the input negative terminal B- is coupled to the negative terminal of the power supply, the output positive terminal P+ is coupled to the positive terminal of the external circuit and coupled to the input positive terminal, and the output negative terminal P- is coupled to the negative terminal of the external circuit 4. The first resistor R1 has a first end and a second end, wherein the first end is coupled to the input positive terminal B+, the first capacitor C1 has a first end and a second end, wherein the first end is coupled to the second end of the first resistor R1, and the second end is coupled to the input negative terminal B-. The power protection chip 2 has an input end, a first output end and a second output end, wherein the input end is coupled to the second end of the first resistor R1. The first gate unit 2061 of the semiconductor device is coupled to the first output end of the power protection chip 2, the second gate unit 2062 is coupled to the second output end of the power protection chip 2, the first source well contact area 211a of the semiconductor device 3 is coupled to the input negative terminal B- through the first source electrode 212a, and the second source well contact area 211b of the semiconductor device is coupled to the output negative terminal P- through the second source electrode 212b. When the control signal of the power protection chip controls the transistors M1 and / or M2 in the semiconductor device to turn off, the power supply loop from the power supply to the external circuit is cut off.

[0135] like Figure 1 As shown, the NPN structure formed between the first electrostatic protection electrode and the second electrostatic protection electrode can be regarded as a pair of anode-coupled diodes, wherein the cathode of one diode is coupled to the first gate unit through the first electrostatic protection electrode, and the cathode of the other diode is coupled to the first source electrode through the second electrostatic protection electrode, for electrostatically protecting the gate of the first transistor M1.

[0136] In the above steps, the specific steps of using the deposition process when forming each layer can be designed according to actual needs, and the embodiments of the present application do not specifically limit this. The specific steps of using the etching process when removing each layer can be designed according to actual needs, and the embodiments of the present application do not specifically limit this. The specific steps of doping each layer can also be designed according to actual needs, wherein the number of doping regions and the doping concentration and doping ions of each doping region can be determined according to actual needs.

[0137] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0138] This document uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solution and its core idea of ​​the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or replace some of the technical features therein with equivalents; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A semiconductor device, characterized in that: include: a semiconductor layer having a first doping type; a drain well region having a second doping type and located in the semiconductor layer; a drain region having a second doping type and located in the drain well region; A first source well region and a second source well region, having a first doping type, are respectively located on both sides of the drain region; A first source region having a second doping type and located in the first source well region; a second source region having a second doping type and located in the second source well region; A first source well contact region, having a first doping type, is located in the first source region and extends to the first source well region; A second source well contact region, having a first doping type, is located in the second source region and extends to the second source well region; A first gate unit is located on the semiconductor layer, extends from the first source well region to the drain region, and covers a portion of the first source well region and a portion of the drain region; A second gate unit is located on the semiconductor layer, extends from the second source well region to the drain region, and covers a portion of the second source well region and a portion of the drain region; A first source electrode having a first portion and a second portion, the first portion of the first source electrode being located above the first source region to form an ohmic contact with the first source region, and the second portion of the first source electrode being located above the first source well contact region to form an ohmic contact with the first source well contact region; and The second source electrode has a first part and a second part. The first part of the second source electrode is located above the second source region to form an ohmic contact with the second source region. The second part of the second source electrode is located above the second source well contact region to form an ohmic contact with the second source well contact region.

2. The semiconductor device according to claim 1, wherein An isolation region is also included, and the isolation region is located above the drain region. 3 . The semiconductor device according to claim 2 , wherein the first gate unit and the second gate unit further cover a portion of the isolation region. 4 . The semiconductor device as claimed in claim 1 , wherein a doping concentration of the first source well contact region is greater than a doping concentration of the first source region. 5 . The semiconductor device according to claim 1 , wherein the first source electrode comprises a first source metal filled in a first source opening region, wherein the first source opening region and the first source well contact region are formed by photolithography using different masks. 6 . The semiconductor device as claimed in claim 1 , wherein the first source opening region is formed by photolithography first and then the first source well contact region is formed by ion implantation.

7. The semiconductor device according to claim 1, wherein: Also included is an electrostatic protection device, the electrostatic protection device comprising: A first dielectric layer, disposed on the semiconductor layer; A polysilicon layer, disposed on the first dielectric layer; The polysilicon layer includes a first N-type doping region and a second N-type doping region, wherein a P-type doping region is located between the first N-type doping region and the second N-type doping region. 8 . The semiconductor device as claimed in claim 7 , wherein the P-type doped region, the first gate unit, and the second gate unit are formed simultaneously. 9 . The semiconductor device as claimed in claim 7 , wherein the first N-type doping region, the second N-type doping region, the first source region and the second source region are formed simultaneously.

10. The semiconductor device according to claim 7, wherein: Also includes: A first electrostatic protection electrode, located above the first N-type doping region and electrically connected to the first N-type doping region; as well as The second electrostatic protection electrode is located above the second N-type doping region and is electrically connected to the second N-type doping region.

11. The semiconductor device according to claim 2, wherein: Also included is an electrostatic protection device, the electrostatic protection device comprising: The electrostatic withstand voltage region is located in the semiconductor layer, and the electrostatic withstand voltage region and the isolation region are formed simultaneously. A first dielectric layer, located on the electrostatic withstand voltage area; A polysilicon layer, disposed on the first dielectric layer; The polysilicon layer includes a first N-type doping region and a second N-type doping region, wherein a P-type doping region is located between the first N-type doping region and the second N-type doping region. 12 . The semiconductor device according to claim 1 , wherein the first doping type is P-type doping, and the second doping type is N-type doping.

13. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor layer of a first doping type; forming a drain well region having a second doping type in the semiconductor layer; forming a drain region of a second doping type in the drain well region; Forming a first source well region and a second source well region of a first doping type symmetrically disposed on both sides of the drain region; forming a first gate unit and a second gate unit; Simultaneously forming a first source region and a second source region by ion implantation, wherein the first source region is in a first source well region, and the second source region is in a second source well region; Forming a first source opening region and a second source opening region according to the opening region mask, wherein the first source opening region leaks a portion of the first source region, and the second source opening region leaks a portion of the second source region; as well as Ions of the first doping type are implanted in the first source region and the second source region according to the source-well contact region mask to form a first source-well contact region and a second source-well contact region.

14. The manufacturing method according to claim 13, characterized in that: Also includes: An isolation region is formed above the drain region, wherein the isolation region is formed by an STI process or a LOCOS process. 15 . The manufacturing method according to claim 13 , wherein ion implantation is performed on polysilicon in the electrostatic protection area while forming the first source region and the second source region to form the first N-type doping region and the second N-type doping region. 16 . The manufacturing method according to claim 13 , wherein the first source well contact region further extends to the first source well region, and the second source well contact region further extends to the second source well region.

17. A method for manufacturing a semiconductor device, characterized in that: include: providing a semiconductor layer of a first doping type; forming a drain well region having a second doping type in the semiconductor layer; forming a drain region of a second doping type in the drain well region; Forming a first source well region and a second source well region of a first doping type symmetrically disposed on both sides of the drain region; forming a first gate unit and a second gate unit; Simultaneously forming a first source region and a second source region by ion implantation, wherein the first source region is in a first source well region, and the second source region is in a second source well region; Implanting first doping type ions into the first source region and the second source region according to the source well contact region mask to form a first source well contact region and a second source well contact region; and A first source opening area and a second source opening area are formed according to the opening area mask, wherein the first source opening area leaks a portion of the first source area and a portion or all of the first source well contact area, and the second source opening area leaks a portion of the second source area and a portion or all of the second source well contact area. 18 . The manufacturing method according to claim 17 , wherein the first source well contact region further extends to the first source well region, and the second source well contact region further extends to the second source well region.

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