Secondary voltage feedback system for packaging impedance voltage drop of ceramic packaging FPGA

Abstract

The invention belongs to the field of circuit application, particularly relates to a secondary voltage feedback system for packaging impedance voltage drop of a ceramic packaging FPGA (Field Programmable Gate Array), and aims to solve the problem that the voltage drop generated by packaging of a ceramic packaging chip cannot be compensated in the conventional method. The method comprises the steps that a sampling point of a feedback loop of a switching power supply is connected to a power supply pin on the back surface of an FPGA chip; the first end of the DAC is connected to the FPGA chip and is used for communicating with the FPGA chip; and the second end of the DAC is connected to an FB pin of a feedback loop of the switching power supply, and is used for outputting current or sucking current, so that the output voltage of the switching power supply is adjusted, and the voltage drop generated by the ceramic packaging FPGA due to packaging impedance is compensated. According to the invention, the voltage compensation of the voltage drop generated by the packaging impedance of the ceramic packaging FPGA is realized, and the stability of the internal voltage of the FPGA is ensured.

Description

Background Art

[0002] In electronic systems with high reliability requirements, the types of high-reliability components in ceramic packages are increasing. The package voltage drop of many ceramic packaged devices is larger than that of plastic packages. When high-power components such as FPGA are in high-power conditions, the core voltage and current are as high as tens of amperes. Under this condition, the impedance of the ceramic package reaches the milliohm level. At this time, the voltage drop (IRDrop) generated by the package cannot be ignored for FPGA. At present, the feedback network of the power chip can only compensate for the voltage drop caused by the wiring on the PCB, but cannot compensate for the voltage drop generated by the ceramic package chip. And because the working current is different under different working conditions of FPGA, the voltage drop generated by the FPGA ceramic package will also change with the change of current, which leads to the fixed value compensation method of increasing the voltage of the switching power supply feedback sampling point by changing the resistance value of the feedback resistor (this method is to output 1.0V originally, but it is designed to output 1.02V, and the extra 0.02V is used to compensate for the voltage drop of the package, but the voltage drop of the package is not 0.02V constant, and this voltage drop may almost not exist when the power consumption is low.), which will cause the voltage value of the FPGA to be too large under low power consumption conditions.

[0003] Therefore, the existing method has the problem of being unable to compensate for the voltage drop caused by the packaging of the ceramic packaged chip. Summary of the invention

[0004] In order to solve the above-mentioned problem in the prior art, that is, the existing method cannot compensate for the voltage drop caused by the packaging of the ceramic packaged chip, the present invention provides a secondary voltage feedback system for the package impedance voltage drop of the ceramic packaged FPGA, the system comprising:

[0005] FPGA chips in ceramic packages, switching power supplies with feedback loops, and DACs with communication functions that can sink or source current;

[0006] The sampling point of the feedback loop of the switching power supply is connected to the power pin on the back of the FPGA chip; the first end of the DAC is connected to the FPGA chip for communicating with the FPGA chip; the second end of the DAC is connected to the FB pin of the feedback loop of the switching power supply for outputting current or sucking current, adjusting the output voltage of the switching power supply and ultimately making the core voltage inside the FPGA chip reach the desired value.

[0007] In a preferred embodiment, the connection method of the DAC also includes: the second end of the DAC, the FB pin, the second end of the first resistor R1, and the first end of the second resistor R2 are commonly connected to the first node; the second end of the second resistor is grounded; the first end of the first resistor is connected to the differential output end of the switching power supply, and the output voltage setting value of the switching power supply is adjusted by setting the resistance values ​​of the first resistor R1 and the second resistor R2.

[0008] In a preferred embodiment, the connection method of the switching power supply also includes: the positive pin and the negative pin of the remote sampling point of the switching power supply are respectively connected to the power supply end and the ground end of the power capacitor pin on the back of the FPGA chip, so as to realize the first-level feedback of the switching power supply, which is used to compensate for the PCB trace voltage drop from the output voltage V1 of the switching power supply to the proximal voltage V2 of the FPGA chip, and keep the proximal voltage V2 of the FPGA chip unchanged; in this feedback mode, the proximal voltage V2 of the FPGA chip reaches the expected value.

[0009] In a preferred implementation, the FPGA chip has an XADC inside, and the XADC is used to detect the actual core voltage inside the FPGA chip.

[0010] In a second aspect of the present invention, a secondary voltage feedback method for a package impedance voltage drop of a ceramic packaged FPGA is proposed. The method is based on the secondary voltage feedback system for the package impedance voltage drop of the ceramic packaged FPGA. The method includes: subtracting the chip internal voltage value detected by the XADC inside the FPGA chip from the expected value to obtain a first difference value. The sum of the first difference value and the FPGA chip proximal voltage V2 is the expected value of the FPGA chip proximal voltage V2. The first difference value is the FPGA chip package voltage drop that needs to be compensated.

[0001] By sucking current from the feedback loop of the switching power supply through the second end of the DAC, the output voltage of the switching power supply can be changed, and the proximal voltage V2 of the FPGA chip can be increased to compensate for the voltage drop caused by the FPGA package so that the internal voltage of the FPGA chip reaches the expected value.

[0002] By sucking current from the feedback loop of the switching power supply through the second end of the DAC, the output voltage of the switching power supply can be changed, and the voltage of the FPGA chip proximal voltage V2 can be increased by a first difference to compensate for the voltage drop caused by the FPGA package.

[0003] In a preferred embodiment, the current is sucked from the feedback loop of the switching power supply through the second end of the DAC, so that the output voltage of the switching power supply can be changed, and the voltage V2 near the FPGA chip can be increased to compensate for the voltage drop caused by the FPGA package, so that the internal voltage of the FPGA chip reaches the expected value, including:

[0004] The first difference is obtained by subtracting the internal voltage value of the chip detected by the XADC inside the FPGA chip from the expected value;

[0005] The first current value obtained by dividing the first difference by the first resistance value is the first current value that the DAC needs to absorb;

[0006] According to the DAC accuracy, a second current value that is closest to the first current value that the DAC can absorb is calculated;

[0007] The FPGA chip communicates with the first end of the DAC through the IO interface, where the communication protocol is SPI or I 2 C, causing the second end of the DAC to absorb a second current value;

[0008] The output voltage of the switching power supply is adjusted by sucking a current of a second current value from the switching power supply through the second end of the DAC to compensate for the voltage drop caused by the FPGA chip package at this time, thereby realizing the second-level feedback and completing the adjustment.

[0009] In a third aspect of the present invention, an electronic device is proposed, comprising: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned secondary voltage feedback method for the package impedance voltage drop of a ceramic packaged FPGA.

[0010] In a fourth aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned secondary voltage feedback method for the package impedance voltage drop of the ceramic packaged FPGA.

[0011] Beneficial effects of the present invention:

[0012] (1) This application uses a high-precision DAC to pull the voltage at the feedback pin of the switching power supply to compensate for the voltage drop of the ceramic package FPGA package, thereby achieving voltage compensation for the voltage drop caused by the package impedance of the ceramic package FPGA, ensuring the stability of the FPGA power supply voltage and avoiding abnormal operation caused by too low internal voltage of the FPGA;

[0013] (2) In the present application, the positive and negative pins of the remote sampling point are connected to the power supply end and the ground end of the power supply 0402 capacitor pin on the back of the FPGA respectively. This connection method can realize the voltage compensation of the PCB impedance drop (IR Drop) from the power supply output to the bottom of the FPGA, and realize a more accurate voltage feedback function; by calculating the difference between the actual core voltage and the expected core voltage, the value of the FPGA proximal voltage V2 is calculated, and by adjusting the current sucked by the DAC, the voltage of the switching power supply output V1 is increased, and then the voltage of V2 is increased to compensate for the impedance generated by the FPGA package, thereby realizing accurate adjustment.

[0014] (3) Using the system of the present application to adjust the pressure drop can stabilize the supply pressure of the device, thereby improving the overall reliability and stability of the system, extending the service life of the device, and reducing maintenance costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Other features, objects and advantages of the present application will become more apparent by reading the detailed description of non-limiting embodiments made with reference to the following drawings:

[0016] Figure 1 It is a secondary voltage feedback system for the package impedance voltage drop of ceramic packaged FPGA;

[0017] Figure 2 It is a structural diagram of a computer system of a server for implementing the method, system, and device embodiments of the present application. DETAILED DESCRIPTION

[0018] The present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It is to be understood that the specific embodiments described herein are only used to explain the relevant invention, rather than to limit the invention. It is also necessary to explain that, for ease of description, only the parts related to the relevant invention are shown in the accompanying drawings.

[0019] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present application can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in combination with the embodiments.

[0020] The present invention provides a secondary voltage feedback system for package impedance voltage drop of ceramic packaged FPGA, the system comprising:

[0021] FPGA chips in ceramic packages, switching power supplies with feedback loops, and DACs with communication functions that can sink or source current;

[0022] The sampling point of the feedback loop of the switching power supply is connected to the power pin on the back of the FPGA chip; the first end (control end) of the DAC is connected to the FPGA chip for communicating with the FPGA chip; the second end (output / input end) of the DAC is connected to the FB pin of the feedback loop of the switching power supply for outputting current or sucking current, adjusting the output voltage of the switching power supply and ultimately making the core voltage inside the FPGA chip reach the desired value.

[0023] In order to more clearly explain the secondary voltage feedback system for the package impedance voltage drop of the ceramic package FPGA of the present invention, the following is combined with Figure 1 Each module in the embodiment of the present invention is described in detail.

[0024] The second-level voltage feedback system for the package impedance voltage drop of a ceramic packaged FPGA according to the first embodiment of the present invention, each module is described in detail as follows:

[0025] A ceramic-packaged FPGA chip, a switching power supply with a feedback loop, and a DAC with communication function that can absorb or output current; the sampling point of the feedback loop of the switching power supply is connected to the power pin on the back of the FPGA chip; the first end of the DAC is connected to the FPGA chip for communicating with the FPGA chip; the second end of the DAC is connected to the FB pin of the feedback loop of the switching power supply for outputting current or absorbing current, and adjusting the output voltage of the switching power supply to ultimately make the core voltage inside the FPGA chip reach the desired value.

[0026] In this embodiment, the FPGA chip is a ceramic packaged FPGA chip selected for a high reliability product;

[0027] In this embodiment, if the power supply has a remote sampling op amp function, a more accurate voltage feedback function can be achieved. The sampling point of the feedback loop of the switching power supply is connected to the power pin on the back of the FPGA chip; the first end (control end) of the DAC is connected to the FPGA chip for communicating with the FPGA chip; the second end (output / input end) of the DAC is connected to the FB pin of the feedback loop of the switching power supply for outputting current or sucking current, thereby adjusting the voltage of the FB pin of the feedback loop of the switching power supply to adjust the output voltage of the switching power supply and finally make the core voltage inside the FPGA chip reach the expected value. This connection method can achieve voltage compensation from the output voltage of the power supply to the PCB impedance drop (IR Drop) at the bottom of the FPGA.

[0028] In this embodiment, the connection method of the DAC also includes: the second end of the DAC, the FB pin, the second end of the first resistor R1, and the first end of the second resistor R2 are commonly connected to the first node; the second end of the second resistor is grounded; and the first end of the first resistor is connected to the differential output end of the switching power supply. By setting the resistance values ​​of the first resistor R1 and the second resistor R2, the output voltage setting value of the switching power supply is adjusted.

[0029] In this embodiment, the connection method of the switching power supply also includes: the connection method of the switching power supply also includes: the positive pin and the negative pin of the remote sampling point of the switching power supply are respectively connected to the power supply end and the ground end of the power capacitor pin on the back of the FPGA chip, which are used to compensate for the PCB trace voltage drop from the output voltage V1 of the switching power supply to the proximal voltage V2 of the FPGA chip; when working in this feedback mode, the proximal voltage V2 of the FPGA chip reaches the expected value.

[0030] In this embodiment, the FPGA chip has an XADC inside, and the XADC is used to detect the actual core voltage inside the FPGA chip.

[0031] It should be noted that the secondary voltage feedback system for the package impedance voltage drop of the ceramic packaged FPGA provided in the above embodiment is only illustrated by the division of the above functional modules. In practical applications, the above functions can be assigned to different functional modules as needed, that is, the modules or steps in the embodiments of the present invention can be decomposed or combined. For example, the modules in the above embodiments can be combined into one module, or further divided into multiple sub-modules to complete all or part of the functions described above. The names of the modules and steps involved in the embodiments of the present invention are only for distinguishing the modules or steps, and are not regarded as improper limitations of the present invention.

[0032] Since the package impedance of ceramic packaged devices is larger than that of plastic packaged devices, when the FPGA is working in a high power state, the core voltage and current are large, and the voltage drop (IR Drop) caused by the package impedance will increase; therefore, the second embodiment of the present invention is a secondary voltage feedback method for the package impedance voltage drop of ceramic packaged FPGA, based on the above-mentioned secondary voltage feedback system for the package impedance voltage drop of ceramic packaged FPGA, and the method includes:

[0033] The first difference is obtained by subtracting the chip internal voltage value detected by the XADC inside the FPGA chip from the expected value. The sum of the first difference value and the FPGA chip proximal voltage V2 is the expected value of the FPGA chip proximal voltage V2. The first difference value is the FPGA chip package voltage drop that needs to be compensated.

[0034] By sucking current from the feedback loop of the switching power supply through the second end of the DAC, the output voltage of the switching power supply can be changed, and the proximal voltage V2 of the FPGA chip can be increased to compensate for the voltage drop caused by the FPGA package so that the internal voltage of the FPGA chip reaches the expected value.

[0035] By sucking current from the feedback loop of the switching power supply through the second end of the DAC, the output voltage of the switching power supply can be changed, and the voltage V2 near the FPGA chip can be increased to compensate for the voltage drop caused by the FPGA package, so that the internal voltage of the FPGA chip reaches the expected value, including:

[0036] The first difference is obtained by subtracting the internal voltage value of the chip detected by the XADC inside the FPGA chip from the expected value;

[0037] The first current value obtained by dividing the first difference by the first resistance value is the first current value that the DAC needs to absorb;

[0038] According to the DAC accuracy, a second current value that is closest to the first current value that the DAC can absorb is calculated;

[0039] The FPGA chip communicates with the first end of the DAC through the IO interface, where the communication protocol is SPI or I2 C, causing the second end of the DAC to absorb a second current value;

[0040] The output voltage of the switching power supply is adjusted by sucking a current of a second current value from the switching power supply through the second end of the DAC to compensate for the voltage drop caused by the FPGA chip package at this time, thereby realizing the second-level feedback and completing the adjustment.

[0041] The set power supply output voltage V0, the reference voltage Vref marked in the switching power supply manual, and the values ​​of R1 and R2 are calculated based on V0 and Vref. These are known quantities. When calculating the DAC current later, the above quantities remain unchanged.

[0042] Depending on the different usage scenarios of the FPGA, the amount of current required by the FPGA changes, and the package impedance voltage drop is different, resulting in different core voltages detected by the XADC inside the FPGA chip. This is an unknown quantity.

[0043] The first difference is obtained by subtracting the internal voltage value of the chip detected by the XADC inside the FPGA chip from the set voltage value V0; because the feedback loop is connected to the back of the FPGA, the proximal voltage of the FPGA chip V2 = V0;

[0044] The first current value obtained by dividing the first difference by the first resistance value is the current value that the DAC needs to absorb;

[0045] In this embodiment, the adjustment process is specifically based on the formula V=IR, where V is the voltage drop in millivolts, I is the current of the core voltage in amperes, and R is the package impedance in milliohms. When the package impedance is constant, the greater the core voltage and current, the greater the voltage drop. The core voltage and current will change as the working state of the FPGA changes.

[0046] The FPGA can communicate with the DAC to change the size of the DAC output current or the suction current to adjust the feedback pin voltage of the switching power supply, thereby adjusting the size of the switching power supply output voltage.

[0047] By changing the DAC output current or inhaled current, the XADC inside the FPGA can detect the core voltage inside the FPGA chip.

[0048] The difference between the voltage detected by the XADC inside the FPGA and the expected voltage is used to calculate the current that the DAC needs to absorb under different differences through a formula. The current value absorbed by the DAC is adjusted in real time through communication between the FPGA and the DAC, and the voltage near the FPGA under different working conditions is adjusted in real time, thereby realizing dynamic compensation for the voltage drop of the ceramic package FPGA package.

[0049] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the system described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here.

[0050] Although the various steps in the above embodiment are described in the above-mentioned order, those skilled in the art can understand that in order to achieve the effect of this embodiment, different steps do not have to be executed in such an order. They can be executed simultaneously (in parallel) or in a reverse order. These simple changes are within the scope of protection of the present invention.

[0051] An electronic device according to the third embodiment of the present invention comprises: at least one processor; and a memory communicatively connected to at least one of the processors; wherein the memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the above-mentioned secondary voltage feedback method for the package impedance voltage drop of a ceramic packaged FPGA.

[0052] A computer-readable storage medium according to a fourth embodiment of the present invention stores computer instructions, and the computer instructions are used to be executed by the computer to implement the above-mentioned secondary voltage feedback method for the package impedance voltage drop of a ceramic packaged FPGA.

[0053] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working process and related instructions of the storage device and processing device described above can refer to the corresponding process in the aforementioned method embodiment and will not be repeated here.

[0054] Those skilled in the art should be able to appreciate that the modules and method steps of each example described in conjunction with the embodiments disclosed herein can be implemented with electronic hardware, computer software or a combination of the two, and the programs corresponding to the software modules and method steps can be placed in random access memory (RAM), internal memory, read-only memory (ROM), electrically programmable ROM, electrically erasable programmable ROM, registers, hard disks, removable disks, CD-ROMs, or any other form of storage medium known in the technical field. In order to clearly illustrate the interchangeability of electronic hardware and software, the composition and steps of each example have been generally described in the above description according to the function. Whether these functions are performed in electronic hardware or software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0055] Reference below Figure 2, which shows a schematic diagram of the structure of a computer system of a server for implementing the method, system, and device embodiments of the present application. Figure 2 The server shown is merely an example and should not bring any limitation to the functions and scope of use of the embodiments of the present application.

[0056] like Figure 2 As shown, the computer system includes a central processing unit (CPU) 601, which can perform various appropriate actions and processes according to the program stored in the read-only memory (ROM) 602 or the program loaded from the storage part 608 to the random access memory (RAM) 603. Various programs and data required for system operation are also stored in the RAM 603. The CPU 601, ROM 602 and RAM 603 are connected to each other through a bus 604. An input / output (I / O) interface 605 is also connected to the bus 604.

[0057] The following components are connected to the I / O interface 605: an input section 606 including a keyboard, a mouse, etc.; an output section 607 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker; a storage section 608 including a hard disk, etc.; and a communication section 609 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 609 performs communication processing via a network such as the Internet. A drive 610 is also connected to the I / O interface 605 as needed. A removable medium 611, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 610 as needed so that a computer program read therefrom is installed into the storage section 608 as needed.

[0058] In particular, according to an embodiment of the present disclosure, the process described above with reference to the flowchart can be implemented as a computer software program. For example, an embodiment of the present disclosure includes a computer program product, which includes a computer program carried on a computer-readable medium, and the computer program includes a program code for executing the method shown in the flowchart. In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 609, and / or installed from the removable medium 611. When the computer program is executed by the central processing unit (CPU) 601, the above-mentioned functions defined in the method of the present application are executed. It should be noted that the above-mentioned computer-readable medium of the present application can be a computer-readable signal medium or a computer-readable storage medium or any combination of the above two. The computer-readable storage medium can be, for example, - but not limited to - an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device or device, or any combination of the above. More specific examples of computer-readable storage media may include, but are not limited to, an electrical connection with one or more conductors, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present application, a computer-readable storage medium may be any tangible medium containing or storing a program that can be used by or in combination with an instruction execution system, an apparatus or a device. In the present application, a computer-readable signal medium may include a data signal propagated in a baseband or as part of a carrier wave, which carries a computer-readable program code. Such propagated data signals may take a variety of forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium may also be any computer-readable medium other than a computer-readable storage medium, which may send, propagate, or transmit a program for use by or in combination with an instruction execution system, an apparatus or a device. The program code contained on the computer-readable medium may be transmitted using any appropriate medium, including but not limited to: wireless, wire, optical cable, RF, etc., or any suitable combination of the above.

[0059] Computer program code for performing the operations of the present application may be written in one or more programming languages ​​or a combination thereof, including object-oriented programming languages, such as Java, Smalltalk, C++, and conventional procedural programming languages, such as "C" or similar programming languages. The program code may be executed entirely on the user's computer, partially on the user's computer, as a separate software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving a remote computer, the remote computer may be connected to the user's computer via any type of network, including a local area network (LAN) or a wide area network (WAN), or may be connected to an external computer (e.g., via the Internet using an Internet service provider).

[0060] The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present application. In this regard, each square box in the flow chart or block diagram can represent a module, a program segment or a part of a code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the square box can also occur in a sequence different from that marked in the accompanying drawings. For example, two square boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each square box in the block diagram and / or flow chart, and the combination of the square boxes in the block diagram and / or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0061] The terms "first", "second", etc. are used to distinguish similar objects rather than to describe or indicate a particular order or sequence.

[0062] The term "comprise" or any other similar term is intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus / device that includes a list of elements includes not only those elements but also other elements not expressly listed, or also includes elements inherent to such process, method, article, or apparatus / device.

[0063] So far, the technical solutions of the present invention have been described in conjunction with the preferred embodiments shown in the accompanying drawings. However, it is easy for those skilled in the art to understand that the protection scope of the present invention is obviously not limited to these specific embodiments. Without departing from the principle of the present invention, those skilled in the art can make equivalent changes or substitutions to the relevant technical features, and the technical solutions after these changes or substitutions will fall within the protection scope of the present invention.

Claims

1. A secondary voltage feedback system for package impedance voltage drop of ceramic packaged FPGA, characterized in that: The system comprises: FPGA chips in ceramic packages, switching power supplies with feedback loops, and DACs with communication functions that can sink or source current; The sampling point of the feedback loop of the switching power supply is connected to the power pin on the back of the FPGA chip; the first end of the DAC is connected to the FPGA chip for communicating with the FPGA chip; the second end of the DAC is connected to the FB pin of the feedback loop of the switching power supply for outputting current or sucking current, adjusting the output voltage of the switching power supply and ultimately making the core voltage inside the FPGA chip reach the desired value.

2. The secondary voltage feedback system for package impedance drop of ceramic packaged FPGA according to claim 1, characterized in that: The connection method of the DAC also includes: the second end of the DAC, the FB pin, the second end of the first resistor R1, and the first end of the second resistor R2 are commonly connected to the first node; the second end of the second resistor is grounded; the first end of the first resistor is connected to the differential output end of the switching power supply, and the output voltage setting value of the switching power supply is adjusted by setting the resistance values ​​of the first resistor R1 and the second resistor R2.

3. The secondary voltage feedback system for package impedance drop of ceramic packaged FPGA according to claim 2, characterized in that: The first-stage voltage feedback connection method of the switching power supply also includes: the positive pin and the negative pin of the remote sampling point of the switching power supply are respectively connected to the power supply end and the ground end of the power capacitor pin on the back of the FPGA chip, which are used to compensate for the PCB trace voltage drop from the output voltage V1 of the switching power supply to the proximal voltage V2 of the FPGA chip; when working in this feedback mode, the proximal voltage V2 of the FPGA chip reaches the expected value.

4. The secondary voltage feedback system for package impedance voltage drop of ceramic packaged FPGA according to claim 3, characterized in that: The FPGA chip has an XADC inside, and the XADC is used to detect the actual core voltage inside the FPGA chip.

5. A secondary voltage feedback method for package impedance voltage drop of ceramic packaged FPGA, based on the secondary voltage feedback system for package impedance voltage drop of ceramic packaged FPGA as described in any one of claims 1 to 4, wherein the second-level voltage feedback is characterized in that the method comprises: The first difference is obtained by subtracting the chip internal voltage value detected by the XADC inside the FPGA chip from the expected value. The sum of the first difference value and the FPGA chip proximal voltage V2 is the expected value of the FPGA chip proximal voltage V2. The first difference value is the FPGA chip package voltage drop that needs to be compensated. By sucking current from the feedback loop of the switching power supply through the second end of the DAC, the output voltage of the switching power supply can be changed, and the proximal voltage V2 of the FPGA chip can be increased to compensate for the voltage drop caused by the FPGA package so that the internal voltage of the FPGA chip reaches the expected value.

6. The secondary voltage feedback method for package impedance voltage drop of ceramic packaged FPGA according to claim 5, characterized in that: By sucking current from the feedback loop of the switching power supply through the second end of the DAC, the output voltage of the switching power supply can be changed, and the voltage V2 near the FPGA chip can be increased to compensate for the voltage drop caused by the FPGA package, so that the internal voltage of the FPGA chip reaches the expected value, including: The first difference is obtained by subtracting the internal voltage value of the chip detected by the XADC inside the FPGA chip from the expected value; The first current value obtained by dividing the first difference by the first resistance value is the first current value that the DAC needs to absorb; According to the DAC accuracy, a second current value that is closest to the first current value that the DAC can absorb is calculated; The FPGA chip communicates with the first end of the DAC through the IO interface, where the communication protocol is SPI or I 2 C, causing the second end of the DAC to absorb a second current value; The output voltage of the switching power supply is adjusted by sucking a current of a second current value from the switching power supply through the second end of the DAC, thereby compensating for the voltage drop caused by the FPGA chip package, realizing the second-level feedback, and completing the adjustment.

7. An electronic device, characterized in that: include: at least one processor; as well as a memory communicatively connected to at least one of the processors; wherein, The memory stores instructions executable by the processor, and the instructions are used to be executed by the processor to implement the secondary voltage feedback method for package impedance voltage drop of ceramic packaged FPGA as described in any one of claims 5-6.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to be executed by the computer to implement the secondary voltage feedback method for the package impedance voltage drop of the ceramic packaged FPGA as described in any one of claims 5-6.

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