Process method for eliminating antenna effect of power device with ESD (Electro-Static Discharge) structure

Abstract

The invention discloses a process method for eliminating an antenna effect of a power device with an ESD (Electro-Static Discharge) structure, which comprises the following steps of: after etching a polycrystalline silicon grid of the power device, depositing to form a silicon nitride layer; forming an ESD (Electro-Static Discharge) oxide layer on the silicon nitride layer, and depositing a polycrystalline silicon layer on the ESD oxide layer; performing ion implantation of the ESD structure; carrying out photoetching and etching on the polycrystalline silicon layer of the ESD structure, completing pattern formation of the polycrystalline silicon structure in the ESD structure, and then carrying out thermal annealing; carrying out a wet etching process of the ESD oxide layer, and removing the redundant ESD oxide layer; removing the silicon nitride layer by a wet etching process; and performing body region injection of the power device. SiN is introduced to serve as a barrier layer for wet etching of the ESD oxide layer, the antenna effect caused by ESD OX local over-etching can be effectively prevented, the convergence of BV voltage resistance and IDSS electric leakage is improved, and the occurrence probability of low product yield can be remarkably reduced.

Description

Technical Field

[0001] The invention relates to the field of semiconductor device technology, and in particular to a process method for eliminating antenna effect of a power device with an ESD structure. Background Art

[0002] In order to prevent power devices (POWER MOS) from being damaged by electrostatic discharge (ESD) and causing the oxide layer, PN junction and even insulation layer to break down, polysilicon diode protection structures are introduced into power devices to form ESD protection structures to enhance the device's anti-static ability. Below the ESD polysilicon layer with a thickness of about 6000Å is a thermal oxide layer (thermal OX) and an APCVD NSG layer (Nondoped Silicate Glass) with a thickness of about 2000Å, while the polysilicon layer is covered with an interlayer dielectric layer ILD.

[0003] The conventional process flow of the ESD structure is to insert an ESD loop process between the gate polysilicon etching and the body implantation process of the power device, including: The polysilicon process after gate trench etching, followed by the formation of the CVD layer below the ESD and the deposition of the ESD polysilicon layer, ESD ion implantation and photolithography, polysilicon dry etching process, annealing and wet etching process of the oxide layer, body region implantation and source region implantation, and then the contact hole process, including isolation layer, metal tungsten deposition and back etching, etc.

[0004] In the above process, the ESD loop process needs to use wet etching to remove the 2000Å APCVD NSG layer before conventional body and source region implantation. Due to the insufficient density of the APCVD NSG film layer, there is a greater risk of excessive wet etching in the wafer, which may cause the thinner thermal oxide layer on the gate polysilicon surface to be etched through and damage the gate oxide layer on the trench sidewalls, such as Figure 1 and Figure 2 As shown. The gate polysilicon is prone to accumulate more ESD. The charging process of the ion implantation process during the polysilicon dry etching process triggers the antenna effect (the antenna effect in the semiconductor process means that the polysilicon in the semiconductor process will collect charges like an overlong metal wire. The charges come from various plasma-related processes. If the polysilicon gate accumulates too much charge, it will cause the gate oxide layer to break down, causing the MOS tube to fail), resulting in device failure. Summary of the invention

[0005] The technical problem to be solved by the present invention is to provide a process method for eliminating the antenna effect of a power device with an ESD structure.

[0006] In order to solve the above problems, a process for eliminating the antenna effect of a power device with an ESD structure according to the present invention comprises: After the polysilicon gate etching of the power device is completed and before the oxide layer forming process of the ESD structure, a silicon nitride layer is first deposited on the surface of the device, and then the ESD structure forming process is performed.

[0007] Furthermore, the silicon nitride layer is formed by deposition using a furnace tube process.

[0008] Furthermore, the thickness of the silicon nitride layer is 60Å.

[0009] The process of the present invention comprises: After etching the polysilicon gate of the power device, a silicon nitride layer is first deposited; forming an ESD oxide layer on the silicon nitride layer, and depositing a polysilicon layer on the ESD oxide layer; Perform ion implantation of ESD structures; Performing photolithography and etching of the polysilicon layer of the ESD structure to complete pattern formation of the polysilicon structure in the ESD structure, and then performing thermal annealing; Performing a wet etching process on the ESD oxide layer to remove excess ESD oxide layer; Removing the silicon nitride layer by wet etching process; Perform body implantation of power devices.

[0010] Furthermore, the silicon nitride layer is used as an etching barrier layer in the wet etching process of the ESD oxide layer to prevent the antenna effect caused by local over-etching during the wet etching process of the ESD oxide layer.

[0011] Furthermore, the wet etching process for removing the silicon nitride layer is to completely remove the silicon nitride layer using a phosphoric acid solution.

[0012] The process method for eliminating the antenna effect of a power device with an ESD structure described in the present invention adds a step of forming an etching barrier layer in time after etching the polysilicon gate, forms an etching barrier during the wet etching of the ESD oxide layer, prevents local over-etching, reduces the impact of the wet etching of the ESD oxide layer on the polysilicon layer, significantly improves the BV withstand voltage characteristics and the convergence of the IDSS leakage of the power device, and can effectively improve the yield. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figures 1-2 It is a schematic diagram illustrating the antenna effect of polysilicon.

[0014] Figure 3This is a micrograph of the damage to the gate oxide layer on the top sidewall of the trench under the existing process.

[0015] Figure 4 It is a microscopic picture of the gate oxide layer on the sidewall of the top of the trench under the process of the present invention.

[0016] Figure 5 It is a flow chart of the process steps of the present invention (mainly the ESD structure process part). DETAILED DESCRIPTION

[0017] The following is a specific implementation of the present invention in conjunction with the accompanying drawings, and the technical solutions in the present invention are clearly and completely described, but the present invention is not limited to the following implementations. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise ratios, which are only used to conveniently and clearly assist in explaining the embodiments of the present invention. All other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0018] The present invention can be implemented in different forms and should not be interpreted as being limited to the embodiments proposed herein. On the contrary, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the present invention to those skilled in the art. In the accompanying drawings, for clarity, the size and relative size of the layers and zones may be exaggerated, and the same reference numerals represent the same elements from beginning to end. In the description of the present application, it should be noted that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "left", "right", "vertical", "horizontal", "inside", "outside", etc. is based on the orientation or positional relationship shown in the accompanying drawings, only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present application. In addition, the terms "first", "second", and "third" are only used for descriptive purposes and cannot be understood as indicating or implying relative importance.

[0019] The present invention provides a new process method, which aims at the problem that power devices with ESD structures are prone to antenna effect under existing processes. The method mainly comprises depositing a 60Å thick SiN layer using a furnace tube machine after etching of gate polysilicon and before deposition of ESD oxide layer and ESD polysilicon, so as to serve as an etching stop layer after subsequent wet etching of the ESD oxide layer, thereby effectively preventing local over-etching of ESD OX and thus avoiding device failure caused by the polysilicon antenna effect.

[0020] Specifically, the process comprises: First, after the polysilicon gate in the power device structure is etched, a layer of silicon nitride is first deposited on the surface of the wafer using a furnace tube process, and the deposition thickness of the silicon nitride layer is about 60Å.

[0021] After the silicon nitride layer is deposited, an ESD oxide layer is formed on the silicon nitride layer according to conventional processes. The thickness of the ESD oxide layer is about 2000Å, and it is deposited by APCVD process. Then a polysilicon layer is deposited on the ESD oxide layer. The polysilicon layer is the ESD polysilicon layer that forms the ESD structure. The thickness of the ESD polysilicon layer is generally 6000Å.

[0022] Perform ion implantation of the ESD structure. The type of ion implantation is selected according to the N-type or P-type product, such as implantation B.

[0023] Performing photolithography and etching of the polysilicon layer of the ESD structure to complete pattern formation of the polysilicon structure in the ESD structure, and then performing thermal annealing; A wet etching process is performed on the ESD oxide layer to remove excess ESD oxide layer.

[0024] Then, a wet etching process is used to remove the silicon nitride layer. The silicon nitride layer is used as an etching barrier layer in the wet etching process of the ESD oxide layer in the previous step. Since the ESD oxide layer is deposited by the APCVD process, its structure is not dense enough, which can easily cause the polysilicon layer of the power device to be over-etched in the wet etching process of the ESD oxide layer. The added silicon nitride layer can effectively prevent local over-etching of the ESD oxide layer. The wet etching removal process of the silicon nitride layer uses a phosphoric acid solution to completely remove the silicon nitride layer.

[0025] Then the manufacturing process of the power device is carried out, including the implantation of the body region and source region.

[0026] The process method provided by the present invention solves the defect of damage to the gate oxide layer at the sidewall of the trench top in the traditional process, such as Figure 3 and Figure 4 Comparison micrographs. The optimized ESD process introduces a SiN layer as a barrier layer in the wet etching process of the ESD oxide layer. After the wet etching process of the ESD oxide layer is completed, the SiN barrier layer is etched cleanly with a phosphoric acid solution; then conventional body injection and source injection are performed, which will not affect the stability and window size of other process steps. The process of the present invention can effectively prevent the antenna effect caused by local over-etching of ESD OX, significantly improve the convergence of BV withstand voltage and IDSS leakage, and effectively avoid the occurrence of low process yield.

[0027] The above are only preferred embodiments of the present invention and are not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention shall be included in the protection scope of the present invention.

Claims

1. A process for eliminating the antenna effect of a power device with an ESD structure, characterized in that: After the polysilicon gate etching of the power device is completed and before the oxide layer forming process of the ESD structure, a silicon nitride layer is first deposited on the surface of the device, and then the ESD structure forming process is performed.

2. The process for eliminating the antenna effect of a power device with an ESD structure according to claim 1, characterized in that: The silicon nitride layer is formed by deposition using a furnace tube process.

3. The process for eliminating the antenna effect of a power device with an ESD structure according to claim 1, characterized in that: The thickness of the silicon nitride layer is 60Å.

4. The process for eliminating the antenna effect of a power device with an ESD structure as claimed in claim 1, characterized in that: The process comprises: After etching the polysilicon gate of the power device, a silicon nitride layer is first deposited; forming an ESD oxide layer on the silicon nitride layer, and depositing an ESD polysilicon layer on the ESD oxide layer; Perform ion implantation of ESD structures; Performing photolithography and etching of the ESD polysilicon layer of the ESD structure to complete structural pattern formation of the ESD polysilicon layer in the ESD structure, and then performing thermal annealing; Performing a wet etching process on the ESD oxide layer to remove excess ESD oxide layer; Removing the silicon nitride layer by wet etching process; Perform body implantation of power devices.

5. The process for eliminating the antenna effect of a power device with an ESD structure as claimed in claim 4, characterized in that: The silicon nitride layer is used as an etching barrier layer in the wet etching process of the ESD oxide layer to prevent the antenna effect caused by local over-etching during the wet etching process of the ESD oxide layer.

6. The process for eliminating the antenna effect of a power device with an ESD structure as claimed in claim 4, characterized in that: The wet etching process for removing the silicon nitride layer is to completely remove the silicon nitride layer using a phosphoric acid solution.

7. The process for eliminating the antenna effect of a power device with an ESD structure as claimed in claim 4, characterized in that: The thickness of the ESD polysilicon layer is 6000Å.

8. The process for eliminating the antenna effect of a power device with an ESD structure as claimed in claim 4, characterized in that: The thickness of the ESD oxide layer is 2000Å and is deposited using an APCVD process.

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