Implementation method compatible with PCS

Abstract

The invention discloses an implementation method compatible with a PCS (Personal Computer System), which can be simultaneously applied to a PCIE2.0 (Peripheral Component Interconnect Express 2.0) mode and a USB3.0 (Universal Serial Bus 3.0) mode, and comprises the following steps of: a, loading all PCS modules in the USB3.0 mode and PCS modules in the PCIE2.0 mode onto one PCS; b, judging whether the operation mode of an external signal is a PCIE2.0 mode or a USB3.0 mode according to the external signal input into the PCS; c, closing the other operation mode of the PCS according to the judgment result; and d, processing the external signal on the PCS according to an operation mode determined by the external signal input to the PCS. The implementation method compatible with the PCS can be applied to a PCIE2.0 mode and a USB3.0 mode at the same time, the workload of design and verification is reduced, the risk in the development period can be minimized, and the development time can be shortened.

Description

Technical Field

[0001] The present invention relates to the field of interface IP chip design, and more specifically to a compatible PCS implementation method which can be applied to both PCIE2.0 mode and USB3.0 mode. Background Art

[0002] In the prior art, the design of the PCS (physical coding sublayer) for the contents of the PCIE 2.0 protocol and the USB 3.0 protocol is mostly performed separately.

[0003] Among them, the TX (Transmit) part of the PCS of USB3.0 mainly includes a data input module (used to receive input from the data link layer, the data input rate is equivalent to 5Gb / s), an 8b / 10b encoding module, a data selection module (used to select normal data, loopback mode data and CP78 according to different modes), and a data buffer output module; while the RX (Receive) part of the PCS of USB3.0 mainly includes a data receiving module (used to receive data from the PMA (physical medium adaptation layer)), a flexible buffer module (used to solve the problem of crossing the clock domain and to compensate for the clock error), an 8b / 10b decoding module, a data output module (this block outputs the PCS data to the data link layer), a clock management module (used to manage the various clocks inside the PCS), a reset management module (used to manage the various clocks inside the PCS), a LFPS (Lowfrequency periodic signaling, a low-frequency periodic signal used to communicate on the link without using ultra-high-speed signals) module and a control module (responsible for the scheduling of the entire PCS) and other parts. These modules together constitute the entire USB PCS, and PCS can realize data transmission and reception, loopback mode, self-test mode, low power mode, LFPS, polarity reversal, receiver detection and other functions. In addition, the function of the CP78 module is to generate and send an alternating sequence of 50 to 250 1s and 50 to 250 0s.

[0004] The TX part of PCS of PCIE2.0 mainly includes data input module (data input is equivalent to supporting 2.5Gb / s and 5Gb / s), 8b / 10b encoding module, data selection (selecting normal data, loopback mode), data buffer output module; and the RX part of PCS of PCIE2.0 mainly includes data receiving module (supporting two frequencies of 2.5Gb / s and 5Gb / s transmission), elastic buffer module, 8b / 10b decoding module and data output module; as well as clock management module (the clock frequency output to the MAC layer is variable), reset management module, BEACON (beacon signal, a pulse signal used to wake up the link) module, control module (for data rate switching) and other parts. These parts together constitute the PCS of the entire PCIE, and PCS can realize data transmission and reception, loopback mode, self-test mode, low power mode, BEACON and other functions.

[0005] As mentioned above, the structures of the PCSs of the two protocols are highly similar in terms of structure. However, due to the different requirements of the two protocols for the PCS in PHY, separate PCS designs are generally performed for different protocols, which lengthens the design cycle and increases the design difficulty. In addition, the separate PCS design also has great requirements for verification, resulting in low efficiency in design and verification.

[0006] Therefore, it is necessary to provide an improved implementation method of PCS compatible with both PCI E2.0 mode and USB 3.0 mode to overcome the above defects. Summary of the invention

[0007] The purpose of the present invention is to provide a PCS-compatible implementation method, which can be applied to both PCI E2.0 mode and USB 3.0 mode, reducing the workload of design and verification, minimizing the risk in the development cycle and reducing development time.

[0008] To achieve the above-mentioned purpose, the present invention provides a PCS compatible implementation method, which can be applied to PCIE2.0 mode and USB3.0 mode at the same time, and is characterized in that it includes the following steps: a. loading all PCS modules in USB3.0 mode and PCS modules in PCIE2.0 mode onto one PCS; b. judging whether the operating mode of the external signal is PCIE2.0 mode or USB3.0 mode according to the external signal input to the PCS; c. closing another operating mode of the PCS according to the judgment result; d. processing the external signal on the PCS according to the operating mode determined by the external signal input to the PCS.

[0009] Preferably, in step a, any one module is selected to load for each PCS template that is the same as the USB 3.0 mode and the PCIE 2.0 mode, and all independent PCS modules of the USB 3.0 mode and the PCIE 2.0 mode are loaded.

[0010] Preferably, in the step b, it is determined whether the current PCS is in USB 3.0 mode or PCIE 2.0 mode according to the PHY_MODE sub-signal in the external signal.

[0011] Preferably, the step b further comprises the steps of: determining the data rate of the external signal currently input to the PCS, and matching the corresponding data rate for the PCS according to the data rate of the external signal currently input.

[0012] Preferably, when it is determined according to the external signal input to the PCS that the current external signal needs to run in the PCIE 2.0 mode, the data rate running in the current PCIE 2.0 mode is switched to a matching data rate on the PCS.

[0013] Preferably, the step c specifically includes shutting down each independent PCS module in another operation mode on the PCS according to the judgment result.

[0014] Compared with the prior art, the implementation method of the PCS compatibility of the present invention loads all PCS modules in USB3.0 mode and PCS modules in PCIE2.0 mode into one PCS, so that one PCS is simultaneously provided with various functional modules in PCIE2.0 mode and USB3.0 mode, and can be compatible with running PCIE2.0 mode and USB3.0 mode, without setting up PCS separately for PCIE2.0 mode and USB3.0 mode, thereby reducing the workload of design and verification and reducing the development time; in addition, in the present invention, another operating mode of the PCS is closed according to the operating mode of the input external signal, and it only operates in the mode corresponding to the external signal, thereby ensuring the normal processing of the external signal on the PCS, and realizing the true compatibility of the PCS with the PCIE2.0 mode and USB3.0 mode.

[0015] The present invention will become more apparent from the following description taken in conjunction with the accompanying drawings, which are used to illustrate embodiments of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 It is a flow chart of the implementation method of PCS compatibility of the present invention. DETAILED DESCRIPTION

[0017] Embodiments of the present invention are now described with reference to the accompanying drawings, in which like element numbers represent like elements. As described above, the present invention provides a method for implementing PCS compatibility, which can be applied to both PCIE 2.0 mode and USB 3.0 mode, reducing the workload of design and verification, minimizing the risk in the development cycle and reducing development time.

[0018] Please refer to Figure 1 , Figure 1 Flow chart of the PCS compatible implementation method of the present invention. As shown in the figure, the PCS compatible implementation method of the present invention can be applied to both PCI E2.0 mode and USB3.0 mode, and includes the following steps:

[0019] Step S100, all PCS modules in USB3.0 mode and PCS modules in PCIE2.0 mode are loaded into one PCS; in this step, all PCS modules in USB3.0 mode and PCS modules in PCIE2.0 mode are loaded into one PCS, so that one PCS is provided with PCS modules in PCIE2.0 mode and USB3.0 mode at the same time, and can run PCIE2.0 mode and USB3.0 mode compatibly, and there is no need to set up PCS separately for PCIE2.0 mode and USB3.0 mode, thereby reducing the workload of design and verification and reducing development time. Specifically, each PCS template that is the same as the USB3.0 mode and the PCIE2.0 mode selects any one module to load, and all PCS modules that are independent of the USB3.0 mode and the PCIE2.0 mode are loaded; its specific manifestation is, for example: the receiver of the USB3.0 mode and the receiver of the PCIE2.0 mode both include an 8b / 10b decoding module, then only one 8b / 10b decoding module needs to be loaded onto the PCS, regardless of whether the 8b / 10b decoding module is of the receiver of the USB3.0 mode or the receiver of the PCIE2.0 mode; and for each independent module in the USB3.0 mode and the PCIE2.0 mode, such as the CP78 module in the USB3.0 mode (a module that generates and sends an alternating sequence of 50 to 250 1s and 50 to 250 0s), the LFPS module, and the BEACON (beacon) module in the PCIE2.0 mode, all need to be loaded onto the PCS, so as to ensure that both the USB3.0 mode and the PCIE2.0 mode can operate normally on the current PCS.

[0020] Step S200, judging whether the operation mode of the external signal is PCIE2.0 mode or USB3.0 mode according to the external signal input to the PCS; in this step, the external signal is input to the PCS from the top-level port. After the external signal is input to the port, the PCS judges whether the operation mode of the input external signal is PCIE2.0 mode or USB3.0 mode according to each specific input sub-signal; specifically, the PCS determines whether the current PCS is in USB3.0 mode or PCIE2.0 mode according to the physical layer mode selection sub-signal (PHY_MODE signal) input by the corresponding port. As is known to all, the external signal includes many groups of sub-signals, each group of sub-signals is input to the PCS through a different port, that is, each group of sub-signals has a fixed input port, and the physical layer mode selection sub-signal is a sub-signal representing the operation mode of this group of external signals. Therefore, the mode of the currently input external signal can be judged specifically by detecting the group of sub-signals input by the corresponding port. Among them, in this step, the data rate of the external signal currently input to the PCS is determined, and the corresponding data rate is matched for the PCS according to the data rate of the current external signal input. The data rates corresponding to signals in different operating modes are different. Therefore, it is necessary to determine the data rate of the external signal currently input to the PCS, and then match the corresponding data rate on the PCS so that it can operate normally on the PCS; further, the PCIE2.0 mode supports data speeds of 2.5Gb / s and 5Gb / s, that is, it can switch between 2.5Gb / s and 5Gb / s. Therefore, when it is determined that the current external signal needs to run in the PCIE2.0 mode, it is necessary to further switch to a matching data rate on the PCS according to the data rate of the current external signal to ensure that the input external signal can operate normally on the PCS and be processed accordingly.

[0021] Step S300, closing another operating mode of the PCS according to the judgment result; in this step, according to the operating mode of the input external signal judged in the previous step, another operating mode is closed on the PCS accordingly, specifically, each independent PCS module of another operating mode is closed on the PCS, and each PCS module with the same two modes is not processed; for example, when the operating mode of the current input external signal is the PCIE2.0 mode, the independent PCS module CP78 module and LFPS module corresponding to the USB3.0 mode on the PCS are closed, and the PCS modules corresponding to the PCIE2.0 mode (such as data input module, 8b / 10b encoding module, elastic buffer module, etc.) continue to be opened and wait for subsequent processing.

[0022] Step S400, processing the external signal on the PCS according to the mode determined by the external signal input to the PCS; in this step, the aforementioned steps have determined the mode in which the external signal input to the PCS needs to run, and at the same time, the PCS modules on the PCS that are not related to the mode are also turned off, so that the PCS can run normally according to the mode of the external signal to complete the function of the PCS itself.

[0023] In summary, the implementation method of compatible PCS of the present invention loads all PCS modules of USB3.0 mode and PCS modules of PCIE2.0 mode into one PCS, so that one PCS is provided with various functional modules of PCIE2.0 mode and USB3.0 mode at the same time, and can run compatibly with PCIE2.0 mode and USB3.0 mode, without setting up PCS separately for PCIE2.0 mode and USB3.0 mode, thereby reducing the workload of design and verification and reducing the development time; in addition, in the present invention, the operation mode of the currently input external signal is first judged, and then another operation mode on the PCS is closed according to the operation mode of the input external signal, that is, it only runs in the mode corresponding to the currently input external signal, thereby ensuring the normal and accurate operation of the external signal on the PCS, realizing the true compatibility of the PCS with the PCIE2.0 mode and USB3.0 mode, and being able to correctly process the input external signal.

[0024] The present invention is described above in conjunction with the best embodiment, but the present invention is not limited to the above disclosed embodiment, but should cover various modifications and equivalent combinations based on the essence of the present invention.

Claims

1. A PCS-compatible implementation method, which can be applied to both PCIE2.0 mode and USB3.0 mode, is characterized in that: The steps include: a. Load all USB3.0 mode PCS modules and PCIE2.0 mode PCS modules into one PCS; b. According to the external signal input to the PCS, determine whether the operation mode of the external signal is PCIE2.0 mode or USB3.0 mode; c. Turn off another operating mode of the PCS according to the judgment result; d. Process external signals on the PCS according to the operating mode determined by the external signals input to the PCS.

2. The method for implementing PCS compatibility according to claim 1, characterized in that: In the step a, any one module is selected to load for each PCS template that is the same as the USB 3.0 mode and the PCIE 2.0 mode, and all PCS modules that are independent of the USB 3.0 mode and the PCIE 2.0 mode are loaded.

3. The method for implementing PCS compatibility according to claim 1, characterized in that: In the step b, it is determined whether the current PCS is in USB 3.0 mode or PCIE 2.0 mode according to the physical layer mode selection sub-signal in the external signal.

4. The method for implementing PCS compatibility according to claim 1, characterized in that: The step b also includes the steps of: determining the data rate of the external signal currently input to the PCS, and matching the corresponding data rate for the PCS according to the data rate of the external signal currently input.

5. The method for implementing PCS compatibility as claimed in claim 4, characterized in that: When it is determined according to the external signal input to the PCS that the current mode of the external signal to be run is the PCIE 2.0 mode, the data rate running in the current PCIE 2.0 mode is switched to a matching data rate on the PCS.

6. The method for implementing PCS compatibility as claimed in claim 2, characterized in that: The step c specifically includes shutting down each independent PCS module in another operation mode on the PCS according to the judgment result.

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