Shallow trench isolation structure, preparation method thereof and semiconductor device

Abstract

The invention provides a shallow trench isolation structure, a preparation method thereof and a semiconductor device, an insulating blocking layer is formed by adopting a non-ISSG process after an oxide repair layer is formed by adopting an ISSG process and before a silicon oxide film is formed, and the blocking layer made of an insulating material can block-OH and-H ions mixed in the oxide repair layer, so that the isolation performance of the semiconductor device is improved. Therefore, nonuniformity of consumption of active sites-C-H when ozone and TEOS thermal chemical reaction are carried out by more-OH ions in the shallow trench and less-OH ions on the hard mask layer is avoided, consistency of deposition rate and uniformity of a silicon oxide film inside and outside the shallow trench is improved, early sealing of the top of the shallow trench is avoided, and the yield of the shallow trench is improved. Holes and / or gaps in the shallow trench isolation structure are reduced, the hole filling capability and quality of the HARP process are improved, and the reliability and stability of a semiconductor device formed subsequently are improved. In addition, the deposition uniformity of the HARP process on ISSG OX can be improved, and the load of the subsequent CMP process is reduced; in addition, a process window of HARP can be increased, and the back etching amount of the hard mask layer is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of semiconductor manufacturing, and in particular relates to a shallow trench isolation structure and a preparation method thereof, and a semiconductor device. Background Art

[0002] With the continuous miniaturization of integrated circuit technology, the insulation structure in the current mainstream integrated circuit manufacturing generally adopts shallow trench isolation (STI) structure to isolate adjacent active areas to meet the requirements of process and devices. STI is widely used, especially in the application of logic nodes.

[0003] In the STI isolation process, the insulation between adjacent active areas is achieved by filling the insulating dielectric layer in the shallow trench between active areas, especially when silicon wafers are used, silicon oxide is used as the material of the insulating dielectric layer. Therefore, filling the insulating dielectric layer is a key process for STI isolation. HARPA (High aspect ratio process) is currently a typical representative of shallow trench isolation technology.

[0004] The HARP process is to form a trench by etching after forming a hard mask layer on the substrate, and use the thermochemical reaction of ozone and TEOS to form an oxide film, namely the HARP film, to fill the trench. No plasma is used in this deposition process, which can achieve the filling of small-sized trenches. At the same time, this process requires the trench to have a specific morphology, such as a V-shaped trench at a specific angle. For the current 40nm node products, the HARP process adds an ISSG (In-Situ Steam Generation) process. Before forming the HARP film, an oxide layer is formed on the surface of the trench using the ISSG process to repair the damage caused after etching the trench and reduce tip discharge. However, with the continuous miniaturization of integrated circuits, the voids and / or seams generated during the HARP process cannot be effectively solved, thereby affecting the insulation effectiveness of STI. Summary of the invention

[0005] In view of the shortcomings of the prior art described above, an object of the present invention is to provide a shallow trench isolation structure and a preparation method thereof, and a semiconductor device, so as to solve the problem that in the prior art, a shallow trench isolation structure formed by a HARP process still has voids and / or seams in the trench, resulting in reduced STI insulation performance.

[0006] To achieve the above-mentioned object and other related objects, the present invention provides a method for preparing a shallow trench isolation structure, the preparation method comprising the following steps:

[0007] Providing a substrate, the substrate comprising a semiconductor substrate and a hard mask layer formed on the semiconductor substrate, wherein the hard mask layer comprises a nitride layer;

[0008] Etching the base to form a shallow trench, wherein the shallow trench penetrates the hard mask layer and extends into the semiconductor substrate;

[0009] An ISSG process is used to form an oxide repair layer, wherein the oxide repair layer is formed on the inner surface of the shallow trench and the surface of the substrate;

[0010] Forming an insulating blocking layer on the surface of the oxide repair layer by a non-ISSG process;

[0011] A silicon oxide film is formed by a thermochemical reaction of ozone and TEOS to fill the shallow trench.

[0012] Optionally, the dielectric constant of the insulating blocking layer is between 2.8 and 4, including endpoint values.

[0013] Furthermore, the semiconductor substrate is a silicon substrate; the hard mask layer includes a silicon oxide layer and a silicon nitride layer from bottom to top; the oxide repair layer is a silicon oxide repair layer, and the insulating blocking layer is a silicon oxide insulating blocking layer.

[0014] Furthermore, the insulating blocking layer is grown by SACVD or ALD.

[0015] Furthermore, when the insulating blocking layer is grown by SACVD, TEOS is thermally catalyzed in an ozone-free environment to form the insulating blocking layer; when the insulating blocking layer is grown by ALD, the precursor includes SAM-24 and O2.

[0016] Further, the temperature of TEOS thermal catalysis is 520° C. to 560° C., and the flow rate is 300 mg / s to 400 mg / s, including endpoint values.

[0017] Furthermore, the thickness of the insulating blocking layer is Endpoint values ​​are included.

[0018] Furthermore, after forming the silicon oxide film, an annealing step is also included.

[0019] Furthermore, before forming the oxide repair layer, it also includes a step of etching back a portion of the thickness of the hard mask layer from the shallow trench mouth to increase the diameter of the shallow trench; after forming the silicon oxide film, it also includes a step of removing the hard mask layer and the material layer in the shallow trench at its corresponding height.

[0020] The present invention also provides a shallow trench isolation structure, comprising:

[0021] A semiconductor substrate provided with a shallow trench;

[0022] An oxide repair layer formed by an ISSG process covers the bottom and sidewalls of the shallow trench;

[0023] An insulating blocking layer formed by a non-ISSG process is formed on the surface of the oxide repair layer;

[0024] A silicon oxide film is formed on the surface of the insulating blocking layer and fills the shallow trench.

[0025] Optionally, the oxide repair layer and the insulating blocking layer are both silicon oxide layers.

[0026] The present invention also provides a semiconductor device, comprising the shallow trench isolation structure as described above.

[0027] As described above, the shallow trench isolation structure and its preparation method, and the semiconductor device of the present invention form an insulating blocking layer by adopting a non-ISSG process after forming an oxide repair layer by adopting an ISSG process and before forming a silicon oxide film. The blocking layer of the insulating material can block the -OH ions and -H ions mixed in the oxide repair layer when the ISSG process forms the oxide repair layer, so as to avoid the uneven consumption of -CH in the active site when the thicker oxide repair layer in the shallow trench and the thinner oxide repair layer on the hard mask layer react with ozone and TEOS thermochemically, so that the HARPA film faces an insulating blocking layer of uniform material during the film formation process, thereby effectively improving the consistency of the deposition rate and deposition uniformity of the silicon oxide film in and outside the shallow trench, avoiding premature sealing of the top of the shallow trench, reducing the voids and / or gaps in the shallow trench isolation structure, increasing the hole filling ability and hole filling quality of the HARP process, and improving the reliability and stability of the subsequently formed semiconductor device; in addition, the HARP process in the ISSG The deposition uniformity on OX can reduce the load of the subsequent CMP process; furthermore, it can also increase the process window of HARP and reduce the amount of back etching on the hard mask layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 The cross-sectional structure diagram of a shallow trench isolation structure in the prior art is shown as an example.

[0029] Figures 2 to 4 Display as Figure 1 TEM and SEM images of holes and gaps in the shallow trench isolation structure. Figure 2 is a cross-sectional TEM image, Figure 3 and Figure 4 The top view SEM image.

[0030] Figures 5 to 7 It is a schematic diagram of the cross-sectional structure of forming a silicon oxide film on a silicon substrate, a silicon nitride substrate and an ISSG OX pad using the same process parameters.

[0031] Figures 8 to 15 It is a schematic diagram of the cross-sectional structure after each step in the method for preparing the shallow trench isolation structure of the present invention is completed.

[0032] Fig.16 and Fig.17 SEM images showing holes and gaps in a shallow trench isolation structure prepared by the method for preparing a shallow trench isolation structure of the present invention and a shallow trench isolation structure in the prior art are shown respectively.

[0033] Component number description

[0034] 1 Base

[0035] 10 Semiconductor substrate

[0036] 11 Hard mask layer

[0037] 12 Silicon oxide layer

[0038] 13 Silicon nitride layer

[0039] 14 Shallow groove

[0040] 15 Oxide repair layer

[0041] 16 Insulation barrier

[0042] 17 Silicon oxide film

[0043] 18 Silicon substrate

[0044] 19 Silicon nitride liner

[0045] 20 ISSG OX liner

[0046] 21 Holes

[0047] 22 Gap DETAILED DESCRIPTION

[0048] The following describes the embodiments of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.

[0049] See also Figures 1 to 17It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the present invention in a schematic manner, and the illustrations only show components related to the present invention rather than being drawn according to the number, shape and size of components in actual implementation. In actual implementation, the type, quantity and proportion of each component may be changed arbitrarily, and the component layout may also be more complicated.

[0050] As described in the background art, in the current technology of filling shallow trenches using the HARP process, an ISSG OX liner 20 is first formed on the surface of the shallow trench using the ISSG process before forming the silicon oxide film 17. Figure 1 As shown in FIG. 1 , the damage caused by etching to form a shallow groove is repaired. Although this method solves the problem of reducing the tip discharge, it cannot effectively solve the problem of the hole 21 and / or the gap 22. Figures 2 to 4 As shown, the insulation effectiveness of the shallow trench isolation structure is affected. Based on this, the inventors conducted various experiments and studies and found that although HARP is a process with excellent conformality, the deposition rate and deposition uniformity of the HARP process are different on deposition substrates of different materials under the same process parameters. Figures 5 to 7 As shown in the figure, the film thickness results of silicon oxide film deposited by HARP process under the same process parameters using silicon, silicon nitride and ISSG OX as substrates are obtained. Figure 5 The thickness of the silicon oxide film 17 formed on the silicon substrate 18 is Figure 6 The thickness of the silicon oxide film 17 formed on the silicon nitride liner 19 is Figure 7 The thickness of the silicon oxide film 17 formed on the ISSG OX pad 20 is In addition, the silicon oxide film was deposited on the silicon substrate using the HARP process under the same process parameters using silicon and ISSG OX as substrates. The uniformity of the silicon oxide film is 3.24% when deposited on ISSG OX substrate. When the silicon oxide film is formed, the uniformity is 8.99%.

[0051] The above experiment found that the deposition rate and deposition uniformity of the HARP process on the ISSG OX substrate were poor. In view of this result, the inventors analyzed the HARP process and the ISSG process. On the one hand, the HARP process is a thermochemical reaction using ozone and TEOS, where the chemical formula of TEOS is as follows:

[0052]

[0053] The chemical reaction formula of ozone and TEOS is: Si(OC2H5)4+8O3—SiO2+10H2O+CO2. TEOS is a surfactant. Under the catalytic action of ozone, the main active site -CH reacts. The loss of its own active site directly affects the deposition effect, including the deposition rate and deposition uniformity. On the other hand, the progressive chemical reaction formula of the ISSG process in the reaction chamber is: H2+O2+reaction source X (high temperature)—H2O+-OH+-H+reaction source X (high temperature)—XO+-OH+-H. From the chemical reaction process of the ISSG process, it can be seen that in the ISSG process, the SiO2 formed is mixed with -OH, which causes the active site -CH bond in TEOS to actively react with -OH, and the reaction of the -CH bond with -OH will continue under the high-temperature catalytic reaction of TEOS and ozone, which will cause the active sites in TEOS to continue to decrease, thereby reducing the deposition rate and deposition uniformity of the HARP process on ISSG OX. Furthermore, since the ISSG process mainly forms the ISSG OX by consuming silicon, when the ISSG OX is formed in the shallow trench isolation structure, Figure 1 As shown, the ISSG OX formed in the shallow trench is thicker, and the ISSG OX formed on the surface of the hard mask layer 11 is thinner. In addition, the growth rate of HARP on the nitride layer is faster than the growth rate on the ISSG OX. Therefore, when the HARP process is finally used to fill the shallow trench, the deposition rate and deposition uniformity of the silicon oxide film in the shallow trench are lower than the deposition rate and deposition uniformity of the silicon oxide film on the hard mask layer, which may eventually cause the top of the shallow trench to be sealed earlier than the bottom, thereby forming a void and / or a seam.

[0054] Based on the above research and analysis, the inventor proposes a method for preparing a shallow trench isolation structure, which comprises the following steps:

[0055] S1. providing a substrate, wherein the substrate comprises a semiconductor substrate and a hard mask layer formed on the semiconductor substrate, wherein the hard mask layer comprises a nitride layer;

[0056] S2, etching the substrate to form a shallow trench, wherein the shallow trench penetrates the hard mask layer and extends into the semiconductor substrate;

[0057] S3, forming an oxide repair layer by using an ISSG process, wherein the oxide repair layer is formed on the inner surface of the shallow trench and the surface of the substrate;

[0058] S4, forming an insulating blocking layer on the surface of the oxide repair layer by a non-ISSG process;

[0059] S5. Form a silicon oxide film by a thermochemical reaction of ozone and TEOS to fill the shallow trench.

[0060] As can be seen from the above analysis, the oxide repair layer formed by the ISSG process will contain -OH ions and -H ions. By forming an insulating blocking layer by a non-ISSG process after the oxide repair layer is formed by the ISSG process and before the silicon oxide film is formed, the insulating material blocking layer can block the -OH ions and -H ions mixed in the oxide repair layer when the ISSG process is formed, so as to avoid the large amount of -OH ions contained in the thicker oxide repair layer in the shallow trench and the small amount of -OH ions contained in the thinner oxide repair layer on the hard mask layer to the ozone. Due to the uneven consumption of -CH in the active sites during the thermochemical reaction of TEOS, the HARPA film faces an insulating blocking layer of uniform material during the film formation process, which can effectively improve the consistency of the deposition rate and deposition uniformity of the silicon oxide film in and outside the shallow trench, avoid premature sealing of the top of the shallow trench, reduce the voids and / or seams in the shallow trench isolation structure, increase the hole filling ability and quality of the HARP process, and improve the reliability and stability of the subsequently formed semiconductor devices; in addition, the deposition uniformity of the HARP process on the ISSG OX can be improved, reducing the load of the subsequent CMP process; furthermore, the process window of HARP can be increased, and the amount of back etching of the hard mask layer can be reduced.

[0061] The method for preparing the shallow trench isolation structure of this embodiment is described in detail below with reference to the specific drawings.

[0062] like Figure 8 As shown, step S1 is first performed to provide a base 1 , wherein the base 1 includes a semiconductor substrate 10 and a hard mask layer 11 formed on the semiconductor substrate 10 , wherein the hard mask layer 11 includes a nitride layer.

[0063] The material of the semiconductor substrate 10 may be silicon, germanium, silicon germanium or silicon carbide, etc., or may be silicon on insulator (SOI) or germanium on insulator (GOI), or other semiconductor materials. In this embodiment, the material of the semiconductor substrate 10 is preferably a silicon substrate, and further, it may be selected as an undoped silicon substrate, an N-type doped silicon substrate, or a P-type doped silicon substrate according to actual needs.

[0064] The hard mask layer 11 is provided to include a nitride layer, and the thickness of the nitride layer is usually large, which is convenient for the subsequent planarization process. When the material of the semiconductor substrate 10 is selected as a silicon material, the nitride layer in the hard mask layer 11 is preferably a silicon nitride layer. More preferably, the hard mask layer 11 can also be provided as a stacked structure of a silicon oxide layer 12 and a silicon nitride layer 13, and the silicon oxide layer 12 can be used as a buffer layer between the semiconductor substrate 10 of silicon material and the silicon nitride layer 13 to reduce the dislocation of the silicon nitride layer 13. At the same time, the silicon oxide layer 12 can also be used as an etching stop layer for the subsequent removal of the silicon nitride layer 13. Among them, the silicon oxide layer 12 can be formed by a thermal oxidation process, and the silicon nitride layer 13 can be formed by a HDP (High Dense Plasma) process or a HARP (High Aspect Ratio Process) process.

[0065] like Fig. 9 As shown, step S2 is then performed to etch the base 1 to form a shallow trench 14 , wherein the shallow trench 14 penetrates the hard mask layer 11 and extends into the semiconductor substrate 10 .

[0066] Specifically, this step includes: coating photoresist, exposing and developing the photoresist through a photolithography process to pattern the photoresist; then etching the substrate 1 by wet etching or dry etching based on the patterned photoresist. When the hard mask layer 11 includes a silicon oxide layer 12 and a silicon nitride layer 13, a plasma etching process can be used to sequentially etch the silicon nitride layer 13 and the silicon oxide layer 12 until the semiconductor substrate 10 of the silicon material is exposed, and then the semiconductor substrate 10 is etched to a preset depth by a plasma etching process; then the patterned photoresist layer is removed to obtain the shallow groove 14.

[0067] The subsequent function of the shallow trench 14 is to isolate the area to be isolated in the semiconductor substrate and / or the semiconductor device formed in the semiconductor substrate, so the number, position, depth, diameter width and other parameters of the shallow trench 14 are set according to the specific situation and are not overly restricted here.

[0068] As an example, the inclination angle of the shallow groove 17 is less than or equal to 87°. The inclination angle here refers to the angle between the shallow groove 17 and the horizontal direction.

[0069] like Fig.11 As shown, step S3 is then performed to form an oxide repair layer 15 using an ISSG process. The oxide repair layer 15 is formed on the inner surface of the shallow trench 14 and the surface of the substrate 1 .

[0070] As mentioned above, the progressive chemical reaction formula of the ISSG (In-Situ Steam Generation) process in the reaction chamber is: H2+O2+Reaction source X (high temperature)—H2O+-OH+-H+Reaction source X (high temperature)—XO+-OH+-H. When the material of the semiconductor substrate 10 is silicon, and the hard mask layer 11 is a stack of a silicon oxide layer 12 and a silicon nitride layer 13, the progressive chemical reaction formula is: H2+O2+Reaction source Si (high temperature)—H2O+-OH+-H+Reaction source Si (high temperature)—SiO2+-OH+-H. That is, when the ISSG OX (i.e., the oxide repair layer 15) is formed during the ISSG process, -OH ions and -H ions are naturally formed in the ISSG OX. The oxide repair layer 15 formed by this process has few internal defects, a relatively small interface state density, and a relatively high quality of the oxide film, which can play a good repair effect on the damage caused in the process of etching the shallow trench 14.

[0071] As a specific example, Fig.10 As shown, before forming the oxide repair layer 15, it also includes a step of etching back a portion of the thickness of the hard mask layer 11 from the opening of the shallow trench 14 to increase the diameter of the shallow trench 14, so as to further reduce the premature sealing of the top of the shallow trench in the subsequent HARP process.

[0072] like Fig.12 As shown, step S4 is then performed to form an insulating blocking layer 16 on the surface of the oxide repair layer 15 using a non-ISSG process. The blocking layer of insulating material can block the -OH ions and -H ions mixed in the oxide repair layer 15 when the ISSG process forms the oxide repair layer 15. This is to avoid the uneven consumption of -CH in active sites during the subsequent ozone and TEOS thermochemical reactions caused by the thicker oxide repair layer 15 in the shallow trench 14 and the thinner oxide repair layer 15 on the hard mask layer 11, so that the subsequent HARPA film faces an insulating blocking layer 16 of uniform material during the film formation process.

[0073] The function of the insulating blocking layer 16 is to block the -OH ions and -H ions in the oxide repair layer 15. In this regard, any insulating material that can block the -OH ions and -H ions in the oxide repair layer 15 can be suitable as the material of the insulating blocking layer 16. Preferably, the insulating material has a dielectric constant between 2.8 and 4, including end values, such as silicon oxide or silicon nitride. However, in order to improve the performance of the entire shallow trench isolation structure, the material of the insulating blocking layer 16 needs to have good adhesion to the previous material layer and the subsequent material layer while having a blocking effect. Therefore, it is preferred that the materials of these layers are the same. For example, when the material of the oxide repair layer 15 is silicon oxide, the material of the insulating blocking layer 16 is also silicon oxide, and the silicon oxide film formed subsequently is also made of silicon oxide.

[0074] The function of the insulating blocking layer 16 is to block the influence of the -OH ions mixed in the oxide repair layer 15 formed by the ISSG process on the subsequent growth of the silicon oxide film. Therefore, in principle, growing a layer of insulating blocking layer 16 of the same material can shield the -OH ions mixed in the oxide repair layer 15, and at the same time make the subsequent silicon oxide film grow based on the insulating blocking layer 16 of the same material, so as to improve the consistency of the deposition rate and deposition uniformity of the subsequent silicon oxide film in and outside the shallow trench. Based on this principle, it is preferred to select an insulating blocking layer 16 with uniform thickness, for example, select a SACVD (sub-atmospheric pressure chemical vapor deposition) process or an ALD (atomic layer deposition) process to form an insulating blocking layer 16 with uniform thickness, so as to improve the compactness of the insulating blocking layer 16, and at the same time, the insulating blocking layer 16 is not mixed with -OH ions, so as not to affect the film formation rate of the subsequent silicon oxide film.

[0075] As an example, when the oxide repairing layer 15 is selected to be silicon oxide, the insulating blocking layer 16 is also preferably silicon oxide, and the precursors may include SAM-24 and O2 and an ALD process may be used to form the insulating blocking layer 16.

[0076] As a preferred example, when the oxide repair layer 15 and the insulating blocking layer 16 are selected as silicon oxide, the SACVD process can be used to make TEOS form the insulating blocking layer 16 only by thermal catalysis in an ozone-free environment. This method does not require the addition of new machines and new processes to achieve low cost. Furthermore, the temperature of TEOS thermal catalysis is 520°C to 560°C, for example, 520°C, 530°C, 540°C, 550°C, 560°C, and the flow rate is 300mg / s to 400mg / s, for example, 300mg / s, 320mg / s, 340mg / s, 360mg / s, 380mg / s, 400mg / s. Too high a temperature of TEOS thermal catalysis and / or too fast a flow rate may lead to island aggregation and accumulation of C elements, thereby deteriorating the quality of the shallow trench isolation structure.

[0077] As another preferred example, the thickness of the insulating blocking layer 16 is For example The thickness of the insulating blocking layer 16 cannot be too thin. If it is too thin, it cannot play a good blocking role on -OH ions and -H ions. If it is too thick, it will lead to poor adhesion between the subsequent silicon oxide film and deteriorate the performance of the shallow trench isolation structure.

[0078] like Fig.13 As shown, step S5 is finally performed to form a silicon oxide film 17 by a thermochemical reaction of ozone and TEOS (ie, HARP process) to fill the shallow trench. The specific parameters and methods used in the HARP process are well known in the art and are set according to actual conditions, and are not excessively limited here.

[0079] As an example, after forming the silicon oxide film 17, an annealing step is further included.

[0080] As an example, after forming the silicon oxide film 17, the step of removing the hard mask layer 11 and the material layer in the shallow trench at a corresponding height is also included. Fig.14 As shown, the silicon oxide film 17 on the surface of the substrate 10 is firstly polished by a CMP process; Fig.15 As shown, dry etching or wet etching is then used to remove the hard mask layer 11 and the material layer in the shallow trench at a corresponding height.

[0081] The following table is an example parameter selected for forming the insulating blocking layer 16 and the silicon oxide film 17 using the HARP Recipe parameters, wherein the TEOS stabilization stage time is 5 seconds, and the flow rate is 350 mg / s; the TEOS thermal catalysis stage time of forming the insulating blocking layer 16 is 80-150 seconds, and the flow rate is 350 mg / s; the thermochemical reaction of TEOS and ozone to form the silicon oxide film 17 is divided into three stages, the first stage time is 168 seconds, the TEOS flow rate is 1125 mg / s, and the ozone flow rate is 27000 mg / s, the first stage time is 142 seconds, the TEOS flow rate is 2700 mg / s, and the ozone flow rate is 27000 mg / s, and the third stage time is 200 seconds, the TEOS flow rate is 6000 mg / s, and the ozone flow rate is 18000 mg / s.

[0082] sheet

[0083]

[0084] The shallow trench isolation structure formed by the above parameters is as follows Fig.17 The shallow trench isolation structure obtained when the insulating blocking layer formed in the TEOS thermal catalysis stage in the above table is not included is as shown in FIG. Fig.16 As shown, the number of holes (Void) and / or gaps (Seam) increases from Fig.16 73 of them were reduced to Fig.17 2 of them, which strongly illustrates that the preparation method of this embodiment effectively improves the filling ability and filling effect of the shallow trench.

[0085] Based on the above-mentioned method for preparing a shallow trench isolation structure, this embodiment further provides a shallow trench isolation structure, such as Fig.15 As shown, including:

[0086] A semiconductor substrate 10 having a shallow trench 14;

[0087] An oxide repair layer 15 formed by ISSG process covers the bottom and sidewalls of the shallow trench 14;

[0088] An insulating blocking layer 16 formed by a non-ISSG process is formed on the surface of the oxide repairing layer 15;

[0089] A silicon oxide film 17 is formed on the surface of the insulating blocking layer 16 and fills the shallow trench 14 .

[0090] This embodiment also provides a semiconductor device, including the shallow trench isolation structure as described above.

[0091] In summary, the present invention provides a shallow trench isolation structure and a preparation method thereof, and a semiconductor device. After an oxide repair layer is formed by an ISSG process and before a silicon oxide film is formed, an insulating blocking layer is formed by a non-ISSG process. The blocking layer of the insulating material can block the -OH ions and -H ions mixed in the oxide repair layer when the ISSG process forms the oxide repair layer, so as to avoid the uneven consumption of -CH in active sites when the thicker oxide repair layer in the shallow trench and the thinner oxide repair layer on the hard mask layer react with ozone and TEOS in a thermochemical reaction, so that the HARPA film faces an insulating blocking layer of uniform material during the film formation process, thereby effectively improving the consistency of the deposition rate and deposition uniformity of the silicon oxide film in and outside the shallow trench, avoiding premature sealing of the top of the shallow trench, reducing the voids and / or seams in the shallow trench isolation structure, increasing the hole filling ability and hole filling quality of the HARP process, and improving the reliability and stability of the subsequently formed semiconductor device; in addition, the HARP process in the ISSG The deposition uniformity on OX can reduce the load of the subsequent CMP process; furthermore, the process window of HARP can be increased to reduce the amount of back etching of the hard mask layer. Therefore, the present invention effectively overcomes various shortcomings of the prior art and has a high industrial utilization value.

[0092] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the art may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A method for preparing a shallow trench isolation structure, characterized in that: The preparation method comprises the following steps: Providing a substrate, the substrate comprising a semiconductor substrate and a hard mask layer formed on the semiconductor substrate, wherein the hard mask layer comprises a nitride layer; Etching the base to form a shallow trench, wherein the shallow trench penetrates the hard mask layer and extends into the semiconductor substrate; An ISSG process is used to form an oxide repair layer, wherein the oxide repair layer is formed on the inner surface of the shallow trench and the surface of the substrate; Forming an insulating blocking layer on the surface of the oxide repair layer by a non-ISSG process; A silicon oxide film is formed by a thermochemical reaction of ozone and TEOS to fill the shallow trench.

2. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The dielectric constant of the insulating blocking layer is between 2.8 and 4, including the end values.

3. The method for preparing a shallow trench isolation structure according to claim 1 or 2, characterized in that: The semiconductor substrate is a silicon substrate; the hard mask layer includes a silicon oxide layer and a silicon nitride layer from bottom to top; the oxide repair layer is a silicon oxide repair layer, and the insulating blocking layer is a silicon oxide insulating blocking layer.

4. The method for preparing a shallow trench isolation structure according to claim 3, characterized in that: The insulating blocking layer is grown by SACVD or ALD.

5. The method for preparing a shallow trench isolation structure according to claim 4, characterized in that: When the insulating blocking layer is grown by SACVD, the insulating blocking layer is formed by thermal catalysis of TEOS in an ozone-free environment; when the insulating blocking layer is grown by ALD, the precursors include SAM-24 and O2.

6. The method for preparing a shallow trench isolation structure according to claim 5, characterized in that: The temperature of TEOS thermal catalysis is 520° C. to 560° C., and the flow rate is 300 mg / s to 400 mg / s, including endpoint values.

7. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: The thickness of the insulating blocking layer is Endpoint values ​​are included.

8. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: After forming the silicon oxide film, an annealing step is also included.

9. The method for preparing a shallow trench isolation structure according to claim 1, characterized in that: Before forming the oxide repair layer, the method also includes a step of etching back a portion of the thickness of the hard mask layer from the shallow trench opening to increase the diameter of the shallow trench; after forming the silicon oxide film, the method also includes a step of removing the hard mask layer and the material layer in the shallow trench at its corresponding height.

10. A shallow trench isolation structure, characterized in that: include: A semiconductor substrate provided with a shallow trench; An oxide repair layer formed by an ISSG process covers the bottom and sidewalls of the shallow trench; An insulating blocking layer formed by a non-ISSG process is formed on the surface of the oxide repair layer; A silicon oxide film is formed on the surface of the insulating blocking layer and fills the shallow trench.

11. The shallow trench isolation structure according to claim 10, characterized in that: The oxide repairing layer and the insulating blocking layer are both silicon oxide layers.

12. A semiconductor device, characterized in that: include: A shallow trench isolation structure as described in any one of claims 10-11.

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