Constant-impedance bidirectional variable gain amplifier and phase shifter

Abstract

The invention belongs to the technical field of millimeter wave integrated circuits, and particularly discloses a constant-impedance bidirectional variable gain amplifier and a phase shifter. The invention discloses a constant-impedance bidirectional variable gain amplifier which comprises a forward differential amplification module, a reverse differential amplification module, a first transistor array, a second transistor array, a third transistor array and a fourth transistor array. The two output ends of the forward differential amplification module are connected with the two input ends of the reverse differential amplification module through the second transistor array, the fourth transistor array, the first transistor array and the third transistor array respectively. Besides two constant-impedance bidirectional variable gain amplifiers, the phase shifter disclosed by the invention also comprises an orthogonal signal generator, a first balun, a second balun, a third balun and a vector synthesizer. By controlling the grid voltage of each transistor on the amplifier, the input and output impedance of the amplifier is ensured to be in a constant state while the bidirectional work of the amplifier is realized, so that the high precision and low insertion loss of the phase shifter are realized. The invention can be widely applied to the millimeter wave active phased array.

Description

Technical Field

[0001] The invention belongs to the technical field of millimeter wave integrated circuits, and in particular relates to a constant impedance bidirectional variable gain amplifier and a phase shifter. Background Art

[0002] Millimeter-wave active phased arrays are widely used in the field of millimeter-wave radars due to their good beam directivity and fast scanning speed. The unidirectional transmit / receive ports used by traditional active phased units require two paths for transmission and reception, which are large in area, high in cost, and complex in system architecture. The bidirectional transceiver port only requires one transceiver path, which can complete the work of the transmitter and receiver, and can play a role in streamlining the transceiver channels, which is of great significance for the miniaturization of phased arrays. As the core part of the phased array, the phase shifter directly determines the directionality of the phased array due to its phase shifting accuracy. Therefore, the study of high-performance active bidirectional phase shifters is the most critical part of studying bidirectional phased arrays.

[0003] The existing active bidirectional phase shifter uses a bidirectional variable gain amplifier and a symmetrical switchable PPF on both sides as the overall architecture of the phase shifter, achieving low insertion loss, but the phase shifting accuracy of this phase shifter is low. The existing passive bidirectional phase shifter is generally composed of digitally controlled transistor array units, which can be reversibly phase tuned. Although the constant port impedance can improve the accuracy of the phase shifter, the gain is too low compared to the variable gain amplifier, which causes the phase shifter to have a large insertion loss. Therefore, in order to solve the above problems, it is necessary to study a bidirectional phase shifter with both high accuracy and low insertion loss. Summary of the invention

[0004] The object of the present invention is to provide a constant impedance bidirectional variable gain amplifier, which can work bidirectionally and ensure that the input and output impedances are in a constant state while being able to change the amplifier gain;

[0005] A second object of the present invention is to provide a phase shifter including the above-mentioned constant impedance bidirectional variable gain amplifier to achieve high precision and low insertion loss of the phase shifter.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is as follows:

[0007] A constant impedance bidirectional variable gain amplifier comprises a forward differential amplifier module, a reverse differential amplifier module and first to fourth transistor arrays;

[0008] The first input terminal and the second input terminal of the forward differential amplifier module are respectively the first input and output terminals and the second input and output terminals of the constant impedance bidirectional variable gain amplifier; the first output terminal of the forward differential amplifier module is respectively connected to the drains of all transistors in the second transistor array and the drains of all transistors in the fourth transistor array; the second output terminal of the forward differential amplifier module is respectively connected to the drains of all transistors in the first transistor array and the drains of all transistors in the third transistor array;

[0009] The sources of all transistors in the first transistor array and the second transistor array are connected to the first input terminal of the reverse differential amplifier module; the sources of all transistors in the third transistor array and the fourth transistor array are connected to the second input terminal of the reverse differential amplifier module; the gates of all transistors in the first to fourth transistor arrays are connected to independent gate voltages;

[0010] The first output terminal and the second output terminal of the reverse differential amplifier module are respectively the third input and output terminal and the fourth input and output terminal of the constant impedance bidirectional variable gain amplifier.

[0011] As a limitation, the forward differential amplifier module includes: a first transistor, a second transistor, a seventh transistor, an eighth transistor, a first DC blocking capacitor, a second DC blocking capacitor, a first inter-stage inductor, a second inter-stage inductor, a first bias resistor, and a second bias resistor;

[0012] One end of the first DC blocking capacitor is connected to the drain of the seventh transistor and serves as the first input end of the forward differential amplifier module, and the gate of the seventh transistor is connected to the fourth gate voltage; the other end of the first DC blocking capacitor is respectively connected to the gate of the first transistor and one end of the first bias resistor; the other end of the first bias resistor is connected to the first gate voltage; the source of the first transistor is grounded, the drain of the first transistor is connected to one end of the first interstage inductor and the source of the eighth transistor, and the other end of the first interstage inductor is the first output end of the forward differential amplifier module;

[0013] One end of the second DC blocking capacitor is connected to the drain of the eighth transistor and serves as the second input end of the forward differential amplifier module, and the gate of the eighth transistor is connected to the fourth gate voltage; the other end of the second DC blocking capacitor is respectively connected to the gate of the second transistor and one end of the second bias resistor; the other end of the second bias resistor is connected to the first gate voltage; the source of the second transistor is grounded, the drain of the second transistor is connected to one end of the second inter-stage inductor and the source of the seventh transistor, and the other end of the second inter-stage inductor is the second output end of the forward differential amplifier module.

[0014] As a second limitation, the reverse differential amplifier module includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third DC blocking capacitor, a fourth DC blocking capacitor, a third inter-stage inductor, a fourth inter-stage inductor, a third bias resistor and a fourth bias resistor;

[0015] One end of the third DC blocking capacitor is connected to the drain of the fifth transistor and serves as the first output end of the reverse differential amplifier module, and the gate of the fifth transistor is connected to the third gate voltage; the other end of the third DC blocking capacitor is respectively connected to the gate of the third transistor and one end of the third bias resistor; the other end of the third bias resistor is connected to the second gate voltage; the source of the third transistor is grounded, the drain of the third transistor is connected to one end of the third inter-stage inductor and the source of the sixth transistor, and the other end of the third inter-stage inductor is the first input end of the reverse differential amplifier module;

[0016] One end of the fourth DC blocking capacitor is connected to the drain of the sixth transistor and serves as the second output end of the reverse differential amplifier module, and the gate of the sixth transistor is connected to the third gate voltage; the other end of the fourth DC blocking capacitor is respectively connected to the gate of the fourth transistor and one end of the fourth bias resistor; the other end of the fourth bias resistor is connected to the second gate voltage; the source of the fourth transistor is grounded, the drain of the fourth transistor is connected to one end of the fourth inter-stage inductor and the source of the fifth transistor, and the other end of the fourth inter-stage inductor is the second input end of the reverse differential amplifier module.

[0017] As a third limitation, in the first to fourth transistor arrays, each transistor array includes N transistors whose widths increase continuously by two times; 5≤N≤7, and N is a positive integer.

[0018] As a further limitation, in the first to fourth transistor arrays, the transistors with the smallest widths have the same width.

[0019] A phase shifter, comprising two of the above-mentioned constant impedance bidirectional variable gain amplifiers, and also comprising an orthogonal signal generator, first to third baluns and a vector synthesizer;

[0020] The input end of the orthogonal signal generator is the input end of the phase shifter, the two output ends of the orthogonal signal generator are respectively connected to the input ends of the first balun and the second balun, the two output ends of the first balun are respectively connected to the first input-output end and the second input-output end of one of the constant impedance bidirectional variable gain amplifiers, and the two output ends of the second balun are respectively connected to the first input-output end and the second input-output end of another constant impedance bidirectional variable gain amplifier; the third input-output end and the fourth input-output end of the two constant impedance bidirectional variable gain amplifiers are respectively connected to the input end of the vector synthesizer; the two output ends of the vector synthesizer are respectively connected to the two input ends of the third balun, and the output end of the third balun is the output end of the phase shifter.

[0021] As a limitation, the first balun includes a first-level coil and a second-level coil, one end of the first-level coil is the input end of the first balun, and the other end is grounded, and the two ends of the second-level coil are the two output ends of the first balun;

[0022] The second balun includes a third coil and a fourth coil, one end of the third coil is the input end of the second balun, and the other end is grounded, and two ends of the fourth coil are two output ends of the second balun;

[0023] The third balun includes a fifth coil and a sixth coil. Two ends of the fifth coil are two input ends of the third balun. One end of the sixth coil is grounded, and the other end is the output end of the third balun.

[0024] As a second limitation, the orthogonal signal generator uses a coupled-line coupler.

[0025] As a third limitation, the vector synthesis method used by the vector synthesizer is a current synthesis method.

[0026] Due to the adoption of the above technical solution, the present invention has the following technical advances compared with the prior art:

[0027] (1) The present invention provides a constant impedance bidirectional variable gain amplifier, which can ensure that the input and output impedances are in a constant state compared to existing amplifiers;

[0028] (2) The present invention sets up four transistor arrays, and the gain of the amplifier can be changed by changing the number of transistors turned on in the transistor array;

[0029] (3) The present invention establishes a phase shifter based on a constant impedance bidirectional variable gain amplifier, which can simultaneously achieve high phase shifting accuracy and low insertion loss;

[0030] (4) The present invention uses a transmission balun to transmit signals, thereby ensuring the strength, stability and reliability of the signal, while also being able to reduce the size of the phase shifter and improve the integration of the phase shifter;

[0031] (5) The present invention uses a coupled line coupler as an orthogonal signal generator, which can transmit signals without introducing additional distortion or noise, thereby ensuring effective signal transmission;

[0032] (6) The present invention uses a vector synthesizer of current synthesis method, which has few circuit elements, simple structure, low cost and high reliability.

[0033] The invention belongs to the technical field of millimeter wave integrated circuits and can ensure that the input and output impedances of a constant impedance bidirectional variable gain amplifier are in a constant state, thereby achieving high precision and low insertion loss of a phase shifter. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The accompanying drawings are used to provide further understanding of the present invention and constitute a part of the specification. They are used to explain the present invention together with the embodiments of the present invention and do not constitute a limitation of the present invention.

[0035] In the attached picture:

[0036] Figure 1 Schematic diagram of the circuit of Embodiment 1 of the present invention;

[0037] Figure 2 This is a structural block diagram of Embodiment 2 of the present invention;

[0038] Figure 3 is a signal synthesis principle diagram of a vector synthesizer in Embodiment 2 of the present invention;

[0039] Figure 4 This is a diagram of the forward phase shift simulation result of Example 2 of the present invention;

[0040] Figure 5 This is a diagram of reverse phase shift simulation results of Example 2 of the present invention;

[0041] Figure 6 1 is a diagram of the forward gain simulation result of Example 2 of the present invention;

[0042] Figure 7 Graph showing the reverse gain simulation result of Embodiment 2 of the present invention;

[0043] Figure 8 This is a diagram of the RMS error simulation results of Example 2 of the present invention. DETAILED DESCRIPTION

[0044] The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

[0045] Embodiment 1 A constant impedance bidirectional variable gain amplifier

[0046] like Figure 1 As shown, this embodiment includes a forward differential amplifier module, a reverse differential amplifier module and first to fourth transistor arrays.

[0047] The first input terminal and the second input terminal of the forward differential amplifier module are respectively the first input-output terminal and the second input-output terminal of the present embodiment. The first output terminal of the forward differential amplifier module is respectively connected to the drains of all transistors in the second transistor array and the drains of all transistors in the fourth transistor array; the second output terminal of the forward differential amplifier module is respectively connected to the drains of all transistors in the first transistor array and the drains of all transistors in the third transistor array;

[0048] The sources of all transistors in the first transistor array and the second transistor array are connected to the first input terminal of the reverse differential amplifier module. The sources of all transistors in the third transistor array and the fourth transistor array are connected to the second input terminal of the reverse differential amplifier module.

[0049] The first output terminal and the second output terminal of the reverse differential amplifier module are respectively the third input-output terminal and the fourth input-output terminal of this embodiment.

[0050] The forward differential amplifier module includes: a first transistor M1, a second transistor M2, a seventh transistor M7, an eighth transistor M8, a first DC blocking capacitor C1, a second DC blocking capacitor C2, a first inter-stage inductor L1, a second inter-stage inductor L2, a first bias resistor RG1 and a second bias resistor RG2.

[0051] One end of the first DC blocking capacitor C1 is connected to the drain of the seventh transistor M7 and serves as the first input end of the forward differential amplifier module, and the gate of the seventh transistor M7 is connected to the fourth gate voltage Vd; the other end of the first DC blocking capacitor C1 is respectively connected to the gate of the first transistor M1 and one end of the first bias resistor RG1; the other end of the first bias resistor RG1 is connected to the first gate voltage Va; the source of the first transistor M1 is grounded, the drain of the first transistor M1 is connected to one end of the first inter-stage inductor L1 and the source of the eighth transistor M8, and the other end of the first inter-stage inductor L1 is the first output end of the forward differential amplifier module.

[0052] One end of the second DC blocking capacitor C2 is connected to the drain of the eighth transistor M8 and serves as the second input end of the forward differential amplifier module, and the gate of the eighth transistor M8 is connected to the fourth gate voltage Vd; the other end of the second DC blocking capacitor C2 is respectively connected to the gate of the second transistor M2 and one end of the second bias resistor RG2; the other end of the second bias resistor RG2 is connected to the first gate voltage Va; the source of the second transistor M2 is grounded, the drain of the second transistor M2 is connected to one end of the second inter-stage inductor L2 and the source of the seventh transistor M7, and the other end of the second inter-stage inductor L2 is the second output end of the forward differential amplifier module.

[0053] The reverse differential amplifier module includes: a third transistor M3, a fourth transistor M4, a fifth transistor M5, a sixth transistor M6, a third DC blocking capacitor C3, a fourth DC blocking capacitor C4, a third inter-stage inductor L3, a fourth inter-stage inductor L4, a third bias resistor RG3, and a fourth bias resistor RG4.

[0054] One end of the third DC blocking capacitor C3 is connected to the drain of the fifth transistor M5 and serves as the first output end of the reverse differential amplifier module, and the gate of the fifth transistor M5 is connected to the third gate voltage Vc; the other end of the third DC blocking capacitor C3 is respectively connected to the gate of the third transistor M3 and one end of the third bias resistor RG3; the other end of the third bias resistor RG3 is connected to the second gate voltage Vb; the source of the third transistor M3 is grounded, the drain of the third transistor M3 is connected to one end of the third inter-stage inductor L3 and the source of the sixth transistor M6, and the other end of the third inter-stage inductor L3 is the first input end of the reverse differential amplifier module;

[0055] One end of the fourth DC blocking capacitor C4 is connected to the drain of the sixth transistor M6 and serves as the second output end of the reverse differential amplifier module, and the gate of the sixth transistor M6 is connected to the third gate voltage Vc; the other end of the fourth DC blocking capacitor C4 is respectively connected to the gate of the fourth transistor M4 and one end of the fourth bias resistor RG4; the other end of the fourth bias resistor RG4 is connected to the second gate voltage Vb; the source of the fourth transistor M4 is grounded, the drain of the fourth transistor M4 is connected to one end of the fourth inter-stage inductor L4 and the source of the fifth transistor M5, and the other end of the fourth inter-stage inductor L4 is the second input end of the reverse differential amplifier module.

[0056] The first to fourth transistor arrays include the ninth to fourteenth transistors M9 to M14, the fifteenth to twentieth transistors M15 to M20, the twenty-first to twenty-sixth transistors M21 to M26, and the twenty-seventh to thirty-second transistors M27 to M32, respectively. The gates of the ninth to thirty-second transistors M9 to M32 are connected to the ninth to thirty-second gate voltages V9 to V32, which are independent of each other. The width ratios of the ninth to fourteenth transistors M9 to M14, the fifteenth to twentieth transistors M15 to M20, the twenty-first to twenty-sixth transistors M21 to M26, and the twenty-seventh to thirty-second transistors M27 to M32 are all 1:2:4:8:16:32. The widths of the ninth transistor M9, the fifteenth transistor M15, the twenty-first transistor M21, and the twenty-seventh transistor M27 are the same.

[0057] When the present embodiment is in working state, in the first transistor array and the fourth transistor array, the gate voltages of transistors with the same width are the same, that is, the ninth gate voltage V9 is the same as the twenty-seventh gate voltage V27, the tenth gate voltage V10 is the same as the twenty-eighth gate voltage V28, the eleventh gate voltage V11 is the same as the twenty-ninth gate voltage V29, the twelfth gate voltage V12 is the same as the thirtieth gate voltage V30, the thirteenth gate voltage V13 is the same as the thirty-first gate voltage V31, and the fourteenth gate voltage V14 is the same as the thirty-second gate voltage V32; in the second transistor array and the third transistor array, the gate voltages of transistors with the same width are the same, that is, the fifteenth gate voltage V15 is the same as the twenty-first gate voltage V21, the sixteenth gate voltage V16 is the same as the twenty-second gate voltage V22, the seventeenth gate voltage V17 is the same as the twenty-third gate voltage V23, the eighteenth gate voltage V18 is the same as the twenty-fourth gate voltage V24, the nineteenth gate voltage V19 is the same as the twenty-fifth gate voltage V25, and the twentieth gate voltage V20 is the same as the twenty-sixth gate voltage V26.

[0058] When this embodiment is in forward operation, the first gate voltage Va is adjusted so that the first transistor M1 and the second transistor M2 operate in the saturation region; the second gate voltage Vb is adjusted so that the third transistor M3 and the fourth transistor M4 are turned off; the third gate voltage Vc is adjusted so that the fifth transistor M5 and the sixth transistor M6 are turned on; and the fourth gate voltage Vd is adjusted so that the seventh transistor M7 and the eighth transistor M8 are turned off.

[0059] The input signal of the first input / output terminal is transmitted to the gate of the first transistor M1 after passing through the first DC blocking capacitor C1. Due to the DC blocking effect of the first DC blocking capacitor C1, the gate bias of the first transistor M1 is provided by the first bias resistor RG1. The input signal of the first input / output terminal is amplified by the first transistor M1, and then enters the second transistor array and the fourth transistor array after further gain by the first interstage inductor L1. The fifteenth to twentieth gate voltages V15-V20 and the twenty-seventh to thirty-second gate voltages V27-V32 are adjusted so that the fifteenth to twentieth gate voltages V15-V20 and the twenty-seventh to thirty-second gate voltages V27-V32 are complementary to each other, and the number of transistors turned on in the two transistor arrays is ensured to be the same while changing the gain, thereby ensuring the constant port impedance of this embodiment. The input signal of the first input / output terminal passes through the second transistor array and the fourth transistor array, respectively passes through the third interstage inductor L3 and the fourth interstage inductor L4, and then respectively passes through the turned-on sixth transistor M6 and the fifth transistor M5 to the fourth input / output terminal and the third input / output terminal.

[0060] The input signal of the second input / output terminal is transmitted to the gate of the second transistor M2 after passing through the second DC blocking capacitor C2. Due to the DC blocking effect of the second DC blocking capacitor C2, the gate bias of the second transistor M2 is provided by the second bias resistor RG2. The input signal of the second input / output terminal is amplified by the second transistor M2, and then enters the first transistor array and the third transistor array after further gain by the second interstage inductor L2. The ninth to fourteenth gate voltages V9-V14 and the twenty-first to twenty-sixth gate voltages V21-V26 are adjusted so that the ninth to fourteenth gate voltages V9-V14 and the twenty-first to twenty-sixth gate voltages V21-V26 are complementary to each other, and the number of transistors turned on in the two transistor arrays is ensured to be the same while changing the gain, thereby ensuring the constant port impedance of this embodiment. The input signal of the second input / output terminal passes through the first transistor array and the third transistor array, respectively passes through the third interstage inductor L3 and the fourth interstage inductor L4, and then respectively passes through the turned-on sixth transistor M6 and the fifth M5 to the fourth input / output terminal and the third input / output terminal.

[0061] When this embodiment is in reverse operation, the first gate voltage Va is adjusted so that the first transistor M1 and the second transistor M2 are turned off; the second gate voltage Vb is adjusted so that the third transistor M3 and the fourth transistor M4 operate in the saturation region; the third gate voltage Vc is adjusted so that the fifth transistor M5 and the sixth transistor M6 are turned off; and the fourth gate voltage Vd is adjusted so that the seventh transistor M7 and the eighth transistor M8 are turned on.

[0062] The input signal of the third input / output terminal is transmitted to the gate of the third transistor M3 after passing through the third DC blocking capacitor C3. Due to the DC blocking effect of the third DC blocking capacitor C3, the gate bias of the third transistor M3 is provided by the third bias resistor RG3. The input signal of the first input / output terminal is amplified by the third transistor M3, and then enters the first transistor array and the second transistor array after further gain by the third interstage inductor L3. The ninth to fourteenth gate voltages V9-V14 and the fifteenth to twentieth gate voltages V15-V20 are adjusted so that the ninth to fourteenth gate voltages V9-V14 and the fifteenth to twentieth gate voltages V15-V20 are complementary to each other, and the number of transistors turned on in the two transistor arrays is ensured to be the same while changing the gain, thereby ensuring the constant port impedance of this embodiment. The input signal of the third input / output terminal passes through the first transistor array and the second transistor array, respectively passes through the second interstage inductor L2 and the first interstage inductor L1, and then respectively passes through the turned-on seventh transistor M7 and the eighth transistor M8 to the first input / output terminal and the second input / output terminal.

[0063] The input signal of the fourth input-output terminal is transmitted to the gate of the fourth transistor M4 after passing through the fourth DC blocking capacitor C4. Due to the DC blocking effect of the fourth DC blocking capacitor C4, the gate bias of the fourth transistor M4 is provided by the fourth bias resistor RG4. The input signal of the second input-output terminal is amplified by the fourth transistor M4, and then enters the third transistor array and the fourth transistor array after further gain by the fourth interstage inductor L4. The twenty-first to twenty-sixth gate voltages V21-V26 and the twenty-seventh to thirty-second gate voltages V27-V32 are adjusted so that the twenty-first to twenty-sixth gate voltages V21-V26 and the twenty-seventh to thirty-second gate voltages V27-V32 are complementary, and the number of transistors turned on in the two transistor arrays is ensured to be the same while changing the gain, thereby ensuring the constant port impedance of this embodiment. The input signal of the fourth input-output terminal passes through the third transistor array and the fourth transistor array, respectively passes through the second interstage inductor L2 and the first interstage inductor L1, and then respectively passes through the turned-on seventh transistor M7 and eighth transistor M8 to the first input-output terminal and the second input-output terminal.

[0064] It should be noted that, in the present embodiment, the ratio of the widths of the ninth to fourteenth transistors M9 to M14, the fifteenth to twentieth transistors M15 to M20, the twenty-first to twenty-sixth transistors M21 to M26, and the twenty-seventh to thirty-second transistors M27 to M32 are all set to 1:2:4:8:16:32, and the widths of the ninth transistor M9, the fifteenth transistor M15, the twenty-first transistor M21, and the twenty-seventh transistor M27 are the same, which can be adjusted according to actual conditions, as long as each transistor array is ensured to be six transistors with widths that are continuously doubled in parallel, and the widths of the transistors with the smallest widths in the first to fourth transistor arrays are the same.

[0065] It should be noted that in the first to fourth transistor arrays in this embodiment, the number of transistors in each transistor array is six, which can be adjusted according to actual conditions. Considering the influence of phase shift accuracy and layout, the number of transistors in each transistor array is more appropriately five to seven.

[0066] In summary, this embodiment can achieve bidirectional operation and can ensure that the input and output impedances are in a constant state while being able to change the amplifier gain.

[0067] Embodiment 2 A phase shifter

[0068] like Figure 2 As shown, this embodiment is a phase shifter, which includes, in addition to the two constant impedance bidirectional variable gain amplifiers described in the first embodiment, an orthogonal signal generator, first to third baluns and a vector synthesizer.

[0069] The input end of the orthogonal signal generator is the input end of this embodiment, and the two output ends of the orthogonal signal generator are respectively connected to the input ends of the first balun and the second balun. The two output ends of the first balun are respectively connected to the first input and output ends and the second input and output ends of one of the constant impedance bidirectional variable gain amplifiers, and the two output ends of the second balun are respectively connected to the first input and output ends and the second input and output ends of another constant impedance bidirectional variable gain amplifier. The third input and output ends and the fourth input and output ends of the two constant impedance bidirectional variable gain amplifiers are respectively connected to the input ends of the vector synthesizer; the two output ends of the vector synthesizer are respectively connected to the two input ends of the third balun, and the output end of the third balun is the output end of this embodiment. In this embodiment, the orthogonal signal generator uses a coupled line coupler; the first to third baluns are transmission type baluns.

[0070] The first balun includes a first-level coil L11 and a second-level coil L12, one end of the first-level coil L11 is the input end of the first balun, the other end is grounded, and the two ends of the second-level coil L12 are the two output ends of the first balun. The second balun includes a third-level coil L21 and a fourth-level coil L22, one end of the third-level coil L21 is the input end of the second balun, the other end is grounded, and the two ends of the fourth-level coil L22 are the two output ends of the second balun. The third balun includes a fifth-level coil L31 and a sixth-level coil L32, the two ends of the fifth-level coil L31 are the two input ends of the third balun, one end of the sixth-level coil L32 is grounded, and the other end is the output end of the third balun.

[0071] In this embodiment, the vector synthesis method used by the vector synthesizer is the current synthesis method. Figure 3 shown.

[0072] like Figure 2 and Figure 3 As shown, in this embodiment, when the signal is input in the forward direction, the two constant impedance bidirectional variable gain amplifiers are adjusted to the forward working state. At this time, the signal is converted into two orthogonal signals through the orthogonal signal generator, and then the two orthogonal signals are converted into four orthogonal signals IN through the single-ended conversion of the first balun and the second balun respectively. in 、IP in , QN in and QP in The four-way orthogonal signal generates a new four-way signal IN after passing through the constant impedance bidirectional variable gain amplifier. out 、IP out , QN out and QP outThen, the new four-way signal is vector synthesized by the vector synthesizer, and finally the output signal is obtained by converting the differential to single-ended by the third balun. When the signal is input in reverse, it is only necessary to adjust the two constant impedance bidirectional variable gain amplifiers to the reverse working state to realize the operation of this embodiment when the signal is input in reverse.

[0073] like Figure 4 and Figure 5 As shown, this embodiment achieves six-bit high-precision phase shifting in both forward phase shifting and reverse phase shifting, wherein the minimum phase shifting step is 5.625°.

[0074] like Figure 6 , Figure 7 and Figure 8 As shown, this embodiment can achieve a phase error of 0.63° to 1.09° and a gain error of 0.28dB to 0.78dB when working in the forward direction, and an average gain of -5.35dB; it can achieve a phase error of 0.76° to 1.3° and a gain error of 0.48dB to 0.9dB when working in the reverse direction, and an average gain of -7.19dB.

[0075] In summary, the constant impedance bidirectional variable gain amplifier used in this embodiment has the characteristic of constant port impedance, which can ensure that the generated orthogonal signal will not be significantly deteriorated, can improve the accuracy of this embodiment, reduce RMS error and achieve lower insertion loss.

Claims

1. A constant impedance bidirectional variable gain amplifier, characterized in that: It includes a forward differential amplifier module, a reverse differential amplifier module and first to fourth transistor arrays; The first input terminal and the second input terminal of the forward differential amplifier module are respectively the first input and output terminals and the second input and output terminals of the constant impedance bidirectional variable gain amplifier; the first output terminal of the forward differential amplifier module is respectively connected to the drains of all transistors in the second transistor array and the drains of all transistors in the fourth transistor array; the second output terminal of the forward differential amplifier module is respectively connected to the drains of all transistors in the first transistor array and the drains of all transistors in the third transistor array; The sources of all transistors in the first transistor array and the second transistor array are connected to the first input terminal of the reverse differential amplifier module; the sources of all transistors in the third transistor array and the fourth transistor array are connected to the second input terminal of the reverse differential amplifier module; the gates of all transistors in the first to fourth transistor arrays are connected to independent gate voltages; The first output terminal and the second output terminal of the reverse differential amplifier module are respectively the third input and output terminal and the fourth input and output terminal of the constant impedance bidirectional variable gain amplifier.

2. A constant impedance bidirectional variable gain amplifier according to claim 1, characterized in that: The forward differential amplifier module includes: a first transistor, a second transistor, a seventh transistor, an eighth transistor, a first DC blocking capacitor, a second DC blocking capacitor, a first inter-stage inductor, a second inter-stage inductor, a first bias resistor, and a second bias resistor; One end of the first DC blocking capacitor is connected to the drain of the seventh transistor and serves as the first input end of the forward differential amplifier module, and the gate of the seventh transistor is connected to the fourth gate voltage; the other end of the first DC blocking capacitor is respectively connected to the gate of the first transistor and one end of the first bias resistor; the other end of the first bias resistor is connected to the first gate voltage; the source of the first transistor is grounded, the drain of the first transistor is connected to one end of the first interstage inductor and the source of the eighth transistor, and the other end of the first interstage inductor is the first output end of the forward differential amplifier module; One end of the second DC blocking capacitor is connected to the drain of the eighth transistor and serves as the second input end of the forward differential amplifier module, and the gate of the eighth transistor is connected to the fourth gate voltage; the other end of the second DC blocking capacitor is respectively connected to the gate of the second transistor and one end of the second bias resistor; the other end of the second bias resistor is connected to the first gate voltage; the source of the second transistor is grounded, the drain of the second transistor is connected to one end of the second inter-stage inductor and the source of the seventh transistor, and the other end of the second inter-stage inductor is the second output end of the forward differential amplifier module.

3. The constant impedance bidirectional variable gain amplifier according to claim 1, characterized in that: The reverse differential amplifier module includes: a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a third DC blocking capacitor, a fourth DC blocking capacitor, a third inter-stage inductor, a fourth inter-stage inductor, a third bias resistor and a fourth bias resistor; One end of the third DC blocking capacitor is connected to the drain of the fifth transistor and serves as the first output end of the reverse differential amplifier module, and the gate of the fifth transistor is connected to the third gate voltage; the other end of the third DC blocking capacitor is respectively connected to the gate of the third transistor and one end of the third bias resistor; the other end of the third bias resistor is connected to the second gate voltage; the source of the third transistor is grounded, the drain of the third transistor is connected to one end of the third inter-stage inductor and the source of the sixth transistor, and the other end of the third inter-stage inductor is the first input end of the reverse differential amplifier module; One end of the fourth DC blocking capacitor is connected to the drain of the sixth transistor and serves as the second output end of the reverse differential amplifier module, and the gate of the sixth transistor is connected to the third gate voltage; the other end of the fourth DC blocking capacitor is respectively connected to the gate of the fourth transistor and one end of the fourth bias resistor; the other end of the fourth bias resistor is connected to the second gate voltage; the source of the fourth transistor is grounded, the drain of the fourth transistor is connected to one end of the fourth inter-stage inductor and the source of the fifth transistor, and the other end of the fourth inter-stage inductor is the second input end of the reverse differential amplifier module.

4. The constant impedance bidirectional variable gain amplifier according to claim 1, characterized in that: In the first to fourth transistor arrays, each transistor array includes N transistors whose widths increase by two times continuously; 5≤N≤7, and N is a positive integer.

5. A constant impedance bidirectional variable gain amplifier according to claim 4, characterized in that: In the first to fourth transistor arrays, the transistors with the smallest widths have the same width.

6. A phase shifter, characterized in that: A constant impedance bidirectional variable gain amplifier comprising two of claims 1 to 5, further comprising an orthogonal signal generator, first to third baluns and a vector synthesizer; The input end of the orthogonal signal generator is the input end of the phase shifter, the two output ends of the orthogonal signal generator are respectively connected to the input ends of the first balun and the second balun, the two output ends of the first balun are respectively connected to the first input-output end and the second input-output end of one of the constant impedance bidirectional variable gain amplifiers, and the two output ends of the second balun are respectively connected to the first input-output end and the second input-output end of another constant impedance bidirectional variable gain amplifier; The third input-output terminal and the fourth input-output terminal of the two constant impedance bidirectional variable gain amplifiers are respectively connected to the input terminal of the vector synthesizer; the two output terminals of the vector synthesizer are respectively connected to the two input terminals of the third balun, and the output terminal of the third balun is the output terminal of the phase shifter.

7. The phase shifter according to claim 6, characterized in that: The first balun includes a first coil and a second coil, one end of the first coil is the input end of the first balun, the other end is grounded, and two ends of the second coil are two output ends of the first balun; The second balun includes a third coil and a fourth coil, one end of the third coil is the input end of the second balun, and the other end is grounded, and two ends of the fourth coil are two output ends of the second balun; The third balun includes a fifth coil and a sixth coil. Two ends of the fifth coil are two input ends of the third balun. One end of the sixth coil is grounded, and the other end is the output end of the third balun.

8. The phase shifter according to claim 6, characterized in that: The orthogonal signal generator uses a coupled line coupler.

9. The phase shifter according to claim 6, characterized in that: The vector synthesis method used by the vector synthesizer is a current synthesis method.

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