DLL circuit, control method and electronic equipment

Abstract

The invention discloses a DLL circuit, a control method and electronic equipment, and belongs to the technical field of electronic equipment. The DLL circuit includes a phase discriminator, a charge pump, a voltage-controlled delay line, and a processing unit. An annular oscillator in the voltage-controlled delay line carries out oscillation processing on an input clock signal and outputs an oscillation signal. Under the condition that the frequency of the oscillation signal does not meet the target frequency, the processing unit adjusts the load capacitance of the second delay unit of the ring oscillator until the target frequency is met, the ring oscillator is controlled to stop working, and the load capacitance of the first delay unit and the load capacitance of the second delay unit are equal to the load capacitance of the first delay unit in the voltage-controlled delay line. The voltage-controlled delay line delays an input clock signal and outputs a target clock signal. The phase discriminator outputs a phase difference signal according to the phases of the target clock signal and the input clock signal. The charge pump outputs a control voltage signal according to the phase difference signal. According to the invention, the adjustment range of the delay duration of the first delay unit is improved.

Description

Technical Field

[0001] The present application belongs to the technical field of electronic equipment, and specifically relates to a DLL circuit, a control method and an electronic equipment. Background Art

[0002] A Delay Locked Loop (DLL) circuit is a clock generation circuit that is used to output a clock signal that is phase-aligned with an input clock signal based on a delayed input clock signal. DLL circuits are widely used in microprocessors, memory interfaces, interfaces between chips, and clock distribution networks for large-scale integrated circuits.

[0003] However, the current DLL circuit is limited by the delay method of the input clock signal. The frequency of the input clock signal that can be delayed by the DLL circuit is positively correlated with the number of delay units in the DLL circuit. That is, the higher the frequency of the input clock signal that the DLL circuit needs to delay, the larger the number of delay units in the DLL circuit. Therefore, the frequency of the input clock signal is limited due to the circuit area of ​​the DLL circuit. Moreover, the frequency of the output signal of the DLL circuit is equal to the frequency of the input clock signal, and the frequency of the output signal of the DLL circuit is also limited accordingly, resulting in the problem that the frequency range of the output signal of the DLL circuit is narrow. Summary of the invention

[0004] A DLL circuit, a control method and an electronic device provided in the embodiments of the present application can, to a certain extent, solve the problem of a narrow frequency range of an output signal of a current DLL circuit.

[0005] In a first aspect, a DLL circuit is provided, the DLL circuit comprising: a phase detector, a charge pump unit, a voltage-controlled delay line and a processing unit connected in sequence, and the voltage-controlled delay line is also connected to the phase detector;

[0006] The voltage-controlled delay line comprises a ring oscillator and a plurality of cascaded first delay units, the ring oscillator comprises a plurality of cascaded second delay units, and the ring oscillator is used to generate an oscillation signal;

[0007] The processing unit is used for adjusting the size of the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, until the frequency of the oscillation signal meets the target frequency, controlling the ring oscillator to stop working, and controlling the sizes of the load capacitances of the first delay unit and the second delay unit to be equal; wherein the target frequency is determined by the product of a first ratio and the frequency of an input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units;

[0008] The voltage-controlled delay line is used to delay the input clock signal through the plurality of cascaded first delay units and output a target clock signal when the ring oscillator is stopped;

[0009] The phase detector is used to output a phase difference signal according to a phase comparison result between the target clock signal and the input clock signal;

[0010] The charge pump unit is used to output a control voltage signal according to the phase difference signal, and the control voltage signal is used at least to adjust the delay time of the first delay unit until the target clock signal is delayed by one clock cycle of the input clock signal compared to the input clock signal.

[0011] In a second aspect, a control method of a DLL circuit is provided, which is applied to any DLL circuit described in the first aspect, and the method comprises:

[0012] Controlling the ring oscillator to operate;

[0013] When the frequency of the oscillation signal output by the ring oscillator does not meet the target frequency, adjusting the size of the load capacitance of the second delay unit, wherein the target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units;

[0014] When the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the ring oscillator is controlled to stop working, and the load capacitances of the first delay unit and the second delay unit are controlled to be equal;

[0015] Delaying the input clock signal through the plurality of cascaded first delay units to obtain a target clock signal;

[0016] Performing phase comparison between the target clock signal and the input clock signal by the phase detector;

[0017] When it is determined based on the phase comparison result that the delay of the target clock signal compared to the input clock signal is less than one clock cycle, the delay duration of the first delay unit is adjusted through the charge pump unit, and the input clock signal is delayed again through the first delay unit until the delay of the target clock signal compared to the input clock signal satisfies one clock cycle.

[0018] According to a third aspect, an electronic device is provided, wherein the electronic device comprises the DLL circuit described in any one of the first aspects.

[0019] In a fourth aspect, an electronic device is provided, comprising: a processor and a memory; the memory is used to store computer programs; and the processor is used to implement any method step described in the second aspect when executing the program stored in the memory.

[0020] In a fifth aspect, a readable storage medium is provided, on which a program or instruction is stored. When the program or instruction is executed by a processor, the method steps described in any one of the second aspects are implemented.

[0021] In a sixth aspect, a computer program product is provided, comprising a computer program / instruction, wherein when the computer program / instruction is executed by a processor, the steps of any method described in the second aspect are implemented.

[0022] In an embodiment of the present application, the DLL circuit includes a phase detector, a charge pump unit, a voltage-controlled delay line and a processing unit connected in sequence, and the voltage-controlled delay line is also connected to the phase detector. The voltage-controlled delay line includes a ring oscillator and a plurality of cascaded first delay units. The ring oscillator includes a plurality of cascaded second delay units.

[0023] The ring oscillator can generate an oscillation signal. When the frequency of the oscillation signal does not meet the target frequency, the processing unit can adjust the delay time of the second delay unit by adjusting the load capacitance of the second delay unit in the ring oscillator, thereby adjusting the oscillation frequency of the ring oscillator until the frequency of the oscillation signal generated by the ring oscillator meets the target frequency. The target frequency is determined by the product of a first ratio and a frequency of an input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units.

[0024] In this way, when the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the processing unit controls the load capacitance of the first delay unit and the load capacitance of the second delay unit in the voltage-controlled delay line to be equal, so that the capacitance value of the load capacitance of each first delay unit meets the capacitance value requirement corresponding to the frequency of the input clock signal. In addition, the voltage-controlled delay line delays the input clock signal through all the first delay units, and can output a target clock signal with a frequency equal to the frequency of the input clock signal. The phase detector outputs a phase difference signal to the charge pump unit based on the phase comparison result of the target clock signal and the input clock signal, so that the charge pump unit outputs a control voltage signal based on the phase difference signal to adjust the delay time of the first delay unit until the target clock signal is delayed by a clock cycle of the input clock signal compared to the input clock signal, thereby achieving effective locking of the DLL circuit.

[0025] In this technical solution, a ring oscillator can be used to adjust the load capacitance of each first delay unit in the voltage-controlled delay line to match the frequency of the input clock signal that the voltage-controlled delay line needs to process for delay, reduce the frequency of the input clock signal processed by the DLL circuit, and affect the number of first delay units in the voltage-controlled delay line and the circuit area of ​​the DLL circuit. This effectively expands the frequency range of the input clock signal that can be processed by the DLL circuit, and then effectively improves the frequency range of the output signal of the DLL circuit. In addition, the delay unit in the voltage-controlled delay line has the problem of differences in the frequency range of the input clock signal supported due to process angle, temperature, etc. The technical solution of this application can also use a ring oscillator to correct the delay and frequency deviation supported by a single first delay unit in the voltage-controlled delay line. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a structural schematic diagram of a DLL circuit provided in an embodiment of the present application;

[0027] Figure 2 is a schematic diagram of the structure of a voltage-controlled delay line provided in an embodiment of the present application;

[0028] Figure 3 is a structural schematic diagram of another DLL circuit provided in an embodiment of the present application;

[0029] Figure 4 is a flow chart of a control method of a DLL circuit provided in an embodiment of the present application;

[0030] Figure 5 This is a block diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0031] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0032] A DLL circuit is a clock generation circuit that is used to output a clock signal that is phase-aligned with an input clock signal. DLL circuits are widely used in microprocessors, memory interfaces, interfaces between chips, and clock distribution networks for large-scale integrated circuits.

[0033] The current DLL circuit mainly includes: a phase comparator, a charge pump unit and a voltage-controlled delay line. The delay unit in the voltage-controlled delay line can delay the input clock signal and output a delayed clock signal. The phase comparator can output a phase difference signal based on the phase comparison result between the delayed clock signal and the input clock signal. The charge pump unit can output a control voltage to the voltage-controlled delay line based on the phase difference signal to change the delay time of the delay unit in the voltage-controlled delay line, thereby causing the delay unit in the voltage-controlled delay line to re-delay the input clock signal until the voltage-controlled delay line outputs a delayed clock signal that is delayed by a target clock cycle compared to the input clock signal, and the DLL circuit is locked. Among them, the frequency of the delayed clock signal output by the voltage-controlled delay line is equal to the frequency of the input clock signal, and the phase difference is a target clock cycle. The target clock cycle is the clock cycle of the input clock signal. In addition, the DLL circuit can also output the delayed clock signal output by each delay unit in the voltage-controlled delay line.

[0034] However, the current DLL circuit is limited by the delay method of the input clock signal. The frequency of the input clock signal that can be delayed by the DLL circuit is positively correlated with the number of delay units in the DLL circuit. That is, the higher the frequency of the input clock signal that the DLL circuit needs to delay, the larger the number of delay units in the DLL circuit. Therefore, the frequency of the input clock signal is limited due to the circuit area of ​​the DLL circuit. Moreover, the frequency of the output signal of the DLL circuit is equal to the frequency of the input clock signal, and the frequency of the output signal of the DLL circuit is also limited accordingly, resulting in the problem that the frequency range of the output signal of the DLL circuit is narrow.

[0035] Please refer to Figure 1 , which shows a structural diagram of a DLL circuit provided by an embodiment of the present application. Figure 1 As shown, the DLL circuit 100 includes: a phase detector (PD) 101, a charge pump (CP) unit 102, a voltage-controlled delay line 103 and a processing unit 104 connected in sequence, and the voltage-controlled delay line 103 is also connected to the phase detector 101. The phase detector 101, the charge pump unit 102, and the voltage-controlled delay line 103 can form a circuit loop.

[0036] The voltage-controlled delay line 103 includes a ring oscillator 1031 and a plurality of cascaded first delay units 1032. The ring oscillator 1031 includes a plurality of cascaded second delay units. The ring oscillator 1031 is used to generate an oscillation signal. Optionally, the ring oscillator 1031 is used to generate an oscillation signal when each second delay unit receives the same voltage control signal transmitted by the charge pump unit 102.

[0037] The processing unit 104 is used to adjust the size of the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency until the frequency of the oscillation signal meets the target frequency, control the ring oscillator 1031 to stop working, and control the sizes of the load capacitances of the first delay unit 1032 and the second delay unit to be equal.

[0038] The voltage-controlled delay line 103 is used to delay the input clock signal through a plurality of cascaded first delay units 1032 (ie, all the first delay units 1032 of the voltage-controlled delay line 103) and output a target clock signal when the ring oscillator 1031 is stopped.

[0039] The phase detector 101 is used to output a phase difference signal according to the phase comparison result of the target clock signal and the input clock signal. Optionally, the phase detector 101 is also called a phase frequency detector (PFD), and the phase difference signal outputted by the phase detector 101 may include a first phase signal DN and a second phase signal UP. In the case where the phase of the input clock signal is ahead of the target clock signal, the first phase signal DN outputted by the phase detector 101 is a low level, and the second phase signal UP is a high level. The phase difference signal indicates that the delay time of the first delay unit needs to be reduced. In the case where the phase of the target clock signal is ahead of the target clock signal, the first phase signal DN outputted by the phase detector 101 is a high level, and the second phase signal UP is a low level. The phase difference signal indicates that the delay time of the first delay unit needs to be increased. In the case where the phase of the target clock signal is equal to the phase of the target clock signal, the first phase signal DN outputted by the phase detector 101 is a low level, and the second phase signal UP is a low level. The phase difference signal indicates that the phase of the target clock signal is aligned with the input clock signal, and the DLL circuit 100 is locked.

[0040] The charge pump unit 102 is used to output a control voltage signal according to the phase difference signal, wherein the control voltage signal is used to at least adjust the delay time of the first delay unit 1032 until the target clock signal is delayed by a clock cycle of the input clock signal compared to the input clock signal.

[0041] In the embodiment of the present application, the voltage-controlled delay line 103 is used to generate an oscillation signal by oscillating the ring oscillator 1031 when the ring oscillator 1031 is in operation. The processing unit 104 is used to determine whether the frequency of the oscillation signal meets the target frequency, so as to adjust the size of the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, until the frequency of the oscillation signal meets the target frequency, stop adjusting the size of the load capacitance of the second delay unit, and control the ring oscillator 1031 to stop working. At this time, the frequency of the oscillation signal meets the target frequency, and the size of the load capacitance of the second delay unit is known. The processing unit 104 can be used to adjust the load capacitance of the first delay unit 1032 to the size of the known load capacitance of the second delay unit, so that the load capacitance of the first delay unit 1032 and the load capacitance of the second delay unit are equal.

[0042] The voltage-controlled delay line 103 is also used to delay the input clock signal through all the first delay units 1032 and output the target clock signal when the ring oscillator 1031 is stopped. The phase detector 101 is used to output a phase difference signal to the charge pump unit 102 according to the phase comparison result between the target clock signal and the input clock signal. The charge pump unit 102 is used to output a control voltage signal to the voltage-controlled delay line 103 according to the phase difference signal, so that the voltage-controlled delay line 103 delays the input clock signal again through all the first delay units 1032 after the delay time is adjusted, and outputs the target clock signal, until the phase detector 101 determines that the phases of the target clock signal and the input clock signal are equal, and the target clock signal is delayed by a clock cycle of the input clock signal compared to the input clock signal.

[0043] Among them, in the DLL output circuit DLL circuit 100, the target clock signal output by all the first delay units 1032 of the voltage-controlled delay line 103 has a signal frequency equal to the signal frequency of the input clock signal. And the oscillation frequency Fosc of the ring oscillator 1031 and the number N of the second delay units it includes satisfy: Fosc=1 / (2×N×Td). Fosc represents the oscillation frequency of the ring oscillator 1031, that is, the frequency of the oscillation signal output by the ring oscillator 1031. N represents the number of second delay units in the ring oscillator 1031, and Td represents the delay time of a single second delay unit.

[0044] Therefore, the target frequency that the ring oscillator 1031 needs to meet can be determined according to the ratio of the number of the second delay unit to the first delay unit. Specifically, the target frequency is determined by the product of the first ratio and the frequency of the input clock signal Ref_clk of the voltage-controlled delay line 103. The first ratio is the ratio of the number of the second delay unit to the number of the first delay unit 1032. That is, the target frequency Fo satisfies: Fo=(N 2 / N 1 )×F Ref_clk Where Fo represents the target frequency. 2 N represents the number of the second delay unit. 1 represents the number of first delay units 1032. Ref_clk Indicates the frequency of the input clock signal.

[0045] Furthermore, since the size of the load capacitance of the second delay unit in the ring oscillator can affect the delay time of the second delay unit, when the number of second delay units in the ring oscillator is determined, the size of the load capacitance of the second delay unit can be adjusted to adjust the delay time of the second delay unit, thereby adjusting the frequency of the oscillation signal output by the ring oscillator.

[0046] Similarly, the size of the load capacitance of the first delay unit 1032 will also affect the delay time of the first delay unit 1032, and further affect the frequency of the output signal of the voltage-controlled delay line 103. The frequency of the input signal (i.e., the input clock signal) of the voltage-controlled delay line 103 is equal to the frequency of the output signal. Therefore, it can be understood that the size of the load capacitance of the first delay unit 1032 will affect the frequency of the input clock signal supported by the voltage-controlled delay line 103. In this way, when the sizes of the load capacitances of the first delay unit 1032 and the second delay unit are equal, the delay times of the first delay unit 1032 and the second delay unit are the same, and the ratio of the oscillation frequency of the ring oscillator to the frequency of the input clock signal supported by the voltage-controlled delay line is equal to the ratio of the number of the second delay unit to the first delay unit.

[0047] In an optional case, the processing unit 104 can be used to adjust the size of the load capacitance of the second delay unit according to the capacitance value variable when the frequency of the oscillation signal does not meet the target frequency. The capacitance value variable can be a fixed value. Or, the size of the capacitance value variable can be reduced as the number of adjustments increases. In this way, when the frequency of the oscillation signal is closer to the target frequency, the smaller the value of the capacitance value variable is, the higher the adjustment accuracy of the delay time length of the second delay unit is.

[0048] In another optional case, both the first delay unit 1032 and the second delay unit include a capacitor array, that is, the load capacitors of the first delay unit 1032 and the second delay unit are capacitor arrays.

[0049] The processing unit 104 can be used to adjust the number of capacitors in the working state in the capacitor array of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, so as to adjust the size of the load capacitance of the second delay unit. Further optionally, the processing unit 104 can adjust the number of capacitors in the working state in the second delay unit by using the dichotomy method according to the number of capacitors in the capacitor array of the second delay unit to adjust the size of the load capacitance of the second delay unit. In this way, by adjusting the size of the load capacitance of the second delay unit by the dichotomy method, the frequency of the oscillation signal of the ring oscillator can be adjusted to the target frequency more quickly, and the adjustment efficiency of the delay time of the first delay unit and the second delay unit can be improved. In addition, the processing unit 104 can also adjust the number of capacitors in the working state in the second delay unit by using the traversal method according to the number of capacitors in the capacitor array of the second delay unit to adjust the size of the load capacitance of the second delay unit, etc. The embodiment of the present application does not limit the adjustment method of the load capacitance size of the second delay unit.

[0050] It should be noted that the implementation manner in which the processing unit 104 adjusts the size of the load capacitance of the first delay unit 1032 may refer to the implementation manner in which the processing unit 104 adjusts the size of the load capacitance of the second delay unit.

[0051] In an embodiment of the present application, the DLL circuit includes a phase detector, a charge pump, a voltage-controlled delay line and a processing unit connected in sequence, and the voltage-controlled delay line is also connected to the phase detector. The voltage-controlled delay line includes a ring oscillator and a plurality of cascaded first delay units. The ring oscillator includes a plurality of cascaded second delay units.

[0052] The ring oscillator can generate an oscillation signal. The processing unit can adjust the size of the load capacitor of the second delay unit to adjust the delay time of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, until the frequency of the oscillation signal meets the target frequency. In this way, when the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the processing unit controls the size of the load capacitor of the first delay unit and the load capacitor of the second delay unit in the voltage-controlled delay line to be equal, so that the capacitance value of the load capacitor of each first delay unit meets the capacitance value requirement corresponding to the frequency of the input clock signal. Then, the voltage-controlled delay line delays the input clock signal through all the first delay units, and can output a target clock signal with a frequency equal to the frequency of the input clock signal. The phase detector outputs a phase difference signal to the charge pump unit according to the phase comparison result of the target clock signal and the input clock signal, so that the charge pump unit outputs a control voltage signal according to the phase difference signal to adjust the delay time of the first delay unit until the target clock signal is delayed by a clock cycle of the input clock signal compared to the input clock signal, thereby achieving effective locking of the DLL circuit.

[0053] In this technical solution, a ring oscillator can be used to adjust the load capacitance of each first delay unit in the voltage-controlled delay line to match the frequency of the input clock signal that the voltage-controlled delay line needs to process for delay, reduce the frequency of the input clock signal processed by the DLL circuit, and the impact on the number of first delay units in the voltage-controlled delay line and the circuit area of ​​the DLL circuit. Thereby effectively expanding the frequency range of the input clock signal that can be processed by the DLL circuit, and then effectively improving the frequency range of the output signal of the DLL circuit. In addition, the delay unit in the voltage-controlled delay line has the problem of differences in the frequency range of the input clock signal supported due to process angle, temperature and other reasons. The technical solution of the present application can also use a ring oscillator to correct the delay and frequency deviation supported by a single first delay unit in the voltage-controlled delay line. In addition, in the DLL circuit of the present application, by adjusting the load capacitance size to adjust the delay time, and by configuring the control voltage signal output by the charge pump to adjust the delay time, the delay time of the first delay unit can be adjusted by using different granularity delay time adjustment methods, effectively improving the adjustment accuracy of the delay time of the first delay unit in the voltage-controlled delay chain.

[0054] In the embodiment of the present application, the voltage-controlled delay line 103 includes a ring oscillator 1031 and a plurality of cascaded first delay units 1032. The ring oscillator 1031 includes a plurality of cascaded second delay units. The ring oscillator 1031 is used to oscillate the input clock signal Ref_clk and output an oscillation signal.

[0055] In an optional case, the plurality of cascaded second delay units are a plurality of first delay units 1032 that are partially cascaded continuously among the plurality of cascaded first delay units 1032. That is, the first delay unit 1032 can be reused to form the ring oscillator 1031, thereby reducing circuit components and simplifying the circuit structure. Figure 2 As shown, the ring oscillator 1031 includes a plurality of first delay units 1032 that are cascaded in series. In addition, the ring oscillator 1031 further includes a switch unit 10311. The switch unit 10311 is respectively connected to the first delay unit and the last delay unit of the plurality of second delay units.

[0056] The ring oscillator 1031 is used to oscillate the input clock signal and output an oscillation signal when the switch unit 10311 is closed. Accordingly, the processing unit 104 is used to control the switch unit 10311 to be disconnected when the frequency of the oscillation signal meets the target frequency, so as to control the ring oscillator 103 to stop working.

[0057] The number of second delay units included in the ring oscillator 1031 is not limited. However, it should be noted that the number of inverters in the ring oscillator 1031 should be an odd number. Therefore, in an optional case, the ring oscillator 1031 includes n cascaded second delay units, where n is an odd number greater than 2.

[0058] In another alternative case, if Figure 2 As shown, the ring oscillator 1031 includes n-1 cascaded second delay units, that is, the number of the second delay units in the ring oscillator 1031 is an even number.

[0059] The switch unit 10311 of the ring oscillator 1031 includes: a first switch element S1, an inverter G, and a second switch element S2. The first end of the first switch element S1 is connected to the first delay unit. The second end of the first switch element S1 is connected to the first end of the second switch element S2 through the inverter G. The second end of the second switch element S2 is connected to the last delay unit.

[0060] The ring oscillator 1031 is used to oscillate the input clock signal and output an oscillation signal when the first switch S1 and the second switch S2 are both closed. The processing unit 104 is also used to control the first switch S1 and the second switch S2 to be disconnected when the frequency of the oscillation signal meets the target frequency, so as to control the ring oscillator 1031 to stop working.

[0061] It should be noted that Figure 2 Taking the example that the voltage-controlled delay line 103 includes 8 first delay units and the ring oscillator 1031 reuses 4 first delay units as an example, it does not limit the number of first delay units that the voltage-controlled delay line 103 can include and the number of first delay units that the ring oscillator 1031 can include.

[0062] For example, Figure 2 As shown, the voltage-controlled delay line 103 includes 8 cascaded first delay units 1032 (first delay unit 0 to first delay unit 8). The ring oscillator 1031 reuses 4 cascaded first delay units 1032 (first delay unit 3 to first delay unit 6). The first end of the first switch element S1 in the ring oscillator 1031 is connected to the first delay unit 3 1032. The second end of the first switch element S1 is connected to the first end of the second switch element S2 through an inverter G. The second end of the second switch element S2 is connected to the first delay unit 6 1032. Wherein, when the first switch element S1 and the second switch element S2 are closed, the first delay unit 3 to the first delay unit 6 form a ring circuit structure through the first switch element S1 and the second switch element S2 to form a ring oscillator.

[0063] Each first delay unit in the voltage-controlled delay line 103 receives the same control voltage signal output by the charge pump. When the first switch S1 and the second switch S2 are both closed, the ring oscillator 1031 oscillates the input clock signal Ref_clk and outputs an oscillation signal Osc between the first delay unit 3 and the first delay unit 4.

[0064] When the frequency of the oscillation signal Osc does not meet the target frequency, the processing unit 104 outputs a capacitance adjustment signal Coarse swf<6:0> to the first delay unit 3 to the first delay unit 6 to adjust the load capacitance of the first delay unit 3 to the first delay unit 6 until the frequency of the oscillation signal meets the target frequency. The target frequency is 4 / 8×F Ref_clk , which is 1 / 2 of F Ref_clk The capacitance adjustment signal is used to control the number of capacitors in the ring oscillator 1031 that are in working state.

[0065] The first delay unit 3 to the first delay unit 6 in the ring oscillator 1031 are respectively used to adjust the number of capacitors in the capacitor array in the working state according to the capacitor adjustment signal. It should be noted that the oscillation signal Osc output by the ring oscillator 1031 can be the output signal between any two second delay units included therein. Figure 2 In the description, the oscillation signal Osc is taken as an output signal between the first second delay unit (first delay unit 3) and the second second delay unit (first delay unit 4) in the ring oscillator 1031. Of course, the oscillation signal Osc may also be an output signal between the second second delay unit and the third second delay unit in the ring oscillator 1031.

[0066] In another optional case, the second delay unit in the ring oscillator 1031 may also be an independent delay unit. In this case, the voltage-controlled delay line 103 includes: a delay chain and a ring oscillator 1031. The delay chain includes a plurality of cascaded first delay units 1032. The delay chain is used to delay the input clock signal through all the first delay units 1032, output the target clock signal to the outside of the DLL circuit, and output the input clock signal and the target clock signal to the phase detector 101. The ring oscillator 1031 is used to oscillate the input clock signal through all the second delay units, and output the oscillation signal to the processing unit 104.

[0067] In an embodiment of the present application, the processing unit 104 is used to adjust the size of the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, until the frequency of the oscillation signal meets the target frequency, control the ring oscillator 1031 to stop working, and the sizes of the load capacitances of the first delay unit 1032 and the second delay unit are equal.

[0068] That is, the processing unit 104 is used to receive the oscillation signal transmitted by the ring oscillator 1031, and determine whether the frequency of the oscillation signal meets the target frequency. When the frequency of the oscillation signal does not meet the target frequency, the size of the load capacitance of the second delay unit is adjusted. When the frequency of the oscillation signal meets the target frequency, the ring oscillator 1031 is controlled to stop working, and the sizes of the load capacitances of the first delay unit 1032 and the second delay unit are equal.

[0069] In an optional case, the processing unit 104 is also used to adjust the size of the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency until the frequency of the oscillation signal meets the target frequency, determine the current target capacitance value of the second delay unit, and adjust the load capacitance of the first delay unit to the target capacitance value.

[0070] In another optional case, when the plurality of cascaded second delay units in the ring oscillator 1031 are a plurality of continuously cascaded first delay units, the processing unit 104 is further used to adjust the load capacitance of all first delay units when the frequency of the oscillation signal does not meet the target frequency until the frequency of the oscillation signal meets the target frequency. The processing unit 104 can adjust the load capacitance of the second delay unit and the load capacitance of the first delay unit by referring to the aforementioned processing unit 104 adjusting the load capacitance of the second delay unit, and the embodiment of the present application will not be described in detail.

[0071] In some embodiments of the present application, the voltage-controlled delay line 103 is further used to output a delayed clock signal after delay processing by each first delay unit 1031. The target clock signal is a delayed clock signal output by the last first delay unit among the multiple first delay units of the voltage-controlled delay line.

[0072] Optionally, the DLL circuit 100 further includes: an anti-error lock control circuit 105. The anti-error lock control circuit 105 is connected to the voltage-controlled delay line 103 and the phase detector 101 respectively.

[0073] The error-proof lock control circuit 105 is used to determine the initial delay time of the voltage-controlled delay line 103 according to a plurality of delayed clock signals with equally spaced phase differences, and output a lock adjustment signal according to the relationship between the initial delay time and the effective delay range. The initial delay time refers to the total delay time of the voltage-controlled delay line before the first delay unit in the voltage-controlled delay line is adjusted by the processing unit 104 and the charge pump unit 102. When the target clock signal output by the voltage-controlled delay line after delay processing within the effective delay range is equal to the phase of the input clock signal, the target clock signal is delayed by one clock cycle compared to the input clock signal. Optionally, the effective delay range can be [0.5Tref_clk , 1.5T ref_clk ]. ref_clk Indicates the clock period of the input clock signal Ref_clk.

[0074] The phase detector 101 is used to output a phase difference signal according to a phase comparison result between the target clock signal and the input clock signal and a lock adjustment signal.

[0075] In the anti-error locking control circuit 105 in the embodiment of the present application, optionally, the locking adjustment signal may include a first locking signal upper, a second locking signal under and a third locking signal lock.

[0076] The error-proof lock control circuit 105 is used to output a high-level second lock signal under when the initial delay time is less than the minimum value of the effective delay range. The high-level second lock signal under indicates that the delay time of the first delay unit needs to be increased to prevent the DLL circuit from losing lock.

[0077] The error-proof lock control circuit 105 is also used to output a high-level first lock signal upper when the initial delay time is greater than the maximum value of the effective delay range. The high-level first lock signal upper indicates that the delay time of the first delay unit needs to be reduced to prevent harmonic lock of the DLL circuit.

[0078] The error-proof lock control circuit 105 is also used to output a third lock signal lock of a high level when the initial delay time is within the effective delay range. The third lock signal lock of a high level indicates that the DLL circuit can be locked.

[0079] The phase detector 101 in the embodiment of the present application can optionally include a phase difference signal output by the phase detector 101 according to a phase comparison result between the target clock signal and the input clock signal and a locking adjustment signal: a first phase signal DN, a second phase signal UP, a third phase signal NDN, and a fourth phase signal NUP.

[0080] The phase detector 101 is used to output a first phase signal DN of a low level, a second phase signal UP of a high level, a third phase signal NDN of a low level, and a fourth phase signal NUP of a high level when the phase of the input clock signal is ahead of the target clock signal and the first lock signal upper of a high level is received. The phase difference signal indicates that the delay time of the first delay unit needs to be reduced.

[0081] The phase detector 101 is used to output a first phase signal DN of a low level, a second phase signal UP of a high level, a third phase signal NDN of a low level, and a fourth phase signal NUP of a low level when the phase of the input clock signal is ahead of the target clock signal and the first lock signal upper of a low level is received. The phase difference signal indicates that the delay time of the first delay unit needs to be reduced.

[0082] The phase detector 101 is used to output a high-level first phase signal DN, a low-level second phase signal UP, a high-level third phase signal NDN, and a low-level fourth phase signal NUP when the phase of the target clock signal is ahead of the target clock signal and the second lock signal under is received. The phase difference signal indicates that the delay time of the first delay unit needs to be increased.

[0083] The phase detector 101 is used to output a first phase signal DN of a high level, a second phase signal UP of a low level, a third phase signal NDN of a low level, and a fourth phase signal NUP of a low level when the phase of the target clock signal is ahead of the target clock signal and the second lock signal under of a low level is received. The phase difference signal indicates that the delay time of the first delay unit needs to be increased.

[0084] The phase detector 101 is used to output a first phase signal DN of low level, a second phase signal UP of low level, a third phase signal NDN of low level, and a fourth phase signal NUP of low level when the phase of the target clock signal is equal to the phase of the input clock signal and a third lock signal of high level is received. The phase difference signal indicates that the phase of the target clock signal is aligned with the input clock signal and the DLL circuit 100 is locked.

[0085] In this way, the phase detector 101 and the anti-error lock control circuit 105 can effectively prevent the DLL circuit from losing lock or harmonic locking, thereby improving the locking effectiveness of the DLL circuit 100.

[0086] Further optionally, the DLL circuit 100 may further include a switch selection circuit (multiplexer, MUX) 106 . The switch selection circuit 106 is connected to the voltage-controlled delay line 103 and the error-proof lock control circuit 105 .

[0087] The switch selection circuit 106 is used to receive the delayed clock signal of each delayed clock signal, and output a plurality of delayed clock signals with equally spaced phase differences to the error protection lock control circuit 105. The switch selection circuit 106 is also used to receive the selection signal Sel, and output the delayed clock signal Vcdl_output_clk corresponding to the selection signal Sel from the received plurality of delayed clock signals. The selection signal Sel is used to select the phase difference of the delayed clock signal output by the DLL circuit 100. In an optional case, the switch selection circuit 106 is also used to output the delayed clock signal of each delayed clock signal.

[0088] Further optionally, if Figure 3 As shown, the charge pump unit 102 includes: a charge pump 1021 and a ring filter 1022. The charge pump 1021 is connected to the phase detector 101 and the ring filter 1022 respectively. The ring filter 1022 is also connected to the voltage-controlled delay line 103. The charge pump 1021 is used to output a control current signal according to the phase difference signal. The ring filter 1022 is used to convert the control current signal into a control voltage signal and output the control voltage signal. Among them, the ring filter 1022 is a low-pass filter, which can be used to filter out high-frequency components and noise in the control voltage signal. For example, the ring filter 1022 can be a capacitor CF. One end of the capacitor CF is connected to the charge pump 1021 and the voltage-controlled delay line 103 respectively. The other end of the capacitor CF is grounded.

[0089] For example, Figure 3 As shown, the DLL circuit 100 further includes: a phase detector 101, a charge pump unit 102, a voltage-controlled delay line 103, a processing unit 104, an anti-error lock control circuit 105 and a switch selection circuit 106. The charge pump unit 102 includes: a charge pump 1021 and a ring filter 1022. The voltage-controlled delay line 103 includes 8 cascaded first delay units, and the ring oscillator 1031 reuses the first delay unit.

[0090] The voltage-controlled delay line 103 can output the input clock signal of the first delay unit, i.e., the input clock signal Clk0 (Ref_clk) and the delayed clock signals Clk1-Clk8 output by each first delay unit to the switch selection circuit 106. The switch selection circuit 106 is also used to transmit the delayed clock signals Clk0, Clk2, Clk4, and Clk6 with equal phase differences to the anti-error lock control circuit 105. The switch selection circuit 106 is also used to transmit the input clock signal Clk0 and the delayed clock signal output by the last first delay unit, i.e., the target clock signal Clk8, to the phase detector 101. The switch selection circuit 106 is also used to output the input clock signal Clk0 and the delayed clock signals Clk1-Clk8 to the outside of the DLL circuit. The switch selection circuit 106 is also used to output the delayed clock signal Vcdl_output_clk corresponding to the selection signal Sel to the outside of the DLL circuit.

[0091] Before the DLL circuit is locked, the charge pump unit 102 outputs an initial control voltage signal Vctr1 to the voltage-controlled delay line 103. The switch unit in the ring oscillator 1031 is closed to generate and output an oscillation signal Osc to the processing unit 104. The processing unit 104 determines whether the frequency of the oscillation signal Osc meets the target frequency.

[0092] When the frequency of the oscillation signal Osc does not meet the target frequency, the processing unit 104 outputs a capacitance adjustment signal Coarse swf to the first delay unit in the ring oscillator 1031, so that the ring oscillator 1031 oscillates the parameter clock signal Ref_clk again through the adjusted first delay unit, and outputs the oscillation signal Osc to the processing unit 104. The capacitance adjustment signal is used to control the number of capacitors in the ring oscillator 1031 that are in working state.

[0093] When the frequency of the oscillation signal Osc meets the target frequency, the processing unit 104 outputs a switch disconnection signal Swi to the switch unit in the ring oscillator 1031, so that the switch unit of the ring oscillator 1031 is disconnected, and the ring oscillator 1031 stops working. When the frequency of the oscillation signal Osc meets the target frequency, the processing unit 104 may also determine the capacitance adjustment signal Coarse swf currently output to the first delay unit, and output the same capacitance adjustment signal Coarse swf to each first delay unit in the voltage-controlled delay line 103 except the first delay unit included in the ring oscillator 1031, so that the delay time length of each first delay unit is equal to the delay time length of the first delay unit in the ring oscillator 1031.

[0094] When the ring oscillator 1031 is stopped, the voltage-controlled delay line 103 delays the input clock signal Ref_clk through all the first delay units to output the target clock signal Clk8 .

[0095] The error-proof lock control circuit 105 determines the initial delay time length of the voltage-controlled delay line 103 according to the delayed clock signals Clk0, Clk2, Clk4, and Clk6 received from the switch selection circuit 106, and outputs a lock adjustment signal according to the relationship between the initial delay time length and the effective delay range. The lock adjustment signal may include a first lock signal upper, a second lock signal under, and a third lock signal lock.

[0096] The phase detector 101 outputs a phase difference signal according to the phase comparison result between the target clock signal Clk8 and the input clock signal Clk0 and the lock adjustment signal. The phase difference signal includes: a first phase signal DN, a second phase signal UP, a third phase signal NDN, and a fourth phase signal NUP.

[0097] The charge pump unit 102 outputs a control current signal according to the phase difference signal. The control current signal is converted by the ring filter 1022 and outputs a control voltage signal Vctrl to the voltage-controlled delay line 103. The control voltage signal Vctrl is used to adjust the delay time of the first delay unit 1032. The voltage-controlled delay line 103 delays the input clock signal again through all the first delay units 1032 after the delay time is adjusted, and outputs the target clock signal until the phase detector 101 determines that the phases of the target clock signal Clk8 and the input clock signal Clk0 are equal, and the target clock signal Clk8 is delayed by a clock cycle of the input clock signal Clk0 compared to the input clock signal Clk0.

[0098] In the embodiment of the present application, the delay time of the first delay unit can meet the delay time requirements corresponding to the oscillation signals of different frequencies. In this way, the frequency range of the oscillation signal corresponding to the first delay unit is greatly expanded, and the delay time of each first delay unit can also be adjusted at different process angles and different temperatures.

[0099] In summary, the DLL circuit provided in the embodiment of the present application includes a phase detector, a charge pump, a voltage-controlled delay line and a processing unit connected in sequence, and the voltage-controlled delay line is also connected to the phase detector. The voltage-controlled delay line includes a ring oscillator and a plurality of cascaded first delay units. The ring oscillator includes a plurality of cascaded second delay units.

[0100] The ring oscillator can generate an oscillation signal. When the frequency of the oscillation signal does not meet the target frequency, the processing unit can adjust the delay time of the second delay unit by adjusting the load capacitance of the second delay unit in the ring oscillator, thereby adjusting the oscillation frequency of the ring oscillator until the frequency of the oscillation signal generated by the ring oscillator meets the target frequency. The target frequency is determined by the product of a first ratio and a frequency of an input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units.

[0101] In this way, when the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the processing unit controls the load capacitance of the first delay unit and the load capacitance of the second delay unit in the voltage-controlled delay line to be equal, so that the capacitance value of the load capacitance of each first delay unit meets the capacitance value requirement corresponding to the frequency of the input clock signal. In addition, the voltage-controlled delay line delays the input clock signal through all the first delay units, and can output a target clock signal with a frequency equal to the frequency of the input clock signal. The phase detector outputs a phase difference signal to the charge pump unit based on the phase comparison result of the target clock signal and the input clock signal, so that the charge pump unit outputs a control voltage signal based on the phase difference signal to adjust the delay time of the first delay unit until the target clock signal is delayed by a clock cycle of the input clock signal compared to the input clock signal, thereby achieving effective locking of the DLL circuit.

[0102] In this technical solution, a ring oscillator can be used to adjust the load capacitance of each first delay unit in the voltage-controlled delay line to match the frequency of the input clock signal that the voltage-controlled delay line needs to process for delay, reduce the frequency of the input clock signal processed by the DLL circuit, and affect the number of first delay units in the voltage-controlled delay line and the circuit area of ​​the DLL circuit. This effectively expands the frequency range of the input clock signal that can be processed by the DLL circuit, and then effectively improves the frequency range of the output signal of the DLL circuit. In addition, the delay unit in the voltage-controlled delay line has the problem of differences in the frequency range of the input clock signal supported due to process angle, temperature, etc. The technical solution of this application can also use a ring oscillator to correct the delay and frequency deviation supported by a single first delay unit in the voltage-controlled delay line.

[0103] Please refer to Figure 4 , which shows a flow chart of a control method of a DLL circuit provided in an embodiment of the present application. The control method can be applied to the DLL circuit provided in an embodiment of the present application. Optionally, the control method can be applied to Figure 1 , Figure 3 The DLL circuit shown in Figure 1 is as follows. Figure 4 As shown, the control method includes:

[0104] Step 401: Control the ring oscillator to operate.

[0105] In the embodiment of the present application, this step may be performed by the processing unit 104. Optionally, the processing unit 104 may control the ring oscillator 103 to work by controlling the switch unit to be closed.

[0106] Step 402: When the frequency of the oscillation signal output by the ring oscillator does not meet the target frequency, adjust the load capacitance of the second delay unit.

[0107] The target frequency is determined by the product of the first ratio and the frequency of the input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units. This step can be performed by the processing unit 104, and the implementation method of the processing unit 104 adjusting the size of the load capacitance of the second delay unit can refer to the above description, and the embodiment of the present application will not be repeated.

[0108] Step 403 : When the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the ring oscillator is controlled to stop working, and the load capacitances of the first delay unit and the second delay unit are equal.

[0109] In an embodiment of the present application, this step can be executed by the processing unit 104, and the processing unit 104 controls the ring oscillator to stop working, and the implementation method of making the load capacitance of the first delay unit and the second delay unit equal can refer to the above description, and the embodiment of the present application will not elaborate on this.

[0110] Step 404: Delay the input clock signal through a plurality of cascaded first delay units to obtain a target clock signal.

[0111] In an embodiment of the present application, this step can be performed by the voltage-controlled delay line 103, and the voltage-controlled delay line 103 delays the input clock signal through all the first delay units. The implementation method of obtaining the target clock signal can refer to the above description, and the embodiment of the present application will not elaborate on this.

[0112] Step 405: perform phase comparison between the target clock signal and the input clock signal through a phase detector.

[0113] In the embodiment of the present application, this step can be performed by the phase detector 101. The implementation method of the phase detector comparing the target clock signal with the input clock signal can refer to the above description, and the embodiment of the present application will not be repeated.

[0114] Step 406: When it is determined based on the phase comparison result that the delay of the target clock signal compared to the input clock signal is less than the clock cycle, the delay time of the first delay unit is adjusted by the charge pump, and the input clock signal is delayed again by the first delay unit until the delay of the target clock signal compared to the input clock signal satisfies one clock cycle.

[0115] In the embodiment of the present application, this step can be performed by the charge pump unit 102. The implementation method of the charge pump unit 102 adjusting the delay time of the first delay unit can refer to the above description, and the embodiment of the present application will not be repeated.

[0116] Optionally, the load capacitor of the second delay unit includes a capacitor array. The process of adjusting the size of the load capacitor of the second delay unit may include: adjusting the number of capacitors in the second delay unit in a working state by using a dichotomy method according to the number of capacitors in the capacitor array.

[0117] In an embodiment of the present application, this step can be performed by the processing unit 104. The implementation method of the processing unit 104 adjusting the number of capacitors in the working state in the second delay unit by using the binary division method according to the number of capacitors in the capacitor array can be referred to the above description, and the embodiment of the present application will not elaborate on this.

[0118] In summary, the DLL circuit provided in the embodiment of the present application includes a phase detector, a charge pump, a voltage-controlled delay line and a processing unit connected in sequence, and the voltage-controlled delay line is also connected to the phase detector. The voltage-controlled delay line includes a ring oscillator and a plurality of cascaded first delay units. The ring oscillator includes a plurality of cascaded second delay units.

[0119] The ring oscillator can generate an oscillation signal. When the frequency of the oscillation signal does not meet the target frequency, the processing unit can adjust the delay time of the second delay unit by adjusting the load capacitance of the second delay unit in the ring oscillator, thereby adjusting the oscillation frequency of the ring oscillator until the frequency of the oscillation signal generated by the ring oscillator meets the target frequency. The target frequency is determined by the product of a first ratio and a frequency of an input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units.

[0120] In this way, when the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the processing unit controls the load capacitance of the first delay unit and the load capacitance of the second delay unit in the voltage-controlled delay line to be equal, so that the capacitance value of the load capacitance of each first delay unit meets the capacitance value requirement corresponding to the frequency of the input clock signal. In addition, the voltage-controlled delay line delays the input clock signal through all the first delay units, and can output a target clock signal with a frequency equal to the frequency of the input clock signal. The phase detector outputs a phase difference signal to the charge pump unit based on the phase comparison result of the target clock signal and the input clock signal, so that the charge pump unit outputs a control voltage signal based on the phase difference signal to adjust the delay time of the first delay unit until the target clock signal is delayed by a clock cycle of the input clock signal compared to the input clock signal, thereby achieving effective locking of the DLL circuit.

[0121] In this technical solution, a ring oscillator can be used to adjust the load capacitance of each first delay unit in the voltage-controlled delay line to match the frequency of the input clock signal that the voltage-controlled delay line needs to process for delay, reduce the frequency of the input clock signal processed by the DLL circuit, and affect the number of first delay units in the voltage-controlled delay line and the circuit area of ​​the DLL circuit. This effectively expands the frequency range of the input clock signal that can be processed by the DLL circuit, and then effectively improves the frequency range of the output signal of the DLL circuit. In addition, the delay unit in the voltage-controlled delay line has the problem of differences in the frequency range of the input clock signal supported due to process angle, temperature, etc. The technical solution of this application can also use a ring oscillator to correct the delay and frequency deviation supported by a single first delay unit in the voltage-controlled delay line.

[0122] The embodiment of the present application further provides an electronic device, which may include the DLL circuit provided by the embodiment of the present application. The electronic device may be a chip or a chip system.

[0123] The present application also provides an electronic device. Figure 5 As shown, the electronic device 500 may include a processor 501 and a memory 502. The memory 501 is used to store computer programs. The processor 502 is used to implement the control method of the DLL circuit provided in the embodiment of the present application when executing the program stored in the memory. Among them, the electronic device may be or include the DLL circuit provided in the embodiment of the present application. The electronic device 500 may be a chip or a chip system.

[0124] The embodiment of the present application also provides a readable storage medium, on which a program or instruction is stored. When the program or instruction is executed by a processor, each process of the control method embodiment of the DLL circuit described above is implemented, and the same technical effect can be achieved. To avoid repetition, it is not repeated here. Among them, the function of the processor can refer to the function of the processor in the electronic device in the above embodiment. The readable storage medium includes a computer-readable storage medium, such as a computer read-only memory ROM, a random access memory RAM, a disk or an optical disk, etc.

[0125] The embodiment of the present application also provides a computer program product, including a computer program / instruction. When the computer program / instruction is executed by a processor, each process of the control method embodiment of the above-mentioned DLL circuit is implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0126] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A delay locked loop (DLL) circuit, characterized in that: The DLL circuit comprises: a phase detector, a charge pump unit, a voltage-controlled delay line and a processing unit connected in sequence, and the voltage-controlled delay line is also connected to the phase detector; The voltage-controlled delay line comprises a ring oscillator and a plurality of cascaded first delay units, the ring oscillator comprises a plurality of cascaded second delay units, and the ring oscillator is used to generate an oscillation signal; The processing unit is used for adjusting the size of the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency, until the frequency of the oscillation signal meets the target frequency, controlling the ring oscillator to stop working, and controlling the sizes of the load capacitances of the first delay unit and the second delay unit to be equal; wherein the target frequency is determined by the product of a first ratio and the frequency of an input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units; The voltage-controlled delay line is used to delay the input clock signal through the plurality of cascaded first delay units and output a target clock signal when the ring oscillator is stopped; The phase detector is used to output a phase difference signal according to a phase comparison result between the target clock signal and the input clock signal; The charge pump unit is used to output a control voltage signal according to the phase difference signal, and the control voltage signal is used at least to adjust the delay time of the first delay unit until the target clock signal is delayed by one clock cycle of the input clock signal compared to the input clock signal.

2. The DLL circuit according to claim 1, characterized in that: The plurality of cascaded second delay units are a plurality of first delay units that are partially and continuously cascaded among the plurality of cascaded first delay units, and the ring oscillator further comprises: a switch unit, the switch unit being respectively connected to a first delay unit and a last delay unit among the plurality of second delay units; The ring oscillator is used to generate the oscillation signal when the switch unit is closed; The processing unit is used for controlling the switch unit to be disconnected when the frequency of the oscillation signal meets the target frequency, so as to control the ring oscillator to stop working.

3. The DLL circuit according to claim 2, characterized in that: The number of the second delay units is an even number; the switch unit comprises: a first switch element, an inverter and a second switch element; The first end of the first switch is connected to the first delay unit, the second end of the first switch is connected to the first end of the second switch through the inverter, and the second end of the second switch is connected to the last delay unit; The ring oscillator is used to generate the oscillation signal when the first switch element and the second switch element are both closed; The processing unit is further configured to control the first switch element and the second switch element to be disconnected when the frequency of the oscillation signal meets the target frequency, so as to control the ring oscillator to stop working.

4. The DLL circuit according to any one of claims 1 to 3, characterized in that: The processing unit is further configured to adjust the load capacitance of the second delay unit when the frequency of the oscillation signal does not meet the target frequency until the frequency of the oscillation signal meets the target frequency, determine the current target capacitance value of the second delay unit, and adjust the load capacitance of the first delay unit to the target capacitance value; Alternatively, in a case where the multiple cascaded second delay units are multiple continuously cascaded first delay units, the processing unit is further used to adjust the load capacitance of all the first delay units until the frequency of the oscillation signal meets the target frequency when the frequency of the oscillation signal does not meet the target frequency.

5. The DLL circuit according to claim 1, characterized in that: The voltage-controlled delay line is also used to output the delayed clock signal after each of the first delay units has been delayed; the DLL circuit also includes: an anti-error lock control circuit; the anti-error lock control circuit is respectively connected to the voltage-controlled delay line and the phase detector; The error-proof lock control circuit is used to determine the initial delay time length of the voltage-controlled delay line according to the multiple delayed clock signals with equal-interval phase differences, and output a lock adjustment signal according to the relationship between the initial delay time length and the effective delay range; The phase detector is used to output the phase difference signal according to the phase comparison result between the target clock signal and the input clock signal and the lock adjustment signal, When the target clock signal output by the voltage-controlled delay line after delay processing within the effective delay range is equal in phase to the input clock signal, the target clock signal is delayed by one clock cycle compared to the input clock signal.

6. The DLL circuit according to claim 5, characterized in that: The DLL circuit further comprises: a switch selection circuit; the switch selection circuit is connected to the voltage-controlled delay line and the error-proof lock control circuit; The switch selection circuit is used to receive the delayed clock signal of each of the delayed clock signals, and output a plurality of the delayed clock signals with equally spaced phase differences to the error-proof lock control circuit; The switch selection circuit is further configured to receive a selection signal and output the delayed clock signal corresponding to the selection signal from the received plurality of delayed clock signals.

7. The DLL circuit according to claim 1, characterized in that: The charge pump unit comprises: a charge pump and a ring filter; the charge pump is connected to the phase detector and the ring filter respectively, and the ring filter is also connected to the voltage-controlled delay line; The charge pump is used to output a control current signal according to the phase difference signal; The loop filter is used to convert the control current signal into the control voltage signal and output the control voltage signal.

8. A control method for a delay locked loop (DLL) circuit, characterized in that: Applied to the DLL circuit according to any one of claims 1 to 7, the method comprises: Controlling the ring oscillator to operate; When the frequency of the oscillation signal output by the ring oscillator does not meet the target frequency, adjusting the size of the load capacitance of the second delay unit, wherein the target frequency is determined by the product of a first ratio and the frequency of the input clock signal of the voltage-controlled delay line, and the first ratio is the ratio of the number of the second delay units to the number of the first delay units; When the frequency of the oscillation signal output by the ring oscillator meets the target frequency, the ring oscillator is controlled to stop working, and the load capacitances of the first delay unit and the second delay unit are controlled to be equal; Delaying the input clock signal through the plurality of cascaded first delay units to obtain a target clock signal; Performing phase comparison between the target clock signal and the input clock signal by the phase detector; When it is determined based on the phase comparison result that the delay of the target clock signal compared to the input clock signal is less than one clock cycle, the delay duration of the first delay unit is adjusted through the charge pump unit, and the input clock signal is delayed again through the first delay unit until the delay of the target clock signal compared to the input clock signal satisfies one clock cycle.

9. The method according to claim 8, characterized in that The load capacitor includes a capacitor array; and adjusting the size of the load capacitor of the second delay unit includes: According to the number of capacitors in the capacitor array, the number of capacitors in the second delay unit in a working state is adjusted by using a dichotomy method.

10. An electronic device, characterized in that: The electronic device comprises the delay locked loop (DLL) circuit according to any one of claims 1 to 7.

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