Semiconductor structure and manufacturing method thereof

Abstract

The invention discloses a semiconductor structure and a manufacturing method thereof. The semiconductor structure includes a substrate, a first doped region having a first conductivity type, a second doped region having the first conductivity type, a first contact, a second contact, a first metal silicide layer, and a second metal silicide layer. The substrate includes a fin portion, wherein the fin portion protrudes from a top surface of the substrate. The first doped region is disposed in the fin portion. The second doped region is arranged in the fin part and is connected with the first doped region, and the doping concentration of the second doped region is greater than that of the first doped region. The first contact is disposed on the first doped region. The second contact is disposed on the second doped region. The first metal silicide layer is arranged between the first contact piece and the first doped region. And the second metal silicide layer is arranged between the second contact piece and the second doped region.

Description

Technical Field

[0001] The present invention relates to a semiconductor structure, and in particular to a semiconductor structure including a Schottky barrier diode (SBD). Background Art

[0002] A Schottky barrier diode is a component formed by the junction of a semiconductor and a metal. Due to its low forward voltage and short reverse recovery time, the Schottky barrier diode is suitable for high-speed switching applications. In addition, the Schottky barrier diode has the characteristic of low leakage current.

[0003] At one end of the Schottky barrier diode, the doped region in the substrate and the metal silicide layer disposed on the doped region may form a Schottky junction at the anode. At the other end of the Schottky barrier diode, the doped region in the substrate and the metal silicide layer disposed on the doped region may form an ohmic junction at the cathode. In addition, the metal silicide layer at the anode and the metal silicide layer at the cathode are separated from each other by an isolation layer (e.g., an oxide layer) disposed on the substrate.

[0004] However, since the metal silicide layer at the anode and the metal silicide layer at the cathode must be separated by an isolation layer, the Schottky barrier diode has a large layout area and cannot meet the requirements of size reduction. In addition, due to the existence of the isolation layer, the distance between the metal silicide layer at the anode and the metal silicide layer at the cathode is too large, resulting in excessive resistance of the Schottky barrier diode and affecting performance. Summary of the invention

[0005] The present invention is directed to a semiconductor structure, wherein a Schottky barrier diode is disposed at a fin portion of a substrate.

[0006] The present invention is directed to a method for manufacturing a semiconductor structure, wherein a Schottky barrier diode is formed at a fin portion of a substrate.

[0007] The semiconductor structure of the present invention comprises a substrate, a first doped region having a first conductivity type, a second doped region having the first conductivity type, a first contact, a second contact, a first metal silicide layer and a second metal silicide layer. The substrate comprises a fin portion, wherein the fin portion protrudes from the top surface of the substrate. The first doped region is disposed in the fin portion. The second doped region is disposed in the fin portion and connected to the first doped region, wherein the doping concentration of the second doped region is greater than the doping concentration of the first doped region. The first contact is disposed on the first doped region. The second contact is disposed on the second doped region. The first metal silicide layer is disposed between the first contact and the first doped region. The second metal silicide layer is disposed between the second contact and the second doped region.

[0008] In one embodiment of the semiconductor structure of the present invention, the doping concentration of the first doping region is between 1×10 18 cm -3 Up to 1×10 19 cm -3 between.

[0009] In one embodiment of the semiconductor structure of the present invention, the doping concentration of the second doping region is between 1×10 20 cm -3 Up to 5×10 20 cm -3 between.

[0010] In an embodiment of the semiconductor structure of the present invention, the fin portion has a second conductivity type.

[0011] In one embodiment of the semiconductor structure of the present invention, it further includes a third doping region having the first conductivity type, disposed below the first doping region, wherein the doping concentration of the third doping region is between the doping concentration of the first doping region and the doping concentration of the second doping region.

[0012] In one embodiment of the semiconductor structure of the present invention, the doping concentration of the third doping region is between 1×10 19 cm -3 Up to 1×10 20 cm -3 between.

[0013] In an embodiment of the semiconductor structure of the present invention, a depth of the third doping region is smaller than a depth of the second doping region.

[0014] In an embodiment of the semiconductor structure of the present invention, the first contact extends into the first doped region.

[0015] In an embodiment of the semiconductor structure of the present invention, the first doping region is located in the entire fin portion, and the second doping region is located in the first doping region.

[0016] In one embodiment of the semiconductor structure of the present invention, the first contact includes a first part and a second part connected to each other, the first part is located on the top surface of the fin part, the second part extends downward along the side wall of the fin part, and the first metal silicide layer is located between the first contact and the top surface and the side wall of the fin part.

[0017] The method for manufacturing a semiconductor structure of the present invention comprises the following steps. A substrate is provided, wherein the substrate comprises a fin portion protruding from a top surface of the substrate. A first doped region having a first conductivity type is formed in the fin portion. A second doped region having the first conductivity type is formed in the fin portion, wherein the second doped region is connected to the first doped region, and the doping concentration of the second doped region is greater than the doping concentration of the first doped region. A first contact is formed on the first doped region. A second contact is formed on the second doped region. A first metal silicide layer is formed between the first contact and the first doped region. A second metal silicide layer is formed between the second contact and the second doped region.

[0018] In one embodiment of the method for manufacturing a semiconductor structure of the present invention, the doping concentration of the first doping region is between 1×10 18 cm -3 Up to 1×10 19 cm -3 between.

[0019] In one embodiment of the method for manufacturing a semiconductor structure of the present invention, the doping concentration of the second doping region is between 1×10 20 cm -3 Up to 5×10 20 cm -3 between.

[0020] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the fin portion has a second conductivity type.

[0021] In one embodiment of the method for manufacturing a semiconductor structure of the present invention, the method further includes forming a third doping region having the first conductivity type below the first doping region, wherein the doping concentration of the third doping region is between the doping concentration of the first doping region and the doping concentration of the second doping region.

[0022] In one embodiment of the method for manufacturing a semiconductor structure of the present invention, the doping concentration of the third doping region is between 1×10 19 cm -3Up to 1×10 20 cm -3 between.

[0023] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, a depth of the third doping region is less than a depth of the second doping region.

[0024] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the first contact extends into the first doped region.

[0025] In one embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the first contact, the second contact, the first metal silicide layer and the second metal silicide layer comprises the following steps. A dielectric layer is formed on the substrate, wherein the dielectric layer covers the fin portion. A first contact opening is formed in the dielectric layer to expose a portion of the first doped region. A second contact opening is formed in the dielectric layer to expose a portion of the second doped region. The first metal silicide layer is formed on the first doped region exposed by the first contact opening. The second metal silicide layer is formed on the second doped region exposed by the second contact opening. A conductive material is formed on the first metal silicide layer and the second metal silicide layer.

[0026] In an embodiment of the method for manufacturing a semiconductor structure of the present invention, the first doping region is formed in the entire fin portion, and the second doping region is formed in the first doping region.

[0027] In one embodiment of the manufacturing method of the semiconductor structure of the present invention, the first contact includes a first part and a second part connected to each other, the first part is located on the top surface of the fin part, the second part extends downward along the side wall of the fin part, and the first metal silicide layer is formed between the first contact and the top surface and the side wall of the fin part.

[0028] In one embodiment of the method for manufacturing a semiconductor structure of the present invention, the method for forming the first contact, the second contact, the first metal silicide layer and the second metal silicide layer comprises the following steps. A dielectric layer is formed on the substrate, wherein the dielectric layer covers the fin portion. A first contact opening is formed in the dielectric layer to expose a portion of the top surface and a portion of the sidewall of the fin portion. A second contact opening is formed in the dielectric layer to expose a portion of the second doped region. The first metal silicide layer is formed on the fin portion exposed by the first contact opening. The second metal silicide layer is formed on the second doped region exposed by the second contact opening. A conductive material is formed on the first metal silicide layer and the second metal silicide layer.

[0029] Based on the above, in the semiconductor structure of the present invention, the first doped region and the first metal silicide layer constitute a Schottky junction of a Schottky barrier diode, the second doped region and the second metal silicide layer constitute an ohmic junction of a Schottky barrier diode, and the Schottky barrier diode is arranged at the fin portion of the substrate, so that the Schottky barrier diode can have a smaller layout area.

[0030] In addition, in the semiconductor structure of the present invention, the first metal silicide layer is formed in the first contact opening, and the second metal silicide layer is formed in the second contact opening, so that the first metal silicide layer and the second metal silicide layer can be separated from each other without an additional isolation layer. In this way, the distance between the first metal silicide layer and the second metal silicide layer can be effectively reduced, so that the Schottky barrier diode can have a lower resistance. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] Figures 1A to 1D is a cross-sectional schematic diagram of the manufacturing process of the semiconductor structure according to the first embodiment of the present invention;

[0032] Figure 2 is a cross-sectional schematic diagram of a semiconductor structure according to a second embodiment of the present invention;

[0033] FIG. 3A to FIG. 3D FIG. 4 is a cross-sectional schematic diagram of the manufacturing process of a semiconductor structure according to a third embodiment of the present invention. DETAILED DESCRIPTION

[0034] The following examples are listed and described in detail with reference to the accompanying drawings, but the examples provided are not intended to limit the scope of the present invention. In addition, the drawings are for illustration purposes only and are not drawn to their original size. For ease of understanding, the same components are indicated by the same symbols in the following description.

[0035] The terms "include", "including", "have", etc. used in this document are open terms, which means "including but not limited to".

[0036] When the terms "first", "second", etc. are used to describe components, they are only used to distinguish these components from each other, and do not limit the order or importance of these components. Therefore, in some cases, the first component may also be referred to as the second component, and the second component may also be referred to as the first component, and this does not deviate from the scope of the present invention.

[0037] In addition, directional terms such as "upper", "lower", etc. mentioned herein are only used to refer to the directions of the drawings and are not used to limit the present invention. Therefore, it should be understood that "upper" can be used interchangeably with "lower", and when a component such as a layer or film is placed "on" another component, the component can be placed directly on the other component, or there can be an intermediate component. On the other hand, when a component is said to be placed "directly" on another component, there is no intermediate component between the two.

[0038] In addition, in this article, the range expressed by "a value to another value" is a summary expression method to avoid listing all the values ​​in the range one by one in the specification. Therefore, the description of a specific numerical range covers any value in the numerical range, and covers a smaller numerical range defined by any value in the numerical range.

[0039] The semiconductor structure of the embodiment of the present invention includes a Schottky barrier diode disposed at the fin portion of the substrate, and the metal silicide layer located at the anode of the Schottky barrier diode and the metal silicide layer located at the cathode of the Schottky barrier diode are each located only between the contact and the fin portion. In this way, the metal silicide layer located at the anode and the metal silicide layer located at the cathode can have a shorter distance between them, so that the Schottky barrier diode can have a lower resistance. The semiconductor structure of the embodiment of the present invention will be further described below.

[0040] Figures 1A to 1D FIG. 1 is a cross-sectional schematic diagram of the manufacturing process of the semiconductor structure of the first embodiment of the present invention. In this embodiment, the conductivity type includes P type and N type. In addition, depending on actual needs, in other embodiments, the P type in this embodiment can be replaced by N type, and the N type in this embodiment can be replaced by P type.

[0041] First, please refer to Figure 1A , providing a substrate 100. In the present embodiment, the substrate 100 is a silicon substrate. Next, a patterning process is performed on the substrate 100 to remove a portion of the substrate 100, so that the substrate 100 has a fin portion 100a protruding from its top surface. Then, an ion implantation process may be performed to form a well region at least in the fin portion 100a. In the present embodiment, a P-type well region is formed in the entire fin portion 100a, but the present invention is not limited thereto. Thereafter, an isolation layer 102 is formed on the substrate 100. In the present embodiment, the isolation layer 102 surrounds the fin portion 100a, and the top surface of the isolation layer 102 is lower than the top surface of the fin portion 100a. In the present embodiment, the isolation layer 102 is an oxide layer, but the present invention is not limited thereto.

[0042] Next, please refer to Figure 1B, an ion implantation process is performed to implant dopants into the fin portion 100a to form a first doping region 104 and a second doping region 106 in the fin portion 100a. In the present embodiment, the first doping region 104 and the second doping region 106 are N-type doping regions. The first doping region 104 and the second doping region 106 are formed at the top surface of the fin portion 100a, and the first doping region 104 and the second doping region 106 are connected together. The depth of the first doping region 104 is less than the depth of the second doping region 106. The doping concentration of the second doping region 106 is greater than the doping concentration of the first doping region 104. In the present embodiment, the doping concentration of the first doping region 104 may be between 1×10 18 cm -3 Up to 1×10 19 cm -3 , and the doping concentration of the second doping region 106 may be between 1×10 20 cm -3 Up to 5×10 20 cm -3 between.

[0043] In addition, in the above-mentioned ion implantation process, a third doping region 108 may be formed below the first doping region 104. The third doping region 108 is an N-type doping region. The third doping region 108 is connected to the first doping region 104 and the second doping region 106. The depth of the third doping region 108 is less than the depth of the second doping region 106. The doping concentration of the third doping region 108 is between the doping concentration of the first doping region 104 and the doping concentration of the second doping region 106. In this embodiment, the doping concentration of the third doping region 108 may be between 1×10 19 cm -3 Up to 1×10 20 cm -3 between.

[0044] Then, please refer to Figure 1C , a dielectric layer 110 is formed on the substrate 100. The dielectric layer 110 covers the fin portion 100a and the isolation layer 102. In the present embodiment, the dielectric layer 110 is an oxide layer. The dielectric layer 110 serves as an inter-layer dielectric layer (ILD layer). Next, a first contact opening 112 exposing a portion of the first doped region 104 and a second contact opening 114 exposing a portion of the second doped region 106 are formed in the dielectric layer 110. The first contact opening 112 and the second contact opening 114 can be formed in the same process step, but the present invention is not limited thereto. In the present embodiment, the bottoms of the first contact opening 112 and the second contact opening 114 are located on the top surface of the fin portion 100a, that is, the first contact opening 112 and the second contact opening 114 have the same depth.

[0045] Afterwards, please refer to Figure 1D , a metal silicide process is performed to form a first metal silicide layer 116 on the first doped region 104 exposed by the first contact opening 112, and a second metal silicide layer 118 on the second doped region 106 exposed by the second contact opening 114. In the present embodiment, the first metal silicide layer 116 and the second metal silicide layer 118 have the same material and can be formed in the same process step, but the present invention is not limited thereto. In other embodiments, the first metal silicide layer 116 and the second metal silicide layer 118 can have different materials and can be formed in different process steps.

[0046] Then, a conductive material is filled into the first contact opening 112 and the second contact opening 114 to form a first contact 120 on the first metal silicide layer 116 and a second contact 122 on the second metal silicide layer 118. In this way, the semiconductor structure 10 of this embodiment is completed.

[0047] In the semiconductor structure 10, the first doped region 104 and the first metal silicide layer 116 form a Schottky junction, and the second doped region 106 and the second metal silicide layer 118 form an ohmic junction. Therefore, the first doped region 104, the second doped region 106, the first metal silicide layer 116 and the second metal silicide layer 118 can form a Schottky barrier diode of this embodiment.

[0048] In the Schottky barrier diode of the present embodiment, the portion including the first doped region 104 and the first metal silicide serves as the anode of the Schottky barrier diode, and the portion including the second doped region 106 and the second metal silicide layer 118 serves as the cathode of the Schottky barrier diode. Therefore, the Schottky barrier diode of the present embodiment is disposed at the fin portion 100a and can have a smaller layout area, which is conducive to the demand for device miniaturization.

[0049] In addition, in the semiconductor structure 10, the first metal silicide layer 116 is located in the first contact opening 112, and the second metal silicide layer 118 is located in the second contact opening 114. Therefore, the first metal silicide layer 116 and the second metal silicide layer 118 can each have a smaller area, and the first metal silicide layer 116 and the second metal silicide layer 118 can be separated from each other without an additional isolation layer. In this way, the distance between the first metal silicide layer 116 and the second metal silicide layer 118 can be effectively reduced, so that the Schottky barrier diode of this embodiment can have a lower resistance.

[0050] In addition, in the semiconductor structure 10 , the third doping region 108 having a doping concentration between the first doping region 104 and the second doping region 106 is located below the first doping region 104 and connected to the second doping region 106 , thereby further reducing the resistance of the Schottky barrier diode.

[0051] Figure 2 2 is a cross-sectional view of a semiconductor structure according to a second embodiment of the present invention. In this embodiment, the same components as those in the first embodiment are denoted by the same reference symbols and will not be described again.

[0052] Please refer to Figure 2 In the semiconductor structure 20 of the present embodiment, the first contact 120 extends into the first doped region 104, and the second contact 122 extends into the second doped region 106. That is, Figure 1C In the above steps, the bottom of the formed first contact opening 112 is located in the first doped region 104, and the bottom of the second contact opening 114 is located in the second doped region 106. In this way, after the metal silicide process is performed, the first metal silicide layer 116 can be formed at the bottom and part of the sidewall of the first contact opening 112, and the second metal silicide layer 118 can be formed at the bottom and part of the sidewall of the second contact opening 114. Therefore, the first metal silicide layer 116 and the first doped region 104 can have a larger contact area, and a Schottky junction with a larger area can be formed, thereby improving the performance of the Schottky barrier diode.

[0053] FIG. 3A to FIG. 3D FIG. 3 is a cross-sectional diagram of a manufacturing process of a semiconductor structure according to a third embodiment of the present invention. In this embodiment, components identical to those in the first embodiment are denoted by identical reference symbols and will not be described again.

[0054] First, please refer to Figure 3A , providing a substrate 100. In this embodiment, the substrate 100 includes a plurality of fin portions 100a. Next, an isolation layer 102 is formed on the substrate 100. The isolation layer 102 is located between two adjacent fin portions 100a to surround each fin portion 100a, and a top surface of the isolation layer 102 is lower than a top surface of the fin portion 100a.

[0055] Next, please refer to Figure 3B, an ion implantation process is performed to form a first doping region 304 and a second doping region 306 in the fin portion 100a. In the present embodiment, the first doping region 304 and the second doping region 306 are N-type doping regions. The first doping region 304 is formed in the entire fin portion 100a and a portion of the substrate 100 therebelow, and the second doping region 306 is formed in the first doping region 304. In other embodiments, the first doping region 304 may be formed only in the entire fin portion 100a, but not in the substrate 100 therebelow. The doping concentration of the second doping region 306 is greater than the doping concentration of the first doping region 304. In the present embodiment, the doping concentration of the first doping region 304 may be between 1×10 18 cm -3 Up to 1×10 19 cm -3 The doping concentration of the second doping region 306 may be between 1×10 20 cm -3 Up to 5×10 20 cm -3 between.

[0056] Then, please refer to Figure 3C , a dielectric layer 110 is formed on the substrate 100. The dielectric layer 110 covers the fin portion 100a and the isolation layer 102. Next, a first contact opening 312 exposing a portion of the top surface and a portion of the sidewall of the fin portion 100a and a second contact opening 314 exposing a portion of the second doped region 306 are formed in the dielectric layer 110.

[0057] In detail, in the present embodiment, the first contact opening 312 is located between two adjacent fin portions 100a, so in addition to exposing a portion of the top surface and a portion of the sidewall of each of the two fin portions 100a, the top surface of the isolation layer 102 located between the two fin portions 100a is also exposed. Therefore, in the present embodiment, the width of the portion of the first contact opening 312 located on the fin portion 100a is greater than the width of the portion of the first contact opening 312 located between the two fin portions 100a.

[0058] In addition, in the present embodiment, in the process of forming the first contact opening 312, in addition to removing a portion of the dielectric layer 110, a portion of the isolation layer 102 between the two fin portions 100a is further removed, so that the isolation layer 102 between the two fin portions 100a has a smaller thickness. In other words, the depth of the first contact opening 312 can be adjusted by controlling the degree of removal of the isolation layer 102. In other embodiments, the isolation layer 102 may not be removed during the process of forming the first contact opening 312.

[0059] Afterwards, please refer to Figure 3D, a metal silicide process is performed to form a first metal silicide layer 316 on the first doped region 104 exposed by the first contact opening 312, and a second metal silicide layer 318 is formed on the second doped region 306 exposed by the second contact opening 314. In the present embodiment, since the first contact opening 312 exposes a portion of the top surface and a portion of the sidewall of the fin portion 100a, the first metal silicide layer 316 is formed on the sidewall of the fin portion 100a in addition to the top surface of the fin portion 100a.

[0060] Then, a conductive material is filled into the first contact opening 312 and the second contact opening 314 to form a first contact 320 in the first contact opening 312 and a second contact 322 in the second contact opening 314. In this way, the semiconductor structure 30 of this embodiment is completed.

[0061] In this embodiment, since the first contact opening 312 extends between two adjacent fin portions 100a, the formed first contact 320 includes a first portion 320a and a second portion 320b connected to each other, wherein the first portion 320a is located on the top surface of the fin portion 100a, and the second portion 320b extends downward along the sidewall of the fin portion 100a to the top surface of the isolation layer 102. The width of the first portion 320a is greater than the width of the second portion 320b.

[0062] In the semiconductor structure 30, the first doped region 304 and the first metal silicide layer 316 form a Schottky junction, and the second doped region 306 and the second metal silicide layer 318 form an ohmic junction, so the first doped region 304, the second doped region 306, the first metal silicide layer 316 and the second metal silicide layer 318 can form a Schottky barrier diode of the present embodiment. The Schottky barrier diode of the present embodiment is disposed at the fin portion 100a, so it can have a smaller layout area, which is conducive to the demand for device miniaturization.

[0063] In addition, in the semiconductor structure 30, the first metal silicide layer 316 is formed on the top surface and sidewalls of the fin portion 100a, so that the first metal silicide layer 316 and the first doped region 304 can have a larger contact area, and a Schottky junction with a larger area can be formed, thereby improving the performance of the Schottky barrier diode.

[0064] In addition, in the semiconductor structure 30, the first metal silicide layer 316 is located in the first contact opening 312, and the second metal silicide layer 318 is located in the second contact opening 314, so the first metal silicide layer 316 and the second metal silicide layer 318 can be separated from each other without an additional isolation layer. In this way, the distance between the first metal silicide layer 316 and the second metal silicide layer 318 can be effectively reduced, so that the Schottky barrier diode of this embodiment can have a lower resistance.

[0065] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor structure, characterized in that: include: a substrate including a fin portion, wherein the fin portion protrudes from a top surface of the substrate; a first doped region having a first conductivity type, disposed in the fin portion; a second doping region of the first conductivity type, disposed in the fin portion and connected to the first doping region, wherein a doping concentration of the second doping region is greater than a doping concentration of the first doping region; A first contact member is disposed on the first doped region; A second contact member is disposed on the second doped region; A first metal silicide layer is disposed between the first contact and the first doped region; as well as The second metal silicide layer is disposed between the second contact and the second doped region.

2. The semiconductor structure according to claim 1, characterized in that: The doping concentration of the first doping region is between 1×10 18 cm -3 Up to 1×10 19 cm -3 between.

3. The semiconductor structure according to claim 1, characterized in that: The doping concentration of the second doping region is between 1×10 20 cm -3 Up to 5×10 20 cm -3 between.

4. The semiconductor structure according to claim 1, characterized in that: The fin portion has a second conductivity type.

5. The semiconductor structure according to claim 4, characterized in that: It also includes a third doping region of the first conductivity type, which is disposed below the first doping region, wherein the doping concentration of the third doping region is between the doping concentration of the first doping region and the doping concentration of the second doping region.

6. The semiconductor structure according to claim 5, characterized in that: The doping concentration of the third doping region is between 1×10 19 cm -3 Up to 1×10 20 cm -3 between.

7. The semiconductor structure according to claim 5, characterized in that: The depth of the third doping region is less than the depth of the second doping region.

8. The semiconductor structure according to claim 4, characterized in that: The first contact extends into the first doped region.

9. The semiconductor structure according to claim 1, characterized in that: The first doping region is located in the entire fin portion, and the second doping region is located in the first doping region.

10. The semiconductor structure according to claim 9, characterized in that: The first contact includes a first portion and a second portion connected to each other, the first portion is located on the top surface of the fin portion, the second portion extends downward along the side wall of the fin portion, and the first metal silicide layer is located between the first contact and the top surface and the side wall of the fin portion.

11. A method for manufacturing a semiconductor structure, characterized in that: include: providing a substrate, wherein the substrate includes a fin portion protruding from a top surface of the substrate; forming a first doped region having a first conductivity type in the fin portion; forming a second doping region having the first conductivity type in the fin portion, wherein the second doping region is connected to the first doping region and a doping concentration of the second doping region is greater than a doping concentration of the first doping region; forming a first contact on the first doped region; forming a second contact on the second doped region; forming a first metal silicide layer between the first contact and the first doped region; as well as A second metal silicide layer is formed between the second contact and the second doped region.

12. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The doping concentration of the first doping region is between 1×10 18 cm -3 Up to 1×10 19 cm -3 between.

13. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The doping concentration of the second doping region is between 1×10 20 cm -3 Up to 5×10 20 cm -3 between.

14. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The fin portion has a second conductivity type.

15. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: The method further includes forming a third doping region having the first conductivity type below the first doping region, wherein a doping concentration of the third doping region is between a doping concentration of the first doping region and a doping concentration of the second doping region.

16. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: The doping concentration of the third doping region is between 1×10 19 cm -3 Up to 1×10 20 cm -3 between.

17. The method for manufacturing a semiconductor structure according to claim 15, characterized in that: The depth of the third doping region is less than the depth of the second doping region.

18. The method for manufacturing a semiconductor structure according to claim 14, characterized in that: The first contact extends into the first doped region.

19. The method for manufacturing a semiconductor structure according to claim 14, wherein: The method for forming the first contact, the second contact, the first metal silicide layer and the second metal silicide layer includes: forming a dielectric layer on the substrate, wherein the dielectric layer covers the fin portion; forming a first contact opening in the dielectric layer to expose a portion of the first doped region; forming a second contact opening in the dielectric layer to expose a portion of the second doped region; forming the first metal silicide layer on the first doped region exposed by the first contact opening; forming the second metal silicide layer on the second doped region exposed by the second contact opening; and A conductive material is formed on the first metal silicide layer and the second metal silicide layer.

20. The method for manufacturing a semiconductor structure according to claim 11, characterized in that: The first doping region is formed in the entire fin portion, and the second doping region is formed in the first doping region.

21. The method for manufacturing a semiconductor structure according to claim 20, characterized in that: The first contact includes a first part and a second part connected to each other, the first part is located on the top surface of the fin part, the second part extends downward along the side wall of the fin part, and the first metal silicide layer is formed between the first contact and the top surface and the side wall of the fin part.

22. The method for manufacturing a semiconductor structure according to claim 21, characterized in that: The method for forming the first contact, the second contact, the first metal silicide layer and the second metal silicide layer includes: forming a dielectric layer on the substrate, wherein the dielectric layer covers the fin portion; forming a first contact opening in the dielectric layer exposing a portion of the top surface and a portion of the sidewall of the fin portion; forming a second contact opening in the dielectric layer to expose a portion of the second doped region; forming the first metal silicide layer on the fin portion exposed by the first contact opening; forming the second metal silicide layer on the second doped region exposed by the second contact opening; and A conductive material is formed on the first metal silicide layer and the second metal silicide layer.

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