Method for improving sheet resistance uniformity of solar cell

Abstract

The invention discloses a method for improving sheet resistance uniformity of a solar cell. The method comprises the following steps: preparing a quartz boat, cleaning, baking at a specific temperature for a specific time, and accurately positioning and placing; silicon wafers are loaded, PE-like wafers are placed in the forward direction at the specific inclination angle of 10-30 degrees and the distance of 2-5 mm, and the operation precision is controlled; putting the quartz boat into a furnace, stably pushing and monitoring; a boron diffusion process: selecting different parameter combinations according to silicon wafer placement parameters and monitoring; the subsequent process treatment relates to etching, cleaning, passivation, electrode preparation, sintering and the like. According to the invention, by optimizing the sheet placing mode and related process parameters, the sheet resistance uniformity is obviously improved, the performance consistency and stability of the cell sheet are enhanced, and the photoelectric conversion efficiency is improved. The process is flexible and optimizable, and can adapt to various production conditions. And meanwhile, the method has cost benefit, is favorable for reducing the production cost, and promotes large-scale production and application of solar cells.

Description

Technical Field

[0001] The present invention relates to the technical field of solar cell manufacturing, and in particular to a method for improving the square resistance uniformity of solar cell sheets by optimizing a sheet placement method and related process parameters. Background Art

[0002] In the current booming solar cell manufacturing field, topcon solar cells have become one of the key research and production directions due to their unique structural and performance advantages. Among them, the boron diffusion process is undoubtedly one of the key links that determine the performance of topcon solar cells, and it plays a fundamental role in shaping the uniformity of the square resistance of the cell. The boron diffusion process aims to form a specific doping distribution on the surface of the silicon wafer by accurately controlling the diffusion process of impurity atoms (boron atoms), thereby laying the foundation for the subsequent electrical performance construction. However, traditional wafer placement methods, such as the widely used horizontal and vertical wafer placement modes, have exposed many difficult-to-overcome disadvantages in actual operation. Under the horizontal wafer placement method, although the airflow can flow smoothly from the furnace mouth to the furnace tail in the furnace tube, the temperature distribution of the heating wire shows a trend of gradually weakening from the furnace wall to the furnace. This uneven temperature distribution directly leads to relatively low square resistance deposition and advancement temperature in the central area of ​​the furnace, which inevitably causes the emergence of high square resistance areas. At the same time, on the entire silicon wafer plane, the temperature differences experienced by different positions are significant, causing large fluctuations in the square resistance in the horizontal direction, which seriously damages the uniformity of the square resistance. The vertical placement method faces the severe challenge of obstructed air flow transmission. When the first silicon wafer is placed on the quartz boat, it acts as a barrier, greatly hindering the uniform transmission of subsequent airflow in the tube. This makes the concentration of the reaction gas exposed to each silicon wafer surface uneven, which leads to the uniformity of the square resistance in the tube being far lower than the ideal level. Even if the temperature can be relatively evenly distributed in the vertical direction, the unevenness of the airflow still becomes a key factor restricting the improvement of the uniformity of the square resistance. This poor uniformity of square resistance has a series of chain reactions in the performance of solar cells. Due to the difference in square resistance in different areas of the cell, local resistance inhomogeneity will be formed during the current transmission process, resulting in inconsistency in the performance of the cell. Specifically, in the process of photoelectric conversion, the transmission of electrons and holes will be disturbed by the uneven square resistance, which will increase the carrier recombination rate in some areas, thereby significantly reducing the photoelectric conversion efficiency of the cell. As one of the core indicators for measuring the performance of solar cells, the decline in photoelectric conversion efficiency directly weakens the ability of the cell to convert solar energy into electrical energy. From the perspective of the entire solar cell module, the inconsistency of the performance of a single cell will form a "barrel effect" inside the module. Poor performance cells will limit the output power of the entire module, reducing the reliability and stability of the module. During long-term outdoor use, the module may fail prematurely due to the performance degradation of local cells, shortening the service life and increasing maintenance costs, which seriously restricts the widespread application and promotion of solar cell modules in photovoltaic power generation systems.In summary, as solar cell manufacturing technology continues to pursue high efficiency, stability and reliability, developing a method that can effectively improve the uniformity of square resistance has become the key to breaking through the current technical bottleneck and improving the quality and performance of solar cells. It has far-reaching strategic significance and urgent practical needs for promoting the sustainable development of the solar cell industry. Summary of the invention

[0003] In order to overcome the above problems or at least partially solve the above problems, the core of the present invention is to provide a method for improving the uniformity of square resistance of a solar cell.

[0004] A method for improving the uniformity of square resistance of a solar cell, characterized by comprising the following steps:

[0005] Quartz boat preparation

[0006] The quartz boat made of high-purity quartz material should be selected, and its specifications should match the size of the furnace tube and silicon wafer used to ensure that the surface flatness of the quartz boat is within ±0.1mm, and there are no scratches and impurities visible to the naked eye. Put the quartz boat into a special cleaning device, first rinse it with deionized water for 3-5 minutes to remove loose particles on the surface, and then soak it in a cleaning solution mixed with hydrofluoric acid and nitric acid in a certain proportion (such as 1:5-1:10) for 10-15 minutes to remove metal impurities and other pollutants that may be adsorbed on the surface. After soaking, rinse it again with deionized water for 5-10 minutes to ensure that the cleaning solution is completely removed. Finally, put the quartz boat into a high-temperature oven for drying. The oven temperature is set to 800℃-1000℃, and the heating rate is controlled at 5℃ / min-10℃ / min. After reaching the set temperature, keep it for 30 minutes-60 minutes to thoroughly dry the quartz boat and remove impurities such as moisture adsorbed on the surface.

[0007] According to the inner diameter and length of the furnace tube, as well as the size of the silicon wafer, the best placement of the quartz boat in the furnace tube is accurately calculated. Using a laser positioning device to assist in positioning, the quartz boat is placed near the center axis of the furnace tube, with the deviation controlled within ±5mm, to ensure that the silicon wafer is heated and the airflow distribution is relatively uniform in the furnace tube.

[0008] Wafer loading

[0009] Place the cleaned and dried silicon wafers on the quartz boat in a PE-like forward placement method. The long side of the silicon wafer is placed at an angle of 10°-30° to the long side of the quartz boat. Different angles such as 15°, 20°, and 25° can be selected for testing, and a high-precision protractor is used to ensure that the tilt angle error of each silicon wafer does not exceed ±0.2°. Before loading the silicon wafer, a thin layer of inert gas (such as argon) is evenly applied to the surface of the quartz boat. The gas film is about 0.1μm-0.5μm thick to reduce the friction between the silicon wafer and the quartz boat, which is convenient for placing the silicon wafer. The spacing between the silicon wafers is maintained at 2mm-5mm, such as 2mm, 3mm, 4mm or 5mm. Use precision spacing measurement tools (such as micrometers) to ensure that the spacing error does not exceed ±0.05mm. During the loading process, automated loading equipment or manual operation with soft tweezers is used. The loading time of each silicon wafer is controlled within 5 seconds to 10 seconds to ensure that the silicon wafer is placed stably, avoid collision and scratches, ensure neat arrangement, and the lateral deviation of adjacent silicon wafers does not exceed ±0.3mm.

[0010] Quartz boat into the furnace

[0011] Place the quartz boat loaded with silicon wafers on the furnace track. The track should be kept horizontal, and its flatness deviation should not exceed ±0.5mm. Use an electric pusher to slowly and steadily push the quartz boat into the furnace tube at a pushing speed of 5cm / s-10cm / s. For example, you can choose 6cm / s, 7cm / s, 8cm / s, 9cm / s or 10cm / s. During the pushing process, the distance between the front end of the quartz boat and the entrance of the furnace tube is monitored in real time by a laser ranging sensor to ensure that the distance deviation does not exceed ±2cm. At the same time, a high-definition camera is set at the entrance of the furnace tube to monitor the status of the silicon wafer in the process of entering the furnace in real time. If the silicon wafer is found to be displaced or shaking, stop pushing immediately and make adjustments. When the quartz boat completely enters the furnace tube, record the time of entering the furnace, accurate to seconds, to provide a time reference for accurate control of subsequent process.

[0012] Boron diffusion process

[0013] Different boron diffusion process parameters were selected for testing according to the tilt angle and spacing of the silicon wafer.

[0014] When the tilt angle is 10 ° and the silicon chip spacing is 2 mm, the BCl3 gas flow rate is set to 80 sccm, the furnace tube pressure is 200 Pa, the boron expansion temperature is 900 ° C, and the boron expansion time is 60 minutes; at the same time, in the boron expansion process, the gas atmosphere in the furnace tube is controlled to keep the oxygen content at 1%-3% (volume fraction) to promote the diffusion and doping reaction of boron atoms. When the tilt angle is 20 ° and the silicon chip spacing is 3 mm, the BCl3 gas flow rate is 120 sccm, the furnace tube pressure is 300 Pa, the boron expansion temperature is 950 ° C, and the boron expansion time is 90 minutes, and the furnace tube is pre-evacuated before the boron expansion, and the vacuum degree reaches 10-2Pa-10-3Pa to reduce the interference of impurity gases to the boron expansion process. When the tilt angle is 30° and the silicon wafer spacing is 4mm, the BCl3 gas flow rate is 150sccm, the furnace tube pressure is 400Pa, the boron expansion temperature is 980℃, and the boron expansion time is 100 minutes. During this process, a small amount of nitrogen (flow rate is 10sccm-20sccm) is introduced into the furnace tube as a protective gas to prevent oxidation of the silicon wafer surface. When the tilt angle is 15° and the silicon wafer spacing is 5mm, the BCl3 gas flow rate is 180sccm, the furnace tube pressure is 500Pa, the boron expansion temperature is 1000℃, and the boron expansion time is 120 minutes. In the later stage of boron expansion, the pressure in the furnace tube is gradually reduced to 100Pa-200Pa to optimize the diffusion depth and distribution of boron atoms. (Different parameter combinations can be further supplemented according to actual conditions) During the boron expansion process, the temperature, pressure and gas flow parameters in the furnace tube are continuously monitored, and the data are recorded every 5 minutes. At the same time, the temperature distribution on the surface of the silicon wafer is monitored to ensure that the temperature uniformity is within ±5℃.

[0015] Cooling and subsequent processing

[0016] After the boron expansion process is completed, the furnace tube is cooled by a graded cooling method. The furnace tube temperature is first reduced to 500℃-600℃ at a cooling rate of 5℃ / min-10℃ / min, and then naturally cooled to room temperature to avoid stress on the silicon wafer due to sudden temperature changes. During the cooling process, pure inert gas (such as argon) is introduced into the furnace tube at a flow rate of 50sccm-100sccm to protect the surface of the silicon wafer from oxidation.

[0017] After the silicon wafer is cooled, it is taken out from the furnace tube and then subjected to subsequent processing, such as etching to remove the phosphorus silicon glass (PSG) layer. Wet etching (such as hydrofluoric acid solution, concentration of 5%-10%) or dry etching method can be used. The etching time is determined according to the thickness of the PSG layer on the surface of the silicon wafer, generally 30 seconds to 60 seconds. After etching, it is rinsed with deionized water for 3-5 times, and then ultrasonic cleaning is performed. The ultrasonic frequency is 20kHz-40kHz, and the cleaning time is 5 minutes to 10 minutes to ensure that the residues generated during the etching process are removed. Then passivation treatment is performed, such as using plasma enhanced chemical vapor deposition (PECVD) technology to deposit a silicon nitride (SiNx) film with a thickness of 50nm-100nm on the surface of the silicon wafer. During the deposition process, the plasma power is controlled to be 100W-200W, and the reaction gas flow ratio (silane: ammonia) is 1:5-1:10. Finally, the electrodes are prepared by screen printing technology, and silver paste or aluminum paste is printed as the front and back electrode materials with a printing thickness of 80μm-120μm. Then, sintering treatment is carried out, and the sintering temperature is 800℃-900℃ and the sintering time is 30 seconds-60 seconds, so that the electrode forms a good ohmic contact with the silicon wafer, and the solar cell manufacturing is completed.

[0018] The embodiments of the present invention have at least the following advantages or beneficial effects:

[0019] 1. The present invention significantly improves the uniformity of square resistance. Through the carefully designed PE-like forward placement method, combined with the precise control of different tilt angles, silicon wafer spacing and optimized boron expansion process parameters, including gas flow, pressure, temperature, time and gas atmosphere, the thermal radiation and airflow transmission of silicon wafers in the furnace tube can be greatly improved. After a large number of experimental tests and comparisons, after adopting the method of the present invention, the uniformity of the square resistance wafer has made a qualitative leap compared with the traditional placement method. For example, the uniformity of the furnace mouth-upper wafer of the traditional horizontal placement may reach 4.71%, while under the optimized parameter combination of the present invention, the uniformity within the wafer can be reduced to less than 1%, such as 0.8%, 0.6%, etc., which significantly improves the consistency and stability of the performance of the battery cell, thereby improving the photoelectric conversion efficiency of solar cells.

[0020] 2. The process involved in the present invention is highly flexible and optimizable. The present invention provides a rich variety of tilt angles and silicon wafer spacing options, as well as a comprehensive and detailed combination of boron expansion process parameters corresponding thereto. This allows for flexible adjustment and deep optimization in the actual production process according to different equipment conditions (such as furnace tube size, heating system performance, etc.), silicon wafer characteristics (such as silicon wafer size, crystal structure, etc.) and product requirements (such as solar cells of different power levels). Enterprises can find the process solution that best suits their own production environment through simple experiments, which not only improves production efficiency, but also ensures the stability and reliability of product quality.

[0021] 3. The method involved in the present invention achieves a significant improvement in square resistance uniformity by only innovating and improving the wafer placement method and finely optimizing the process parameters without introducing expensive new equipment or complicated additional process steps. This helps to significantly reduce production costs, including reduced raw material consumption (due to good square resistance uniformity, the number of silicon wafers scrapped due to poor performance can be reduced), reduced energy consumption (optimized process parameters make processes such as heating and gas supply more efficient), and shortened production cycles (rapidly finding the optimal process parameters can reduce debugging time). Ultimately, the market competitiveness of solar cells is improved, which is conducive to large-scale production applications and promotes the development of the solar cell industry. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for use in the embodiments are briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present invention and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without creative work.

[0023] Figure 1 It is a schematic diagram of the film placing step of the present invention;

[0024] Figure 2 It is a schematic diagram of the principles of different film placing methods in the present invention;

[0025] Figure 3 The figure is a test data diagram of the corresponding square resistance of different chip placement methods in the present invention. DETAILED DESCRIPTION

[0026] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Generally, the components of the embodiments of the present invention described and shown in the drawings here can be arranged and designed in various different configurations.

[0027] Therefore, the following detailed description of the embodiments of the present invention provided in the accompanying drawings is not intended to limit the scope of the invention claimed for protection, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0028] Example 1

[0029] Quartz boat preparation

[0030] Select a quartz boat with a surface roughness of less than 0.1μm, rinse it with deionized water for 5 minutes, then soak it in a mixed cleaning solution of hydrofluoric acid and nitric acid with a volume ratio of 1:8 for 12 minutes, rinse it with deionized water for 8 minutes, and bake it in a high-temperature oven at 900℃ for 45 minutes with a heating rate of 8℃ / min. Place the quartz boat so that the deviation of the central axis of the furnace tube is within ±3mm.

[0031] An argon film with a thickness of 0.3 μm was evenly applied on the surface of the quartz boat.

[0032] Wafer loading

[0033] The silicon wafers are placed on the quartz boat in a PE-like forward placement method. The long side of the silicon wafer is tilted at an angle of 15° to the long side of the quartz boat. A high-precision protractor is used to ensure that the angle error is within ±0.3°. The silicon wafer spacing is 3mm, and a micrometer is used to ensure that the spacing error is within ±0.08mm. Using automated loading equipment, the loading time for each silicon wafer is 8 seconds, and the lateral deviation of adjacent silicon wafers does not exceed ±0.4mm.

[0034] Quartz boat into the furnace

[0035] The flatness deviation of the furnace entry track is ±0.3mm. The quartz boat is pushed at a speed of 8cm / s by an electric pushing device. The high-definition camera monitoring at the entrance of the furnace tube shows that the silicon wafer has no displacement or shaking. The furnace entry time is accurately recorded as 10:0:0.

[0036] Boron diffusion process

[0037] The BCl3 gas flow rate was 120 sccm, the furnace pressure was 300 Pa, the boron expansion temperature was 950°C, the boron expansion time was 90 minutes, and the furnace was pre-evacuated to 10-2.5 Pa before the boron expansion. The data recorded every 5 minutes during the boron expansion process showed that the temperature fluctuation was within ±3°C, the pressure fluctuation was within ±10 Pa, and the gas flow fluctuation was within ±5 sccm.

[0038] Cooling and subsequent processing

[0039] Step cooling, first reduce to 550℃ at 8℃ / min, then cool naturally. The argon flow rate during cooling is 80sccm. Etching is done by wet etching with 5% hydrofluoric acid solution for 45 seconds, followed by rinsing with deionized water 4 times and ultrasonic cleaning for 8 minutes. For passivation, a 70nm thick SiNx film is deposited by PECVD, with a plasma power of 150W and a silane:ammonia flow ratio of 1:8. The screen-printed electrode thickness is 100μm and sintered at 850℃ for 45 seconds.

[0040] After testing, the square resistance uniformity of the solar cell prepared in this embodiment is significantly improved, and the uniformity within the cell reaches 1.2%, which is a significant improvement compared to the traditional cell placement method (such as horizontal or vertical cell placement in the comparative example), and the photoelectric conversion efficiency of the cell is increased by about 0.8%, and the fill factor is also improved to a certain extent, indicating that the performance of the cell is effectively enhanced.

[0041] Example 2

[0042] Quartz boat preparation

[0043] The quartz boat preparation steps are the same as those in Example 1, but the baking temperature is 950° C. and the baking time is 50 minutes.

[0044] Wafer loading

[0045] The silicon wafer tilt angle is 20°, the angle error is ±0.2°, the spacing is 4mm, and the spacing error is ±0.06mm. The loading time of each silicon wafer is 6 seconds, and the lateral deviation of adjacent silicon wafers does not exceed ±0.3mm.

[0046] Quartz boat into the furnace

[0047] The flatness deviation of the furnace entry track is ±0.2mm, the pushing speed is 9cm / s, and the furnace entry time is 10 hours, 10 minutes and 0 seconds.

[0048] Boron diffusion process

[0049] BCl3 gas flow rate is 150sccm, furnace tube pressure is 400Pa, boron expansion temperature is 980℃, boron expansion time is 100 minutes, and nitrogen flow rate is 15sccm during boron expansion. Temperature fluctuation is ±2℃, pressure fluctuation is ±8Pa, and gas flow fluctuation is ±3sccm.

[0050] Cooling and subsequent processing

[0051] The cooling method is the same as that in Example 1, the etching adopts dry etching, and the passivation, screen printing and sintering parameters are the same as those in Example 1.

[0052] The test results show that the cell sheet resistance uniformity of this embodiment is good, and the uniformity within the cell is 1.0%, which is significantly better than the traditional cell placement method. The photoelectric conversion efficiency of the cell sheet is increased by about 1.0%, and the fill factor is also optimized, thanks to the improvement of the uniformity of the square resistance and the synergy of each process step.

[0053] Example 3

[0054] Quartz boat preparation

[0055] Same as Example 1, but the cleaning solution immersion time is 10 minutes, the baking temperature is 850° C., and the baking time is 35 minutes.

[0056] Wafer loading

[0057] The silicon wafer tilt angle is 25°, the angle error is ±0.4°, the spacing is 2mm, and the spacing error is ±0.05mm. Automatic loading, each silicon wafer loading time is 7 seconds, and the lateral deviation of adjacent silicon wafers does not exceed ±0.35mm.

[0058] Quartz boat into the furnace

[0059] The flatness deviation of the furnace entry track is ±0.4mm, the pushing speed is 7cm / s, and the furnace entry time is 10:20:00.

[0060] Boron diffusion process

[0061] The BCl3 gas flow rate is 100 sccm, the furnace pressure is 250 Pa, the boron expansion temperature is 920°C, the boron expansion time is 70 minutes, and the oxygen content is controlled at 2% during the boron expansion process. The temperature fluctuation is ±4°C, the pressure fluctuation is ±12 Pa, and the gas flow fluctuation is ±6 sccm.

[0062] Cooling and subsequent processing

[0063] The cooling method is the same as that in Example 1. The etching adopts wet etching (hydrofluoric acid concentration is 8%, etching time is 50 seconds). The passivation, screen printing and sintering parameters are the same as those in Example 1.

[0064] The square resistance uniformity of the cell prepared in this embodiment reaches 1.3%, which is a significant improvement over the traditional cell placement method. The photoelectric conversion efficiency of the cell is increased by about 0.7%, and the fill factor is also improved, further proving the effectiveness of the method of the present invention.

[0065] 2. Comparison

[0066] Comparative Example 1 (Traditional horizontal film placement method)

[0067] Quartz boat preparation

[0068] After briefly cleaning the quartz boat, it was baked at 800°C for 30 minutes and randomly placed in the furnace tube (the position was not precisely controlled).

[0069] Wafer loading

[0070] The silicon wafers are placed horizontally on the quartz boat without any tilt angle, and the silicon wafers are closely arranged (with a spacing of less than 1 mm).

[0071] Quartz boat into the furnace

[0072] The quartz boat was pushed into the furnace tube manually and quickly at a speed of about 15 cm / s, and the time of entering the furnace was not recorded.

[0073] Boron diffusion process

[0074] The BCl3 gas flow rate was 100 sccm, the furnace tube pressure was 200 Pa, the boron diffusion temperature was 900°C, and the boron diffusion time was 60 minutes. No special atmosphere control or other optimization was performed.

[0075] Cooling and subsequent processing

[0076] Natural cooling, etching, passivation, screen printing and sintering use conventional but unoptimized process parameters (poor etching effect, uneven electrode thickness, etc.).

[0077] Tests show that its square resistance uniformity is poor, with the intra-chip uniformity reaching 4.5%, the photoelectric conversion efficiency is relatively low, and the fill factor is not ideal either. This is due to the uneven distribution of airflow and thermal radiation when the chip is placed horizontally.

[0078] Comparative Example 2 (Traditional vertical film placement method)

[0079] Quartz boat preparation

[0080] The quartz boat preparation steps are the same as those in Comparative Example 1.

[0081] Wafer loading

[0082] The silicon wafers were placed vertically on a quartz boat, with a spacing of about 0.5 mm between the wafers.

[0083] Quartz boat into the furnace

[0084] The same furnace entry method as Comparative Example 1.

[0085] Boron diffusion process

[0086] The boron diffusion process parameters are the same as those of Comparative Example 1.

[0087] Cooling and subsequent processing

[0088] The cooling and subsequent treatment methods are the same as those of Comparative Example 1.

[0089] The square resistance uniformity of the cell in this comparative example is also poor, with an intra-cell uniformity of 5.0%. The photoelectric conversion efficiency and fill factor are poor. The main reason is that the air flow transmission is blocked when the cell is placed vertically, which affects the boron diffusion effect and square resistance uniformity.

[0090] By comparing the embodiments and comparative examples, it can be clearly seen that the method of the present invention has significant advantages in improving the uniformity of square resistance of solar cell sheets and enhancing the overall performance of the cells (photoelectric conversion efficiency, fill factor, etc.), providing a strong basis for improving the solar cell manufacturing process.

[0091] It will be apparent to those skilled in the art that the present application is not limited to the details of the exemplary embodiments described above, and that the present application can be implemented in other specific forms without departing from the spirit or essential features of the present application. Therefore, the embodiments should be considered exemplary and non-limiting in all respects, and the scope of the present application is defined by the appended claims rather than the above description, and it is intended that all changes falling within the meaning and scope of the equivalent elements of the claims be included in the present application. Any reference numeral in a claim should not be considered as limiting the claim to which it relates.

Claims

1. A method for improving the uniformity of square resistance of a solar cell, characterized in that: The following steps are involved: Step 1. Quartz boat preparation: select a quartz boat of suitable specifications with smooth surface, no scratches and impurities, clean it and dry it by high-temperature baking. The baking temperature is controlled at 800℃-1000℃ and the baking time is 30 minutes-60 minutes. According to the size of the furnace tube and the size of the silicon wafer, place the quartz boat near the central axis of the furnace tube, with a deviation of no more than ±5mm; Step 2. Wafer loading: Place the cleaned and dried silicon wafers on the quartz boat in a PE-like forward placement method, with the long side of the silicon wafer tilted at 10°-30° to the long side of the quartz boat, and use a high-precision protractor to ensure that the tilt angle error of each silicon wafer does not exceed ±0.5°; maintain a spacing of 2mm-5mm between the silicon wafers, and use a precision spacing measurement tool to ensure that the spacing error does not exceed ±0.1mm; use automated loading equipment or manual soft tweezers during the loading process, and control the loading time of each silicon wafer within 5 seconds to 10 seconds to ensure that the silicon wafers are placed stably, avoid collisions and scratches, ensure neat arrangement, and the lateral deviation of adjacent silicon wafers does not exceed ±0.5mm; Step 3. Quartz boat into the furnace: Slowly and steadily push the quartz boat loaded with silicon wafers into the furnace tube at a pushing speed of 5cm / s-10cm / s, and ensure that the distance deviation between the front end of the quartz boat and the entrance of the furnace tube does not exceed ±2cm; during the feeding process, closely observe whether the silicon wafer is displaced or shaken, and make timely adjustments if there is any abnormality, and accurately record the time when the quartz boat enters the furnace, accurate to seconds; Step 4. Boron expansion process: different boron expansion process parameters are selected according to the inclination angle and spacing of the silicon wafers for boron expansion. During the boron expansion process, the temperature, pressure, gas flow and other parameters in the furnace tube are continuously monitored, and the data are recorded every 5 minutes. After the boron expansion is completed, the furnace tube is cooled, and then the silicon wafer is taken out of the furnace tube for subsequent process processing; Step 5. Subsequent process treatment: including etching process to remove the phosphosilicate glass (PSG) layer, cleaning to remove residues after etching, passivation treatment, and finally preparing electrodes through screen printing technology, sintering treatment to make good ohmic contact between the electrodes and the silicon wafer to complete the solar cell manufacturing.

2. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: In the quartz boat preparation step, the quartz boat is first rinsed with deionized water for 3-5 minutes, then immersed in a cleaning solution prepared by mixing hydrofluoric acid and nitric acid in a ratio of 1:5-1:10 for 10-15 minutes, and then rinsed again with deionized water for 5-10 minutes after immersion.

3. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: In the silicon wafer loading step, a layer of inert gas film with a thickness of 0.1 μm-0.5 μm is evenly applied on the surface of the quartz boat before loading the silicon wafer.

4. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: During the step of putting the quartz boat into the furnace, the flatness deviation of the furnace track does not exceed ±0.5mm. An electric pushing device is used to push the quartz boat, and a high-definition camera is set at the entrance of the furnace tube to monitor the status of the silicon wafer entering the furnace in real time.

5. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: When the silicon wafer inclination angle is 10° and the silicon wafer spacing is 2 mm, the boron expansion process parameters are BCl3 gas flow rate 80 sccm, furnace tube pressure 200 Pa, boron expansion temperature 900°C, boron expansion time 60 minutes, and the oxygen content in the furnace tube is controlled to be maintained at 1%-3% (volume fraction) during the boron expansion process.

6. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: When the silicon wafer tilt angle is 20° and the silicon wafer spacing is 3mm, the boron expansion process parameters are BCl3 gas flow rate 120sccm, furnace tube pressure 300Pa, boron expansion temperature 950℃, boron expansion time 90 minutes, and the furnace tube is pre-vacuumed before boron expansion, and the vacuum degree reaches 10-2Pa-10-3Pa.

7. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: When the silicon wafer inclination angle is 30° and the silicon wafer spacing is 4mm, the boron expansion process parameters are BCl3 gas flow rate 150sccm, furnace tube pressure 400Pa, boron expansion temperature 980℃, boron expansion time 100 minutes, and during the boron expansion process, nitrogen with a flow rate of 10sccm-20sccm is introduced into the furnace tube as a protective gas.

8. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: When the silicon wafer tilt angle is 15° and the silicon wafer spacing is 5mm, the boron expansion process parameters are BCl3 gas flow rate 180sccm, furnace tube pressure 500Pa, boron expansion temperature 1000℃, boron expansion time 120 minutes, and the pressure in the furnace tube is gradually reduced to 100Pa-200Pa in the later stage of boron expansion.

9. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: In the cooling and subsequent processing steps, a graded cooling method is adopted after the boron expansion process is completed. The furnace tube temperature is first reduced to 500℃-600℃ at a cooling rate of 5℃ / min-10℃ / min, and then naturally cooled to room temperature. During the cooling process, an inert gas with a flow rate of 50sccm-100sccm is introduced into the furnace tube.

10. The method for improving the uniformity of square resistance of a solar cell according to claim 1, characterized in that: In the subsequent process steps, the etching process adopts wet etching using a hydrofluoric acid solution with a concentration of 5%-10%, and the etching time is 30 seconds-60 seconds; the passivation treatment adopts plasma enhanced chemical vapor deposition (PECVD) technology, and the thickness of the deposited silicon nitride (SiNx) film is 50nm-100nm. During the deposition process, the plasma power is controlled to 100W-200W, and the reaction gas flow ratio (silane: ammonia) is 1:5-1:10; the screen-printed electrode thickness is 80μm-120μm, the sintering temperature is 800℃-900℃, and the sintering time is 30 seconds-60 seconds.

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