Solar cell and preparation method thereof

Abstract

The invention relates to a solar cell and a preparation method thereof, and the method comprises the following steps: providing a semiconductor substrate, and forming a doping structure on the lower surface of the semiconductor substrate, the doping structure comprises a tunneling layer, an intrinsic layer, a first doping structure, a second doping structure and an isolation structure, wherein the tunneling layer and the intrinsic layer are stacked in sequence; the first doping structure and the second doping structure are located in the intrinsic layer and have opposite conduction types; forming passivation anti-reflection material layers on the upper surface of the semiconductor substrate and the lower surface of the doping structure respectively; removing the passivation anti-reflection material layer on the lower surfaces of the first doping structure and the second doping structure to form a passivation anti-reflection layer comprising a first passivation anti-reflection layer and a second passivation anti-reflection layer which are respectively arranged on the lower surface of the isolation structure and the upper surface of the semiconductor substrate; forming a first conductive part and a second conductive part which at least cover the lower surface of the first doping structure and the lower surface of the second doping structure, wherein one ends, close to the isolation structure, of the first conductive part and the second conductive part are arranged at intervals. According to the solar cell and the preparation method thereof, parasitic absorption of the solar cell is greatly improved.

Description

Technical Field

[0001] The present application relates to the technical field of solar cells, and in particular to a solar cell and a method for preparing the same. Background Art

[0002] Back-contact solar cells are an advanced solar cell design whose core concept is to place all metal electrodes on the back of the cell, thereby ensuring that the front of the cell is not blocked by any metal grid lines. This design maximizes the area of ​​the cell that absorbs sunlight, reduces optical losses, and improves photoelectric conversion efficiency. The advantage of the back-contact (BC) cell structure is that its front side can be fully used for light absorption, while the back side is used to collect current, thereby improving the overall performance of the cell.

[0003] In recent years, research institutions and enterprises at home and abroad have been actively exploring interdigitated back contact (IBC) solar cell technology. IBC cells place all electrodes on the back of the cell, eliminating the shading of the front grid lines, thereby improving the photoelectric conversion efficiency of the cell. However, conventional IBC solar cells are limited by metal composites and passivation film layers, and cannot further improve the conversion efficiency. In order to overcome this limitation, the cell structure needs to be improved.

[0004] Tunnel Oxide Passivated Contact (TOPCon) technology is a technology that realizes high-efficiency solar cells by forming a tunnel oxide layer and a doped polysilicon layer on the surface of the cell. This technology suppresses the recombination rate of minority carriers at the interface through the tunnel oxide passivation contact structure, greatly improving the open circuit voltage and fill factor of the cell.

[0005] In order to further improve the performance of solar cells, a new generation of Tunnel Oxide Passivated Back Contact (TBC) solar cells have been developed in combination with the tunnel oxide passivation contact technology of TOPCon cells. The electrodes of this type of cell are all located on the back of the cell, and there is no need to consider the optical problems on the front side. By making a tunnel oxide passivation contact structure, the recombination rate of minority carriers at the interface is effectively suppressed, thereby greatly improving the open circuit voltage and fill factor of the cell. TBC solar cells use a low-pressure chemical vapor deposition (LPCVD) process to realize tunnel oxide and intrinsic polysilicon passivation layers. The selective carrier transport of these layers and the doped polysilicon passivation contact are of great significance for the realization of high-efficiency solar cells.

[0006] Although TBC solar cells have excellent electrical performance, the problem of optical loss still exists, mainly due to the parasitic absorption of polysilicon. In order to further improve the photoelectric conversion efficiency of solar cells, it is necessary to solve this problem and optimize the cell structure and process selection. Summary of the invention

[0007] Based on this, it is necessary to provide a solar cell and a method for preparing the same in order to solve the problem that parasitic absorption exists in solar cells in the prior art and greatly affects the photoelectric conversion efficiency of the solar cell.

[0008] In order to achieve the above object, on the one hand, the present invention provides a method for preparing a solar cell, comprising the following steps:

[0009] Providing a semiconductor substrate;

[0010] forming a doping structure on the lower surface of the semiconductor substrate, the doping structure comprising a tunneling layer, an intrinsic layer, and a first doping structure, a second doping structure, and an isolation structure located in the intrinsic layer, wherein the isolation structure isolates the first doping structure from the second doping structure, and the first doping structure and the second doping structure have opposite conductivity types;

[0011] forming a passivation anti-reflection material layer on the upper surface of the semiconductor substrate and the lower surface of the doping structure respectively;

[0012] Removing the passivation anti-reflection material layer located on the lower surfaces of the first doping structure and the second doping structure to form a passivation anti-reflection layer, wherein the passivation anti-reflection layer includes a first passivation anti-reflection layer located on the lower surface of the isolation structure and a second passivation anti-reflection layer located on the upper surface of the semiconductor substrate;

[0013] A first conductive portion is formed to at least cover the lower surface of the first doped structure, and a second conductive portion is formed to at least cover the lower surface of the second doped structure, wherein an end of the first conductive portion close to the isolation structure is spaced from an end of the second conductive portion close to the isolation structure.

[0014] In one embodiment, forming the doping structure on the lower surface of the semiconductor substrate comprises the following steps:

[0015] Forming the tunneling layer and the intrinsic layer stacked in sequence on the lower surface of the semiconductor substrate;

[0016] forming a first doped initial structure and a second doped initial structure on the lower surface of the intrinsic layer, wherein the first doped initial structure and the second doped initial structure are spaced apart and have opposite conductivity types;

[0017] The intrinsic layer after the first doping initial structure and the second doping initial structure are formed on the lower surface is annealed. After the annealing, the first doping initial structure forms the first doping structure in the intrinsic layer, and the first doping initial structure forms the second doping structure in the intrinsic layer. The undoped intrinsic layer between the first doping structure and the second doping structure serves as the isolation structure.

[0018] In one embodiment, before forming the passivation anti-reflection material layer on the upper surface of the semiconductor substrate, the method further includes:

[0019] A textured structure is formed on the upper surface of the semiconductor substrate.

[0020] In one embodiment, forming the textured structure on the upper surface of the semiconductor substrate comprises the following steps:

[0021] forming a protective layer on the lower surface of the doping structure;

[0022] Wet etching the upper surface of the semiconductor substrate to form the textured structure;

[0023] The protective layer is removed.

[0024] In one embodiment, after forming the passivation anti-reflection material layer on the upper surface of the semiconductor substrate and the lower surface of the doped structure, and before removing the passivation anti-reflection material layer located on the lower surfaces of the first doped structure and the second doped structure, the method further includes:

[0025] The passivation anti-reflection material layer is annealed.

[0026] In one embodiment, the passivation anti-reflection material layer includes a first passivation material and a second passivation material stacked in sequence, wherein the first passivation material includes Al x O y The second passivation material includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

[0027] In one embodiment, the first conductive portion and / or the second conductive portion extends to the lower surface of the first passivation anti-reflection layer.

[0028] In one embodiment, forming the first conductive portion at least covering the lower surface of the first doped structure, and forming the second conductive portion at least covering the lower surface of the second doped structure, comprises the following steps:

[0029] forming a conductive material layer covering the lower surface of the first doped structure, the lower surface of the second doped structure, and the exposed surface of the first passivation anti-reflection layer;

[0030] An isolation groove is formed in the conductive material layer, wherein the isolation groove penetrates the conductive material layer and the opening width of the isolation groove is not greater than the width of the isolation structure, so as to form the first conductive part that at least covers the lower surface of the first doped structure and the second conductive part that at least covers the lower surface of the second doped structure.

[0031] In one embodiment, after forming the first conductive portion that at least covers the lower surface of the first doping structure and forming the second conductive portion that at least covers the lower surface of the second doping structure, the method further includes:

[0032] A first lead-out electrode is formed on the lower surface of the first conductive portion, and a second lead-out electrode is formed on the lower surface of the second conductive portion.

[0033] The present invention also provides a solar cell, wherein the solar cell is prepared by using any one of the above-mentioned methods for preparing a solar cell.

[0034] The solar cell and preparation method thereof of the present invention have the following beneficial effects: by forming a passivation anti-reflection material layer on the lower surface of the doped structure, the free hydrogen in the passivation anti-reflection material layer repairs the defect centers and dangling bonds of the first doped structure, the second doped structure and the tunneling layer during the annealing process, thereby improving the quality of the first doped structure, the second doped structure and the tunneling layer, and improving the performance of the solar cell; and removing the passivation anti-reflection material layer located on the lower surface of the first doped structure and the second doped structure to form a first passivation anti-reflection layer located on the lower surface of the isolation structure, thereby ensuring a good interface passivation effect and an isolation effect of the first doped structure and the second doped structure, and also facilitating the subsequent realization of good electrical contact; by directly forming at least A first conductive portion covering the lower surface of the first doped structure and a second conductive portion at least covering the lower surface of the second doped structure, the first conductive portion and the second conductive portion have good conductivity, achieve higher transmittance, lower resistivity and efficient carrier collection, greatly improve the battery conversion efficiency loss caused by parasitic absorption, and the first conductive portion is arranged at an interval between one end of the isolation structure close to the isolation structure and the second conductive portion is arranged at an interval, which realizes the isolation of the first doped structure and the second doped structure while ensuring lateral current conduction; in addition, in some embodiments, the first doped structure, the second doped structure and the isolation structure are directly formed in the intrinsic layer through annealing treatment, which avoids the formation of a "leakage current" channel and greatly simplifies the process flow. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the conventional technology, the drawings required for use in the embodiments or the conventional technology descriptions are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0036] Figure 1 is a flow chart of a method for preparing a solar cell provided in one embodiment;

[0037] Figure 2 It is a schematic diagram of the cross-sectional structure after forming a tunneling layer and an intrinsic layer in a method for preparing a solar cell provided in an embodiment;

[0038] Figure 3 It is a schematic diagram of a cross-sectional structure after a first doping initial structure and a second doping initial structure are formed in a method for preparing a solar cell provided in an embodiment;

[0039] Figure 4 It is a schematic diagram of a cross-sectional structure after a first doping structure, a second doping structure and an isolation structure are formed in a method for preparing a solar cell provided in an embodiment;

[0040] Figure 5 A schematic diagram of a cross-sectional structure after a protective layer is formed in a method for preparing a semiconductor structure provided in an embodiment;

[0041] Figure 6 It is a schematic diagram of the cross-sectional structure after a velvet structure is formed in a method for preparing a solar cell provided in an embodiment;

[0042] Figure 7 It is a schematic diagram of the cross-sectional structure after a passivation anti-reflection material layer is formed in a method for preparing a solar cell provided in an embodiment;

[0043] Figure 8 It is a schematic diagram of the cross-sectional structure after a passivation anti-reflection layer is formed in the method for preparing a solar cell provided in an embodiment;

[0044] Fig. 9 It is a schematic diagram of the cross-sectional structure after a conductive material layer is formed in a method for preparing a solar cell provided in an embodiment;

[0045] Fig.10 It is a schematic diagram of the cross-sectional structure after forming the first conductive part and the second conductive part in the preparation method of the solar cell provided in one embodiment.

[0046] Fig.11 It is a schematic diagram of the cross-sectional structure after forming the first extraction electrode and the second extraction electrode in the preparation method of the solar cell provided in one embodiment.

[0047] Description of reference numerals:

[0048] 1-semiconductor substrate, 2-doping structure, 21-tunneling layer, 22-intrinsic layer, 23-first doping structure, 24-second doping structure, 25-isolation structure, 26-first doping initial structure, 27-second doping initial structure, 3-passivation anti-reflection layer, 31-passivation anti-reflection material layer, 32-first passivation anti-reflection layer, 33-second passivation anti-reflection layer, 4-first conductive part, 5-second conductive part, 6-protective layer, 7-conductive material layer, 8-isolation groove, 9-first lead-out electrode, 10-second lead-out electrode. DETAILED DESCRIPTION

[0049] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0050] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0051] It should be understood that when an element or layer is referred to as being "on, adjacent to, connected to or coupled to other elements or layers, it may be directly on, adjacent to, connected to or coupled to other elements or layers, or there may be intervening elements or layers. On the contrary, when an element is referred to as being "directly on, directly adjacent to, directly connected to or directly coupled to other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0052] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0053] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0054] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic diagrams of ideal embodiments (and intermediate structures) of the invention, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Thus, embodiments of the invention should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation is performed. Thus, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the invention.

[0055] See also Figure 1 , is a flow chart of a method for preparing a solar cell. The present invention provides a method for preparing a solar cell, comprising the following steps:

[0056] S1: providing a semiconductor substrate 1;

[0057] S2: forming a doping structure 2 on the lower surface of the semiconductor substrate 1, wherein the doping structure 2 comprises a tunneling layer 21, an intrinsic layer 22, and a first doping structure 23, a second doping structure 24 and an isolation structure 25 which are stacked in sequence, wherein the isolation structure 25 isolates the first doping structure 23 from the second doping structure 24, and the first doping structure 23 and the second doping structure 24 have opposite conductivity types;

[0058] S3: forming a passivation anti-reflection material layer 31 on the upper surface of the semiconductor substrate 1 and the lower surface of the doping structure 2 respectively;

[0059] S4: removing the passivation anti-reflection material layer 31 located on the lower surfaces of the first doping structure 21 and the second doping structure 22 to form a passivation anti-reflection layer 3, wherein the passivation anti-reflection layer 3 includes a first passivation anti-reflection layer 32 located on the lower surface of the isolation structure 25 and a second passivation anti-reflection layer 33 located on the upper surface of the semiconductor substrate 1;

[0060] S5: forming a first conductive portion 4 that at least covers the lower surface of the first doped structure 23 , and forming a second conductive portion 5 that at least covers the lower surface of the second doped structure 24 , with an end of the first conductive portion 4 close to the isolation structure 25 and an end of the second conductive portion 5 close to the isolation structure 25 spaced apart.

[0061] The above-mentioned preparation method of the solar cell forms a passivation anti-reflection material layer 31 on the lower surface of the doping structure 2, so that the free hydrogen in the passivation anti-reflection material layer 31 repairs the defect centers and dangling bonds of the first doping structure 23, the second doping structure 24 and the tunneling layer 21 during the annealing process, thereby improving the quality of the first doping structure 23, the second doping structure 24 and the tunneling layer 21, and improving the performance of the solar cell. The passivation anti-reflection material layer 31 located on the lower surface of the first doping structure 23 and the second doping structure 24 is removed to form a first passivation anti-reflection layer 32 located on the lower surface of the isolation structure 25, which ensures a good interface passivation effect and an isolation effect of the first doping structure 23 and the second doping structure 24, while also facilitating the subsequent realization of good electrical contact; by directly forming at least the first doping structure 23 and the second doping structure 24, the passivation anti-reflection material layer 31 covering the first doping structure 23 and the second doping structure 24 is removed. The first conductive part 4 on the lower surface of the doped structure 23 and the second conductive part 5 at least covering the lower surface of the second doped structure 24, the first conductive part 4 and the second conductive part 5 have good conductivity, achieve higher transmittance, lower resistivity and efficient carrier collection, greatly improve the battery conversion efficiency loss caused by parasitic absorption, and the first conductive part 4 is arranged at an interval between one end of the isolation structure 25 and one end of the second conductive part 5 close to the isolation structure 25, so as to achieve the isolation of the first doped structure 23 and the second doped structure 24 while ensuring the lateral current conduction; in addition, in some embodiments, the first doped structure 23, the second doped structure 24 and the isolation structure 25 are directly formed in the intrinsic layer 22 by annealing treatment, which avoids the formation of a "leakage current" channel and greatly simplifies the process flow.

[0062] Step S1 is performed to provide a semiconductor substrate 1. The material of the semiconductor substrate 1 includes single crystal silicon, polycrystalline silicon, and compound semiconductors (for example, gallium nitride, gallium arsenide, etc.), but may also include one or more other semiconductor materials. In this embodiment, the material of the semiconductor substrate 1 is single crystal silicon, and the semiconductor substrate 1 is also doped with N-type or P-type doping elements.

[0063] In some embodiments, step S1 further includes step S11 of cleaning the semiconductor substrate 1, wherein the cleaning of the semiconductor substrate 1 includes the following steps S111 to S114:

[0064] S111: Pre-polishing the surface of the semiconductor substrate 1; the pre-polishing of the surface of the semiconductor substrate 1 is to use chemical reagents to clean the mechanical cutting damage layer, metal ions, dirt and impurities of the substrate 1 for pre-polishing, so as to modify the semiconductor substrate 1 into a smoother interface; wherein, the reagents used for the pre-polishing of the surface of the semiconductor substrate 1 include at least one of NH4OH, NaOH, KOH, H2O or other suitable reagents, the pre-polishing temperature ranges from 65°C to 80°C, and the pre-polishing time ranges from 180s to 300s.

[0065] S112: Pre-cleaning the surface of the semiconductor substrate 1 after the pre-polishing treatment; pre-cleaning the surface of the semiconductor substrate 1 after the pre-polishing treatment can effectively remove impurities on the surface of the semiconductor substrate 1 after the pre-polishing treatment; wherein the reagents used for pre-cleaning the surface of the semiconductor substrate 1 after the pre-polishing treatment include one of NaOH, KOH, H2O2, H2O or other suitable reagents, and when NaOH is used for pre-cleaning, the concentration range of NaOH is 45wt%~55wt%, the concentration range of KOH is 45wt%~55wt%, the concentration range of H2O2 is 25wt%~35wt%, the temperature range of pre-cleaning is about 55℃~65℃, and the time range of pre-cleaning is 120s~180s.

[0066] S113: performing a hydrophobic treatment on the surface of the semiconductor substrate 1 after the pre-cleaning treatment; performing a hydrophobic treatment on the surface of the semiconductor substrate 1 can ensure the cleanliness of the surface of the semiconductor substrate 1 and improve the anti-pollution ability of the surface of the semiconductor substrate 1, wherein the reagent used for performing the hydrophobic treatment on the surface of the semiconductor substrate 1 includes at least one of HF, HCL, and H2O, and when HF is used for the hydrophobic treatment, the concentration range of HF is 45wt%~55wt%, and when HCL is used for the hydrophobic treatment, the concentration range of HCL is 30wt%~40wt%, the hydrophobic treatment is performed at room temperature, and the time range of the hydrophobic treatment is 120s~360s.

[0067] S114: Drying the surface of the semiconductor substrate 1 after the hydrophobic treatment. Drying the semiconductor substrate 1 fully removes water vapor impurities on the surface of the semiconductor substrate 1, which is helpful for the subsequent process. The semiconductor substrate 1 is dried under an inert gas atmosphere, and the inert gas includes nitrogen or other suitable inert gases. The drying time ranges from 480s to 800s.

[0068] See also Figures 2 to 4 , perform step S2 to form a doping structure 2 on the lower surface of the semiconductor substrate 1, the doping structure 2 includes a tunneling layer 21, an intrinsic layer 22, and a first doping structure 23, a second doping structure 24 and an isolation structure 25 stacked in sequence, the isolation structure 25 is located in the intrinsic layer 22, and the first doping structure 23 and the second doping structure 24 are isolated, and the first doping structure 23 and the second doping structure 24 have opposite conductivity types.

[0069] In some embodiments, step S2 further includes steps S21 to S23 of forming a doping structure 2, including:

[0070] S21: forming a tunneling layer 21 and an intrinsic layer 22 stacked in sequence on the lower surface of the semiconductor substrate 1; the tunneling layer 21 and the intrinsic layer 22 are used to achieve efficient back passivation and selective collection of carriers, wherein the material of the tunneling layer 21 includes SiO x The method of forming the tunneling layer 21 includes thermal oxidation, nitric acid oxidation, ozone oxidation or other suitable methods, and the thickness of the tunneling layer 21 ranges from 1nm to 3nm; the material of the intrinsic layer 22 includes amorphous silicon or other suitable materials, and the intrinsic layer 22 of amorphous silicon material is formed by decomposition of silane, and the method of forming the intrinsic layer 22 includes low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition, physical vapor deposition or other suitable methods, and the thickness of the intrinsic layer 22 ranges from 40nm to 80nm.

[0071] S22: forming a first doping initial structure 26 and a second doping initial structure 27 on the lower surface of the intrinsic layer 22, respectively, wherein the first doping initial structure 26 and the second doping initial structure 27 are arranged at an interval and have opposite conductivity types; wherein the first doping initial structure 26 includes boron element, and the second doping initial structure 27 includes phosphorus element, and the method for forming the first doping initial structure 26 is slurry brushing, and when the first doping initial structure 26 is formed by slurry brushing, the solid content of the first doping initial structure 26 is in the range of 20% to 55%, and the viscosity is in the range of 2 0Pa~50Pa, the method for forming the second doped initial structure 27 is slurry brushing, and when the second doped initial structure 27 is formed by slurry brushing, the solid content range of the second doped initial structure 27 is 15%~35%, the viscosity range is 20Pa~50Pa, the width range of the first doped initial structure 26 is 600nm~800nm, the width range of the second doped initial structure 27 is 400nm~600nm, and the ratio of the width of the first doped initial structure 26 to the second doped initial structure 27 is in the range of 3:2~4:3.

[0072] S23: Annealing is performed on the intrinsic layer 22 after the first doping initial structure 26 and the second doping initial structure 27 are formed on the lower surface. After the annealing, the first doping initial structure 26 forms a first doping structure 23 in the intrinsic layer 27, and the second doping initial structure 27 forms a second doping structure 24 in the intrinsic layer 22. The undoped area of ​​the intrinsic layer 22 between the first doping structure 23 and the second doping structure 24 serves as an isolation structure 25. After the first doping initial structure 26 and the second doping initial structure 27 are formed on the lower surface, the intrinsic layer 22 is annealed to realize the transformation of the intrinsic layer 25 to the doping structure. Due to the presence of the tunneling layer 21 and the low surface concentration, it is ensured that there will be no large amount of "dead layer" at the interface, which provides a large space for the passivation of the existing thin intrinsic layer 22. During the period, a part of the intrinsic layer 22 that has not been doped with any element is retained as an isolation structure 25 to prevent the conduction from forming a back "leakage current" channel, and the first doping structure 23, the second doping structure 24 and the isolation structure 25 are directly formed by annealing, which greatly simplifies the process flow. Among them, the annealing treatment is carried out in a nitrogen or oxygen atmosphere, the annealing treatment temperature range is 850°C~1050°C, and the annealing treatment time range is 10min~30min. Exemplarily, the width of the first doping structure 23 is greater than the width of the second doping structure 24. The width of the first doping structure 23 can also be less than or equal to the width of the second doping structure 24, which can be selected according to actual conditions.

[0073] See also Figures 5 to 7 , executing step S3, forming a passivation anti-reflection material layer 31 on the upper surface of the semiconductor substrate 1 and the lower surface of the doping structure 2 respectively.

[0074] In some embodiments, step S3 further includes step S31, that is, before forming the passivation anti-reflection material layer 31 on the upper surface of the semiconductor substrate 1, it also includes: forming a velvet structure 11 on the upper surface of the semiconductor substrate 1. The velvet structure 11 is a tiny pyramid-shaped structure or other microstructure formed on the upper surface of the semiconductor substrate 1, which increases the surface area above the semiconductor substrate 1, thereby improving the absorption of sunlight.

[0075] In some embodiments, forming the textured structure 11 on the upper surface of the semiconductor substrate 1 includes the following steps S311-S313:

[0076] S311: forming a protective layer 6 on the lower surface of the doped structure 2; the protective layer 6 is used to protect the lower surface of the doped structure 2 when the velvet structure 11 is formed on the upper surface of the semiconductor substrate 1, the material of the protective layer 6 includes at least one of silicon oxide, silicon oxynitride, borosilicate glass or other suitable materials, and the method of forming the protective layer 6 includes low-pressure chemical vapor deposition, plasma enhanced chemical vapor deposition, physical vapor deposition, catalytic chemical vapor deposition, atomic layer deposition or other suitable methods, and the thickness of the formed protective layer 6 ranges from 2nm to 50nm.

[0077] S312: wet-etching the upper surface of the semiconductor substrate 1 to form a velvet structure 11; the reagent used for wet-etching the upper surface of the semiconductor substrate 1 includes at least one of NaOH, KOH, and H2O. Exemplarily, when the reagent used is a mixed solution of NaOH or KOH and H2O, the volume ratio of NaOH or KOH to H2O is 1:15, the processing temperature ranges from 75°C to 83°C, and the processing time ranges from 360s to 420s. In addition, the reflectivity of the upper surface of the semiconductor substrate 1 after the velvet structure 11 is formed ranges from 8% to 11%.

[0078] S313: removing the protective layer 6. To ensure the smooth progress of the subsequent processes, the protective layer 6 is actually removed by at least one of HF and H2O. For example, when the reagent used is a mixed solution of HF and H2O, the volume ratio of HF to H2O is 1:20, and the time range for removing the protective layer 6 is 100s to 400s.

[0079] In some embodiments, the passivation anti-reflection material layer 31 includes a first passivation material and a second passivation material stacked in sequence, wherein the first passivation material includes Al x O y The second passivation material includes at least one of silicon nitride, silicon oxide, and silicon oxynitride. x O y As the first passivation material, Al x O y The negative charge effect of the second passivation material can ensure the efficient passivation effect and better saturate the dangling bonds on the silicon surface. The second passivation material can effectively protect the first passivation material and achieve efficient defect center repair through chemical passivation. For example, the first passivation material is Al x O yThe first passivation material is prepared based on the reaction of trimethylaluminum and H2O or trimethylaluminum and O3, the thickness range of the first passivation material is 3nm~10nm, and the method of forming the first passivation material includes plasma enhanced atomic layer deposition, atomic layer deposition, physical vapor deposition or other suitable methods; the thickness range of the second passivation material is 70nm~110nm, and the refractive index range of the second passivation material is 2.0%~2.4%.

[0080] Step S3 also includes step S32, that is, after forming the passivation anti-reflection material layer 31 on the upper surface of the semiconductor substrate 1 and the lower surface of the doping structure 2, before removing the passivation anti-reflection material layer 31 located on the lower surface of the first doping structure 23 and the second doping structure 24, it also includes: annealing the passivation anti-reflection material layer 31. The annealing of the passivation anti-reflection material layer 31 is performed at a medium-high temperature, and the annealing of the passivation anti-reflection material layer 31 can make the free hydrogen in the passivation anti-reflection material layer 31 diffuse into the first doping structure 23, the second doping structure 24 and the tunneling layer 21, repair the defect center, and neutralize the dangling bond, and finally improve the quality of the first doping structure 23, the second doping structure 24 and the tunneling layer 21.

[0081] See also Figure 8 , perform step S4 to remove the passivation anti-reflection material layer 31 located on the lower surface of the first doping structure 23 and the second doping structure 24 to form a passivation anti-reflection layer 3, the passivation anti-reflection layer 3 includes a first passivation anti-reflection layer 32 located on the lower surface of the isolation structure 25 and a second passivation anti-reflection layer 33 located on the upper surface of the semiconductor substrate 1.

[0082] In some embodiments, the width of the first passivation anti-reflection layer 32 is less than the difference between the width of the first doping structure 23 and the width of the second doping structure 24, that is, the second passivation anti-reflection layer 32 is arranged on the upper surface of the isolation structure 25, which ensures good interface passivation effect and isolation effect of the first doping structure 23 and the second doping structure 24, while also achieving good electrical contact. By forming the second passivation anti-reflection layer 33 on the upper surface of the velvet structure 11, light absorption can be improved and the recombination loss of carriers on the front side can be reduced, thereby improving the open circuit voltage and short circuit current of the battery, thereby obtaining a higher conversion efficiency.

[0083] In some embodiments, the method for removing the passivation anti-reflection material layer 31 located on the lower surface of the first doping structure 23 and the second doping structure 24 includes laser etching or other suitable methods. The passivation anti-reflection material layer 31 located on the lower surface of the first doping structure 23 and the second doping structure 24 is removed by laser etching, thereby achieving high-precision and high-efficiency processing, reducing errors and losses in the production process, avoiding affecting the first doping structure 23 and the second doping structure 24, and improving the yield of solar cells. When laser etching is used to remove the passivation anti-reflection material layer 31 located on the lower surface of the first doping structure 23 and the second doping structure 24, the laser wavelength used is 355nm, and the power range is 50W~120W.

[0084] See also Figures 9 and 10 , execute step S5 to form a first conductive portion 4 that at least covers the lower surface of the first doped structure 23, and to form a second conductive portion 5 that at least covers the lower surface of the second doped structure 24, and an end of the first conductive portion 4 close to the isolation structure 25 is spaced apart from an end of the second conductive portion 5 close to the isolation structure 25.

[0085] In some embodiments, step S5 further includes S51-S52, that is, forming a first conductive portion 4 at least covering the lower surface of the first doping structure 23, and forming a second conductive portion 5 at least covering the lower surface of the second doping structure 24, including the following steps:

[0086] S51: forming a conductive material layer 7 covering the lower surface of the first doping structure 23, the lower surface of the second doping structure 24 and the exposed surface of the first passivation anti-reflection layer 32;

[0087] S52: An isolation groove 8 is formed in the conductive material layer 7, wherein the isolation groove 8 penetrates the conductive material layer 7 and the opening width of the isolation groove 8 is not greater than the width of the isolation structure 25, so as to form a first conductive portion 4 that at least covers the lower surface of the first doping structure 23 and a second conductive portion 5 that at least covers the lower surface of the second doping structure 24. By forming the first conductive portion 4 that covers the lower surface of the first doping structure 23 and the second conductive portion 5 that covers the lower surface of the second doping structure 24, the first conductive portion 4 and the second conductive portion 5 have good conductivity, and can achieve higher transmittance, lower resistivity and efficient carrier collection, thereby improving the performance of the solar cell. In addition, the first conductive portion 4 covers the lower surface of the first doping structure 23, and the second conductive portion 5 covers the lower surface of the second doping structure 24, that is, the first conductive portion 4 and the second conductive portion 5 are not in contact with each other, thereby ensuring that the lateral current is conducted and the isolation of the first doping structure 23 and the second doping structure 24 is achieved. The method of forming the conductive material layer 7 includes magnetron sputtering or other suitable methods. When the conductive material layer 7 is formed by magnetron sputtering, the working atmosphere gas used includes argon gas, the working gas pressure range is 0.2Pa~10Pa, and the power density range is 60W~500W.

[0088] In some embodiments, the method of forming the isolation groove 8 includes laser etching or other suitable methods; the isolation groove 8 is formed in the conductive material layer 7, and the opening width of the isolation groove 8 is not greater than the width of the isolation structure 25, so as to avoid the first doping structure 23 and the second doping structure 24 from being exposed, and realize the lateral current conduction of the solar cell. Exemplarily, the opening width of the isolation groove 8 is 60μm~300μm. Laser etching technology can achieve high-precision and high-efficiency processing, reduce errors and losses in the production process, avoid affecting the isolation structure 25 and the first passivation anti-reflection layer 32, and improve the yield of the solar cell. Among them, when laser etching is used to form the isolation groove 8, the laser wavelength includes 355nm and 532nm, which can be selected according to actual conditions, and the laser power range is 40W~80W.

[0089] In some embodiments, the conductive material layer 7 includes a transparent conductive oxide. Using a transparent conductive oxide as the conductive material layer 7 to prepare the first conductive part 4 and the second conductive part 5 can achieve higher light transmittance and conductivity, thereby greatly improving the photoelectric conversion efficiency of the battery.

[0090] In some embodiments, the first conductive portion 4 and / or the second conductive portion 5 extend to the lower surface of the first passivation anti-reflection layer 32. That is, the first conductive portion 4 and / or the second conductive portion 5 also cover a portion of the lower surface of the first passivation anti-reflection layer 32, and the first conductive portion 4 and the second conductive portion 5 are not in contact with each other, thereby ensuring the lateral current conduction and improving the isolation effect of the first doping structure 23 and the second doping structure 24.

[0091] See also Fig.11 In some embodiments, the method for preparing a solar cell further includes step S6, after forming the first conductive portion 4 covering the lower surface of the first doping structure 23 and the second conductive portion 5 covering the lower surface of the second doping structure 24, further includes forming a first extraction electrode 9 on the lower surface of the first conductive portion 4 and forming a second extraction electrode 10 on the lower surface of the second conductive portion 5. The first extraction electrode 9 and the second extraction electrode 10 are respectively used as a positive electrode and a negative electrode for extracting current.

[0092] The process of forming the first extraction electrode 9 and the second extraction electrode 10 includes the following steps S61-S62:

[0093] S61: forming a first electrode material (not shown) on the lower surface of the first conductive portion 4, and forming a second electrode material (not shown) on the lower surface of the second conductive portion 5; wherein the method of forming the first electrode material comprises slurry brushing, and the material of the first electrode material comprises silver, aluminum, copper or other suitable conductive materials; the method of forming the second electrode material comprises slurry brushing, and the material of the second electrode material comprises silver, aluminum, copper or other suitable conductive materials.

[0094] S62: The first electrode material and the second electrode material are cured to form the first extraction electrode 9 and the second extraction electrode 10. The method used for curing the first electrode material and the second electrode material includes sintering, and when the first electrode material and the second electrode material are cured by the sintering method, the sintering temperature ranges from 150° C. to 1000° C., and the processing time is about 60s to 600s.

[0095] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily performed at the same time, but can be performed at different times. The execution order of these steps or stages is not necessarily sequential, but can be performed in turn or alternately with other steps or at least part of the steps or stages in other steps.

[0096] Please continue reading Fig.11 The present invention also provides a solar cell, and the solar cell is prepared by the above-mentioned method for preparing a solar cell, comprising: a semiconductor substrate 1, a doping structure 2, a passivation anti-reflection layer 3, a first conductive part 4 and a second conductive part 5, wherein the doping structure 2 is located on the lower surface of the semiconductor substrate 1, and the doping structure 2 comprises a tunneling layer 21, an intrinsic layer 22, and a first doping structure 23, a second doping structure 24 and an isolation structure 25 for isolating the first doping structure 23 from the second doping structure 24, which are stacked in sequence, and the first doping structure 23 and the second doping structure 24 have opposite conductivity types; the passivation anti-reflection layer 3 comprises a first passivation anti-reflection layer 32 located on the lower surface of the isolation structure 25 and a second passivation anti-reflection layer 33 located on the upper surface of the semiconductor substrate 1; the first conductive part 4 at least covers the lower surface of the first doping structure 23, the second conductive part 5 at least covers the lower surface of the second doping structure 24, and an end of the first conductive part 4 close to the isolation structure 25 and an end of the second conductive part 5 close to the isolation structure 25 are arranged at intervals.

[0097] In some embodiments, a textured structure 11 is further provided on the upper surface of the semiconductor substrate 1 , and the second passivation anti-reflection layer 33 covers the upper surface of the textured structure 11 .

[0098] In some embodiments, the first conductive portion 4 and / or the second conductive portion 5 extend to the lower surface of the first passivation anti-reflection layer 32 , that is, the first conductive portion 4 and / or the second conductive portion 5 also partially covers the lower surface of the first passivation anti-reflection layer 32 .

[0099] In some embodiments, the solar cell further includes a first extraction electrode 9 and a second extraction electrode 10 . The first extraction electrode 9 is located on the lower surface of the first conductive portion 4 ; the second extraction electrode 10 is located on the lower surface of the second conductive portion 5 .

[0100] In the description of this specification, the description with reference to the terms "some embodiments", "other embodiments", "ideal embodiments", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example.

[0101] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0102] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be construed as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent application shall be subject to the attached claims.

Claims

1. A method for preparing a solar cell, characterized in that: The steps include: Providing a semiconductor substrate; forming a doping structure on the lower surface of the semiconductor substrate, the doping structure comprising a tunneling layer, an intrinsic layer, and a first doping structure, a second doping structure, and an isolation structure located in the intrinsic layer, wherein the isolation structure isolates the first doping structure from the second doping structure, and the first doping structure and the second doping structure have opposite conductivity types; forming a passivation anti-reflection material layer on the upper surface of the semiconductor substrate and the lower surface of the doping structure respectively; Removing the passivation anti-reflection material layer located on the lower surfaces of the first doping structure and the second doping structure to form a passivation anti-reflection layer, wherein the passivation anti-reflection layer includes a first passivation anti-reflection layer located on the lower surface of the isolation structure and a second passivation anti-reflection layer located on the upper surface of the semiconductor substrate; A first conductive portion is formed to at least cover the lower surface of the first doped structure, and a second conductive portion is formed to at least cover the lower surface of the second doped structure, wherein an end of the first conductive portion close to the isolation structure is spaced from an end of the second conductive portion close to the isolation structure.

2. The method for preparing a solar cell according to claim 1, characterized in that: Forming the doping structure on the lower surface of the semiconductor substrate comprises the following steps: Forming the tunneling layer and the intrinsic layer stacked in sequence on the lower surface of the semiconductor substrate; forming a first doped initial structure and a second doped initial structure on the lower surface of the intrinsic layer, wherein the first doped initial structure and the second doped initial structure are spaced apart and have opposite conductivity types; The intrinsic layer after the first doping initial structure and the second doping initial structure are formed on the lower surface is annealed. After the annealing, the first doping initial structure forms the first doping structure in the intrinsic layer, and the first doping initial structure forms the second doping structure in the intrinsic layer. The undoped intrinsic layer between the first doping structure and the second doping structure serves as the isolation structure.

3. The method for preparing a solar cell according to claim 1, characterized in that: Before forming the passivation anti-reflection material layer on the upper surface of the semiconductor substrate, the method further includes: A textured structure is formed on the upper surface of the semiconductor substrate.

4. The method for preparing a solar cell according to claim 3, characterized in that: Forming the textured structure on the upper surface of the semiconductor substrate comprises the following steps: forming a protective layer on the lower surface of the doping structure; Wet etching the upper surface of the semiconductor substrate to form the textured structure; The protective layer is removed.

5. The method for preparing a solar cell according to claim 1, characterized in that: After forming the passivation anti-reflection material layer on the upper surface of the semiconductor substrate and the lower surface of the doped structure, and before removing the passivation anti-reflection material layer located on the lower surfaces of the first doped structure and the second doped structure, the method further includes: The passivation anti-reflection material layer is annealed.

6. The method for preparing a solar cell according to claim 1, characterized in that: The passivation anti-reflection material layer includes a first passivation material and a second passivation material stacked in sequence, wherein the first passivation material includes Al x O y The second passivation material includes at least one of silicon nitride, silicon oxide, and silicon oxynitride.

7. The method for preparing a solar cell according to claim 1, characterized in that: The first conductive portion and / or the second conductive portion extends to the lower surface of the first passivation anti-reflection layer.

8. The method for preparing a solar cell according to claim 1, characterized in that: Forming the first conductive portion that at least covers the lower surface of the first doping structure, and forming the second conductive portion that at least covers the lower surface of the second doping structure, comprises the following steps: forming a conductive material layer covering the lower surface of the first doped structure, the lower surface of the second doped structure, and the exposed surface of the first passivation anti-reflection layer; An isolation groove is formed in the conductive material layer, wherein the isolation groove penetrates the conductive material layer and the opening width of the isolation groove is not greater than the width of the isolation structure, so as to form the first conductive part that at least covers the lower surface of the first doped structure and the second conductive part that at least covers the lower surface of the second doped structure.

9. The method for preparing a solar cell according to claim 1, characterized in that: After forming the first conductive portion that at least covers the lower surface of the first doping structure and forming the second conductive portion that at least covers the lower surface of the second doping structure, the method further includes: A first lead-out electrode is formed on the lower surface of the first conductive portion, and a second lead-out electrode is formed on the lower surface of the second conductive portion.

10. A solar cell, characterized in that: The solar cell is prepared by the method for preparing a solar cell according to any one of claims 1 to 9.

Images